diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index d3a20ee892..aac2e7bdee 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -461,7 +461,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .amdgcn,
         .avr,
         .msp430,
-        .spu_2,
         .ve,
         .bpfel,
         .bpfeb,
@@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .spu_2,
         .xcore,
         .xtensa,
         => return null,
@@ -620,8 +618,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .wasm32 => "wasm32",
         .wasm64 => "wasm64",
         .ve => "ve",
-        // Note: spu_2 is not supported in LLVM; this is the Zig arch name
-        .spu_2 => "spu_2",
     };
     writer.writeAll(llvm_arch) catch unreachable;
     writer.writeByte('-') catch unreachable;
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index 42267f0ae1..2391f64238 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1085,7 +1085,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
         .s390x => .S390,
         .sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
         .sparc64 => .SPARCV9,
-        .spu_2 => .SPU_2,
         .ve => .VE,
         .x86 => if (target.os.tag == .elfiamcu) .IAMCU else .@"386",
         .x86_64 => .X86_64,
@@ -1148,7 +1147,6 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
         .spirv,
         .spirv32,
         .spirv64,
-        .spu_2,
         .ve,
         .wasm32,
         .wasm64,
@@ -1378,7 +1376,6 @@ pub const Cpu = struct {
         spirv,
         spirv32,
         spirv64,
-        spu_2,
         ve,
         wasm32,
         wasm64,
@@ -1564,7 +1561,6 @@ pub const Cpu = struct {
                 .xcore,
                 .thumb,
                 .ve,
-                .spu_2,
                 // GPU bitness is opaque. For now, assume little endian.
                 .spirv,
                 .spirv32,
@@ -1954,7 +1950,6 @@ pub const Cpu = struct {
                 .xtensa => &xtensa.cpu.generic,
 
                 .kalimba,
-                .spu_2,
                 => &S.generic_model,
             };
         }
@@ -2627,7 +2622,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
     return switch (cpu.arch) {
         .avr,
         .msp430,
-        .spu_2,
         => 16,
 
         .arc,
@@ -3164,7 +3158,6 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
             .x86,
             .xcore,
             .kalimba,
-            .spu_2,
             .xtensa,
             .propeller1,
             .propeller2,
@@ -3260,7 +3253,6 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
             .csky,
             .xcore,
             .kalimba,
-            .spu_2,
             .xtensa,
             .propeller1,
             .propeller2,
@@ -3371,7 +3363,6 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
         .propeller1 => .{ .propeller1_sysv = .{} },
         .propeller2 => .{ .propeller2_sysv = .{} },
         .s390x => .{ .s390x_sysv = .{} },
-        .spu_2 => null,
         .ve => .{ .ve_sysv = .{} },
         .xcore => .{ .xcore_xs1 = .{} },
         .xtensa => .{ .xtensa_call0 = .{} },
diff --git a/lib/std/debug/Dwarf/abi.zig b/lib/std/debug/Dwarf/abi.zig
index e0a2a4858b..001e1977f9 100644
--- a/lib/std/debug/Dwarf/abi.zig
+++ b/lib/std/debug/Dwarf/abi.zig
@@ -17,7 +17,6 @@ pub fn supportsUnwinding(target: std.Target) bool {
         .spirv,
         .spirv32,
         .spirv64,
-        .spu_2,
         => false,
 
         // Enabling this causes relocation errors such as:
diff --git a/lib/std/elf.zig b/lib/std/elf.zig
index 5ffcc629cc..f326b6b5a9 100644
--- a/lib/std/elf.zig
+++ b/lib/std/elf.zig
@@ -1178,8 +1178,6 @@ pub const EM = enum(u16) {
     MIPS_RS3_LE = 10,
     /// Old version of Sparc v9, from before the ABI (deprecated)
     OLD_SPARCV9 = 11,
-    /// SPU Mark II
-    SPU_2 = 13,
     /// HPPA
     PARISC = 15,
     /// Fujitsu VPP500 (also old version of PowerPC; deprecated)
diff --git a/src/Type.zig b/src/Type.zig
index d058e6a363..0f03380b73 100644
--- a/src/Type.zig
+++ b/src/Type.zig
@@ -1698,7 +1698,6 @@ pub fn maxIntAlignment(target: std.Target) u16 {
 
         // Below this comment are unverified but based on the fact that C requires
         // int128_t to be 16 bytes aligned, it's a safe default.
-        .spu_2,
         .csky,
         .arc,
         .m68k,
diff --git a/src/Zcu.zig b/src/Zcu.zig
index ca3ae0ea71..1c7b4d2876 100644
--- a/src/Zcu.zig
+++ b/src/Zcu.zig
@@ -3594,7 +3594,6 @@ pub fn atomicPtrAlignment(
     const max_atomic_bits: u16 = switch (target.cpu.arch) {
         .avr,
         .msp430,
-        .spu_2,
         => 16,
 
         .arc,
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 97ed00c98d..25b49d2b35 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -98,7 +98,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .ve => "ve",
 
         .kalimba,
-        .spu_2,
         .propeller1,
         .propeller2,
         => unreachable, // Gated by hasLlvmSupport().
@@ -13024,7 +13023,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
 
         // LLVM does does not have a backend for these.
         .kalimba,
-        .spu_2,
         .propeller1,
         .propeller2,
         => unreachable,
diff --git a/src/target.zig b/src/target.zig
index 3d7abb935d..9487d0937e 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -195,7 +195,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
 
         // No LLVM backend exists.
         .kalimba,
-        .spu_2,
         .propeller1,
         .propeller2,
         => false,