mirror of
https://github.com/ziglang/zig.git
synced 2025-12-06 06:13:07 +00:00
x86_64: improve inline assembly support
* instruction prefixes * mnemonic fixes * labels * memory operands * read-write constraint modifier * register and memory alternative constraint
This commit is contained in:
Jacob Young
parent
7436f3efc9
commit
b19fd485b1
@ -32,10 +32,10 @@ const Target = std.Target;
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const Type = @import("../../type.zig").Type;
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const TypedValue = @import("../../TypedValue.zig");
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const Value = @import("../../value.zig").Value;
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const Instruction = @import("encoder.zig").Instruction;
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const abi = @import("abi.zig");
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const bits = @import("bits.zig");
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const encoder = @import("encoder.zig");
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const errUnionErrorOffset = codegen.errUnionErrorOffset;
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const errUnionPayloadOffset = codegen.errUnionPayloadOffset;
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@ -1275,6 +1275,17 @@ fn asmJccReloc(self: *Self, target: Mir.Inst.Index, cc: bits.Condition) !Mir.Ins
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});
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}
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fn asmReloc(self: *Self, tag: Mir.Inst.FixedTag, target: Mir.Inst.Index) !void {
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_ = try self.addInst(.{
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.tag = tag[1],
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.ops = .inst,
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.data = .{ .inst = .{
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.fixes = tag[0],
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.inst = target,
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} },
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});
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}
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fn asmPlaceholder(self: *Self) !Mir.Inst.Index {
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return self.addInst(.{
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.tag = .pseudo,
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@ -2174,7 +2185,7 @@ fn genLazy(self: *Self, lazy_sym: link.File.LazySymbol) InnerError!void {
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const ret_reg = param_regs[0];
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const enum_mcv = MCValue{ .register = param_regs[1] };
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var exitlude_jump_relocs = try self.gpa.alloc(u32, enum_ty.enumFieldCount(mod));
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var exitlude_jump_relocs = try self.gpa.alloc(Mir.Inst.Index, enum_ty.enumFieldCount(mod));
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defer self.gpa.free(exitlude_jump_relocs);
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const data_reg = try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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@ -5887,7 +5898,7 @@ fn store(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) InnerErr
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try self.genCopy(src_ty, .{ .indirect = .{ .reg = addr_reg } }, src_mcv);
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},
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.air_ref => |ptr_ref| try self.store(ptr_ty, ptr_mcv, try self.resolveInst(ptr_ref)),
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.air_ref => |ptr_ref| try self.store(ptr_ty, try self.resolveInst(ptr_ref), src_mcv),
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}
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}
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@ -9313,7 +9324,7 @@ fn airDbgVar(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, .unreach, .{ operand, .none, .none });
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}
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fn genCondBrMir(self: *Self, ty: Type, mcv: MCValue) !u32 {
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fn genCondBrMir(self: *Self, ty: Type, mcv: MCValue) !Mir.Inst.Index {
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const mod = self.bin_file.options.module.?;
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const abi_size = ty.abiSize(mod);
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switch (mcv) {
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@ -9695,7 +9706,7 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {
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const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
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const loop = self.air.extraData(Air.Block, ty_pl.payload);
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const body = self.air.extra[loop.end..][0..loop.data.body_len];
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const jmp_target: u32 = @intCast(self.mir_instructions.len);
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const jmp_target: Mir.Inst.Index = @intCast(self.mir_instructions.len);
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self.scope_generation += 1;
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const state = try self.saveState();
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@ -9772,7 +9783,7 @@ fn airSwitchBr(self: *Self, inst: Air.Inst.Index) !void {
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const case_body = self.air.extra[case.end + items.len ..][0..case.data.body_len];
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extra_index = case.end + items.len + case_body.len;
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var relocs = try self.gpa.alloc(u32, items.len);
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var relocs = try self.gpa.alloc(Mir.Inst.Index, items.len);
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defer self.gpa.free(relocs);
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try self.spillEflagsIfOccupied();
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@ -9929,22 +9940,35 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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.none => self.typeOfIndex(inst),
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else => self.typeOf(output).childType(mod),
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};
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const arg_maybe_reg: ?Register = if (mem.eql(u8, constraint, "=r"))
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const is_read = switch (constraint[0]) {
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'=' => false,
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'+' => read: {
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if (output == .none) return self.fail(
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"read-write constraint unsupported for asm result: '{s}'",
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.{constraint},
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);
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break :read true;
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},
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else => return self.fail("invalid constraint: '{s}'", .{constraint}),
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};
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const arg_maybe_reg: ?Register = if (mem.eql(u8, constraint[1..], "r"))
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self.register_manager.tryAllocReg(maybe_inst, self.regClassForType(ty)) orelse
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return self.fail("ran out of registers lowering inline asm", .{})
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else if (mem.eql(u8, constraint, "=m"))
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else if (mem.eql(u8, constraint[1..], "m"))
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if (output != .none) null else return self.fail(
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"memory constraint unsupported for asm result",
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.{},
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"memory constraint unsupported for asm result: '{s}'",
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.{constraint},
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)
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else if (mem.eql(u8, constraint, "=g"))
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else if (mem.eql(u8, constraint[1..], "g") or
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mem.eql(u8, constraint[1..], "rm") or mem.eql(u8, constraint[1..], "mr") or
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mem.eql(u8, constraint[1..], "r,m") or mem.eql(u8, constraint[1..], "m,r"))
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self.register_manager.tryAllocReg(maybe_inst, self.regClassForType(ty)) orelse
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if (output != .none) null else return self.fail(
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"ran out of register lowering inline asm",
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.{},
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)
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else if (mem.startsWith(u8, constraint, "={") and mem.endsWith(u8, constraint, "}"))
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parseRegName(constraint["={".len .. constraint.len - "}".len]) orelse
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if (output != .none)
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null
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else
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return self.fail("ran out of registers lowering inline asm", .{})
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else if (mem.startsWith(u8, constraint[1..], "{") and mem.endsWith(u8, constraint[1..], "}"))
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parseRegName(constraint[1 + "{".len .. constraint.len - "}".len]) orelse
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return self.fail("invalid register constraint: '{s}'", .{constraint})
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else
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return self.fail("invalid constraint: '{s}'", .{constraint});
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@ -9965,6 +9989,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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arg_map.putAssumeCapacityNoClobber(name, @intCast(args.items.len));
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args.appendAssumeCapacity(arg_mcv);
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if (output == .none) result = arg_mcv;
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if (is_read) try self.load(arg_mcv, self.typeOf(output), .{ .air_ref = output });
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}
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for (inputs) |input| {
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@ -9999,7 +10024,10 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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};
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try self.genSetReg(addr_reg, Type.usize, input_mcv.address());
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break :arg .{ .indirect = .{ .reg = addr_reg } };
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} else if (mem.eql(u8, constraint, "g")) arg: {
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} else if (mem.eql(u8, constraint, "g") or
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mem.eql(u8, constraint, "rm") or mem.eql(u8, constraint, "mr") or
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mem.eql(u8, constraint, "r,m") or mem.eql(u8, constraint, "m,r"))
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arg: {
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switch (input_mcv) {
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.register, .indirect, .load_frame => break :arg input_mcv,
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.memory => |addr| if (math.cast(i32, @as(i64, @bitCast(addr)))) |_|
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@ -10038,44 +10066,141 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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}
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}
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const Label = struct {
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target: Mir.Inst.Index = undefined,
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pending_relocs: std.ArrayListUnmanaged(Mir.Inst.Index) = .{},
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const Kind = enum { definition, reference };
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fn isValid(kind: Kind, name: []const u8) bool {
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for (name, 0..) |c, i| switch (c) {
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else => return false,
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'$' => if (i == 0) return false,
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'.' => {},
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'0'...'9' => if (i == 0) switch (kind) {
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.definition => if (name.len != 1) return false,
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.reference => {
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if (name.len != 2) return false;
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switch (name[1]) {
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else => return false,
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'B', 'F', 'b', 'f' => {},
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}
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},
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},
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'@', 'A'...'Z', '_', 'a'...'z' => {},
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};
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return name.len > 0;
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}
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};
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var labels: std.StringHashMapUnmanaged(Label) = .{};
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defer {
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var label_it = labels.valueIterator();
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while (label_it.next()) |label| label.pending_relocs.deinit(self.gpa);
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labels.deinit(self.gpa);
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}
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const asm_source = mem.sliceAsBytes(self.air.extra[extra_i..])[0..extra.data.source_len];
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var line_it = mem.tokenizeAny(u8, asm_source, "\n\r;");
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while (line_it.next()) |line| {
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next_line: while (line_it.next()) |line| {
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var mnem_it = mem.tokenizeAny(u8, line, " \t");
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const mnem_str = mnem_it.next() orelse continue;
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if (mem.startsWith(u8, mnem_str, "#")) continue;
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const mnem_size: ?Memory.PtrSize = if (mem.endsWith(u8, mnem_str, "b"))
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.byte
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else if (mem.endsWith(u8, mnem_str, "w"))
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.word
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else if (mem.endsWith(u8, mnem_str, "l"))
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.dword
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else if (mem.endsWith(u8, mnem_str, "q"))
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.qword
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else
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null;
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const mnem_tag = Mir.Inst.FixedTag{ ._, mnem: {
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if (mnem_size) |_| {
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if (std.meta.stringToEnum(Mir.Inst.Tag, mnem_str[0 .. mnem_str.len - 1])) |mnem| {
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break :mnem mnem;
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}
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var prefix: Instruction.Prefix = .none;
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const mnem_str = while (mnem_it.next()) |mnem_str| {
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if (mem.startsWith(u8, mnem_str, "#")) continue :next_line;
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if (std.meta.stringToEnum(Instruction.Prefix, mnem_str)) |pre| {
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if (prefix != .none) return self.fail("extra prefix: '{s}'", .{mnem_str});
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prefix = pre;
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continue;
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}
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break :mnem std.meta.stringToEnum(Mir.Inst.Tag, mnem_str) orelse
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return self.fail("invalid mnemonic: '{s}'", .{mnem_str});
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} };
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if (!mem.endsWith(u8, mnem_str, ":")) break mnem_str;
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const label_name = mnem_str[0 .. mnem_str.len - ":".len];
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if (!Label.isValid(.definition, label_name))
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return self.fail("invalid label: '{s}'", .{label_name});
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const label_gop = try labels.getOrPut(self.gpa, label_name);
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if (!label_gop.found_existing) label_gop.value_ptr.* = .{} else {
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const anon = std.ascii.isDigit(label_name[0]);
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if (!anon and label_gop.value_ptr.pending_relocs.items.len == 0)
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return self.fail("redefined label: '{s}'", .{label_name});
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for (label_gop.value_ptr.pending_relocs.items) |pending_reloc|
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try self.performReloc(pending_reloc);
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if (anon)
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label_gop.value_ptr.pending_relocs.clearRetainingCapacity()
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else
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label_gop.value_ptr.pending_relocs.clearAndFree(self.gpa);
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}
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label_gop.value_ptr.target = @intCast(self.mir_instructions.len);
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} else continue;
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var op_it = mem.tokenizeScalar(u8, mnem_it.rest(), ',');
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var ops = [1]encoder.Instruction.Operand{.none} ** 4;
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for (&ops) |*op| {
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const op_str = mem.trim(u8, op_it.next() orelse break, " \t");
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if (mem.startsWith(u8, op_str, "#")) break;
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var mnem_size: ?Memory.PtrSize = null;
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const mnem_tag = mnem: {
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mnem_size = if (mem.endsWith(u8, mnem_str, "b"))
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.byte
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else if (mem.endsWith(u8, mnem_str, "w"))
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.word
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else if (mem.endsWith(u8, mnem_str, "l"))
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.dword
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else if (mem.endsWith(u8, mnem_str, "q"))
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.qword
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else if (mem.endsWith(u8, mnem_str, "t"))
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.tbyte
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else
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break :mnem null;
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break :mnem std.meta.stringToEnum(Instruction.Mnemonic, mnem_str[0 .. mnem_str.len - 1]);
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} orelse mnem: {
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mnem_size = null;
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break :mnem std.meta.stringToEnum(Instruction.Mnemonic, mnem_str);
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} orelse return self.fail("invalid mnemonic: '{s}'", .{mnem_str});
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const mnem_name = @tagName(mnem_tag);
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const mnem_fixed_tag: Mir.Inst.FixedTag = for (std.enums.values(Mir.Inst.Fixes)) |fixes| {
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const fixes_name = @tagName(fixes);
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const space_i = mem.indexOfScalar(u8, fixes_name, ' ');
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const fixes_prefix = if (space_i) |i|
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std.meta.stringToEnum(Instruction.Prefix, fixes_name[0..i]).?
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else
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.none;
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if (fixes_prefix != prefix) continue;
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const pattern = fixes_name[if (space_i) |i| i + " ".len else 0..];
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const wildcard_i = mem.indexOfScalar(u8, pattern, '_').?;
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const mnem_prefix = pattern[0..wildcard_i];
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const mnem_suffix = pattern[wildcard_i + "_".len ..];
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if (!mem.startsWith(u8, mnem_name, mnem_prefix)) continue;
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if (!mem.endsWith(u8, mnem_name, mnem_suffix)) continue;
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break .{ fixes, std.meta.stringToEnum(
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Mir.Inst.Tag,
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mnem_name[mnem_prefix.len .. mnem_name.len - mnem_suffix.len],
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) orelse continue };
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} else {
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assert(prefix != .none);
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return self.fail("invalid prefix for mnemonic: '{s} {s}'", .{
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@tagName(prefix), mnem_str,
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});
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};
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const Operand = union(enum) {
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none,
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reg: Register,
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mem: Memory,
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imm: Immediate,
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inst: Mir.Inst.Index,
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};
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var ops: [4]Operand = .{.none} ** 4;
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var last_op = false;
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var op_it = mem.splitScalar(u8, mnem_it.rest(), ',');
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next_op: for (&ops) |*op| {
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const op_str = while (!last_op) {
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const full_str = op_it.next() orelse break :next_op;
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const trim_str = mem.trim(u8, if (mem.indexOfScalar(u8, full_str, '#')) |hash| hash: {
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last_op = true;
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break :hash full_str[0..hash];
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} else full_str, " \t");
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if (trim_str.len > 0) break trim_str;
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} else break;
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if (mem.startsWith(u8, op_str, "%%")) {
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const colon = mem.indexOfScalarPos(u8, op_str, "%%".len + 2, ':');
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const reg = parseRegName(op_str["%%".len .. colon orelse op_str.len]) orelse
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return self.fail("invalid register: '{s}'", .{op_str});
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if (colon) |colon_pos| {
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const disp = std.fmt.parseInt(i32, op_str[colon_pos + 1 ..], 0) catch
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const disp = std.fmt.parseInt(i32, op_str[colon_pos + ":".len ..], 0) catch
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return self.fail("invalid displacement: '{s}'", .{op_str});
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op.* = .{ .mem = Memory.sib(
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mnem_size orelse return self.fail("unknown size: '{s}'", .{op_str}),
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@ -10089,7 +10214,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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} else if (mem.startsWith(u8, op_str, "%[") and mem.endsWith(u8, op_str, "]")) {
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const colon = mem.indexOfScalarPos(u8, op_str, "%[".len, ':');
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const modifier = if (colon) |colon_pos|
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op_str[colon_pos + 1 .. op_str.len - "]".len]
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op_str[colon_pos + ":".len .. op_str.len - "]".len]
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else
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"";
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op.* = switch (args.items[
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@ -10140,64 +10265,113 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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}
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op.* = .{ .imm = Immediate.u(u) };
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} else |_| return self.fail("invalid immediate: '{s}'", .{op_str});
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} else if (mem.endsWith(u8, op_str, ")")) {
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const open = mem.indexOfScalar(u8, op_str, '(') orelse
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return self.fail("invalid operand: '{s}'", .{op_str});
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var sib_it = mem.splitScalar(u8, op_str[open + "(".len .. op_str.len - ")".len], ',');
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const base_str = sib_it.next() orelse
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return self.fail("invalid memory operand: '{s}'", .{op_str});
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if (base_str.len > 0 and !mem.startsWith(u8, base_str, "%%"))
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return self.fail("invalid memory operand: '{s}'", .{op_str});
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const index_str = sib_it.next() orelse "";
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if (index_str.len > 0 and !mem.startsWith(u8, base_str, "%%"))
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return self.fail("invalid memory operand: '{s}'", .{op_str});
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const scale_str = sib_it.next() orelse "";
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if (index_str.len == 0 and scale_str.len > 0)
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return self.fail("invalid memory operand: '{s}'", .{op_str});
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const scale = if (scale_str.len > 0) switch (std.fmt.parseInt(u4, scale_str, 10) catch
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return self.fail("invalid scale: '{s}'", .{op_str})) {
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1, 2, 4, 8 => |scale| scale,
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else => return self.fail("invalid scale: '{s}'", .{op_str}),
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} else 1;
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if (sib_it.next()) |_| return self.fail("invalid memory operand: '{s}'", .{op_str});
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op.* = .{ .mem = Memory.sib(mnem_size orelse
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return self.fail("unknown size: '{s}'", .{op_str}), .{
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.disp = if (open > 0) std.fmt.parseInt(i32, op_str[0..open], 0) catch
|
||||
return self.fail("invalid displacement: '{s}'", .{op_str}) else 0,
|
||||
.base = if (base_str.len > 0) .{ .reg = parseRegName(base_str["%%".len..]) orelse
|
||||
return self.fail("invalid base register: '{s}'", .{base_str}) } else .none,
|
||||
.scale_index = if (index_str.len > 0) .{
|
||||
.index = parseRegName(index_str["%%".len..]) orelse
|
||||
return self.fail("invalid index register: '{s}'", .{op_str}),
|
||||
.scale = scale,
|
||||
} else null,
|
||||
}) };
|
||||
} else if (Label.isValid(.reference, op_str)) {
|
||||
const anon = std.ascii.isDigit(op_str[0]);
|
||||
const label_gop = try labels.getOrPut(self.gpa, op_str[0..if (anon) 1 else op_str.len]);
|
||||
if (!label_gop.found_existing) label_gop.value_ptr.* = .{};
|
||||
if (anon and (op_str[1] == 'b' or op_str[1] == 'B') and !label_gop.found_existing)
|
||||
return self.fail("undefined label: '{s}'", .{op_str});
|
||||
const pending_relocs = &label_gop.value_ptr.pending_relocs;
|
||||
if (if (anon)
|
||||
op_str[1] == 'f' or op_str[1] == 'F'
|
||||
else
|
||||
!label_gop.found_existing or pending_relocs.items.len > 0)
|
||||
try pending_relocs.append(self.gpa, @intCast(self.mir_instructions.len));
|
||||
op.* = .{ .inst = label_gop.value_ptr.target };
|
||||
} else return self.fail("invalid operand: '{s}'", .{op_str});
|
||||
} else if (op_it.next()) |op_str| return self.fail("extra operand: '{s}'", .{op_str});
|
||||
|
||||
(switch (ops[0]) {
|
||||
.none => self.asmOpOnly(mnem_tag),
|
||||
.none => self.asmOpOnly(mnem_fixed_tag),
|
||||
.reg => |reg0| switch (ops[1]) {
|
||||
.none => self.asmRegister(mnem_tag, reg0),
|
||||
.none => self.asmRegister(mnem_fixed_tag, reg0),
|
||||
.reg => |reg1| switch (ops[2]) {
|
||||
.none => self.asmRegisterRegister(mnem_tag, reg1, reg0),
|
||||
.none => self.asmRegisterRegister(mnem_fixed_tag, reg1, reg0),
|
||||
.reg => |reg2| switch (ops[3]) {
|
||||
.none => self.asmRegisterRegisterRegister(mnem_tag, reg2, reg1, reg0),
|
||||
.none => self.asmRegisterRegisterRegister(mnem_fixed_tag, reg2, reg1, reg0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.mem => |mem2| switch (ops[3]) {
|
||||
.none => self.asmMemoryRegisterRegister(mnem_tag, mem2, reg1, reg0),
|
||||
.none => self.asmMemoryRegisterRegister(mnem_fixed_tag, mem2, reg1, reg0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.mem => |mem1| switch (ops[2]) {
|
||||
.none => self.asmMemoryRegister(mnem_tag, mem1, reg0),
|
||||
.none => self.asmMemoryRegister(mnem_fixed_tag, mem1, reg0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.mem => |mem0| switch (ops[1]) {
|
||||
.none => self.asmMemory(mnem_tag, mem0),
|
||||
.none => self.asmMemory(mnem_fixed_tag, mem0),
|
||||
.reg => |reg1| switch (ops[2]) {
|
||||
.none => self.asmRegisterMemory(mnem_tag, reg1, mem0),
|
||||
.none => self.asmRegisterMemory(mnem_fixed_tag, reg1, mem0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.imm => |imm0| switch (ops[1]) {
|
||||
.none => self.asmImmediate(mnem_tag, imm0),
|
||||
.none => self.asmImmediate(mnem_fixed_tag, imm0),
|
||||
.reg => |reg1| switch (ops[2]) {
|
||||
.none => self.asmRegisterImmediate(mnem_tag, reg1, imm0),
|
||||
.none => self.asmRegisterImmediate(mnem_fixed_tag, reg1, imm0),
|
||||
.reg => |reg2| switch (ops[3]) {
|
||||
.none => self.asmRegisterRegisterImmediate(mnem_tag, reg2, reg1, imm0),
|
||||
.none => self.asmRegisterRegisterImmediate(mnem_fixed_tag, reg2, reg1, imm0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.mem => |mem2| switch (ops[3]) {
|
||||
.none => self.asmMemoryRegisterImmediate(mnem_tag, mem2, reg1, imm0),
|
||||
.none => self.asmMemoryRegisterImmediate(mnem_fixed_tag, mem2, reg1, imm0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.mem => |mem1| switch (ops[2]) {
|
||||
.none => self.asmMemoryImmediate(mnem_tag, mem1, imm0),
|
||||
.none => self.asmMemoryImmediate(mnem_fixed_tag, mem1, imm0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
.inst => |inst0| switch (ops[1]) {
|
||||
.none => self.asmReloc(mnem_fixed_tag, inst0),
|
||||
else => error.InvalidInstruction,
|
||||
},
|
||||
}) catch |err| switch (err) {
|
||||
error.InvalidInstruction => return self.fail(
|
||||
"Invalid instruction: '{s} {s} {s} {s} {s}'",
|
||||
"invalid instruction: '{s} {s} {s} {s} {s}'",
|
||||
.{
|
||||
@tagName(mnem_tag[1]),
|
||||
mnem_str,
|
||||
@tagName(ops[0]),
|
||||
@tagName(ops[1]),
|
||||
@tagName(ops[2]),
|
||||
@ -10208,7 +10382,11 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
|
||||
};
|
||||
}
|
||||
|
||||
for (outputs, args.items[0..outputs.len]) |output, mcv| {
|
||||
var label_it = labels.iterator();
|
||||
while (label_it.next()) |label| if (label.value_ptr.pending_relocs.items.len > 0)
|
||||
return self.fail("undefined label: '{s}'", .{label.key_ptr.*});
|
||||
|
||||
for (outputs, args.items[0..outputs.len]) |output, arg_mcv| {
|
||||
const extra_bytes = mem.sliceAsBytes(self.air.extra[outputs_extra_i..]);
|
||||
const constraint =
|
||||
mem.sliceTo(mem.sliceAsBytes(self.air.extra[outputs_extra_i..]), 0);
|
||||
@ -10218,8 +10396,8 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
|
||||
outputs_extra_i += (constraint.len + name.len + (2 + 3)) / 4;
|
||||
|
||||
if (output == .none) continue;
|
||||
if (mcv != .register) continue;
|
||||
try self.store(self.typeOf(output), try self.resolveInst(output), mcv);
|
||||
if (arg_mcv != .register) continue;
|
||||
try self.store(self.typeOf(output), .{ .air_ref = output }, arg_mcv);
|
||||
}
|
||||
|
||||
simple: {
|
||||
@ -11510,7 +11688,7 @@ fn atomicOp(
|
||||
defer self.register_manager.unlockReg(tmp_lock);
|
||||
|
||||
try self.asmRegisterMemory(.{ ._, .mov }, registerAlias(.rax, val_abi_size), ptr_mem);
|
||||
const loop: u32 = @intCast(self.mir_instructions.len);
|
||||
const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
|
||||
if (rmw_op != std.builtin.AtomicRmwOp.Xchg) {
|
||||
try self.genSetReg(tmp_reg, val_ty, .{ .register = .rax });
|
||||
}
|
||||
@ -11584,7 +11762,7 @@ fn atomicOp(
|
||||
.scale_index = ptr_mem.scaleIndex(),
|
||||
.disp = ptr_mem.sib.disp + 8,
|
||||
}));
|
||||
const loop: u32 = @intCast(self.mir_instructions.len);
|
||||
const loop: Mir.Inst.Index = @intCast(self.mir_instructions.len);
|
||||
const val_mem_mcv: MCValue = switch (val_mcv) {
|
||||
.memory, .indirect, .load_frame => val_mcv,
|
||||
else => .{ .indirect = .{
|
||||
|
||||
@ -42,7 +42,6 @@ test "module level assembly" {
|
||||
|
||||
test "output constraint modifiers" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -66,7 +65,6 @@ test "output constraint modifiers" {
|
||||
|
||||
test "alternative constraints" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -163,8 +161,8 @@ export fn derp() i32 {
|
||||
}
|
||||
|
||||
test "rw constraint (x86_64)" {
|
||||
if (builtin.target.cpu.arch != .x86_64 or builtin.zig_backend != .stage2_llvm)
|
||||
return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
|
||||
if (builtin.target.cpu.arch != .x86_64) return error.SkipZigTest;
|
||||
|
||||
var res: i32 = 5;
|
||||
asm ("addl %[b], %[a]"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user