diff --git a/lib/compiler/aro/aro/Toolchain.zig b/lib/compiler/aro/aro/Toolchain.zig index 1313675f6c..fca44e07ec 100644 --- a/lib/compiler/aro/aro/Toolchain.zig +++ b/lib/compiler/aro/aro/Toolchain.zig @@ -89,7 +89,7 @@ pub fn discover(tc: *Toolchain) !void { .{ .unknown = {} } // TODO else if (target.cpu.arch.isMIPS()) .{ .unknown = {} } // TODO - else if (target.cpu.arch.isPPC()) + else if (target.cpu.arch.isPowerPC()) .{ .unknown = {} } // TODO else if (target.cpu.arch == .ve) .{ .unknown = {} } // TODO diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 2f46ebd605..a876723302 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -264,7 +264,7 @@ pub fn systemCompiler(target: std.Target) LangOpts.Compiler { pub fn hasFloat128(target: std.Target) bool { if (target.cpu.arch.isWasm()) return true; if (target.isDarwin()) return false; - if (target.cpu.arch.isPPC() or target.cpu.arch.isPPC64()) return std.Target.powerpc.featureSetHas(target.cpu.features, .float128); + if (target.cpu.arch.isPowerPC()) return std.Target.powerpc.featureSetHas(target.cpu.features, .float128); return switch (target.os.tag) { .dragonfly, .haiku, diff --git a/lib/compiler_rt/common.zig b/lib/compiler_rt/common.zig index 5b3d0324b5..552fc07efd 100644 --- a/lib/compiler_rt/common.zig +++ b/lib/compiler_rt/common.zig @@ -22,7 +22,7 @@ pub const want_aeabi = switch (builtin.abi) { }, else => false, }; -pub const want_ppc_abi = builtin.cpu.arch.isPPC() or builtin.cpu.arch.isPPC64(); +pub const want_ppc_abi = builtin.cpu.arch.isPowerPC(); pub const want_float_exceptions = !builtin.cpu.arch.isWasm(); diff --git a/lib/std/Target.zig b/lib/std/Target.zig index d53ae65bfc..4d42ba674b 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1084,6 +1084,13 @@ pub const Cpu = struct { }; } + pub inline fn isLoongArch(arch: Arch) bool { + return switch (arch) { + .loongarch32, .loongarch64 => true, + else => false, + }; + } + pub inline fn isRISCV(arch: Arch) bool { return switch (arch) { .riscv32, .riscv64 => true, @@ -1092,20 +1099,35 @@ pub const Cpu = struct { } pub inline fn isMIPS(arch: Arch) bool { + return arch.isMIPS32() or arch.isMIPS64(); + } + + pub inline fn isMIPS32(arch: Arch) bool { return switch (arch) { - .mips, .mipsel, .mips64, .mips64el => true, + .mips, .mipsel => true, else => false, }; } - pub inline fn isPPC(arch: Arch) bool { + pub inline fn isMIPS64(arch: Arch) bool { + return switch (arch) { + .mips64, .mips64el => true, + else => false, + }; + } + + pub inline fn isPowerPC(arch: Arch) bool { + return arch.isPowerPC32() or arch.isPowerPC64(); + } + + pub inline fn isPowerPC32(arch: Arch) bool { return switch (arch) { .powerpc, .powerpcle => true, else => false, }; } - pub inline fn isPPC64(arch: Arch) bool { + pub inline fn isPowerPC64(arch: Arch) bool { return switch (arch) { .powerpc64, .powerpc64le => true, else => false, diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig index 198481c373..4e1dd8cda3 100644 --- a/lib/std/os/linux.zig +++ b/lib/std/os/linux.zig @@ -16,8 +16,7 @@ const native_arch = builtin.cpu.arch; const native_abi = builtin.abi; const native_endian = native_arch.endian(); const is_mips = native_arch.isMIPS(); -const is_ppc = native_arch.isPPC(); -const is_ppc64 = native_arch.isPPC64(); +const is_ppc = native_arch.isPowerPC(); const is_sparc = native_arch.isSPARC(); const iovec = std.posix.iovec; const iovec_const = std.posix.iovec_const; @@ -434,10 +433,9 @@ fn getauxvalImpl(index: usize) callconv(.C) usize { // Some architectures (and some syscalls) require 64bit parameters to be passed // in a even-aligned register pair. const require_aligned_register_pair = - builtin.cpu.arch.isPPC() or - builtin.cpu.arch.isMIPS() or - builtin.cpu.arch.isARM() or - builtin.cpu.arch.isThumb(); + builtin.cpu.arch.isPowerPC32() or + builtin.cpu.arch.isMIPS32() or + builtin.cpu.arch.isArmOrThumb(); // Split a 64bit value into a {LSB,MSB} pair. // The LE/BE variants specify the endianness to assume. @@ -2228,7 +2226,7 @@ pub fn process_vm_writev(pid: pid_t, local: []const iovec_const, remote: []const } pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize { - if (comptime native_arch.isARM() or native_arch.isPPC()) { + if (comptime native_arch.isArmOrThumb() or native_arch.isPowerPC32()) { // These architectures reorder the arguments so that a register is not skipped to align the // register number that `offset` is passed in. @@ -3575,7 +3573,7 @@ pub const SO = if (is_mips) struct { pub const RCVTIMEO_NEW = 66; pub const SNDTIMEO_NEW = 67; pub const DETACH_REUSEPORT_BPF = 68; -} else if (is_ppc or is_ppc64) struct { +} else if (is_ppc) struct { pub const DEBUG = 1; pub const REUSEADDR = 2; pub const TYPE = 3; @@ -4023,8 +4021,8 @@ pub const T = struct { pub const IOCSPGRP = if (is_mips) 0x741d else 0x5410; pub const IOCOUTQ = if (is_mips) 0x7472 else 0x5411; pub const IOCSTI = if (is_mips) 0x5472 else 0x5412; - pub const IOCGWINSZ = if (is_mips or is_ppc64) 0x40087468 else 0x5413; - pub const IOCSWINSZ = if (is_mips or is_ppc64) 0x80087467 else 0x5414; + pub const IOCGWINSZ = if (is_mips or is_ppc) 0x40087468 else 0x5413; + pub const IOCSWINSZ = if (is_mips or is_ppc) 0x80087467 else 0x5414; pub const IOCMGET = if (is_mips) 0x741d else 0x5415; pub const IOCMBIS = if (is_mips) 0x741b else 0x5416; pub const IOCMBIC = if (is_mips) 0x741c else 0x5417; diff --git a/lib/std/simd.zig b/lib/std/simd.zig index f5eef1cf97..236b9fbab8 100644 --- a/lib/std/simd.zig +++ b/lib/std/simd.zig @@ -18,7 +18,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu) if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256; if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128; if (std.Target.x86.featureSetHasAny(cpu.features, .{ .mmx, .@"3dnow" })) break :blk 64; - } else if (cpu.arch.isARM()) { + } else if (cpu.arch.isArmOrThumb()) { if (std.Target.arm.featureSetHas(cpu.features, .neon)) break :blk 128; } else if (cpu.arch.isAARCH64()) { // SVE allows up to 2048 bits in the specification, as of 2022 the most powerful machine has implemented 512-bit @@ -26,7 +26,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu) // TODO: Check on this return when bigger values are more common if (std.Target.aarch64.featureSetHas(cpu.features, .sve)) break :blk 128; if (std.Target.aarch64.featureSetHas(cpu.features, .neon)) break :blk 128; - } else if (cpu.arch.isPPC() or cpu.arch.isPPC64()) { + } else if (cpu.arch.isPowerPC()) { if (std.Target.powerpc.featureSetHas(cpu.features, .altivec)) break :blk 128; } else if (cpu.arch.isMIPS()) { if (std.Target.mips.featureSetHas(cpu.features, .msa)) break :blk 128; diff --git a/lib/std/start.zig b/lib/std/start.zig index fd8661660b..c975c888af 100644 --- a/lib/std/start.zig +++ b/lib/std/start.zig @@ -495,7 +495,7 @@ fn posixCallMainAndExit(argc_argv_ptr: [*]usize) callconv(.C) noreturn { // ARMv6 targets (and earlier) have no support for TLS in hardware. // FIXME: Elide the check for targets >= ARMv7 when the target feature API // becomes less verbose (and more usable). - if (comptime native_arch.isARM()) { + if (comptime native_arch.isArmOrThumb()) { if (at_hwcap & std.os.linux.HWCAP.TLS == 0) { // FIXME: Make __aeabi_read_tp call the kernel helper kuser_get_tls // For the time being use a simple trap instead of a @panic call to diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 23e39caa98..1ba1ed8b6f 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -399,7 +399,7 @@ const DataLayoutBuilder = struct { else if (self.target.cpu.arch == .powerpc64 and self.target.os.tag != .freebsd and self.target.abi != .musl) try writer.writeAll("-Fi64") - else if (self.target.cpu.arch.isPPC() or self.target.cpu.arch.isPPC64()) + else if (self.target.cpu.arch.isPowerPC()) try writer.writeAll("-Fn32"); if (self.target.cpu.arch != .hexagon) { if (self.target.cpu.arch == .arc or self.target.cpu.arch == .s390x) @@ -659,7 +659,7 @@ const DataLayoutBuilder = struct { 128 => abi = 64, else => {}, } - } else if ((self.target.cpu.arch.isPPC64() and self.target.os.tag == .linux and + } else if ((self.target.cpu.arch.isPowerPC64() and self.target.os.tag == .linux and (size == 256 or size == 512)) or (self.target.cpu.arch.isNvptx() and (size == 16 or size == 32))) { diff --git a/src/glibc.zig b/src/glibc.zig index 5214d0a977..b218b98fd8 100644 --- a/src/glibc.zig +++ b/src/glibc.zig @@ -392,9 +392,9 @@ pub fn buildCRTFile(comp: *Compilation, crt_file: CRTFile, prog_node: std.Progre fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![]const u8 { const arch = comp.getTarget().cpu.arch; - const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le; - const is_aarch64 = arch == .aarch64 or arch == .aarch64_be; - const is_sparc = arch == .sparc or arch == .sparc64; + const is_ppc = arch.isPowerPC(); + const is_aarch64 = arch.isAARCH64(); + const is_sparc = arch.isSPARC(); const is_64 = comp.getTarget().ptrBitWidth() == 64; const s = path.sep_str; @@ -412,7 +412,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![ try result.appendSlice("sparc" ++ s ++ "sparc32"); } } - } else if (arch.isARM()) { + } else if (arch.isArmOrThumb()) { try result.appendSlice("arm"); } else if (arch.isMIPS()) { if (!mem.eql(u8, basename, "crti.S") and !mem.eql(u8, basename, "crtn.S")) { @@ -529,10 +529,10 @@ fn add_include_dirs_arch( dir: []const u8, ) error{OutOfMemory}!void { const arch = target.cpu.arch; - const is_x86 = arch == .x86 or arch == .x86_64; - const is_aarch64 = arch == .aarch64 or arch == .aarch64_be; - const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le; - const is_sparc = arch == .sparc or arch == .sparc64; + const is_x86 = arch.isX86(); + const is_aarch64 = arch.isAARCH64(); + const is_ppc = arch.isPowerPC(); + const is_sparc = arch.isSPARC(); const is_64 = target.ptrBitWidth() == 64; const s = path.sep_str; @@ -562,7 +562,7 @@ fn add_include_dirs_arch( try args.append("-I"); try args.append(try path.join(arena, &[_][]const u8{ dir, "x86" })); } - } else if (arch.isARM()) { + } else if (arch.isArmOrThumb()) { if (opt_nptl) |nptl| { try args.append("-I"); try args.append(try path.join(arena, &[_][]const u8{ dir, "arm", nptl })); diff --git a/src/libunwind.zig b/src/libunwind.zig index 7783876827..dd2ed39130 100644 --- a/src/libunwind.zig +++ b/src/libunwind.zig @@ -131,7 +131,7 @@ pub fn buildStaticLib(comp: *Compilation, prog_node: std.Progress.Node) BuildErr if (!comp.config.any_non_single_threaded) { try cflags.append("-D_LIBUNWIND_HAS_NO_THREADS"); } - if (target.cpu.arch.isARM() and target.abi.floatAbi() == .hard) { + if (target.cpu.arch.isArmOrThumb() and target.abi.floatAbi() == .hard) { try cflags.append("-DCOMPILER_RT_ARMHF_TARGET"); } try cflags.append("-Wno-bitwise-conditional-parentheses"); diff --git a/test/behavior/union.zig b/test/behavior/union.zig index b1c36c42cc..f5cd61f6f4 100644 --- a/test/behavior/union.zig +++ b/test/behavior/union.zig @@ -1903,7 +1903,7 @@ test "reinterpret packed union" { try comptime S.doTheTest(); if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; // TODO + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; // TODO if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; // TODO try S.doTheTest(); } diff --git a/test/c_abi/main.zig b/test/c_abi/main.zig index 2bc93cc89e..86b9584a6e 100644 --- a/test/c_abi/main.zig +++ b/test/c_abi/main.zig @@ -11,7 +11,7 @@ const print = std.debug.print; const expect = std.testing.expect; const expectEqual = std.testing.expectEqual; const have_i128 = builtin.cpu.arch != .x86 and !builtin.cpu.arch.isARM() and - !builtin.cpu.arch.isMIPS() and !builtin.cpu.arch.isPPC(); + !builtin.cpu.arch.isMIPS() and !builtin.cpu.arch.isPowerPC32(); const have_f128 = builtin.cpu.arch.isX86() and !builtin.os.tag.isDarwin(); const have_f80 = builtin.cpu.arch.isX86(); @@ -123,8 +123,7 @@ test "C ABI floats" { } test "C ABI long double" { - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; c_long_double(12.34); } @@ -182,7 +181,7 @@ extern fn c_cmultf(a: ComplexFloat, b: ComplexFloat) ComplexFloat; extern fn c_cmultd(a: ComplexDouble, b: ComplexDouble) ComplexDouble; const complex_abi_compatible = builtin.cpu.arch != .x86 and !builtin.cpu.arch.isMIPS() and - !builtin.cpu.arch.isARM() and !builtin.cpu.arch.isPPC() and !builtin.cpu.arch.isRISCV(); + !builtin.cpu.arch.isARM() and !builtin.cpu.arch.isPowerPC32() and !builtin.cpu.arch.isRISCV(); test "C ABI complex float" { if (!complex_abi_compatible) return error.SkipZigTest; @@ -324,7 +323,7 @@ extern fn c_struct_u64_u64_8(usize, usize, usize, usize, usize, usize, usize, us test "C ABI struct u64 u64" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const s = c_ret_struct_u64_u64(); try expect(s.a == 21); @@ -361,7 +360,7 @@ extern fn c_struct_f32f32_f32(Struct_f32f32_f32) void; test "C ABI struct {f32,f32} f32" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const s = c_ret_struct_f32f32_f32(); try expect(s.a.b == 1.0); @@ -391,7 +390,7 @@ extern fn c_struct_f32_f32f32(Struct_f32_f32f32) void; test "C ABI struct f32 {f32,f32}" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const s = c_ret_struct_f32_f32f32(); try expect(s.a == 1.0); @@ -426,8 +425,7 @@ extern fn c_struct_u32_union_u32_u32u32(Struct_u32_Union_u32_u32u32) void; test "C ABI struct{u32,union{u32,struct{u32,u32}}}" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const s = c_ret_struct_u32_union_u32_u32u32(); try expect(s.a == 1); @@ -447,7 +445,7 @@ extern fn c_big_struct(BigStruct) void; test "C ABI big struct" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const s = BigStruct{ .a = 1, @@ -473,7 +471,7 @@ const BigUnion = extern union { extern fn c_big_union(BigUnion) void; test "C ABI big union" { - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const x = BigUnion{ .a = BigStruct{ @@ -506,8 +504,7 @@ extern fn c_ret_med_struct_mixed() MedStructMixed; test "C ABI medium struct of ints and floats" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const s = MedStructMixed{ .a = 1234, @@ -539,8 +536,7 @@ extern fn c_ret_small_struct_ints() SmallStructInts; test "C ABI small struct of ints" { if (builtin.cpu.arch == .x86) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const s = SmallStructInts{ .a = 1, @@ -573,8 +569,7 @@ extern fn c_ret_med_struct_ints() MedStructInts; test "C ABI medium struct of ints" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const s = MedStructInts{ .x = 1, @@ -652,8 +647,7 @@ extern fn c_split_struct_ints(SplitStructInt) void; test "C ABI split struct of ints" { if (builtin.cpu.arch == .x86) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const s = SplitStructInt{ .a = 1234, @@ -680,8 +674,7 @@ extern fn c_ret_split_struct_mixed() SplitStructMixed; test "C ABI split struct of ints and floats" { if (builtin.cpu.arch == .x86) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const s = SplitStructMixed{ .a = 1234, @@ -708,7 +701,7 @@ extern fn c_multiple_struct_floats(FloatRect, FloatRect) void; test "C ABI sret and byval together" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const s = BigStruct{ .a = 1, @@ -760,8 +753,7 @@ extern fn c_big_struct_floats(Vector5) void; test "C ABI structs of floats as parameter" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const v3 = Vector3{ .x = 3.0, @@ -800,8 +792,7 @@ export fn zig_multiple_struct_ints(x: Rect, y: Rect) void { } test "C ABI structs of ints as multiple parameters" { - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const r1 = Rect{ .left = 1, @@ -838,7 +829,7 @@ export fn zig_multiple_struct_floats(x: FloatRect, y: FloatRect) void { test "C ABI structs of floats as multiple parameters" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const r1 = FloatRect{ .left = 1, @@ -951,8 +942,7 @@ extern fn c_ret_struct_with_array() StructWithArray; test "Struct with array as padding." { if (builtin.cpu.arch == .x86) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; c_struct_with_array(.{ .a = 1, .padding = undefined, .b = 2 }); @@ -977,7 +967,7 @@ extern fn c_ret_float_array_struct() FloatArrayStruct; test "Float array like struct" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; c_float_array_struct(.{ .origin = .{ @@ -1004,7 +994,7 @@ extern fn c_ret_small_vec() SmallVec; test "small simd vector" { if (builtin.cpu.arch == .x86) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; c_small_vec(.{ 1, 2 }); @@ -1022,7 +1012,7 @@ test "medium simd vector" { if (builtin.zig_backend == .stage2_x86_64 and !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .avx)) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; c_medium_vec(.{ 1, 2, 3, 4 }); @@ -1042,7 +1032,7 @@ test "big simd vector" { if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest; if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and builtin.os.tag == .macos and builtin.mode != .Debug) return error.SkipZigTest; c_big_vec(.{ 1, 2, 3, 4, 5, 6, 7, 8 }); @@ -5352,7 +5342,7 @@ extern fn c_ret_ptr_size_float_struct() Vector2; test "C ABI pointer sized float struct" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; c_ptr_size_float_struct(.{ .x = 1, .y = 2 }); @@ -5374,29 +5364,25 @@ const DC = extern struct { v1: f64, v2: u8 }; test "DC: Zig passes to C" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_assert_DC(.{ .v1 = -0.25, .v2 = 15 })); } test "DC: Zig returns to C" { if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest; if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_assert_ret_DC()); } test "DC: C passes to Zig" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_send_DC()); } test "DC: C returns to Zig" { if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest; if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectEqual(DC{ .v1 = -0.25, .v2 = 15 }, c_ret_DC()); } @@ -5421,14 +5407,12 @@ const CFF = extern struct { v1: u8, v2: f32, v3: f32 }; test "CFF: Zig passes to C" { if (builtin.target.cpu.arch == .x86) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_assert_CFF(.{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 })); } test "CFF: Zig returns to C" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_assert_ret_CFF()); } test "CFF: C passes to Zig" { @@ -5436,8 +5420,7 @@ test "CFF: C passes to Zig" { if (builtin.cpu.arch.isRISCV() and builtin.mode != .Debug) return error.SkipZigTest; if (builtin.cpu.arch == .aarch64 and builtin.mode != .Debug) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_send_CFF()); } @@ -5445,8 +5428,7 @@ test "CFF: C returns to Zig" { if (builtin.cpu.arch == .aarch64 and builtin.mode != .Debug) return error.SkipZigTest; if (builtin.cpu.arch.isRISCV() and builtin.mode != .Debug) return error.SkipZigTest; if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectEqual(CFF{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }, c_ret_CFF()); } pub extern fn c_assert_CFF(lv: CFF) c_int; @@ -5470,26 +5452,22 @@ const PD = extern struct { v1: ?*anyopaque, v2: f64 }; test "PD: Zig passes to C" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_assert_PD(.{ .v1 = null, .v2 = 0.5 })); } test "PD: Zig returns to C" { if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_assert_ret_PD()); } test "PD: C passes to Zig" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectOk(c_send_PD()); } test "PD: C returns to Zig" { if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; try expectEqual(PD{ .v1 = null, .v2 = 0.5 }, c_ret_PD()); } pub extern fn c_assert_PD(lv: PD) c_int; @@ -5521,7 +5499,7 @@ const ByRef = extern struct { extern fn c_modify_by_ref_param(ByRef) ByRef; test "C function modifies by ref param" { - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const res = c_modify_by_ref_param(.{ .val = 1, .arr = undefined }); try expect(res.val == 42); @@ -5543,7 +5521,7 @@ const ByVal = extern struct { extern fn c_func_ptr_byval(*anyopaque, *anyopaque, ByVal, c_ulong, *anyopaque, c_ulong) void; test "C function that takes byval struct called via function pointer" { if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; var fn_ptr = &c_func_ptr_byval; _ = &fn_ptr; @@ -5574,8 +5552,7 @@ const f16_struct = extern struct { extern fn c_f16_struct(f16_struct) f16_struct; test "f16 struct" { if (builtin.target.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.target.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.target.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.target.cpu.arch.isPowerPC32()) return error.SkipZigTest; if (builtin.cpu.arch.isARM() and builtin.mode != .Debug) return error.SkipZigTest; const a = c_f16_struct(.{ .a = 12 }); @@ -5690,8 +5667,7 @@ const Coord2 = extern struct { extern fn stdcall_coord2(Coord2, Coord2, Coord2) callconv(stdcall_callconv) Coord2; test "Stdcall ABI structs" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; const res = stdcall_coord2( .{ .x = 0x1111, .y = 0x2222 }, @@ -5704,7 +5680,7 @@ test "Stdcall ABI structs" { extern fn stdcall_big_union(BigUnion) callconv(stdcall_callconv) void; test "Stdcall ABI big union" { - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; const x = BigUnion{ .a = BigStruct{ @@ -5776,7 +5752,7 @@ const byval_tail_callsite_attr = struct { test "byval tail callsite attribute" { if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; - if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; + if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; // Originally reported at https://github.com/ziglang/zig/issues/16290 // the bug was that the extern function had the byval attribute, but