From af8205e25ee1781e3747246a45e8c30b65486ab3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 23 Jun 2024 17:44:56 +0200 Subject: [PATCH] std.Target: Remove `nacl` OS specifier and `le32`/`le64` arch specifiers. Native Client is dead. https://developer.chrome.com/docs/native-client --- lib/compiler/aro/aro/target.zig | 8 -------- lib/std/Target.zig | 23 ----------------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 8 -------- src/target.zig | 2 -- 6 files changed, 45 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 826c0c6a25..807bbcd20f 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -39,7 +39,6 @@ pub fn intMaxType(target: std.Target) Type { pub fn intPtrType(target: std.Target) Type { switch (target.os.tag) { .haiku => return .{ .specifier = .long }, - .nacl => return .{ .specifier = .int }, else => {}, } @@ -467,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .csky, .hexagon, .m68k, - .le32, .mips, .mipsel, .powerpc, @@ -500,7 +498,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .aarch64 => copy.cpu.arch = .arm, .aarch64_be => copy.cpu.arch = .armeb, - .le64 => copy.cpu.arch = .le32, .amdil64 => copy.cpu.arch = .amdil, .nvptx64 => copy.cpu.arch = .nvptx, .wasm64 => copy.cpu.arch = .wasm32, @@ -547,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .amdgcn, .bpfeb, .bpfel, - .le64, .amdil64, .nvptx64, .wasm64, @@ -572,7 +568,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .arm => copy.cpu.arch = .aarch64, .armeb => copy.cpu.arch = .aarch64_be, .hsail => copy.cpu.arch = .hsail64, - .le32 => copy.cpu.arch = .le64, .loongarch32 => copy.cpu.arch = .loongarch64, .mips => copy.cpu.arch = .mips64, .mipsel => copy.cpu.arch = .mips64el, @@ -643,8 +638,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .le32 => "le32", - .le64 => "le64", .amdil => "amdil", .amdil64 => "amdil64", .hsail => "hsail", @@ -685,7 +678,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .haiku => "haiku", .minix => "minix", .rtems => "rtems", - .nacl => "nacl", .aix => "aix", .cuda => "cuda", .nvcl => "nvcl", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index d29a036d0c..30daa57071 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -35,7 +35,6 @@ pub const Os = struct { haiku, minix, rtems, - nacl, aix, cuda, nvcl, @@ -144,7 +143,6 @@ pub const Os = struct { .haiku, .minix, .rtems, - .nacl, .aix, .cuda, .nvcl, @@ -377,7 +375,6 @@ pub const Os = struct { .haiku, .minix, .rtems, - .nacl, .aix, .cuda, .nvcl, @@ -564,7 +561,6 @@ pub const Os = struct { .zos, .minix, .rtems, - .nacl, .aix, .cuda, .nvcl, @@ -668,7 +664,6 @@ pub const Abi = enum { .zos, .minix, .rtems, - .nacl, .aix, .cuda, .nvcl, @@ -1018,8 +1013,6 @@ pub const Cpu = struct { xtensa, nvptx, nvptx64, - le32, - le64, amdil, amdil64, hsail, @@ -1153,7 +1146,6 @@ pub const Cpu = struct { .hexagon => .HEXAGON, .dxil => .NONE, .m68k => .@"68K", - .le32 => .NONE, .mips => .MIPS, .mipsel => .MIPS_RS3_LE, .powerpc, .powerpcle => .PPC, @@ -1187,7 +1179,6 @@ pub const Cpu = struct { .riscv64 => .RISCV, .x86_64 => .X86_64, .nvptx64 => .NONE, - .le64 => .NONE, .amdil64 => .NONE, .hsail64 => .NONE, .spir64 => .NONE, @@ -1219,7 +1210,6 @@ pub const Cpu = struct { .dxil => .Unknown, .hexagon => .Unknown, .m68k => .Unknown, - .le32 => .Unknown, .mips => .Unknown, .mipsel => .Unknown, .powerpc, .powerpcle => .POWERPC, @@ -1253,7 +1243,6 @@ pub const Cpu = struct { .riscv64 => .RISCV64, .x86_64 => .X64, .nvptx64 => .Unknown, - .le64 => .Unknown, .amdil64 => .Unknown, .hsail64 => .Unknown, .spir64 => .Unknown, @@ -1291,8 +1280,6 @@ pub const Cpu = struct { .hsail, .hsail64, .kalimba, - .le32, - .le64, .mipsel, .mips64el, .msp430, @@ -1799,8 +1786,6 @@ pub const DynamicLinker = struct { .tce, .tcele, .xcore, - .le32, - .le64, .amdil, .amdil64, .hsail, @@ -1854,7 +1839,6 @@ pub const DynamicLinker = struct { .zos, .minix, .rtems, - .nacl, .aix, .cuda, .nvcl, @@ -1897,7 +1881,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .csky, .hexagon, .m68k, - .le32, .mips, .mipsel, .powerpc, @@ -1936,7 +1919,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .riscv64, .x86_64, .nvptx64, - .le64, .amdil64, .hsail64, .spir64, @@ -2372,7 +2354,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .lv2, .zos, .rtems, - .nacl, .aix, .elfiamcu, .mesa3d, @@ -2439,7 +2420,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .le32, .amdil, .hsail, .spir, @@ -2467,7 +2447,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .sparcel, .sparc64, .lanai, - .le64, .nvptx, .nvptx64, .r600, @@ -2560,7 +2539,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .le32, .amdil, .hsail, .spir, @@ -2595,7 +2573,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .sparcel, .sparc64, .lanai, - .le64, .nvptx, .nvptx64, .r600, diff --git a/src/Type.zig b/src/Type.zig index 825cc2dc5b..6ccd2841a6 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1651,7 +1651,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .m68k, .tce, .tcele, - .le32, .amdil, .hsail, .spir, @@ -1660,7 +1659,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .spirv, .spirv32, .shave, - .le64, .amdil64, .hsail64, .spir64, diff --git a/src/Zcu.zig b/src/Zcu.zig index dbc2e5a2c4..2e44c53884 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3243,7 +3243,6 @@ pub fn atomicPtrAlignment( .armeb, .hexagon, .m68k, - .le32, .mips, .mipsel, .nvptx, @@ -3277,7 +3276,6 @@ pub fn atomicPtrAlignment( .amdgcn, .bpfel, .bpfeb, - .le64, .mips64, .mips64el, .nvptx64, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 0ca154a07a..7ec9de4a10 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .le32 => "le32", - .le64 => "le64", .amdil => "amdil", .amdil64 => "amdil64", .hsail => "hsail", @@ -120,7 +118,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .zos => "zos", .haiku => "haiku", .rtems => "rtems", - .nacl => "nacl", .aix => "aix", .cuda => "cuda", .nvcl => "nvcl", @@ -242,7 +239,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType { .zos => .ZOS, .haiku => .Haiku, .rtems => .RTEMS, - .nacl => .NaCl, .aix => .AIX, .cuda => .CUDA, .nvcl => .NVCL, @@ -311,8 +307,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .xtensa => .xtensa, .nvptx => .nvptx, .nvptx64 => .nvptx64, - .le32 => .le32, - .le64 => .le64, .amdil => .amdil, .amdil64 => .amdil64, .hsail => .hsail, @@ -12098,8 +12092,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { .tce, .tcele, .r600, - .le32, - .le64, .amdil, .amdil64, .hsail, diff --git a/src/target.zig b/src/target.zig index b80a4977c3..23f7b285de 100644 --- a/src/target.zig +++ b/src/target.zig @@ -153,8 +153,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .xtensa, .nvptx, .nvptx64, - .le32, - .le64, .amdil, .amdil64, .hsail,