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https://github.com/ziglang/zig.git
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x64: make genBinOp operate on MCValues directly
This commit is contained in:
Jakub Konka
parent
252c5a2339
commit
af3ecd04b4
@ -1089,8 +1089,15 @@ fn airBoolToInt(self: *Self, inst: Air.Inst.Index) !void {
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fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand = try self.resolveInst(ty_op.operand);
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if (self.liveness.isUnused(inst)) {
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return self.finishAir(inst, .dead, .{ ty_op.operand, .none, .none });
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}
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const operand_ty = self.air.typeOf(ty_op.operand);
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const operand = try self.resolveInst(ty_op.operand);
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const result: MCValue = result: {
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switch (operand) {
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.dead => unreachable,
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.unreach => unreachable,
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@ -1122,7 +1129,28 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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},
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else => {},
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}
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break :result try self.genBinOp(.not, inst, ty_op.operand, .bool_true);
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const operand_lock: ?RegisterLock = switch (operand) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (operand_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_mcv: MCValue = blk: {
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if (self.reuseOperand(inst, ty_op.operand, 0, operand) and operand.isRegister()) {
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break :blk operand;
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}
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break :blk try self.copyToRegisterWithInstTracking(inst, operand_ty, operand);
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};
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const dst_mcv_lock: ?RegisterLock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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};
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defer if (dst_mcv_lock) |lock| self.register_manager.unlockReg(lock);
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try self.genBinOpMir(.xor, operand_ty, dst_mcv, .{ .immediate = 1 });
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break :result dst_mcv;
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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@ -1214,7 +1242,13 @@ fn airBinOp(self: *Self, inst: Air.Inst.Index) !void {
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}
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const tag = self.air.instructions.items(.tag)[inst];
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const result = try self.genBinOp(tag, inst, bin_op.lhs, bin_op.rhs);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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const rhs_ty = self.air.typeOf(bin_op.rhs);
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const result = try self.genBinOp(tag, inst, lhs, rhs, lhs_ty, rhs_ty);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1263,7 +1297,10 @@ fn airAddWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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const partial = try self.genBinOp(.add, inst, bin_op.lhs, bin_op.rhs);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const partial = try self.genBinOp(.add, null, lhs, rhs, ty, ty);
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const result: MCValue = switch (int_info.signedness) {
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.signed => .{ .register_overflow_signed = partial.register },
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.unsigned => .{ .register_overflow_unsigned = partial.register },
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@ -1295,7 +1332,10 @@ fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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const partial = try self.genBinOp(.sub, inst, bin_op.lhs, bin_op.rhs);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const partial = try self.genBinOp(.sub, null, lhs, rhs, ty, ty);
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const result: MCValue = switch (int_info.signedness) {
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.signed => .{ .register_overflow_signed = partial.register },
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.unsigned => .{ .register_overflow_unsigned = partial.register },
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@ -1330,9 +1370,12 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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try self.spillCompareFlagsIfOccupied();
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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if (math.isPowerOfTwo(int_info.bits)) {
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self.compare_flags_inst = inst;
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const partial = try self.genBinOp(.mul, inst, bin_op.lhs, bin_op.rhs);
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const partial = try self.genBinOp(.mul, null, lhs, rhs, ty, ty);
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break :result switch (int_info.signedness) {
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.signed => MCValue{ .register_overflow_signed = partial.register },
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.unsigned => MCValue{ .register_overflow_unsigned = partial.register },
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@ -1344,9 +1387,6 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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const dst_reg: Register = dst_reg: {
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switch (int_info.signedness) {
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.signed => {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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@ -1375,7 +1415,7 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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break :dst_reg dst_reg;
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},
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.unsigned => {
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const dst_mcv = try self.genBinOp(.mul, null, bin_op.lhs, bin_op.rhs);
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const dst_mcv = try self.genBinOp(.mul, null, lhs, rhs, ty, ty);
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break :dst_reg dst_mcv.register;
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},
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}
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@ -3137,8 +3177,10 @@ fn genBinOp(
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self: *Self,
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tag: Air.Inst.Tag,
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maybe_inst: ?Air.Inst.Index,
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op_lhs: Air.Inst.Ref,
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op_rhs: Air.Inst.Ref,
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lhs: MCValue,
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rhs: MCValue,
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lhs_ty: Type,
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rhs_ty: Type,
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) !MCValue {
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const is_commutative: bool = switch (tag) {
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.add,
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@ -3148,7 +3190,6 @@ fn genBinOp(
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.bool_and,
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.bit_and,
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.xor,
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.not,
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=> true,
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.sub,
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@ -3169,14 +3210,12 @@ fn genBinOp(
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else => unreachable,
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};
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const dst_ty = self.air.typeOf(op_lhs);
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const src_ty = self.air.typeOf(op_rhs);
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if (dst_ty.zigTypeTag() == .Vector or dst_ty.zigTypeTag() == .Float) {
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return self.fail("TODO implement genBinOp for {}", .{dst_ty.fmtDebug()});
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if (lhs_ty.zigTypeTag() == .Vector or lhs_ty.zigTypeTag() == .Float) {
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return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
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}
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if (dst_ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genBinOp for {}", .{dst_ty.fmtDebug()});
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if (lhs_ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
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}
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switch (tag) {
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@ -3191,24 +3230,21 @@ fn genBinOp(
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self.register_manager.unlockReg(reg);
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};
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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const int_info = dst_ty.intInfo(self.target.*);
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const int_info = lhs_ty.intInfo(self.target.*);
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try self.genIntMulDivOpMir(switch (int_info.signedness) {
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.signed => .imul,
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.unsigned => .mul,
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}, dst_ty, int_info.signedness, lhs, rhs);
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}, lhs_ty, int_info.signedness, lhs, rhs);
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return switch (int_info.signedness) {
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.signed => MCValue{ .register = .rax },
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.unsigned => MCValue{ .register = registerAlias(.rax, @intCast(u32, dst_ty.abiSize(self.target.*))) },
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.unsigned => MCValue{ .register = registerAlias(.rax, @intCast(u32, lhs_ty.abiSize(self.target.*))) },
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};
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},
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.mod,
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.rem,
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=> {
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const int_info = dst_ty.intInfo(self.target.*);
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const int_info = lhs_ty.intInfo(self.target.*);
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const track_inst_rdx: ?Air.Inst.Index = switch (tag) {
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.mod => if (int_info.signedness == .unsigned) maybe_inst else null,
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.rem => maybe_inst,
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@ -3223,27 +3259,24 @@ fn genBinOp(
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self.register_manager.unlockReg(reg);
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};
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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switch (int_info.signedness) {
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.signed => {
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switch (tag) {
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.rem => {
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try self.genIntMulDivOpMir(.idiv, dst_ty, .signed, lhs, rhs);
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try self.genIntMulDivOpMir(.idiv, lhs_ty, .signed, lhs, rhs);
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return MCValue{ .register = .rdx };
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},
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.mod => {
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const div_floor = try self.genInlineIntDivFloor(dst_ty, lhs, rhs);
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try self.genIntMulComplexOpMir(dst_ty, div_floor, rhs);
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const div_floor = try self.genInlineIntDivFloor(lhs_ty, lhs, rhs);
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try self.genIntMulComplexOpMir(lhs_ty, div_floor, rhs);
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const div_floor_lock = self.register_manager.lockReg(div_floor.register);
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defer if (div_floor_lock) |lock| self.register_manager.unlockReg(lock);
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const result: MCValue = if (maybe_inst) |inst|
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try self.copyToRegisterWithInstTracking(inst, dst_ty, lhs)
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try self.copyToRegisterWithInstTracking(inst, lhs_ty, lhs)
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else
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MCValue{ .register = try self.copyToTmpRegister(dst_ty, lhs) };
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try self.genBinOpMir(.sub, dst_ty, result, div_floor);
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MCValue{ .register = try self.copyToTmpRegister(lhs_ty, lhs) };
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try self.genBinOpMir(.sub, lhs_ty, result, div_floor);
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return result;
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},
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@ -3251,7 +3284,7 @@ fn genBinOp(
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}
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},
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.unsigned => {
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try self.genIntMulDivOpMir(.div, dst_ty, .unsigned, lhs, rhs);
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try self.genIntMulDivOpMir(.div, lhs_ty, .unsigned, lhs, rhs);
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return MCValue{ .register = .rdx };
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},
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}
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@ -3259,14 +3292,12 @@ fn genBinOp(
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else => {},
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}
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const lhs = try self.resolveInst(op_lhs);
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs = try self.resolveInst(op_rhs);
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const rhs_lock: ?RegisterLock = switch (rhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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@ -3276,16 +3307,17 @@ fn genBinOp(
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var flipped: bool = false;
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const dst_mcv: MCValue = blk: {
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if (maybe_inst) |inst| {
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if (self.reuseOperand(inst, op_lhs, 0, lhs) and lhs.isRegister()) {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.reuseOperand(inst, bin_op.lhs, 0, lhs) and lhs.isRegister()) {
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break :blk lhs;
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}
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if (is_commutative and self.reuseOperand(inst, op_rhs, 1, rhs) and rhs.isRegister()) {
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if (is_commutative and self.reuseOperand(inst, bin_op.rhs, 1, rhs) and rhs.isRegister()) {
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flipped = true;
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break :blk rhs;
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}
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break :blk try self.copyToRegisterWithInstTracking(inst, dst_ty, lhs);
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break :blk try self.copyToRegisterWithInstTracking(inst, lhs_ty, lhs);
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}
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break :blk MCValue{ .register = try self.copyToTmpRegister(dst_ty, lhs) };
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break :blk MCValue{ .register = try self.copyToTmpRegister(lhs_ty, lhs) };
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};
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const dst_mcv_lock: ?RegisterLock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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@ -3296,7 +3328,7 @@ fn genBinOp(
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const src_mcv: MCValue = blk: {
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const mcv = if (flipped) lhs else rhs;
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if (mcv.isRegister() or mcv.isMemory()) break :blk mcv;
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break :blk MCValue{ .register = try self.copyToTmpRegister(src_ty, mcv) };
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break :blk MCValue{ .register = try self.copyToTmpRegister(rhs_ty, mcv) };
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};
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const src_mcv_lock: ?RegisterLock = switch (src_mcv) {
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.register => |reg| self.register_manager.lockReg(reg),
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@ -3307,11 +3339,11 @@ fn genBinOp(
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switch (tag) {
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.add,
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.addwrap,
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=> try self.genBinOpMir(.add, dst_ty, dst_mcv, src_mcv),
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=> try self.genBinOpMir(.add, lhs_ty, dst_mcv, src_mcv),
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.sub,
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.subwrap,
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=> try self.genBinOpMir(.sub, dst_ty, dst_mcv, src_mcv),
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=> try self.genBinOpMir(.sub, lhs_ty, dst_mcv, src_mcv),
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.ptr_add,
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.ptr_sub,
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@ -3321,22 +3353,20 @@ fn genBinOp(
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.ptr_sub => .sub,
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else => unreachable,
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};
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const elem_size = dst_ty.elemType2().abiSize(self.target.*);
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try self.genIntMulComplexOpMir(src_ty, src_mcv, .{ .immediate = elem_size });
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try self.genBinOpMir(mir_tag, dst_ty, dst_mcv, src_mcv);
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const elem_size = lhs_ty.elemType2().abiSize(self.target.*);
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try self.genIntMulComplexOpMir(rhs_ty, src_mcv, .{ .immediate = elem_size });
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try self.genBinOpMir(mir_tag, lhs_ty, dst_mcv, src_mcv);
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},
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.bool_or,
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.bit_or,
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=> try self.genBinOpMir(.@"or", dst_ty, dst_mcv, src_mcv),
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=> try self.genBinOpMir(.@"or", lhs_ty, dst_mcv, src_mcv),
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.bool_and,
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.bit_and,
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=> try self.genBinOpMir(.@"and", dst_ty, dst_mcv, src_mcv),
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=> try self.genBinOpMir(.@"and", lhs_ty, dst_mcv, src_mcv),
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.xor,
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.not,
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=> try self.genBinOpMir(.xor, dst_ty, dst_mcv, src_mcv),
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.xor => try self.genBinOpMir(.xor, lhs_ty, dst_mcv, src_mcv),
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else => unreachable,
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}
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