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stage2 ARM: fix load and store for abi_size < 4
Previously, in these cases, we would emit the ldr instruction even though ldrb oder ldrh are the correct instructions.
This commit is contained in:
joachimschmidt557
Jakub Konka
parent
4468abfc42
commit
adc9a282d8
@ -647,11 +647,6 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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}
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}
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fn writeInt(self: *Self, comptime T: type, buf: *[@divExact(@typeInfo(T).Int.bits, 8)]u8, value: T) void {
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const endian = self.target.cpu.arch.endian();
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std.mem.writeInt(T, buf, value, endian);
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}
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/// Asserts there is already capacity to insert into top branch inst_table.
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fn processDeath(self: *Self, inst: Air.Inst.Index) void {
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const air_tags = self.air.instructions.items(.tag);
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@ -906,7 +901,7 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
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break :result r;
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},
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else => {
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break :result try self.genArmBinOp(inst, ty_op.operand, .bool_true, .not);
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break :result try self.genBinOp(inst, ty_op.operand, .bool_true, .not);
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},
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}
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};
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@ -934,7 +929,7 @@ fn airSlice(self: *Self, inst: Air.Inst.Index) !void {
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fn airAdd(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .add);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .add);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -952,7 +947,7 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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fn airSub(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .sub);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .sub);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -970,7 +965,7 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
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fn airMul(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmMul(inst, bin_op.lhs, bin_op.rhs);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genMul(inst, bin_op.lhs, bin_op.rhs);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1026,25 +1021,25 @@ fn airMod(self: *Self, inst: Air.Inst.Index) !void {
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fn airBitAnd(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_and);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_and);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airBitOr(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_or);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .bit_or);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airXor(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .xor);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .xor);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airShl(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .shl);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .shl);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1056,7 +1051,7 @@ fn airShlSat(self: *Self, inst: Air.Inst.Index) !void {
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fn airShr(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .shr);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .shr);
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -1296,7 +1291,7 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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else => {
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const dst_mcv = try self.allocRegOrMem(inst, true);
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const offset_mcv = try self.genArmMulConstant(bin_op.rhs, @intCast(u32, elem_size));
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const offset_mcv = try self.genMulConstant(bin_op.rhs, @intCast(u32, elem_size));
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assert(offset_mcv == .register); // result of multiplication should always be register
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self.register_manager.freezeRegs(&.{offset_mcv.register});
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@ -1304,7 +1299,7 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
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try self.genBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
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// At this point in time, neither the base register
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// nor the offset register contains any valuable data
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@ -1415,6 +1410,8 @@ fn reuseOperand(self: *Self, inst: Air.Inst.Index, operand: Air.Inst.Ref, op_ind
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fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!void {
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const elem_ty = ptr_ty.elemType();
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const elem_size = @intCast(u32, elem_ty.abiSize(self.target.*));
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switch (ptr) {
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.none => unreachable,
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.undef => unreachable,
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@ -1440,24 +1437,17 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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.compare_flags_signed, .compare_flags_unsigned => unreachable,
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.embedded_in_code => unreachable,
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.register => |dst_reg| {
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_ = try self.addInst(.{
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.tag = .ldr,
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.data = .{ .rr_offset = .{
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.rt = dst_reg,
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.rn = reg,
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.offset = .{ .offset = Instruction.Offset.none },
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} },
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});
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try self.genLdrRegister(dst_reg, reg, elem_size);
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},
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.stack_offset => |off| {
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if (elem_ty.abiSize(self.target.*) <= 4) {
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if (elem_size <= 4) {
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const tmp_reg = try self.register_manager.allocReg(null);
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self.register_manager.freezeRegs(&.{tmp_reg});
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defer self.register_manager.unfreezeRegs(&.{tmp_reg});
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try self.load(.{ .register = tmp_reg }, ptr, ptr_ty);
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try self.genSetStack(elem_ty, off, MCValue{ .register = tmp_reg });
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} else if (elem_ty.abiSize(self.target.*) == 8) {
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} else if (elem_size == 8) {
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// TODO generalize this: maybe add a
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// genArmMemcpy function which manually copies
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// data if the size is below a certain
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@ -1500,7 +1490,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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const tmp_reg = regs[3];
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// sub dst_reg, fp, #off
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const elem_size = @intCast(u32, elem_ty.abiSize(self.target.*));
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const adj_off = off + elem_size;
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const offset_op: Instruction.Operand = if (Instruction.Operand.fromU32(adj_off)) |x| x else {
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return self.fail("TODO load: set reg to stack offset with all possible offsets", .{});
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@ -1528,7 +1517,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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});
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// memcpy(src, dst, len)
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try self.genArmInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
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try self.genInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
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}
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},
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else => return self.fail("TODO load from register into {}", .{dst_mcv}),
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@ -1600,14 +1589,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
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switch (value) {
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.register => |value_reg| {
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_ = try self.addInst(.{
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.tag = .str,
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.data = .{ .rr_offset = .{
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.rt = value_reg,
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.rn = addr_reg,
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.offset = .{ .offset = Instruction.Offset.none },
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} },
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});
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try self.genStrRegister(value_reg, addr_reg, @intCast(u32, value_ty.abiSize(self.target.*)));
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},
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else => {
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if (value_ty.abiSize(self.target.*) <= 4) {
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@ -1723,7 +1705,7 @@ fn armOperandShouldBeRegister(self: *Self, mcv: MCValue) !bool {
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};
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}
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fn genArmBinOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref, op: Air.Inst.Tag) !MCValue {
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fn genBinOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref, op: Air.Inst.Tag) !MCValue {
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// In the case of bitshifts, the type of rhs is different
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// from the resulting type
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const ty = self.air.typeOf(op_lhs);
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@ -1732,17 +1714,17 @@ fn genArmBinOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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.Vector => return self.fail("TODO ARM binary operations on vectors", .{}),
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.Bool => {
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return self.genArmBinIntOp(inst, op_lhs, op_rhs, op, 1, .unsigned);
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return self.genBinIntOp(inst, op_lhs, op_rhs, op, 1, .unsigned);
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},
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.Int => {
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const int_info = ty.intInfo(self.target.*);
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return self.genArmBinIntOp(inst, op_lhs, op_rhs, op, int_info.bits, int_info.signedness);
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return self.genBinIntOp(inst, op_lhs, op_rhs, op, int_info.bits, int_info.signedness);
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},
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else => unreachable,
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}
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}
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fn genArmBinIntOp(
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fn genBinIntOp(
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self: *Self,
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inst: Air.Inst.Index,
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op_lhs: Air.Inst.Ref,
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@ -1852,7 +1834,7 @@ fn genArmBinIntOp(
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try self.genSetReg(self.air.typeOf(op_rhs), rhs_mcv.register, rhs);
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}
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try self.genArmBinOpCode(
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try self.genBinOpCode(
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dst_mcv.register,
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lhs_mcv,
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rhs_mcv,
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@ -1863,7 +1845,7 @@ fn genArmBinIntOp(
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return dst_mcv;
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}
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fn genArmBinOpCode(
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fn genBinOpCode(
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self: *Self,
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dst_reg: Register,
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lhs_mcv: MCValue,
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@ -1971,7 +1953,7 @@ fn genArmBinOpCode(
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}
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}
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fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref) !MCValue {
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fn genMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Air.Inst.Ref) !MCValue {
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const lhs = try self.resolveInst(op_lhs);
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const rhs = try self.resolveInst(op_rhs);
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@ -2050,7 +2032,7 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
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return dst_mcv;
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}
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fn genArmMulConstant(self: *Self, op: Air.Inst.Ref, imm: u32) !MCValue {
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fn genMulConstant(self: *Self, op: Air.Inst.Ref, imm: u32) !MCValue {
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const lhs = try self.resolveInst(op);
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const rhs = MCValue{ .immediate = imm };
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@ -2097,7 +2079,71 @@ fn genArmMulConstant(self: *Self, op: Air.Inst.Ref, imm: u32) !MCValue {
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return dst_mcv;
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}
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fn genArmInlineMemcpy(
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fn genLdrRegister(self: *Self, dest_reg: Register, addr_reg: Register, abi_size: u32) !void {
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switch (abi_size) {
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1, 3, 4 => {
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const tag: Mir.Inst.Tag = switch (abi_size) {
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1 => .ldrb,
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3, 4 => .ldr,
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = tag,
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.data = .{ .rr_offset = .{
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.rt = dest_reg,
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.rn = addr_reg,
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.offset = .{ .offset = Instruction.Offset.none },
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} },
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});
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},
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2 => {
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_ = try self.addInst(.{
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.tag = .ldrh,
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.data = .{ .rr_extra_offset = .{
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.rt = dest_reg,
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.rn = addr_reg,
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.offset = .{ .offset = Instruction.ExtraLoadStoreOffset.none },
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} },
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});
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},
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else => unreachable, // invalid abi_size for a register
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}
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}
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fn genStrRegister(self: *Self, source_reg: Register, addr_reg: Register, abi_size: u32) !void {
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switch (abi_size) {
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1, 3, 4 => {
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const tag: Mir.Inst.Tag = switch (abi_size) {
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1 => .strb,
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3, 4 => .str,
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = tag,
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.data = .{ .rr_offset = .{
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.rt = source_reg,
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.rn = addr_reg,
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.offset = .{ .offset = Instruction.Offset.none },
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} },
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});
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},
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2 => {
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_ = try self.addInst(.{
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.tag = .strh,
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.data = .{ .rr_extra_offset = .{
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.rt = source_reg,
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.rn = addr_reg,
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.offset = .{ .offset = Instruction.ExtraLoadStoreOffset.none },
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} },
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});
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},
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else => unreachable, // invalid abi_size for a register
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}
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}
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fn genInlineMemcpy(
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self: *Self,
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src: Register,
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dst: Register,
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@ -2469,7 +2515,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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// The destination register is not present in the cmp instruction
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// The signedness of the integer does not matter for the cmp instruction
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try self.genArmBinOpCode(undefined, lhs_mcv, rhs_mcv, false, .cmp_eq, undefined);
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try self.genBinOpCode(undefined, lhs_mcv, rhs_mcv, false, .cmp_eq, undefined);
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break :result switch (signedness) {
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.signed => MCValue{ .compare_flags_signed = op },
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@ -2701,7 +2747,7 @@ fn isNull(self: *Self, ty: Type, operand: MCValue) !MCValue {
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else => .{ .register = try self.copyToTmpRegister(ty, operand) },
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};
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try self.genArmBinOpCode(undefined, reg_mcv, .{ .immediate = 0 }, false, .cmp_eq, undefined);
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try self.genBinOpCode(undefined, reg_mcv, .{ .immediate = 0 }, false, .cmp_eq, undefined);
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return MCValue{ .compare_flags_unsigned = .eq };
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} else {
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@ -2731,7 +2777,7 @@ fn isErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
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else => .{ .register = try self.copyToTmpRegister(error_type, operand) },
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};
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try self.genArmBinOpCode(undefined, reg_mcv, .{ .immediate = 0 }, false, .cmp_eq, undefined);
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try self.genBinOpCode(undefined, reg_mcv, .{ .immediate = 0 }, false, .cmp_eq, undefined);
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return MCValue{ .compare_flags_unsigned = .gt };
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} else {
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@ -2946,8 +2992,8 @@ fn airBoolOp(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const air_tags = self.air.instructions.items(.tag);
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else switch (air_tags[inst]) {
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.bool_and => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bool_and),
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.bool_or => try self.genArmBinOp(inst, bin_op.lhs, bin_op.rhs, .bool_or),
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||||
.bool_and => try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .bool_and),
|
||||
.bool_or => try self.genBinOp(inst, bin_op.lhs, bin_op.rhs, .bool_or),
|
||||
else => unreachable, // Not a boolean operation
|
||||
};
|
||||
return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
|
||||
@ -3242,7 +3288,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
|
||||
});
|
||||
|
||||
// memcpy(src, dst, len)
|
||||
try self.genArmInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
|
||||
try self.genInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
|
||||
}
|
||||
},
|
||||
}
|
||||
@ -3439,14 +3485,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
|
||||
// The value is in memory at a hard-coded address.
|
||||
// If the type is a pointer, it means the pointer address is at this memory location.
|
||||
try self.genSetReg(ty, reg, .{ .immediate = @intCast(u32, addr) });
|
||||
_ = try self.addInst(.{
|
||||
.tag = .ldr,
|
||||
.data = .{ .rr_offset = .{
|
||||
.rt = reg,
|
||||
.rn = reg,
|
||||
.offset = .{ .offset = Instruction.Offset.none },
|
||||
} },
|
||||
});
|
||||
try self.genLdrRegister(reg, reg, @intCast(u32, ty.abiSize(self.target.*)));
|
||||
},
|
||||
.stack_offset => |unadjusted_off| {
|
||||
// TODO: maybe addressing from sp instead of fp
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user