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AstGen: fix elision of unnecessary dbg_stmt instructions
AstGen has logic to elide leading `dbg_stmt` instructions when multiple are emitted consecutively; however, it only applied in some cases. A simple reshuffle here makes this logic apply universally, saving some bytes in ZIR.
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@ -3332,31 +3332,11 @@ fn emitDbgNode(gz: *GenZir, node: Ast.Node.Index) !void {
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// If the current block will be evaluated only during semantic analysis
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// then no dbg_stmt ZIR instruction is needed.
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if (gz.is_comptime) return;
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const astgen = gz.astgen;
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astgen.advanceSourceCursorToNode(node);
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const line = astgen.source_line - gz.decl_line;
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const column = astgen.source_column;
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if (gz.instructions.items.len > 0) {
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const last = gz.instructions.items[gz.instructions.items.len - 1];
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const zir_tags = astgen.instructions.items(.tag);
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if (zir_tags[@intFromEnum(last)] == .dbg_stmt) {
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const zir_datas = astgen.instructions.items(.data);
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zir_datas[@intFromEnum(last)].dbg_stmt = .{
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.line = line,
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.column = column,
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};
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return;
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}
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}
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_ = try gz.add(.{ .tag = .dbg_stmt, .data = .{
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.dbg_stmt = .{
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.line = line,
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.column = column,
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},
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} });
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try emitDbgStmt(gz, .{ line, column });
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}
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fn assign(gz: *GenZir, scope: *Scope, infix_node: Ast.Node.Index) InnerError!void {
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@ -7143,7 +7123,7 @@ fn switchExprErrUnion(
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block_scope.setBreakResultInfo(block_ri);
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// Sema expects a dbg_stmt immediately before switch_block_err_union
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try emitDbgStmt(parent_gz, operand_lc);
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try emitDbgStmtForceCurrentIndex(parent_gz, operand_lc);
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// This gets added to the parent block later, after the item expressions.
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const switch_block = try parent_gz.makeBlockInst(.switch_block_err_union, switch_node);
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@ -7723,7 +7703,7 @@ fn switchExpr(
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block_scope.setBreakResultInfo(block_ri);
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// Sema expects a dbg_stmt immediately before switch_block(_ref)
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try emitDbgStmt(parent_gz, operand_lc);
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try emitDbgStmtForceCurrentIndex(parent_gz, operand_lc);
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// This gets added to the parent block later, after the item expressions.
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const switch_tag: Zir.Inst.Tag = if (any_payload_is_ref) .switch_block_ref else .switch_block;
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const switch_block = try parent_gz.makeBlockInst(switch_tag, switch_node);
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@ -9847,13 +9827,8 @@ fn callExpr(
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astgen.advanceSourceCursor(astgen.tree.tokens.items(.start)[call.ast.lparen]);
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const line = astgen.source_line - gz.decl_line;
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const column = astgen.source_column;
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_ = try gz.add(.{ .tag = .dbg_stmt, .data = .{
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.dbg_stmt = .{
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.line = line,
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.column = column,
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},
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} });
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// Sema expects a dbg_stmt immediately before call,
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try emitDbgStmtForceCurrentIndex(gz, .{ line, column });
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}
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switch (callee) {
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@ -13536,6 +13511,44 @@ fn countBodyLenAfterFixups(astgen: *AstGen, body: []const Zir.Inst.Index) u32 {
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fn emitDbgStmt(gz: *GenZir, lc: LineColumn) !void {
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if (gz.is_comptime) return;
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if (gz.instructions.items.len > 0) {
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const astgen = gz.astgen;
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const last = gz.instructions.items[gz.instructions.items.len - 1];
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if (astgen.instructions.items(.tag)[@intFromEnum(last)] == .dbg_stmt) {
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astgen.instructions.items(.data)[@intFromEnum(last)].dbg_stmt = .{
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.line = lc[0],
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.column = lc[1],
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};
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return;
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}
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}
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_ = try gz.add(.{ .tag = .dbg_stmt, .data = .{
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.dbg_stmt = .{
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.line = lc[0],
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.column = lc[1],
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},
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} });
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}
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/// In some cases, Sema expects us to generate a `dbg_stmt` at the instruction
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/// *index* directly preceding the next instruction (e.g. if a call is %10, it
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/// expects a dbg_stmt at %9). TODO: this logic may allow redundant dbg_stmt
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/// instructions; fix up Sema so we don't need it!
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fn emitDbgStmtForceCurrentIndex(gz: *GenZir, lc: LineColumn) !void {
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const astgen = gz.astgen;
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if (gz.instructions.items.len > 0 and
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@intFromEnum(gz.instructions.items[gz.instructions.items.len - 1]) == astgen.instructions.len - 1)
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{
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const last = astgen.instructions.len - 1;
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if (astgen.instructions.items(.tag)[last] == .dbg_stmt) {
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astgen.instructions.items(.data)[last].dbg_stmt = .{
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.line = lc[0],
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.column = lc[1],
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};
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return;
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}
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}
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_ = try gz.add(.{ .tag = .dbg_stmt, .data = .{
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.dbg_stmt = .{
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