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Merge pull request #15474 from Luukdegram/wasm-atomics
wasm: implement atomic instructions
This commit is contained in:
Andrew Kelley
GitHub
commit
aa3405aabc
@ -940,6 +940,20 @@ fn addMemArg(func: *CodeGen, tag: Mir.Inst.Tag, mem_arg: Mir.MemArg) error{OutOf
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try func.addInst(.{ .tag = tag, .data = .{ .payload = extra_index } });
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}
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/// Inserts an instruction from the 'atomics' feature which accesses wasm's linear memory dependent on the
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/// given `tag`.
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fn addAtomicMemArg(func: *CodeGen, tag: wasm.AtomicsOpcode, mem_arg: Mir.MemArg) error{OutOfMemory}!void {
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const extra_index = try func.addExtra(@as(struct { val: u32 }, .{ .val = wasm.atomicsOpcode(tag) }));
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_ = try func.addExtra(mem_arg);
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try func.addInst(.{ .tag = .atomics_prefix, .data = .{ .payload = extra_index } });
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}
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/// Helper function to emit atomic mir opcodes.
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fn addAtomicTag(func: *CodeGen, tag: wasm.AtomicsOpcode) error{OutOfMemory}!void {
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const extra_index = try func.addExtra(@as(struct { val: u32 }, .{ .val = wasm.atomicsOpcode(tag) }));
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try func.addInst(.{ .tag = .atomics_prefix, .data = .{ .payload = extra_index } });
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}
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/// Appends entries to `mir_extra` based on the type of `extra`.
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/// Returns the index into `mir_extra`
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fn addExtra(func: *CodeGen, extra: anytype) error{OutOfMemory}!u32 {
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@ -1958,15 +1972,6 @@ fn genInst(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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.is_err_ptr,
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.is_non_err_ptr,
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.cmpxchg_weak,
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.cmpxchg_strong,
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.fence,
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.atomic_load,
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.atomic_store_unordered,
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.atomic_store_monotonic,
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.atomic_store_release,
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.atomic_store_seq_cst,
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.atomic_rmw,
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.err_return_trace,
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.set_err_return_trace,
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.save_err_return_trace_index,
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@ -1979,6 +1984,18 @@ fn genInst(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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.c_va_start,
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=> |tag| return func.fail("TODO: Implement wasm inst: {s}", .{@tagName(tag)}),
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.atomic_load => func.airAtomicLoad(inst),
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.atomic_store_unordered,
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.atomic_store_monotonic,
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.atomic_store_release,
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.atomic_store_seq_cst,
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// in WebAssembly, all atomic instructions are sequentially ordered.
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=> func.airAtomicStore(inst),
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.atomic_rmw => func.airAtomicRmw(inst),
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.cmpxchg_weak => func.airCmpxchg(inst),
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.cmpxchg_strong => func.airCmpxchg(inst),
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.fence => func.airFence(inst),
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.add_optimized,
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.addwrap_optimized,
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.sub_optimized,
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@ -6636,3 +6653,319 @@ fn airErrorSetHasValue(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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return func.finishAir(inst, result, &.{ty_op.operand});
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}
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inline fn useAtomicFeature(func: *const CodeGen) bool {
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return std.Target.wasm.featureSetHas(func.target.cpu.features, .atomics);
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}
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fn airCmpxchg(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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const ty_pl = func.air.instructions.items(.data)[inst].ty_pl;
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const extra = func.air.extraData(Air.Cmpxchg, ty_pl.payload).data;
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const ptr_ty = func.air.typeOf(extra.ptr);
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const ty = ptr_ty.childType();
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const result_ty = func.air.typeOfIndex(inst);
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const ptr_operand = try func.resolveInst(extra.ptr);
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const expected_val = try func.resolveInst(extra.expected_value);
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const new_val = try func.resolveInst(extra.new_value);
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const cmp_result = try func.allocLocal(Type.bool);
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const ptr_val = if (func.useAtomicFeature()) val: {
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const val_local = try func.allocLocal(ty);
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try func.emitWValue(ptr_operand);
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try func.lowerToStack(expected_val);
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try func.lowerToStack(new_val);
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try func.addAtomicMemArg(switch (ty.abiSize(func.target)) {
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1 => .i32_atomic_rmw8_cmpxchg_u,
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2 => .i32_atomic_rmw16_cmpxchg_u,
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4 => .i32_atomic_rmw_cmpxchg,
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8 => .i32_atomic_rmw_cmpxchg,
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else => |size| return func.fail("TODO: implement `@cmpxchg` for types with abi size '{d}'", .{size}),
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}, .{
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.offset = ptr_operand.offset(),
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.alignment = ty.abiAlignment(func.target),
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});
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try func.addLabel(.local_tee, val_local.local.value);
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_ = try func.cmp(.stack, expected_val, ty, .eq);
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try func.addLabel(.local_set, cmp_result.local.value);
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break :val val_local;
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} else val: {
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if (ty.abiSize(func.target) > 8) {
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return func.fail("TODO: Implement `@cmpxchg` for types larger than abi size of 8 bytes", .{});
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}
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const ptr_val = try WValue.toLocal(try func.load(ptr_operand, ty, 0), func, ty);
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try func.lowerToStack(ptr_operand);
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try func.lowerToStack(new_val);
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try func.emitWValue(ptr_val);
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_ = try func.cmp(ptr_val, expected_val, ty, .eq);
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try func.addLabel(.local_tee, cmp_result.local.value);
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try func.addTag(.select);
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try func.store(.stack, .stack, ty, 0);
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break :val ptr_val;
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};
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const result_ptr = if (isByRef(result_ty, func.target)) val: {
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try func.emitWValue(cmp_result);
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try func.addImm32(-1);
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try func.addTag(.i32_xor);
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try func.addImm32(1);
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try func.addTag(.i32_and);
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const and_result = try WValue.toLocal(.stack, func, Type.bool);
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const result_ptr = try func.allocStack(result_ty);
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try func.store(result_ptr, and_result, Type.bool, @intCast(u32, ty.abiSize(func.target)));
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try func.store(result_ptr, ptr_val, ty, 0);
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break :val result_ptr;
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} else val: {
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try func.addImm32(0);
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try func.emitWValue(ptr_val);
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try func.emitWValue(cmp_result);
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try func.addTag(.select);
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break :val try WValue.toLocal(.stack, func, result_ty);
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};
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return func.finishAir(inst, result_ptr, &.{ extra.ptr, extra.new_value, extra.expected_value });
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}
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fn airAtomicLoad(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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const atomic_load = func.air.instructions.items(.data)[inst].atomic_load;
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const ptr = try func.resolveInst(atomic_load.ptr);
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const ty = func.air.typeOfIndex(inst);
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if (func.useAtomicFeature()) {
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const tag: wasm.AtomicsOpcode = switch (ty.abiSize(func.target)) {
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1 => .i32_atomic_load8_u,
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2 => .i32_atomic_load16_u,
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4 => .i32_atomic_load,
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8 => .i64_atomic_load,
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else => |size| return func.fail("TODO: @atomicLoad for types with abi size {d}", .{size}),
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};
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try func.emitWValue(ptr);
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try func.addAtomicMemArg(tag, .{
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.offset = ptr.offset(),
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.alignment = ty.abiAlignment(func.target),
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});
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} else {
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_ = try func.load(ptr, ty, 0);
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}
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const result = try WValue.toLocal(.stack, func, ty);
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return func.finishAir(inst, result, &.{atomic_load.ptr});
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}
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fn airAtomicRmw(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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const pl_op = func.air.instructions.items(.data)[inst].pl_op;
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const extra = func.air.extraData(Air.AtomicRmw, pl_op.payload).data;
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const ptr = try func.resolveInst(pl_op.operand);
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const operand = try func.resolveInst(extra.operand);
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const ty = func.air.typeOfIndex(inst);
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const op: std.builtin.AtomicRmwOp = extra.op();
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if (func.useAtomicFeature()) {
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switch (op) {
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.Max,
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.Min,
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.Nand,
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=> {
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const tmp = try func.load(ptr, ty, 0);
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const value = try tmp.toLocal(func, ty);
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// create a loop to cmpxchg the new value
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try func.startBlock(.loop, wasm.block_empty);
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try func.emitWValue(ptr);
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try func.emitWValue(value);
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if (op == .Nand) {
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const wasm_bits = toWasmBits(@intCast(u16, ty.bitSize(func.target))).?;
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const and_res = try func.binOp(value, operand, ty, .@"and");
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if (wasm_bits == 32)
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try func.addImm32(-1)
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else if (wasm_bits == 64)
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try func.addImm64(@bitCast(u64, @as(i64, -1)))
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else
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return func.fail("TODO: `@atomicRmw` with operator `Nand` for types larger than 64 bits", .{});
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_ = try func.binOp(and_res, .stack, ty, .xor);
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} else {
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try func.emitWValue(value);
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try func.emitWValue(operand);
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_ = try func.cmp(value, operand, ty, if (op == .Max) .gt else .lt);
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try func.addTag(.select);
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}
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try func.addAtomicMemArg(
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switch (ty.abiSize(func.target)) {
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1 => .i32_atomic_rmw8_cmpxchg_u,
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2 => .i32_atomic_rmw16_cmpxchg_u,
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4 => .i32_atomic_rmw_cmpxchg,
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8 => .i64_atomic_rmw_cmpxchg,
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else => return func.fail("TODO: implement `@atomicRmw` with operation `{s}` for types larger than 64 bits", .{@tagName(op)}),
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},
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.{
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.offset = ptr.offset(),
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.alignment = ty.abiAlignment(func.target),
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},
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);
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const select_res = try func.allocLocal(ty);
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try func.addLabel(.local_tee, select_res.local.value);
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_ = try func.cmp(.stack, value, ty, .neq); // leave on stack so we can use it for br_if
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try func.emitWValue(select_res);
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try func.addLabel(.local_set, value.local.value);
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try func.addLabel(.br_if, 0);
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try func.endBlock();
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return func.finishAir(inst, value, &.{ pl_op.operand, extra.operand });
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},
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// the other operations have their own instructions for Wasm.
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else => {
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try func.emitWValue(ptr);
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try func.emitWValue(operand);
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const tag: wasm.AtomicsOpcode = switch (ty.abiSize(func.target)) {
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1 => switch (op) {
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.Xchg => .i32_atomic_rmw8_xchg_u,
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.Add => .i32_atomic_rmw8_add_u,
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.Sub => .i32_atomic_rmw8_sub_u,
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.And => .i32_atomic_rmw8_and_u,
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.Or => .i32_atomic_rmw8_or_u,
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.Xor => .i32_atomic_rmw8_xor_u,
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else => unreachable,
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},
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2 => switch (op) {
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.Xchg => .i32_atomic_rmw16_xchg_u,
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.Add => .i32_atomic_rmw16_add_u,
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.Sub => .i32_atomic_rmw16_sub_u,
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.And => .i32_atomic_rmw16_and_u,
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.Or => .i32_atomic_rmw16_or_u,
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.Xor => .i32_atomic_rmw16_xor_u,
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else => unreachable,
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},
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4 => switch (op) {
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.Xchg => .i32_atomic_rmw_xchg,
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.Add => .i32_atomic_rmw_add,
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.Sub => .i32_atomic_rmw_sub,
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.And => .i32_atomic_rmw_and,
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.Or => .i32_atomic_rmw_or,
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.Xor => .i32_atomic_rmw_xor,
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else => unreachable,
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},
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8 => switch (op) {
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.Xchg => .i64_atomic_rmw_xchg,
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.Add => .i64_atomic_rmw_add,
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.Sub => .i64_atomic_rmw_sub,
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.And => .i64_atomic_rmw_and,
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.Or => .i64_atomic_rmw_or,
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.Xor => .i64_atomic_rmw_xor,
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else => unreachable,
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},
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else => |size| return func.fail("TODO: Implement `@atomicRmw` for types with abi size {d}", .{size}),
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};
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try func.addAtomicMemArg(tag, .{
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.offset = ptr.offset(),
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.alignment = ty.abiAlignment(func.target),
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});
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const result = try WValue.toLocal(.stack, func, ty);
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return func.finishAir(inst, result, &.{ pl_op.operand, extra.operand });
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},
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}
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} else {
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const loaded = try func.load(ptr, ty, 0);
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const result = try loaded.toLocal(func, ty);
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switch (op) {
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.Xchg => {
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try func.store(ptr, operand, ty, 0);
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},
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.Add,
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.Sub,
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.And,
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.Or,
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.Xor,
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=> {
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try func.emitWValue(ptr);
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_ = try func.binOp(result, operand, ty, switch (op) {
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.Add => .add,
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.Sub => .sub,
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.And => .@"and",
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.Or => .@"or",
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.Xor => .xor,
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else => unreachable,
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});
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if (ty.isInt() and (op == .Add or op == .Sub)) {
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_ = try func.wrapOperand(.stack, ty);
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}
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try func.store(.stack, .stack, ty, ptr.offset());
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},
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.Max,
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.Min,
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=> {
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try func.emitWValue(ptr);
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try func.emitWValue(result);
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try func.emitWValue(operand);
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_ = try func.cmp(result, operand, ty, if (op == .Max) .gt else .lt);
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try func.addTag(.select);
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try func.store(.stack, .stack, ty, ptr.offset());
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},
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.Nand => {
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const wasm_bits = toWasmBits(@intCast(u16, ty.bitSize(func.target))).?;
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try func.emitWValue(ptr);
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const and_res = try func.binOp(result, operand, ty, .@"and");
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if (wasm_bits == 32)
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try func.addImm32(-1)
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else if (wasm_bits == 64)
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try func.addImm64(@bitCast(u64, @as(i64, -1)))
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else
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return func.fail("TODO: `@atomicRmw` with operator `Nand` for types larger than 64 bits", .{});
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_ = try func.binOp(and_res, .stack, ty, .xor);
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try func.store(.stack, .stack, ty, ptr.offset());
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},
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}
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return func.finishAir(inst, result, &.{ pl_op.operand, extra.operand });
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}
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}
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fn airFence(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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// Only when the atomic feature is enabled, and we're not building
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// for a single-threaded build, can we emit the `fence` instruction.
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// In all other cases, we emit no instructions for a fence.
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if (func.useAtomicFeature() and !func.bin_file.base.options.single_threaded) {
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try func.addAtomicTag(.atomic_fence);
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}
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return func.finishAir(inst, .none, &.{});
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}
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fn airAtomicStore(func: *CodeGen, inst: Air.Inst.Index) InnerError!void {
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const bin_op = func.air.instructions.items(.data)[inst].bin_op;
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const ptr = try func.resolveInst(bin_op.lhs);
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const operand = try func.resolveInst(bin_op.rhs);
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const ptr_ty = func.air.typeOf(bin_op.lhs);
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const ty = ptr_ty.childType();
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if (func.useAtomicFeature()) {
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const tag: wasm.AtomicsOpcode = switch (ty.abiSize(func.target)) {
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1 => .i32_atomic_store8,
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2 => .i32_atomic_store16,
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4 => .i32_atomic_store,
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8 => .i64_atomic_store,
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else => |size| return func.fail("TODO: @atomicLoad for types with abi size {d}", .{size}),
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};
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try func.emitWValue(ptr);
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try func.lowerToStack(operand);
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try func.addAtomicMemArg(tag, .{
|
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.offset = ptr.offset(),
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.alignment = ty.abiAlignment(func.target),
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});
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} else {
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try func.store(ptr, operand, ty, 0);
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}
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return func.finishAir(inst, .none, &.{ bin_op.lhs, bin_op.rhs });
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}
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@ -521,8 +521,88 @@ fn emitSimd(emit: *Emit, inst: Mir.Inst.Index) !void {
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}
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fn emitAtomic(emit: *Emit, inst: Mir.Inst.Index) !void {
|
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_ = inst;
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return emit.fail("TODO: Implement atomics instructions", .{});
|
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const extra_index = emit.mir.instructions.items(.data)[inst].payload;
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const opcode = emit.mir.extra[extra_index];
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const writer = emit.code.writer();
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try emit.code.append(std.wasm.opcode(.atomics_prefix));
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try leb128.writeULEB128(writer, opcode);
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switch (@intToEnum(std.wasm.AtomicsOpcode, opcode)) {
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.i32_atomic_load,
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.i64_atomic_load,
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.i32_atomic_load8_u,
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.i32_atomic_load16_u,
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.i64_atomic_load8_u,
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.i64_atomic_load16_u,
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.i64_atomic_load32_u,
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.i32_atomic_store,
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.i64_atomic_store,
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.i32_atomic_store8,
|
||||
.i32_atomic_store16,
|
||||
.i64_atomic_store8,
|
||||
.i64_atomic_store16,
|
||||
.i64_atomic_store32,
|
||||
.i32_atomic_rmw_add,
|
||||
.i64_atomic_rmw_add,
|
||||
.i32_atomic_rmw8_add_u,
|
||||
.i32_atomic_rmw16_add_u,
|
||||
.i64_atomic_rmw8_add_u,
|
||||
.i64_atomic_rmw16_add_u,
|
||||
.i64_atomic_rmw32_add_u,
|
||||
.i32_atomic_rmw_sub,
|
||||
.i64_atomic_rmw_sub,
|
||||
.i32_atomic_rmw8_sub_u,
|
||||
.i32_atomic_rmw16_sub_u,
|
||||
.i64_atomic_rmw8_sub_u,
|
||||
.i64_atomic_rmw16_sub_u,
|
||||
.i64_atomic_rmw32_sub_u,
|
||||
.i32_atomic_rmw_and,
|
||||
.i64_atomic_rmw_and,
|
||||
.i32_atomic_rmw8_and_u,
|
||||
.i32_atomic_rmw16_and_u,
|
||||
.i64_atomic_rmw8_and_u,
|
||||
.i64_atomic_rmw16_and_u,
|
||||
.i64_atomic_rmw32_and_u,
|
||||
.i32_atomic_rmw_or,
|
||||
.i64_atomic_rmw_or,
|
||||
.i32_atomic_rmw8_or_u,
|
||||
.i32_atomic_rmw16_or_u,
|
||||
.i64_atomic_rmw8_or_u,
|
||||
.i64_atomic_rmw16_or_u,
|
||||
.i64_atomic_rmw32_or_u,
|
||||
.i32_atomic_rmw_xor,
|
||||
.i64_atomic_rmw_xor,
|
||||
.i32_atomic_rmw8_xor_u,
|
||||
.i32_atomic_rmw16_xor_u,
|
||||
.i64_atomic_rmw8_xor_u,
|
||||
.i64_atomic_rmw16_xor_u,
|
||||
.i64_atomic_rmw32_xor_u,
|
||||
.i32_atomic_rmw_xchg,
|
||||
.i64_atomic_rmw_xchg,
|
||||
.i32_atomic_rmw8_xchg_u,
|
||||
.i32_atomic_rmw16_xchg_u,
|
||||
.i64_atomic_rmw8_xchg_u,
|
||||
.i64_atomic_rmw16_xchg_u,
|
||||
.i64_atomic_rmw32_xchg_u,
|
||||
|
||||
.i32_atomic_rmw_cmpxchg,
|
||||
.i64_atomic_rmw_cmpxchg,
|
||||
.i32_atomic_rmw8_cmpxchg_u,
|
||||
.i32_atomic_rmw16_cmpxchg_u,
|
||||
.i64_atomic_rmw8_cmpxchg_u,
|
||||
.i64_atomic_rmw16_cmpxchg_u,
|
||||
.i64_atomic_rmw32_cmpxchg_u,
|
||||
=> {
|
||||
const mem_arg = emit.mir.extraData(Mir.MemArg, extra_index + 1).data;
|
||||
try encodeMemArg(mem_arg, writer);
|
||||
},
|
||||
.atomic_fence => {
|
||||
// TODO: When multi-memory proposal is accepted and implemented in the compiler,
|
||||
// change this to (user-)specified index, rather than hardcode it to memory index 0.
|
||||
const memory_index: u32 = 0;
|
||||
try leb128.writeULEB128(writer, memory_index);
|
||||
},
|
||||
else => |tag| return emit.fail("TODO: Implement atomic instruction: {s}", .{@tagName(tag)}),
|
||||
}
|
||||
}
|
||||
|
||||
fn emitMemFill(emit: *Emit) !void {
|
||||
|
||||
@ -11,7 +11,6 @@ const supports_128_bit_atomics = switch (builtin.cpu.arch) {
|
||||
};
|
||||
|
||||
test "cmpxchg" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -38,7 +37,6 @@ fn testCmpxchg() !void {
|
||||
}
|
||||
|
||||
test "fence" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
|
||||
@ -48,7 +46,6 @@ test "fence" {
|
||||
}
|
||||
|
||||
test "atomicrmw and atomicload" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -76,7 +73,6 @@ fn testAtomicLoad(ptr: *u8) !void {
|
||||
}
|
||||
|
||||
test "cmpxchg with ptr" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -101,7 +97,6 @@ test "cmpxchg with ptr" {
|
||||
}
|
||||
|
||||
test "cmpxchg with ignored result" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -146,7 +141,6 @@ fn test_u128_cmpxchg() !void {
|
||||
var a_global_variable = @as(u32, 1234);
|
||||
|
||||
test "cmpxchg on a global variable" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -161,7 +155,6 @@ test "cmpxchg on a global variable" {
|
||||
}
|
||||
|
||||
test "atomic load and rmw with enum" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -178,7 +171,6 @@ test "atomic load and rmw with enum" {
|
||||
}
|
||||
|
||||
test "atomic store" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -191,7 +183,6 @@ test "atomic store" {
|
||||
}
|
||||
|
||||
test "atomic store comptime" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -209,7 +200,6 @@ fn testAtomicStore() !void {
|
||||
}
|
||||
|
||||
test "atomicrmw with floats" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
@ -239,7 +229,6 @@ fn testAtomicRmwFloat() !void {
|
||||
}
|
||||
|
||||
test "atomicrmw with ints" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
@ -413,7 +402,6 @@ fn testAtomicsWithType(comptime T: type, a: T, b: T) !void {
|
||||
}
|
||||
|
||||
test "return @atomicStore, using it as a void value" {
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user