mirror of
https://github.com/ziglang/zig.git
synced 2026-01-20 14:25:16 +00:00
update_cpu_features: Update for LLVM 19.
* Add `ProcessorAlias` support. * Bump output buffer size. * Include `i` extension in RISC-V baselines. * Update evaluation branch quota for RISC-V. * Retain some CPU features that LLVM removed. * Flatten more 'meta-features' used for CPU models. * Remove some superfluous dependencies.
This commit is contained in:
Alex Rønne Petersen
Andrew Kelley
parent
9f669df1b3
commit
a4af54b4e5
@ -56,15 +56,15 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "all",
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.omit = true,
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},
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.{
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.llvm_name = "v8a",
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.extra_deps = &.{ "fp_armv8", "neon" },
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},
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.{
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.llvm_name = "CONTEXTIDREL2",
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.zig_name = "contextidr_el2",
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.desc = "Enable RW operand Context ID Register (EL2)",
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},
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.{
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.llvm_name = "v8a",
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.extra_deps = &.{"neon"},
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},
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.{
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.llvm_name = "neoversee1",
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.flatten = true,
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@ -77,6 +77,10 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "neoversen2",
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.flatten = true,
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},
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.{
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.llvm_name = "neoversen3",
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.flatten = true,
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},
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.{
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.llvm_name = "neoversev1",
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.flatten = true,
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@ -85,32 +89,37 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "neoversev2",
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.flatten = true,
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},
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.{
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.llvm_name = "neoversev3",
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.flatten = true,
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},
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.{
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.llvm_name = "neoversev3AE",
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.flatten = true,
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},
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.{
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.llvm_name = "neoverse512tvb",
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.flatten = true,
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},
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.{
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.llvm_name = "oryon-1",
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.flatten = true,
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},
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.{
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.llvm_name = "exynosm3",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "exynosm4",
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.flatten = true,
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},
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.{
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.llvm_name = "v8.1a",
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "a35",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "a53",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "a55",
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@ -119,34 +128,75 @@ const llvm_targets = [_]LlvmTarget{
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.{
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.llvm_name = "a57",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "a510",
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.flatten = true,
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},
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.{
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.llvm_name = "a520",
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.flatten = true,
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},
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.{
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.llvm_name = "a520ae",
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.flatten = true,
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},
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.{
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.llvm_name = "a64fx",
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.flatten = true,
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},
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.{
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.llvm_name = "a65",
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.flatten = true,
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},
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.{
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.llvm_name = "a72",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "a73",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "a75",
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.flatten = true,
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},
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.{
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.llvm_name = "a76",
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.flatten = true,
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},
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.{
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.llvm_name = "a77",
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.flatten = true,
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},
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.{
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.llvm_name = "a78",
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.flatten = true,
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},
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.{
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.llvm_name = "a78ae",
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.flatten = true,
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},
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.{
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.llvm_name = "a78c",
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.flatten = true,
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},
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.{
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.llvm_name = "a710",
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.flatten = true,
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},
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.{
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.llvm_name = "a715",
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.flatten = true,
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},
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.{
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.llvm_name = "a720",
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.flatten = true,
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},
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.{
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.llvm_name = "a720ae",
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.flatten = true,
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},
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.{
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.llvm_name = "ampere1a",
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.flatten = true,
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@ -191,14 +241,30 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "apple-a7-sysreg",
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.flatten = true,
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},
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.{
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.llvm_name = "apple-m4",
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.flatten = true,
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},
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.{
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.llvm_name = "carmel",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-a725",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-a78",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-r82",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-r82ae",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-x1",
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.flatten = true,
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@ -215,15 +281,17 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "cortex-x4",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-x925",
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.flatten = true,
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},
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.{
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.llvm_name = "falkor",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "kryo",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "saphira",
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@ -232,7 +300,6 @@ const llvm_targets = [_]LlvmTarget{
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.{
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.llvm_name = "thunderx",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "thunderx2t99",
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@ -245,17 +312,14 @@ const llvm_targets = [_]LlvmTarget{
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.{
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.llvm_name = "thunderxt81",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "thunderxt83",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "thunderxt88",
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.flatten = true,
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.extra_deps = &.{"v8a"},
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},
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.{
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.llvm_name = "tsv110",
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@ -308,8 +372,6 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = null,
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.zig_name = "xgene1",
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.features = &.{
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"fp_armv8",
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"neon",
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"perfmon",
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"v8a",
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},
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@ -320,13 +382,16 @@ const llvm_targets = [_]LlvmTarget{
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.features = &.{
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"crc",
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"crypto",
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"fp_armv8",
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"neon",
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"perfmon",
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"v8a",
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},
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},
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},
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.omit_cpus = &.{
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// Who thought this alias was a good idea? Upgrade your compiler and suddenly your
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// programs SIGILL because this changed meaning. Brilliant.
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"apple-latest",
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},
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},
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.{
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.zig_name = "amdgpu",
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@ -383,10 +448,18 @@ const llvm_targets = [_]LlvmTarget{
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},
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},
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.feature_overrides = &.{
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.{
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.llvm_name = "exynos",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-a78",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-a78ae",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-a710",
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.flatten = true,
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@ -420,6 +493,14 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "cortex-x1c",
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.flatten = true,
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},
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.{
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.llvm_name = "r4",
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.flatten = true,
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},
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.{
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.llvm_name = "r52plus",
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.flatten = true,
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},
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.{
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.llvm_name = "r5",
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.flatten = true,
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@ -432,6 +513,10 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "r7",
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.flatten = true,
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},
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.{
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.llvm_name = "m3",
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.flatten = true,
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},
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.{
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.llvm_name = "m7",
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.flatten = true,
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@ -444,6 +529,10 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "kryo",
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.flatten = true,
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},
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.{
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.llvm_name = "swift",
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.flatten = true,
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},
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.{
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.llvm_name = "cortex-x1",
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.flatten = true,
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@ -512,6 +601,10 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "a75",
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.flatten = true,
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},
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.{
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.llvm_name = "a76",
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.flatten = true,
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},
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.{
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.llvm_name = "a77",
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.flatten = true,
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@ -903,6 +996,7 @@ const llvm_targets = [_]LlvmTarget{
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.zig_name = "riscv",
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.llvm_name = "RISCV",
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.td_name = "RISCV.td",
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.branch_quota = 2000,
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.feature_overrides = &.{
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.{
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.llvm_name = "sifive7",
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@ -913,12 +1007,12 @@ const llvm_targets = [_]LlvmTarget{
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.{
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.llvm_name = null,
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.zig_name = "baseline_rv32",
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.features = &.{ "32bit", "a", "c", "d", "f", "m" },
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.features = &.{ "32bit", "a", "c", "d", "f", "i", "m" },
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},
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.{
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.llvm_name = null,
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.zig_name = "baseline_rv64",
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.features = &.{ "64bit", "a", "c", "d", "f", "m" },
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.features = &.{ "64bit", "a", "c", "d", "f", "i", "m" },
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},
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},
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},
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@ -957,10 +1051,130 @@ const llvm_targets = [_]LlvmTarget{
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.llvm_name = "64bit-mode",
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.omit = true,
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},
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.{
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.llvm_name = "amdfam10",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon64",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon64-sse3",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon-4",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon-fx",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon-mp",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon-tbird",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "athlon-xp",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "barcelona",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "c3",
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.extra_deps = &.{"3dnow"},
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},
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.{
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.llvm_name = "geode",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "k6-2",
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.extra_deps = &.{"3dnow"},
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},
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.{
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.llvm_name = "k6-3",
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.extra_deps = &.{"3dnow"},
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},
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.{
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.llvm_name = "k8",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "k8-sse3",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "knl",
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.extra_deps = &.{
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"avx512er",
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"avx512pf",
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"prefetchwt1",
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},
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},
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.{
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.llvm_name = "knm",
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.extra_deps = &.{
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"avx512er",
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"avx512pf",
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"prefetchwt1",
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},
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},
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.{
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.llvm_name = "lakemont",
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.extra_deps = &.{"soft_float"},
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},
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.{
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.llvm_name = "opteron",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "opteron-sse3",
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.extra_deps = &.{"3dnowa"},
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},
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.{
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.llvm_name = "winchip2",
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.extra_deps = &.{"3dnow"},
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},
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},
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// Features removed from LLVM
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.extra_features = &.{
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.{
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.zig_name = "3dnow",
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.desc = "Enable 3DNow! instructions",
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.deps = &.{"mmx"},
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},
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.{
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.zig_name = "3dnowa",
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.desc = "Enable 3DNow! Athlon instructions",
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.deps = &.{"3dnow"},
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},
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.{
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.zig_name = "avx512er",
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.desc = "Enable AVX-512 Exponential and Reciprocal Instructions",
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.deps = &.{"avx512f"},
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},
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.{
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.zig_name = "avx512pf",
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.desc = "Enable AVX-512 PreFetch Instructions",
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.deps = &.{"avx512f"},
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},
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.{
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.zig_name = "prefetchwt1",
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.desc = "Prefetch with Intent to Write and T1 Hint",
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.deps = &.{},
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},
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},
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.omit_cpus = &.{
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// LLVM defines a bunch of dumb aliases with foreach loops in X86.td.
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@ -1111,7 +1325,7 @@ fn processOneTarget(job: Job) anyerror!void {
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const child_result = try std.process.Child.run(.{
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.allocator = arena,
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.argv = &child_args,
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.max_output_bytes = 400 * 1024 * 1024,
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.max_output_bytes = 500 * 1024 * 1024,
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});
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tblgen_progress.end();
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if (child_result.stderr.len != 0) {
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@ -1138,6 +1352,36 @@ fn processOneTarget(job: Job) anyerror!void {
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const render_progress = progress_node.start("render zig code", 0);
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|
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// So far LLVM has only had a few aliases for the same CPU.
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var cpu_aliases = std.StringHashMap(std.SegmentedList(struct {
|
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llvm: []const u8,
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zig: []const u8,
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}, 4)).init(arena);
|
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|
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{
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var it = root_map.iterator();
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while (it.next()) |kv| {
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if (kv.key_ptr.len == 0) continue;
|
||||
if (kv.key_ptr.*[0] == '!') continue;
|
||||
if (kv.value_ptr.* != .object) continue;
|
||||
if (hasSuperclass(&kv.value_ptr.object, "ProcessorAlias")) {
|
||||
// Note that `Name` is actually the alias, while `Alias` is the name that will have
|
||||
// a full `Processor` object defined.
|
||||
const llvm_alias = kv.value_ptr.object.get("Name").?.string;
|
||||
const llvm_name = kv.value_ptr.object.get("Alias").?.string;
|
||||
|
||||
const gop = try cpu_aliases.getOrPut(try llvmNameToZigName(arena, llvm_name));
|
||||
|
||||
if (!gop.found_existing) gop.value_ptr.* = .{};
|
||||
|
||||
try gop.value_ptr.append(arena, .{
|
||||
.llvm = llvm_alias,
|
||||
.zig = try llvmNameToZigName(arena, llvm_alias),
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
var features_table = std.StringHashMap(Feature).init(arena);
|
||||
var all_features = std.ArrayList(Feature).init(arena);
|
||||
var all_cpus = std.ArrayList(Cpu).init(arena);
|
||||
@ -1184,7 +1428,7 @@ fn processOneTarget(job: Job) anyerror!void {
|
||||
const other_key = imply.object.get("def").?.string;
|
||||
const other_obj = &root_map.getPtr(other_key).?.object;
|
||||
const other_llvm_name = other_obj.get("Name").?.string;
|
||||
const other_zig_name = (try llvmNameToZigNameOmit(
|
||||
const other_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
other_llvm_name,
|
||||
@ -1241,7 +1485,7 @@ fn processOneTarget(job: Job) anyerror!void {
|
||||
const feature_obj = &root_map.getPtr(feature_key).?.object;
|
||||
const feature_llvm_name = feature_obj.get("Name").?.string;
|
||||
if (feature_llvm_name.len == 0) continue;
|
||||
const feature_zig_name = (try llvmNameToZigNameOmit(
|
||||
const feature_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
feature_llvm_name,
|
||||
@ -1261,7 +1505,7 @@ fn processOneTarget(job: Job) anyerror!void {
|
||||
const feature_obj = &root_map.getPtr(feature_key).?.object;
|
||||
const feature_llvm_name = feature_obj.get("Name").?.string;
|
||||
if (feature_llvm_name.len == 0) continue;
|
||||
const feature_zig_name = (try llvmNameToZigNameOmit(
|
||||
const feature_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
feature_llvm_name,
|
||||
@ -1287,6 +1531,22 @@ fn processOneTarget(job: Job) anyerror!void {
|
||||
.zig_name = zig_name,
|
||||
.features = deps.items,
|
||||
});
|
||||
|
||||
if (cpu_aliases.get(zig_name)) |aliases| {
|
||||
var alias_it = aliases.constIterator(0);
|
||||
|
||||
alias_it: while (alias_it.next()) |alias| {
|
||||
for (llvm_target.omit_cpus) |omit_cpu_name| {
|
||||
if (mem.eql(u8, omit_cpu_name, alias.llvm)) continue :alias_it;
|
||||
}
|
||||
|
||||
try all_cpus.append(.{
|
||||
.llvm_name = alias.llvm,
|
||||
.zig_name = alias.zig,
|
||||
.features = deps.items,
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1525,7 +1785,7 @@ fn llvmNameToZigName(arena: mem.Allocator, llvm_name: []const u8) ![]const u8 {
|
||||
return duped;
|
||||
}
|
||||
|
||||
fn llvmNameToZigNameOmit(
|
||||
fn llvmFeatureNameToZigNameOmit(
|
||||
arena: mem.Allocator,
|
||||
llvm_target: LlvmTarget,
|
||||
llvm_name: []const u8,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user