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stage2 sparcv9: Add register definitions & instruction formats
This adds the GPR/FPR register definitions and instruction formats for SPARCv9. I need to implement a separate enc() function because the register values for the FPRs have to be encoded to a special format that's separate from the normal register ID.
This commit is contained in:
Koakuma
parent
8a43d67c3b
commit
a212d5931d
447
src/arch/sparcv9/bits.zig
Normal file
447
src/arch/sparcv9/bits.zig
Normal file
@ -0,0 +1,447 @@
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const std = @import("std");
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const DW = std.dwarf;
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const testing = std.testing;
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/// General purpose registers in the SPARCv9 instruction set
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pub const Register = enum(u6) {
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// zig fmt: off
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g0, g1, g2, g3, g4, g5, g6, g7,
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o0, o1, o2, o3, o4, o5, o6, o7,
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l0, l1, l2, l3, l4, l5, l6, l7,
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@"i0", @"i1", @"i2", @"i3", @"i4", @"i5", @"i6", @"i7",
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sp = 46, // stack pointer (o6)
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fp = 62, // frame pointer (i6)
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// zig fmt: on
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pub fn id(self: Register) u5 {
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return @truncate(u5, @enumToInt(self));
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}
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pub fn enc(self: Register) u5 {
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// For integer registers, enc() == id().
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return self.id();
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}
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pub fn dwarfLocOp(reg: Register) u8 {
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return @as(u8, reg.id()) + DW.OP.reg0;
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}
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};
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test "Register.id" {
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// SP
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try testing.expectEqual(@as(u5, 14), Register.o6.id());
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try testing.expectEqual(Register.o6.id(), Register.sp.id());
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// FP
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try testing.expectEqual(@as(u5, 30), Register.@"i6".id());
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try testing.expectEqual(Register.@"i6".id(), Register.fp.id());
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// x0
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try testing.expectEqual(@as(u5, 0), Register.g0.id());
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try testing.expectEqual(@as(u5, 8), Register.o0.id());
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try testing.expectEqual(@as(u5, 16), Register.l0.id());
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try testing.expectEqual(@as(u5, 24), Register.@"i0".id());
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}
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test "Register.enc" {
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// x0
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try testing.expectEqual(@as(u5, 0), Register.g0.enc());
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try testing.expectEqual(@as(u5, 8), Register.o0.enc());
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try testing.expectEqual(@as(u5, 16), Register.l0.enc());
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try testing.expectEqual(@as(u5, 24), Register.@"i0".enc());
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// For integer registers, enc() == id().
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try testing.expectEqual(Register.g0.enc(), Register.g0.id());
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try testing.expectEqual(Register.o0.enc(), Register.o0.id());
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try testing.expectEqual(Register.l0.enc(), Register.l0.id());
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try testing.expectEqual(Register.@"i0".enc(), Register.@"i0".id());
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}
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/// Scalar floating point registers in the SPARCv9 instruction set
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pub const FloatingPointRegister = enum(u7) {
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// SPARCv9 has 64 f32 registers, 32 f64 registers, and 16 f128 registers,
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// which are aliased in this way:
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//
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// | %d0 | %d2 |
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// %q0 | %f0 | %f1 | %f2 | %f3 |
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// | %d4 | %d6 |
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// %q4 | %f4 | %f5 | %f6 | %f7 |
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// ...
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// | %d60 | %d62 |
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// %q60 | %f60 | %f61 | %f62 | %f63 |
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//
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// Though, since the instructions uses five-bit addressing, only %f0-%f31
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// is usable with f32 instructions.
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// zig fmt: off
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// 32-bit registers
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@"f0", @"f1", @"f2", @"f3", @"f4", @"f5", @"f6", @"f7",
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@"f8", @"f9", @"f10", @"f11", @"f12", @"f13", @"f14", @"f15",
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@"f16", @"f17", @"f18", @"f19", @"f20", @"f21", @"f22", @"f23",
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@"f24", @"f25", @"f26", @"f27", @"f28", @"f29", @"f30", @"f31",
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// 64-bit registers
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d0, d2, d4, d6, d8, d10, d12, d14,
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d16, d18, d20, d22, d24, d26, d28, d30,
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d32, d34, d36, d38, d40, d42, d44, d46,
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d48, d50, d52, d54, d56, d58, d60, d62,
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// 128-bit registers
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q0, q4, q8, q12, q16, q20, q24, q28,
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q32, q36, q40, q44, q48, q52, q56, q60,
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// zig fmt: on
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pub fn id(self: FloatingPointRegister) u6 {
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return switch (self.size()) {
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32 => @truncate(u6, @enumToInt(self)),
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64 => @truncate(u6, (@enumToInt(self) - 32) * 2),
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128 => @truncate(u6, (@enumToInt(self) - 64) * 4),
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else => unreachable,
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};
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}
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pub fn enc(self: FloatingPointRegister) u5 {
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// Floating point registers use an encoding scheme to map from the 6-bit
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// ID to 5-bit encoded value.
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// (See section 5.1.4.1 of SPARCv9 ISA specification)
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const reg_id = self.id();
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return @truncate(u5, reg_id | (reg_id >> 5));
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}
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/// Returns the bit-width of the register.
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pub fn size(self: FloatingPointRegister) u8 {
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return switch (@enumToInt(self)) {
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0...31 => 32,
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32...63 => 64,
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64...79 => 128,
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else => unreachable,
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};
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}
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};
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test "FloatingPointRegister.id" {
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// Low region
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try testing.expectEqual(@as(u6, 0), FloatingPointRegister.q0.id());
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try testing.expectEqual(FloatingPointRegister.q0.id(), FloatingPointRegister.d0.id());
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try testing.expectEqual(FloatingPointRegister.d0.id(), FloatingPointRegister.@"f0".id());
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try testing.expectEqual(@as(u6, 28), FloatingPointRegister.q28.id());
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try testing.expectEqual(FloatingPointRegister.q28.id(), FloatingPointRegister.d28.id());
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try testing.expectEqual(FloatingPointRegister.d28.id(), FloatingPointRegister.@"f28".id());
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// High region
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try testing.expectEqual(@as(u6, 32), FloatingPointRegister.q32.id());
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try testing.expectEqual(FloatingPointRegister.q32.id(), FloatingPointRegister.d32.id());
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try testing.expectEqual(@as(u6, 60), FloatingPointRegister.q60.id());
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try testing.expectEqual(FloatingPointRegister.q60.id(), FloatingPointRegister.d60.id());
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}
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test "FloatingPointRegister.enc" {
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// f registers
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try testing.expectEqual(@as(u5, 0), FloatingPointRegister.@"f0".enc());
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try testing.expectEqual(@as(u5, 1), FloatingPointRegister.@"f1".enc());
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try testing.expectEqual(@as(u5, 31), FloatingPointRegister.@"f31".enc());
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// d registers
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try testing.expectEqual(@as(u5, 0), FloatingPointRegister.d0.enc());
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try testing.expectEqual(@as(u5, 1), FloatingPointRegister.d32.enc());
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try testing.expectEqual(@as(u5, 31), FloatingPointRegister.d62.enc());
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// q registers
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try testing.expectEqual(@as(u5, 0), FloatingPointRegister.q0.enc());
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try testing.expectEqual(@as(u5, 1), FloatingPointRegister.q32.enc());
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try testing.expectEqual(@as(u5, 29), FloatingPointRegister.q60.enc());
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}
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/// Represents an instruction in the SPARCv9 instruction set
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pub const Instruction = union(enum) {
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// Some of the instruction formats have several minor formats, here I
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// name them with letters since there's no official naming scheme.
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// TODO: need to rename the minor formats to a more descriptive name.
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// Format 1 (op = 1): CALL
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format_1: packed struct {
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op: u2 = 0b01,
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disp30: u30,
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},
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// Format 2 (op = 0): SETHI & Branches (Bicc, BPcc, BPr, FBfcc, FBPfcc)
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format_2a: packed struct {
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op: u2 = 0b00,
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rd: u5,
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op2: u3,
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imm22: u22,
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},
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format_2b: packed struct {
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op: u2 = 0b00,
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a: u1,
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cond: u4,
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op2: u3,
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disp22: u22,
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},
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format_2c: packed struct {
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op: u2 = 0b00,
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a: u1,
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cond: u4,
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op2: u3,
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cc1: u1,
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cc0: u1,
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p: u1,
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disp19: u19,
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},
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format_2d: packed struct {
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op: u2 = 0b00,
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a: u1,
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fixed: u1 = 0b0,
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rcond: u3,
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op2: u3,
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d16hi: u2,
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p: u1,
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rs1: u5,
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d16lo: u14,
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},
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// Format 3 (op = 2 or 3): Arithmetic, Logical, MOVr, MEMBAR, Load, and Store
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format_3a: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b0,
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reserved: u8 = 0b00000000,
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rs2: u5,
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},
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format_3b: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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simm13: u13,
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},
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format_3c: packed struct {
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op: u2,
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reserved1: u5 = 0b00000,
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op3: u6,
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rs1: u5,
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i: u1 = 0b0,
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reserved2: u8 = 0b00000000,
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rs2: u5,
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},
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format_3d: packed struct {
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op: u2,
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reserved: u5 = 0b00000,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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simm13: u13,
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},
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format_3e: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b0,
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rcond: u3,
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reserved: u5 = 0b00000,
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rs2: u5,
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},
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format_3f: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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rcond: u3,
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simm10: u10,
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},
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format_3g: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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reserved: u8 = 0b00000000,
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rs2: u5,
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},
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format_3h: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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reserved: u6,
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cmask: u3,
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mmask: u4,
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},
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format_3i: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b0,
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imm_asi: u8,
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rs2: u5,
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},
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format_3j: packed struct {
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op: u2,
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impl_dep1: u5,
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op3: u6,
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impl_dep2: u19,
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},
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format_3k: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b0,
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x: u1,
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reserved: u7 = 0b0000000,
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rs2: u5,
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},
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format_3l: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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x: u1 = 0b0,
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reserved: u7 = 0b0000000,
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shcnt32: u5,
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},
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format_3m: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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x: u1 = 0b1,
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reserved: u6 = 0b000000,
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shcnt64: u6,
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},
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format_3n: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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reserved: u5 = 0b00000,
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opf: u9,
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rs2: u5,
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},
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format_3o: packed struct {
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op: u2,
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fixed: u3 = 0b000,
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cc1: u1,
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cc0: i1,
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op3: u6,
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opf: u9,
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rs2: u5,
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},
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format_3p: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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opf: u9,
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rs2: u5,
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},
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format_3q: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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rs1: u5,
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reserved: u14 = 0b00000000000000,
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},
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format_3r: packed struct {
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op: u2,
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fcn: u5,
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op3: u6,
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reserved: u19 = 0b0000000000000000000,
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},
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format_3s: packed struct {
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op: u2,
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rd: u5,
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op3: u6,
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reserved: u19 = 0b0000000000000000000,
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},
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//Format 4 (op = 2): MOVcc, FMOVr, FMOVcc, and Tcc
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format_4a: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b0,
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cc1: u1,
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cc0: u1,
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reserved: u6 = 0b000000,
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rs2: u5,
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},
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format_4b: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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cc1: u1,
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cc0: u1,
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simm11: u11,
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},
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format_4c: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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cc2: u1,
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cond: u4,
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i: u1 = 0b0,
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cc1: u1,
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cc0: u1,
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reserved: u6 = 0b000000,
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rs2: u5,
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},
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format_4d: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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cc2: u1,
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cond: u4,
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i: u1 = 0b1,
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cc1: u1,
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cc0: u1,
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simm11: u11,
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},
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format_4e: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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rs1: u5,
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i: u1 = 0b1,
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cc1: u1,
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cc0: u1,
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reserved: u4 = 0b0000,
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sw_trap: u7,
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},
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format_4f: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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rs1: u5,
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fixed: u1 = 0b0,
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rcond: u3,
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opf_low: u5,
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rs2: u5,
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},
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format_4g: packed struct {
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op: u2 = 0b10,
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rd: u5,
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op3: u6,
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fixed: u1 = 0b0,
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cond: u4,
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opf_cc: u3,
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opf_low: u6,
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rs2: u5,
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},
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};
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