From 9fde44229c30d6dbdc943af2a2c2cb82adf703f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 21 Oct 2025 04:07:19 +0200
Subject: [PATCH] std.os.linux.tls: add alpha support

---
 lib/std/os/linux/tls.zig | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/lib/std/os/linux/tls.zig b/lib/std/os/linux/tls.zig
index 62df828916..ba77e25788 100644
--- a/lib/std/os/linux/tls.zig
+++ b/lib/std/os/linux/tls.zig
@@ -63,12 +63,13 @@ const Variant = enum {
 };
 
 const current_variant: Variant = switch (native_arch) {
+    .aarch64,
+    .aarch64_be,
+    .alpha,
     .arc,
     .arceb,
     .arm,
     .armeb,
-    .aarch64,
-    .aarch64_be,
     .csky,
     .thumb,
     .thumbeb,
@@ -138,6 +139,7 @@ const AbiTcb = switch (current_variant) {
         // usual, while the second one is unspecified.
         .aarch64,
         .aarch64_be,
+        .alpha,
         .arm,
         .armeb,
         .thumb,
@@ -244,6 +246,14 @@ pub fn setThreadPointer(addr: usize) void {
                 : [addr] "r" (addr),
             );
         },
+        .alpha => {
+            asm volatile (
+                \\ lda a0, %[addr]
+                \\ wruniq
+                :
+                : [addr] "r" (addr),
+            );
+        },
         .arc, .arceb => {
             // We apparently need to both set r25 (TP) *and* inform the kernel...
             asm volatile (