From 9fc9235ac815f8b0ad88445216407a0a9f747d5f Mon Sep 17 00:00:00 2001 From: Jacob Young Date: Sun, 8 Oct 2023 01:28:17 -0400 Subject: [PATCH] x86_64: fix undersized vector binary operations --- src/arch/x86_64/CodeGen.zig | 10 ++++++++-- test/behavior/maximum_minimum.zig | 3 ++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index b2f03a993f..bdad8312d5 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -7733,7 +7733,10 @@ fn genBinOp( mir_tag, dst_reg, lhs_reg, - src_mcv.mem(Memory.PtrSize.fromSize(abi_size)), + src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) { + else => Memory.PtrSize.fromSize(abi_size), + .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()), + }), ) else try self.asmRegisterRegisterRegister( mir_tag, dst_reg, @@ -7748,7 +7751,10 @@ fn genBinOp( if (src_mcv.isMemory()) try self.asmRegisterMemory( mir_tag, dst_reg, - src_mcv.mem(Memory.PtrSize.fromSize(abi_size)), + src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) { + else => Memory.PtrSize.fromSize(abi_size), + .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()), + }), ) else try self.asmRegisterRegister( mir_tag, dst_reg, diff --git a/test/behavior/maximum_minimum.zig b/test/behavior/maximum_minimum.zig index efd4f55c8e..c76dd7573d 100644 --- a/test/behavior/maximum_minimum.zig +++ b/test/behavior/maximum_minimum.zig @@ -276,7 +276,8 @@ test "@min/@max notices bounds from vector types when element of comptime-known if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; - if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; + if (builtin.zig_backend == .stage2_x86_64 and + !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest; var x: @Vector(2, u32) = .{ 1_000_000, 12345 }; const y: @Vector(2, u16) = .{ 10, undefined };