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Merge pull request #23188 from jacobly0/fix-23143
x86_64: fix crashes with symbols
This commit is contained in:
Andrew Kelley
GitHub
commit
982c500be5
@ -97980,16 +97980,150 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
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switch (pred_mcv) {
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.register => |pred_reg| switch (pred_reg.class()) {
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.general_purpose => {},
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.sse => if (need_xmm0 and pred_reg.id() != comptime Register.xmm0.id()) {
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.sse => if (elem_ty.toIntern() == .bool_type)
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if (need_xmm0 and pred_reg.id() != comptime Register.xmm0.id()) {
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try self.register_manager.getKnownReg(.xmm0, null);
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try self.genSetReg(.xmm0, pred_ty, pred_mcv, .{});
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break :mask .xmm0;
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} else break :mask if (has_blend)
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pred_reg
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else
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try self.copyToTmpRegister(pred_ty, pred_mcv),
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try self.copyToTmpRegister(pred_ty, pred_mcv)
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else
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return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)}),
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else => unreachable,
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},
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.register_mask => |pred_reg_mask| {
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if (pred_reg_mask.info.scalar.bitSize(self.target) != 8 * elem_abi_size)
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return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
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const mask_reg: Register = if (need_xmm0 and pred_reg_mask.reg.id() != comptime Register.xmm0.id()) mask_reg: {
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try self.register_manager.getKnownReg(.xmm0, null);
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try self.genSetReg(.xmm0, ty, .{ .register = pred_reg_mask.reg }, .{});
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break :mask_reg .xmm0;
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} else pred_reg_mask.reg;
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const mask_alias = registerAlias(mask_reg, abi_size);
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const mask_lock = self.register_manager.lockRegAssumeUnused(mask_reg);
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defer self.register_manager.unlockReg(mask_lock);
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const lhs_mcv = try self.resolveInst(extra.lhs);
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const lhs_lock = switch (lhs_mcv) {
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.register => |lhs_reg| self.register_manager.lockRegAssumeUnused(lhs_reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs_mcv = try self.resolveInst(extra.rhs);
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const rhs_lock = switch (rhs_mcv) {
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.register => |rhs_reg| self.register_manager.lockReg(rhs_reg),
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else => null,
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const order = has_blend != pred_reg_mask.info.inverted;
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const reuse_mcv, const other_mcv = if (order)
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.{ rhs_mcv, lhs_mcv }
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else
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.{ lhs_mcv, rhs_mcv };
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const dst_mcv: MCValue = if (reuse_mcv.isRegister() and self.reuseOperand(
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inst,
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if (order) extra.rhs else extra.lhs,
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@intFromBool(order),
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reuse_mcv,
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)) reuse_mcv else if (has_avx)
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.{ .register = try self.register_manager.allocReg(inst, abi.RegisterClass.sse) }
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else
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try self.copyToRegisterWithInstTracking(inst, ty, reuse_mcv);
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const dst_reg = dst_mcv.getReg().?;
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const dst_alias = registerAlias(dst_reg, abi_size);
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const dst_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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const mir_tag = @as(?Mir.Inst.FixedTag, if ((pred_reg_mask.info.kind == .all and
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elem_ty.toIntern() != .f32_type and elem_ty.toIntern() != .f64_type) or pred_reg_mask.info.scalar == .byte)
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if (has_avx)
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.{ .vp_b, .blendv }
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else if (has_blend)
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.{ .p_b, .blendv }
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else if (pred_reg_mask.info.kind == .all)
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.{ .p_, undefined }
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else
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null
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else if ((pred_reg_mask.info.kind == .all and (elem_ty.toIntern() != .f64_type or !self.hasFeature(.sse2))) or
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pred_reg_mask.info.scalar == .dword)
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if (has_avx)
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.{ .v_ps, .blendv }
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else if (has_blend)
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.{ ._ps, .blendv }
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else if (pred_reg_mask.info.kind == .all)
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.{ ._ps, undefined }
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else
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null
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else if (pred_reg_mask.info.kind == .all or pred_reg_mask.info.scalar == .qword)
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if (has_avx)
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.{ .v_pd, .blendv }
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else if (has_blend)
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.{ ._pd, .blendv }
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else if (pred_reg_mask.info.kind == .all)
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.{ ._pd, undefined }
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else
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null
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else
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null) orelse return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
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if (has_avx) {
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const rhs_alias = if (reuse_mcv.isRegister())
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registerAlias(reuse_mcv.getReg().?, abi_size)
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else rhs: {
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try self.genSetReg(dst_reg, ty, reuse_mcv, .{});
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break :rhs dst_alias;
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};
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if (other_mcv.isBase()) try self.asmRegisterRegisterMemoryRegister(
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mir_tag,
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dst_alias,
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rhs_alias,
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try other_mcv.mem(self, .{ .size = self.memSize(ty) }),
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mask_alias,
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) else try self.asmRegisterRegisterRegisterRegister(
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mir_tag,
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dst_alias,
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rhs_alias,
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registerAlias(if (other_mcv.isRegister())
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other_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, other_mcv), abi_size),
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mask_alias,
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);
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} else if (has_blend) if (other_mcv.isBase()) try self.asmRegisterMemoryRegister(
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mir_tag,
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dst_alias,
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try other_mcv.mem(self, .{ .size = self.memSize(ty) }),
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mask_alias,
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) else try self.asmRegisterRegisterRegister(
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mir_tag,
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dst_alias,
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registerAlias(if (other_mcv.isRegister())
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other_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, other_mcv), abi_size),
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mask_alias,
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) else {
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try self.asmRegisterRegister(.{ mir_tag[0], .@"and" }, dst_alias, mask_alias);
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if (other_mcv.isBase()) try self.asmRegisterMemory(
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.{ mir_tag[0], .andn },
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mask_alias,
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try other_mcv.mem(self, .{ .size = .fromSize(abi_size) }),
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) else try self.asmRegisterRegister(
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.{ mir_tag[0], .andn },
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mask_alias,
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if (other_mcv.isRegister())
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other_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, other_mcv),
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);
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try self.asmRegisterRegister(.{ mir_tag[0], .@"or" }, dst_alias, mask_alias);
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}
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break :result dst_mcv;
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},
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else => {},
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}
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const mask_reg: Register = if (need_xmm0) mask_reg: {
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@ -98192,7 +98326,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
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const dst_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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const mir_tag = @as(?Mir.Inst.FixedTag, switch (ty.childType(zcu).zigTypeTag(zcu)) {
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const mir_tag = @as(?Mir.Inst.FixedTag, switch (elem_ty.zigTypeTag(zcu)) {
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else => null,
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.int => switch (abi_size) {
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0 => unreachable,
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@ -98208,7 +98342,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
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null,
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else => null,
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},
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.float => switch (ty.childType(zcu).floatBits(self.target.*)) {
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.float => switch (elem_ty.floatBits(self.target.*)) {
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else => unreachable,
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16, 80, 128 => null,
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32 => switch (vec_len) {
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@ -98262,30 +98396,20 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
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try self.copyToTmpRegister(ty, lhs_mcv), abi_size),
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mask_alias,
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) else {
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const mir_fixes = @as(?Mir.Inst.Fixes, switch (elem_ty.zigTypeTag(zcu)) {
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else => null,
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.int => .p_,
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.float => switch (elem_ty.floatBits(self.target.*)) {
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32 => ._ps,
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64 => ._pd,
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16, 80, 128 => null,
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else => unreachable,
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},
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}) orelse return self.fail("TODO implement airSelect for {}", .{ty.fmt(pt)});
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try self.asmRegisterRegister(.{ mir_fixes, .@"and" }, dst_alias, mask_alias);
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try self.asmRegisterRegister(.{ mir_tag[0], .@"and" }, dst_alias, mask_alias);
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if (rhs_mcv.isBase()) try self.asmRegisterMemory(
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.{ mir_fixes, .andn },
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.{ mir_tag[0], .andn },
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mask_alias,
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try rhs_mcv.mem(self, .{ .size = .fromSize(abi_size) }),
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) else try self.asmRegisterRegister(
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.{ mir_fixes, .andn },
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.{ mir_tag[0], .andn },
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mask_alias,
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if (rhs_mcv.isRegister())
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rhs_mcv.getReg().?
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else
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try self.copyToTmpRegister(ty, rhs_mcv),
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);
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try self.asmRegisterRegister(.{ mir_fixes, .@"or" }, dst_alias, mask_alias);
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try self.asmRegisterRegister(.{ mir_tag[0], .@"or" }, dst_alias, mask_alias);
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}
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break :result dst_mcv;
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};
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@ -100824,11 +100948,11 @@ const Temp = struct {
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const new_temp_index = cg.next_temp_index;
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cg.temp_type[@intFromEnum(new_temp_index)] = .usize;
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cg.next_temp_index = @enumFromInt(@intFromEnum(new_temp_index) + 1);
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switch (temp.tracking(cg).short) {
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else => |mcv| std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
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const mcv = temp.tracking(cg).short;
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switch (mcv) {
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else => std.debug.panic("{s}: {}\n", .{ @src().fn_name, mcv }),
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.register => |reg| {
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const new_reg =
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try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
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const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
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new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
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try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{
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.base = .{ .reg = reg.to64() },
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@ -100836,33 +100960,22 @@ const Temp = struct {
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});
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},
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.register_offset => |reg_off| {
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const new_reg =
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try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
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const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
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new_temp_index.tracking(cg).* = .init(.{ .register = new_reg });
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try cg.asmRegisterMemory(.{ ._, .lea }, new_reg.to64(), .{
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.base = .{ .reg = reg_off.reg.to64() },
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.mod = .{ .rm = .{ .disp = reg_off.off + off } },
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});
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},
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.load_symbol, .load_frame => {
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const new_reg = try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
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new_temp_index.tracking(cg).* = .init(.{ .register_offset = .{ .reg = new_reg, .off = off } });
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try cg.genSetReg(new_reg, .usize, mcv, .{});
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},
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.lea_symbol => |sym_off| new_temp_index.tracking(cg).* = .init(.{ .lea_symbol = .{
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.sym_index = sym_off.sym_index,
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.off = sym_off.off + off,
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} }),
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.load_frame => |frame_addr| {
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const new_reg =
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try cg.register_manager.allocReg(new_temp_index.toIndex(), abi.RegisterClass.gp);
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new_temp_index.tracking(cg).* = .init(.{ .register_offset = .{
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.reg = new_reg,
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.off = off,
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} });
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try cg.asmRegisterMemory(.{ ._, .mov }, new_reg.to64(), .{
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.base = .{ .frame = frame_addr.index },
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.mod = .{ .rm = .{
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.size = .qword,
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.disp = frame_addr.off,
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} },
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});
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},
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.lea_frame => |frame_addr| new_temp_index.tracking(cg).* = .init(.{ .lea_frame = .{
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.index = frame_addr.index,
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.off = frame_addr.off + off,
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@ -101179,7 +101292,8 @@ const Temp = struct {
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=> return temp.toRegClass(true, .general_purpose, cg),
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.lea_symbol => |sym_off| {
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const off = sym_off.off;
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if (off == 0) return false;
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// hack around linker relocation bugs
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if (false and off == 0) return false;
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try temp.toOffset(-off, cg);
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while (try temp.toRegClass(true, .general_purpose, cg)) {}
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try temp.toOffset(off, cg);
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@ -2008,9 +2008,9 @@ pub const WipNav = struct {
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.decl_const_runtime_bits,
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.decl_const_comptime_state,
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.decl_const_runtime_bits_comptime_state,
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.decl_empty_func,
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.decl_nullary_func,
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.decl_func,
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.decl_empty_func_generic,
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.decl_nullary_func_generic,
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.decl_func_generic,
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=> false,
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.generic_decl_var,
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@ -2626,8 +2626,8 @@ pub fn finishWipNavFunc(
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abbrev_code_buf,
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try dwarf.refAbbrevCode(switch (abbrev_code) {
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else => unreachable,
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.decl_func => .decl_empty_func,
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.decl_instance_func => .decl_instance_empty_func,
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.decl_func => .decl_nullary_func,
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.decl_instance_func => .decl_instance_nullary_func,
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}),
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);
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}
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@ -3012,29 +3012,34 @@ fn updateComptimeNavInner(dwarf: *Dwarf, pt: Zcu.PerThread, nav_index: InternPoo
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if (nav_gop.found_existing) switch (try dwarf.debug_info.declAbbrevCode(wip_nav.unit, nav_gop.value_ptr.*)) {
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.null => {},
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else => unreachable,
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.decl_empty_func, .decl_func, .decl_instance_empty_func, .decl_instance_func => return,
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.decl_empty_func_generic,
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.decl_nullary_func, .decl_func, .decl_instance_nullary_func, .decl_instance_func => return,
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.decl_nullary_func_generic,
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.decl_func_generic,
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.decl_instance_empty_func_generic,
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.decl_instance_nullary_func_generic,
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.decl_instance_func_generic,
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=> dwarf.debug_info.section.getUnit(wip_nav.unit).getEntry(nav_gop.value_ptr.*).clear(),
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} else nav_gop.value_ptr.* = try dwarf.addCommonEntry(wip_nav.unit);
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wip_nav.entry = nav_gop.value_ptr.*;
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const func_type = ip.indexToKey(func.ty).func_type;
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const is_nullary = !func_type.is_var_args and for (0..func_type.param_types.len) |param_index| {
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if (!func_type.paramIsComptime(std.math.cast(u5, param_index) orelse break false)) break false;
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} else true;
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const diw = wip_nav.debug_info.writer(dwarf.gpa);
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try wip_nav.declCommon(if (func_type.param_types.len > 0 or func_type.is_var_args) .{
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try wip_nav.declCommon(if (is_nullary) .{
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.decl = .decl_nullary_func_generic,
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.generic_decl = .generic_decl_func,
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.decl_instance = .decl_instance_nullary_func_generic,
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} else .{
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.decl = .decl_func_generic,
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.generic_decl = .generic_decl_func,
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.decl_instance = .decl_instance_func_generic,
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} else .{
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.decl = .decl_empty_func_generic,
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.generic_decl = .generic_decl_func,
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.decl_instance = .decl_instance_empty_func_generic,
|
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}, &nav, inst_info.file, &decl);
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try wip_nav.refType(.fromInterned(func_type.return_type));
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if (func_type.param_types.len > 0 or func_type.is_var_args) {
|
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if (!is_nullary) {
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for (0..func_type.param_types.len) |param_index| {
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if (std.math.cast(u5, param_index)) |small_param_index|
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if (func_type.paramIsComptime(small_param_index)) continue;
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try wip_nav.abbrevCode(.func_type_param);
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try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
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}
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@ -3568,12 +3573,14 @@ fn updateLazyType(
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};
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try diw.writeByte(@intFromEnum(cc));
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try wip_nav.refType(.fromInterned(func_type.return_type));
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if (!is_nullary) {
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for (0..func_type.param_types.len) |param_index| {
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try wip_nav.abbrevCode(.func_type_param);
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try wip_nav.refType(.fromInterned(func_type.param_types.get(ip)[param_index]));
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}
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if (func_type.is_var_args) try wip_nav.abbrevCode(.is_var_args);
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if (!is_nullary) try uleb128(diw, @intFromEnum(AbbrevCode.null));
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try uleb128(diw, @intFromEnum(AbbrevCode.null));
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}
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},
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.error_set_type => |error_set_type| {
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try wip_nav.abbrevCode(if (error_set_type.names.len == 0) .generated_empty_enum_type else .generated_enum_type);
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@ -4787,9 +4794,9 @@ const AbbrevCode = enum {
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decl_const_runtime_bits,
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decl_const_comptime_state,
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decl_const_runtime_bits_comptime_state,
|
||||
decl_empty_func,
|
||||
decl_nullary_func,
|
||||
decl_func,
|
||||
decl_empty_func_generic,
|
||||
decl_nullary_func_generic,
|
||||
decl_func_generic,
|
||||
generic_decl_var,
|
||||
generic_decl_const,
|
||||
@ -4806,9 +4813,9 @@ const AbbrevCode = enum {
|
||||
decl_instance_const_runtime_bits,
|
||||
decl_instance_const_comptime_state,
|
||||
decl_instance_const_runtime_bits_comptime_state,
|
||||
decl_instance_empty_func,
|
||||
decl_instance_nullary_func,
|
||||
decl_instance_func,
|
||||
decl_instance_empty_func_generic,
|
||||
decl_instance_nullary_func_generic,
|
||||
decl_instance_func_generic,
|
||||
// the rest are unrestricted other than empty variants must not be longer
|
||||
// than the non-empty variant, and so should appear first
|
||||
@ -5019,7 +5026,7 @@ const AbbrevCode = enum {
|
||||
.{ .ZIG_comptime_value, .ref_addr },
|
||||
},
|
||||
},
|
||||
.decl_empty_func = .{
|
||||
.decl_nullary_func = .{
|
||||
.tag = .subprogram,
|
||||
.attrs = decl_abbrev_common_attrs ++ .{
|
||||
.{ .linkage_name, .strp },
|
||||
@ -5044,7 +5051,7 @@ const AbbrevCode = enum {
|
||||
.{ .noreturn, .flag },
|
||||
},
|
||||
},
|
||||
.decl_empty_func_generic = .{
|
||||
.decl_nullary_func_generic = .{
|
||||
.tag = .subprogram,
|
||||
.attrs = decl_abbrev_common_attrs ++ .{
|
||||
.{ .type, .ref_addr },
|
||||
@ -5167,7 +5174,7 @@ const AbbrevCode = enum {
|
||||
.{ .ZIG_comptime_value, .ref_addr },
|
||||
},
|
||||
},
|
||||
.decl_instance_empty_func = .{
|
||||
.decl_instance_nullary_func = .{
|
||||
.tag = .subprogram,
|
||||
.attrs = decl_instance_abbrev_common_attrs ++ .{
|
||||
.{ .linkage_name, .strp },
|
||||
@ -5192,7 +5199,7 @@ const AbbrevCode = enum {
|
||||
.{ .noreturn, .flag },
|
||||
},
|
||||
},
|
||||
.decl_instance_empty_func_generic = .{
|
||||
.decl_instance_nullary_func_generic = .{
|
||||
.tag = .subprogram,
|
||||
.attrs = decl_instance_abbrev_common_attrs ++ .{
|
||||
.{ .type, .ref_addr },
|
||||
|
||||
@ -66,3 +66,23 @@ fn selectArrays() !void {
|
||||
const xyz = @select(f32, x, y, z);
|
||||
try expect(mem.eql(f32, &@as([4]f32, xyz), &[4]f32{ 0.0, 312.1, -145.9, -3381.233 }));
|
||||
}
|
||||
|
||||
test "@select compare result" {
|
||||
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
|
||||
|
||||
const S = struct {
|
||||
fn min(comptime V: type, lhs: V, rhs: V) V {
|
||||
return @select(@typeInfo(V).vector.child, lhs < rhs, lhs, rhs);
|
||||
}
|
||||
|
||||
fn doTheTest() !void {
|
||||
try expect(@reduce(.And, min(@Vector(4, f32), .{ -1, 2, -3, 4 }, .{ 1, -2, 3, -4 }) == @Vector(4, f32){ -1, -2, -3, -4 }));
|
||||
try expect(@reduce(.And, min(@Vector(2, f64), .{ -1, 2 }, .{ 1, -2 }) == @Vector(2, f64){ -1, -2 }));
|
||||
}
|
||||
};
|
||||
|
||||
try S.doTheTest();
|
||||
try comptime S.doTheTest();
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user