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x64: consolidate shifts into single MIR helper fn
This commit is contained in:
Jakub Konka
parent
a9514ae173
commit
9725205859
@ -1708,7 +1708,7 @@ fn airOptionalPayload(self: *Self, inst: Air.Inst.Index) !void {
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// TODO reuse the operand
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const result = try self.copyToRegisterWithInstTracking(inst, optional_ty, operand);
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const shift = @intCast(u8, offset * @sizeOf(usize));
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try self.shiftRegisterRightUnsigned(result.register, @intCast(u8, shift));
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try self.genShiftBinOpMir(optional_ty, result.register, .{ .immediate = @intCast(u8, shift) }, .right);
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break :result result;
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},
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else => return self.fail("TODO implement optional_payload when operand is {}", .{operand}),
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@ -1795,7 +1795,7 @@ fn airUnwrapErrPayload(self: *Self, inst: Air.Inst.Index) !void {
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// TODO reuse operand
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const shift = @intCast(u6, err_abi_size * @sizeOf(usize));
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const result = try self.copyToRegisterWithInstTracking(inst, err_union_ty, operand);
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try self.shiftRegisterRightUnsigned(result.register.to64(), shift);
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try self.genShiftBinOpMir(Type.usize, result.register, .{ .immediate = shift }, .right);
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break :result MCValue{
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.register = registerAlias(result.register, @intCast(u32, payload_ty.abiSize(self.target.*))),
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};
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@ -2307,7 +2307,7 @@ fn airGetUnionTag(self: *Self, inst: Air.Inst.Index) !void {
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else
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0;
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const result = try self.copyToRegisterWithInstTracking(inst, union_ty, operand);
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try self.shiftRegisterRightUnsigned(result.register.to64(), shift);
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try self.genShiftBinOpMir(Type.usize, result.register, .{ .immediate = shift }, .right);
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break :blk MCValue{
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.register = registerAlias(result.register, @intCast(u32, layout.tag_size)),
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};
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@ -2906,7 +2906,7 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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// Shift by struct_field_offset.
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const shift = @intCast(u8, struct_field_offset * @sizeOf(usize));
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try self.shiftRegisterRightUnsigned(dst_mcv.register, shift);
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try self.genShiftBinOpMir(Type.usize, dst_mcv.register, .{ .immediate = shift }, .right);
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// Mask with reg.size() - struct_field_size
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const max_reg_bit_width = Register.rax.size();
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@ -2982,6 +2982,74 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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/// Clobbers .rcx for non-immediate shift value.
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fn genShiftBinOpMir(self: *Self, ty: Type, reg: Register, shift: MCValue, direction: enum { left, right }) !void {
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assert(reg.to64() != .rcx);
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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const signedness: std.builtin.Signedness = blk: {
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if (ty.zigTypeTag() != .Int) break :blk .unsigned;
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break :blk ty.intInfo(self.target.*).signedness;
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};
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const tag: Mir.Inst.Tag = switch (signedness) {
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.signed => switch (direction) {
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.left => Mir.Inst.Tag.sal,
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.right => Mir.Inst.Tag.sar,
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},
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.unsigned => switch (direction) {
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.left => Mir.Inst.Tag.shl,
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.right => Mir.Inst.Tag.shr,
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},
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};
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blk: {
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switch (shift) {
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.immediate => |imm| switch (imm) {
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0 => return,
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1 => {
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_ = try self.addInst(.{
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.tag = tag,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, abi_size),
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.flags = 0b00,
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}).encode(),
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.data = undefined,
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});
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return;
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},
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else => {
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_ = try self.addInst(.{
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.tag = tag,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, abi_size),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = @intCast(u8, imm) },
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});
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return;
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},
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},
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.register => |shift_reg| {
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if (shift_reg == .rcx) break :blk;
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},
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else => {},
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}
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assert(self.register_manager.isRegFree(.rcx));
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try self.register_manager.getReg(.rcx, null);
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try self.genSetReg(Type.u8, .rcx, shift);
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}
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_ = try self.addInst(.{
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.tag = tag,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, abi_size),
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.flags = 0b01,
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}).encode(),
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.data = undefined,
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});
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}
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/// Result is always a register.
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/// Clobbers .rcx for non-immediate rhs, therefore care is needed to spill .rcx upfront.
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/// Asserts .rcx is free.
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@ -3003,9 +3071,6 @@ fn genShiftBinOp(
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assert(rhs_ty.abiSize(self.target.*) == 1);
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const int_info = lhs_ty.intInfo(self.target.*);
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const signedness = int_info.signedness;
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockReg(reg),
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else => null,
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@ -3018,28 +3083,10 @@ fn genShiftBinOp(
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const flags: u2 = blk: {
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if (rhs.isImmediate()) {
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const flags: u2 = switch (rhs.immediate) {
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0 => unreachable, // TODO is this valid?
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1 => 0b00,
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else => 0b10,
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};
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break :blk flags;
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}
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assert(self.register_manager.isRegFree(.rcx));
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try self.register_manager.getReg(.rcx, null);
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try self.genSetReg(rhs_ty, .rcx, rhs);
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const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
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defer self.register_manager.unlockReg(rcx_lock);
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break :blk 0b01;
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};
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const data: Mir.Inst.Data = if (rhs.isImmediate()) .{
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.imm = @intCast(u8, rhs.immediate),
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} else undefined;
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assert(self.register_manager.isRegFree(.rcx));
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try self.register_manager.getReg(.rcx, null);
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const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
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defer self.register_manager.unlockReg(rcx_lock);
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const dst: MCValue = blk: {
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if (maybe_inst) |inst| {
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@ -3054,50 +3101,8 @@ fn genShiftBinOp(
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};
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switch (tag) {
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.shl => switch (signedness) {
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.signed => {
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_ = try self.addInst(.{
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.tag = .sal,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = flags,
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}).encode(),
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.data = data,
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});
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},
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.unsigned => {
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_ = try self.addInst(.{
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.tag = .shl,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = flags,
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}).encode(),
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.data = data,
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});
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},
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},
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.shr => switch (signedness) {
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.signed => {
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = flags,
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}).encode(),
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.data = data,
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});
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},
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.unsigned => {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = dst.register,
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.flags = flags,
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}).encode(),
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.data = data,
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});
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},
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},
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.shl => try self.genShiftBinOpMir(lhs_ty, dst.register, rhs, .left),
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.shr => try self.genShiftBinOpMir(lhs_ty, dst.register, rhs, .right),
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else => unreachable,
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}
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@ -5422,14 +5427,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
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});
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if (nearest_power_of_two > 1) {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = tmp_reg,
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = nearest_power_of_two * 8 },
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});
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try self.genShiftBinOpMir(ty, tmp_reg, .{ .immediate = nearest_power_of_two * 8 }, .right);
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}
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remainder -= nearest_power_of_two;
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@ -6798,29 +6796,6 @@ fn registerAlias(reg: Register, size_bytes: u32) Register {
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}
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}
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/// Shifts register right without sign-extension.
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fn shiftRegisterRightUnsigned(self: *Self, reg: Register, shift: u8) !void {
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if (shift == 0) return;
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if (shift == 1) {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = reg,
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}).encode(),
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.data = undefined,
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});
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} else {
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_ = try self.addInst(.{
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.tag = .shr,
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.ops = (Mir.Ops{
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.reg1 = reg,
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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}
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}
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/// Truncates the value in the register in place.
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/// Clobbers any remaining bits.
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fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
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@ -6829,22 +6804,8 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
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switch (int_info.signedness) {
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.signed => {
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const shift = @intCast(u6, max_reg_bit_width - int_info.bits);
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_ = try self.addInst(.{
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.tag = .sal,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = shift },
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});
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try self.genShiftBinOpMir(Type.isize, reg, .{ .immediate = shift }, .left);
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try self.genShiftBinOpMir(Type.isize, reg, .{ .immediate = shift }, .right);
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},
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.unsigned => {
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const shift = @intCast(u6, max_reg_bit_width - int_info.bits);
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