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https://github.com/ziglang/zig.git
synced 2026-02-01 20:23:38 +00:00
x64: refactor use of inline memcpy
This commit is contained in:
Jakub Konka
parent
09d468b237
commit
94474ec7c7
@ -1782,36 +1782,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
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return self.genSetStack(elem_ty, off, MCValue{ .register = tmp_reg });
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}
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self.register_manager.freezeRegs(&.{ .rax, .rcx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx });
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null });
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const addr_reg = regs[0];
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const count_reg = regs[1];
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const tmp_reg = regs[2];
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rcx, null);
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// TODO allow for abi size to be u64
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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return self.genInlineMemcpy(
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-off,
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.rbp,
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registerAlias(addr_reg, @divExact(reg.size(), 8)),
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count_reg.to64(),
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tmp_reg.to8(),
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);
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try self.genInlineMemcpy(off, .rbp, elem_ty, ptr);
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},
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else => return self.fail("TODO implement loading from register into {}", .{dst_mcv}),
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}
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@ -3626,62 +3597,7 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
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}
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self.register_manager.freezeRegs(&.{ .rax, .rcx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx });
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const addr_reg: Register = blk: {
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switch (mcv) {
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.got_load,
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.direct_load,
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=> |sym_index| {
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const flags: u2 = switch (mcv) {
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.got_load => 0b00,
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.direct_load => 0b01,
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else => unreachable,
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};
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const addr_reg = try self.register_manager.allocReg(null);
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_ = try self.addInst(.{
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.tag = .lea_pie,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.flags = flags,
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}).encode(),
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.data = .{
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.load_reloc = .{
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.atom_index = self.mod_fn.owner_decl.link.macho.local_sym_index,
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.sym_index = sym_index,
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},
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},
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});
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break :blk addr_reg;
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},
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.memory => |addr| {
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const addr_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = addr });
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break :blk addr_reg;
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},
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else => unreachable,
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}
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};
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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const count_reg = regs[0];
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const tmp_reg = regs[1];
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rcx, null);
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// TODO allow for abi_size to be u64
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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try self.genInlineMemcpy(
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-stack_offset,
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.rsp,
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addr_reg.to64(),
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count_reg.to64(),
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tmp_reg.to8(),
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);
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try self.genInlineMemcpy(stack_offset, .rsp, ty, mcv);
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},
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.register => |reg| {
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_ = try self.addInst(.{
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@ -3698,41 +3614,13 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
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const reg = try self.copyToTmpRegister(ty, mcv);
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return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
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},
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.stack_offset => |off| {
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.stack_offset => {
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if (abi_size <= 8) {
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const reg = try self.copyToTmpRegister(ty, mcv);
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return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
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}
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self.register_manager.freezeRegs(&.{ .rax, .rcx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx });
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null });
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const addr_reg = regs[0];
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const count_reg = regs[1];
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const tmp_reg = regs[2];
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rcx, null);
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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// TODO allow for abi_size to be u64
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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try self.genInlineMemcpy(
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-stack_offset,
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.rsp,
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addr_reg.to64(),
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count_reg.to64(),
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tmp_reg.to8(),
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);
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try self.genInlineMemcpy(stack_offset, .rsp, ty, mcv);
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},
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else => return self.fail("TODO implement args on stack for {}", .{mcv}),
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}
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@ -3847,65 +3735,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerErro
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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}
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rcx, null);
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self.register_manager.freezeRegs(&.{ .rax, .rcx, .rbp });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx, .rbp });
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const addr_reg: Register = blk: {
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switch (mcv) {
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.memory => |addr| {
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const reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = addr });
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break :blk reg;
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},
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.direct_load,
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.got_load,
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=> |sym_index| {
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const flags: u2 = switch (mcv) {
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.got_load => 0b00,
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.direct_load => 0b01,
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else => unreachable,
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};
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const addr_reg = try self.register_manager.allocReg(null);
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_ = try self.addInst(.{
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.tag = .lea_pie,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.flags = flags,
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}).encode(),
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.data = .{
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.load_reloc = .{
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.atom_index = self.mod_fn.owner_decl.link.macho.local_sym_index,
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.sym_index = sym_index,
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},
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},
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});
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break :blk addr_reg;
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},
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else => {
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return self.fail("TODO implement memcpy for setting stack from {}", .{mcv});
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},
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}
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};
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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const count_reg = regs[0];
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const tmp_reg = regs[1];
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// TODO allow for abi_size to be u64
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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return self.genInlineMemcpy(
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-stack_offset,
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.rbp,
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addr_reg.to64(),
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count_reg.to64(),
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tmp_reg.to8(),
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);
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try self.genInlineMemcpy(stack_offset, .rbp, ty, mcv);
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},
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.ptr_stack_offset => {
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const reg = try self.copyToTmpRegister(ty, mcv);
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@ -3922,48 +3752,89 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerErro
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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}
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self.register_manager.freezeRegs(&.{ .rax, .rcx, .rbp });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx, .rbp });
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const regs = try self.register_manager.allocRegs(3, .{ null, null, null });
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const addr_reg = regs[0];
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const count_reg = regs[1];
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const tmp_reg = regs[2];
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rcx, null);
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg.to64(),
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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// TODO allow for abi_size to be u64
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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return self.genInlineMemcpy(
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-stack_offset,
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.rbp,
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addr_reg.to64(),
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count_reg.to64(),
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tmp_reg.to8(),
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);
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try self.genInlineMemcpy(stack_offset, .rbp, ty, mcv);
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},
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}
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}
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fn genInlineMemcpy(
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self: *Self,
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stack_offset: i32,
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stack_reg: Register,
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addr_reg: Register,
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count_reg: Register,
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tmp_reg: Register,
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) InnerError!void {
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fn genInlineMemcpy(self: *Self, stack_offset: i32, stack_reg: Register, ty: Type, val: MCValue) InnerError!void {
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const abi_size = ty.abiSize(self.target.*);
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rcx, null);
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self.register_manager.freezeRegs(&.{ .rax, .rcx, .rbp });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rcx, .rbp });
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const addr_reg: Register = blk: {
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switch (val) {
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.memory => |addr| {
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const reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = addr });
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break :blk reg;
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},
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.direct_load,
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.got_load,
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=> |sym_index| {
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const flags: u2 = switch (val) {
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.got_load => 0b00,
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.direct_load => 0b01,
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else => unreachable,
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};
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const addr_reg = (try self.register_manager.allocReg(null)).to64();
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_ = try self.addInst(.{
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.tag = .lea_pie,
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.ops = (Mir.Ops{
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.reg1 = addr_reg,
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.flags = flags,
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}).encode(),
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.data = .{
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.load_reloc = .{
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.atom_index = self.mod_fn.owner_decl.link.macho.local_sym_index,
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.sym_index = sym_index,
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},
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},
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});
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break :blk addr_reg;
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},
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.stack_offset => |off| {
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const addr_reg = (try self.register_manager.allocReg(null)).to64();
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = addr_reg,
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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break :blk addr_reg;
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},
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.register => |reg| {
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const addr_reg = try self.register_manager.allocReg(null);
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
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.reg2 = reg,
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}).encode(),
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.data = undefined,
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});
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break :blk addr_reg.to64();
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},
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else => {
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return self.fail("TODO implement memcpy for setting stack from {}", .{val});
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},
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}
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};
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self.register_manager.freezeRegs(&.{addr_reg});
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defer self.register_manager.unfreezeRegs(&.{addr_reg});
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const regs = try self.register_manager.allocRegs(2, .{ null, null });
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const count_reg = regs[0].to64();
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const tmp_reg = regs[1].to8();
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try self.genSetReg(Type.u32, count_reg, .{ .immediate = @intCast(u32, abi_size) });
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// mov rcx, 0
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_ = try self.addInst(.{
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.tag = .mov,
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@ -4016,7 +3887,7 @@ fn genInlineMemcpy(
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.reg1 = stack_reg,
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.reg2 = tmp_reg.to8(),
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}).encode(),
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.data = .{ .imm = @bitCast(u32, stack_offset) },
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.data = .{ .imm = @bitCast(u32, -stack_offset) },
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});
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// add rcx, 1
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@ -4959,8 +4830,8 @@ fn parseRegName(name: []const u8) ?Register {
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return std.meta.stringToEnum(Register, name);
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}
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/// Returns register wide enough to hold at least `size_bytes`.
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fn registerAlias(reg: Register, size_bytes: u32) Register {
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// For x86_64 we have to pick a smaller register alias depending on abi size.
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if (size_bytes == 0) {
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unreachable; // should be comptime known
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} else if (size_bytes <= 1) {
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