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Merge pull request #11723 from koachan/sparc64-codegen
stage2: sparc64: Small refactorings and stack pointer accounting fixes
This commit is contained in:
Jakub Konka
GitHub
commit
90f12a9186
@ -352,7 +352,7 @@ fn gen(self: *Self) !void {
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if (cc != .Naked) {
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// TODO Finish function prologue and epilogue for sparc64.
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// save %sp, stack_save_area, %sp
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// save %sp, stack_reserved_area, %sp
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const save_inst = try self.addInst(.{
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.tag = .save,
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.data = .{
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@ -360,7 +360,7 @@ fn gen(self: *Self) !void {
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.is_imm = true,
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.rd = .sp,
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.rs1 = .sp,
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.rs2_or_imm = .{ .imm = -abi.stack_save_area },
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.rs2_or_imm = .{ .imm = -abi.stack_reserved_area },
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},
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},
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});
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@ -407,7 +407,7 @@ fn gen(self: *Self) !void {
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}
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// Backpatch stack offset
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const total_stack_size = self.max_end_stack + abi.stack_save_area; // TODO + self.saved_regs_stack_space;
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const total_stack_size = self.max_end_stack + abi.stack_reserved_area;
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const stack_size = mem.alignForwardGeneric(u32, total_stack_size, self.stack_align);
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if (math.cast(i13, stack_size)) |size| {
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self.mir_instructions.set(save_inst, .{
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@ -1677,7 +1677,7 @@ fn binOp(
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.cmp_eq => .subcc,
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.cmp_eq => .cmp,
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else => unreachable,
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};
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@ -1891,7 +1891,7 @@ fn binOpImmediate(
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.is_imm = true,
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .imm = @intCast(i13, rhs.immediate) },
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.rs2_or_imm = .{ .imm = @intCast(u12, rhs.immediate) },
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},
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},
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.sllx => .{
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@ -1903,6 +1903,13 @@ fn binOpImmediate(
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.rs2_or_imm = .{ .imm = @intCast(u6, rhs.immediate) },
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},
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},
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.cmp => .{
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.arithmetic_2op = .{
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.is_imm = true,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .imm = @intCast(u12, rhs.immediate) },
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},
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},
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else => unreachable,
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};
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@ -2012,6 +2019,13 @@ fn binOpRegister(
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.rs2_or_imm = .{ .rs2 = rhs_reg },
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},
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},
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.cmp => .{
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.arithmetic_2op = .{
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.is_imm = false,
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.rs1 = lhs_reg,
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.rs2_or_imm = .{ .rs2 = rhs_reg },
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},
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},
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else => unreachable,
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};
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@ -2285,7 +2299,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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return self.genSetReg(ty, reg, .{ .immediate = 0xaaaaaaaaaaaaaaaa });
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},
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.ptr_stack_offset => |off| {
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const simm13 = math.cast(u12, off) catch
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const simm13 = math.cast(u12, off + abi.stack_bias + abi.stack_reserved_area) catch
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return self.fail("TODO larger stack offsets", .{});
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_ = try self.addInst(.{
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@ -2303,12 +2317,11 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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.immediate => |x| {
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if (x <= math.maxInt(u12)) {
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_ = try self.addInst(.{
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.tag = .@"or",
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.tag = .mov,
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.data = .{
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.arithmetic_3op = .{
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.arithmetic_2op = .{
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.is_imm = true,
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.rd = reg,
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.rs1 = .g0,
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.rs1 = reg,
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.rs2_or_imm = .{ .imm = @truncate(u12, x) },
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},
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},
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@ -2400,14 +2413,12 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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if (src_reg.id() == reg.id())
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return;
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// or %g0, src, dst (aka mov src, dst)
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_ = try self.addInst(.{
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.tag = .@"or",
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.tag = .mov,
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.data = .{
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.arithmetic_3op = .{
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.arithmetic_2op = .{
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.is_imm = false,
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.rd = reg,
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.rs1 = .g0,
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.rs1 = reg,
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.rs2_or_imm = .{ .rs2 = src_reg },
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},
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},
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@ -2420,7 +2431,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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try self.genLoad(reg, reg, i13, 0, ty.abiSize(self.target.*));
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},
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.stack_offset => |off| {
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const real_offset = off + abi.stack_bias + abi.stack_save_area;
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const real_offset = off + abi.stack_bias + abi.stack_reserved_area;
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const simm13 = math.cast(i13, real_offset) catch
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return self.fail("TODO larger stack offsets", .{});
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try self.genLoad(reg, .sp, i13, simm13, ty.abiSize(self.target.*));
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@ -2454,7 +2465,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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return self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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},
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.register => |reg| {
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const real_offset = stack_offset + abi.stack_bias + abi.stack_save_area;
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const real_offset = stack_offset + abi.stack_bias + abi.stack_reserved_area;
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const simm13 = math.cast(i13, real_offset) catch
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return self.fail("TODO larger stack offsets", .{});
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return self.genStore(reg, .sp, i13, simm13, abi_size);
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@ -2625,12 +2636,11 @@ fn isErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
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};
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_ = try self.addInst(.{
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.tag = .subcc,
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.data = .{ .arithmetic_3op = .{
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.tag = .cmp,
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.data = .{ .arithmetic_2op = .{
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.is_imm = true,
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.rs1 = reg_mcv.register,
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.rs2_or_imm = .{ .imm = 0 },
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.rd = .g0,
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} },
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});
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@ -3163,12 +3173,11 @@ fn truncRegister(
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},
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64 => {
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_ = try self.addInst(.{
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.tag = .@"or",
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.tag = .mov,
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.data = .{
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.arithmetic_3op = .{
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.arithmetic_2op = .{
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.is_imm = true,
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.rd = dest_reg,
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.rs1 = .g0,
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.rs1 = dest_reg,
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.rs2_or_imm = .{ .rs2 = operand_reg },
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},
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},
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@ -121,6 +121,10 @@ pub fn emitMir(
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.subcc => try emit.mirArithmetic3Op(inst),
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.tcc => try emit.mirTrap(inst),
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.cmp => try emit.mirArithmetic2Op(inst),
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.mov => try emit.mirArithmetic2Op(inst),
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}
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}
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}
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@ -179,12 +183,16 @@ fn mirArithmetic2Op(emit: *Emit, inst: Mir.Inst.Index) !void {
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const imm = data.rs2_or_imm.imm;
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switch (tag) {
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.@"return" => try emit.writeInstruction(Instruction.@"return"(i13, rs1, imm)),
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.cmp => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, .g0)),
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.mov => try emit.writeInstruction(Instruction.@"or"(i13, .g0, imm, rs1)),
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else => unreachable,
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}
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} else {
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const rs2 = data.rs2_or_imm.rs2;
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switch (tag) {
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.@"return" => try emit.writeInstruction(Instruction.@"return"(Register, rs1, rs2)),
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.cmp => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, .g0)),
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.mov => try emit.writeInstruction(Instruction.@"or"(Register, .g0, rs2, rs1)),
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else => unreachable,
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}
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}
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@ -125,9 +125,23 @@ pub const Inst = struct {
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/// This uses the trap field.
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tcc,
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// TODO add synthetic instructions
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// TODO add cmp synthetic instruction to avoid wasting a register when
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// comparing with subcc
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// SPARCv9 synthetic instructions
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// Note that the instructions that is added here are only those that
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// will simplify backend development. Synthetic instructions that is
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// only used to provide syntactic sugar in, e.g. inline assembly should
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// be deconstructed inside the parser instead.
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// See also: G.3 Synthetic Instructions
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// TODO add more synthetic instructions
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/// Comparison
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/// This uses the arithmetic_2op field.
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cmp, // cmp rs1, rs2/imm -> subcc rs1, rs2/imm, %g0
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/// Copy register/immediate contents to another register
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/// This uses the arithmetic_2op field, with rs1
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/// being the *destination* register.
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// TODO is it okay to abuse rs1 in this way?
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mov, // mov rs2/imm, rs1 -> or %g0, rs2/imm, rs1
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};
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/// The position of an MIR instruction within the `Mir` instructions array.
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@ -3,17 +3,17 @@ const bits = @import("bits.zig");
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const Register = bits.Register;
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const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
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// SPARCv9 stack constants.
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// SPARCv9 SysV ABI stack constants.
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// See: Registers and the Stack Frame, page 3P-8, SCD 2.4.1.
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// On SPARCv9, %sp points to top of stack + stack bias,
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// and %fp points to top of previous frame + stack bias.
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// The ABI specifies that %sp points to top of stack - stack bias,
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// and %fp points to top of previous frame - stack bias.
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pub const stack_bias = 2047;
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// The first 176 bytes of the stack is reserved for register saving purposes.
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// SPARCv9 requires to reserve space in the stack for the first six arguments,
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// even though they are usually passed in registers.
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pub const stack_save_area = 176;
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// The first 128 bytes of the stack is reserved for register saving purposes.
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// The ABI also requires to reserve space in the stack for the first six
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// outgoing arguments, even though they are usually passed in registers.
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pub const stack_reserved_area = 128 + 48;
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// There are no callee-preserved registers since the windowing
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// mechanism already takes care of them.
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