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Merge pull request #21505 from alexrp/cpu-features-exts

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`update_cpu_features`: Add support for parsing `DefaultExts` as used for aarch64.
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Alex Rønne Petersen 2024-10-03 00:41:48 +02:00 committed by GitHub
commit 8ee52f99ce
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3 changed files with 33 additions and 77 deletions
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86
lib/std/Target/aarch64.zig
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@ -1373,6 +1373,7 @@ pub const all_features = blk: {
.llvm_name = "v8.3a",
.description = "Support ARM v8.3a architecture",
.dependencies = featureSet(&[_]Feature{
.ccidx,
.complxnum,
.jsconv,
.pauth,
@ -1409,6 +1410,7 @@ pub const all_features = blk: {
.predres,
.sb,
.specrestrict,
.ssbs,
.v8_4a,
}),
};
@ -1470,18 +1472,26 @@ pub const all_features = blk: {
.llvm_name = "v8r",
.description = "Support ARM v8r architecture",
.dependencies = featureSet(&[_]Feature{
.ccidx,
.ccpp,
.complxnum,
.contextidr_el2,
.crc,
.dit,
.dotprod,
.flagm,
.fp16fml,
.jsconv,
.lse,
.pan_rwv,
.pauth,
.ras,
.rcpc_immo,
.rdm,
.sb,
.sel2,
.specrestrict,
.ssbs,
.tlb_rmi,
.tracev8_4,
.uaops,
@ -1491,6 +1501,7 @@ pub const all_features = blk: {
.llvm_name = "v9.1a",
.description = "Support ARM v9.1a architecture",
.dependencies = featureSet(&[_]Feature{
.rme,
.v8_6a,
.v9a,
}),
@ -1499,6 +1510,7 @@ pub const all_features = blk: {
.llvm_name = "v9.2a",
.description = "Support ARM v9.2a architecture",
.dependencies = featureSet(&[_]Feature{
.mec,
.v8_7a,
.v9_1a,
}),
@ -1524,6 +1536,8 @@ pub const all_features = blk: {
.description = "Support ARM v9.5a architecture",
.dependencies = featureSet(&[_]Feature{
.cpa,
.faminmax,
.lut,
.v9_4a,
}),
};
@ -1531,6 +1545,7 @@ pub const all_features = blk: {
.llvm_name = "v9a",
.description = "Support ARM v9a architecture",
.dependencies = featureSet(&[_]Feature{
.sve2,
.v8_5a,
}),
};
@ -1607,7 +1622,6 @@ pub const cpu = struct {
.aggressive_fma,
.alu_lsl_fast,
.arith_bcc_fusion,
.ccidx,
.cmp_bcc_fusion,
.fullfp16,
.fuse_address,
@ -1618,7 +1632,6 @@ pub const cpu = struct {
.perfmon,
.rand,
.sha3,
.ssbs,
.store_pair_suppress,
.stp_aligned_only,
.use_postra_scheduler,
@ -1633,7 +1646,6 @@ pub const cpu = struct {
.aggressive_fma,
.alu_lsl_fast,
.arith_bcc_fusion,
.ccidx,
.cmp_bcc_fusion,
.fullfp16,
.fuse_address,
@ -1647,7 +1659,6 @@ pub const cpu = struct {
.rand,
.sha3,
.sm4,
.ssbs,
.store_pair_suppress,
.stp_aligned_only,
.use_postra_scheduler,
@ -1662,7 +1673,6 @@ pub const cpu = struct {
.aggressive_fma,
.alu_lsl_fast,
.arith_bcc_fusion,
.ccidx,
.cmp_bcc_fusion,
.cssc,
.enable_select_opt,
@ -1678,7 +1688,6 @@ pub const cpu = struct {
.rand,
.sha3,
.sm4,
.ssbs,
.store_pair_suppress,
.stp_aligned_only,
.use_postra_scheduler,
@ -1819,7 +1828,6 @@ pub const cpu = struct {
.fuse_literals,
.perfmon,
.sha3,
.ssbs,
.store_pair_suppress,
.v8_6a,
.zcm,
@ -1846,7 +1854,6 @@ pub const cpu = struct {
.hcx,
.perfmon,
.sha3,
.ssbs,
.store_pair_suppress,
.v8_6a,
.zcm,
@ -1873,7 +1880,6 @@ pub const cpu = struct {
.hcx,
.perfmon,
.sha3,
.ssbs,
.store_pair_suppress,
.v8_6a,
.zcm,
@ -1990,7 +1996,6 @@ pub const cpu = struct {
.fuse_literals,
.perfmon,
.sha3,
.ssbs,
.store_pair_suppress,
.v8_6a,
.zcm,
@ -2017,7 +2022,6 @@ pub const cpu = struct {
.hcx,
.perfmon,
.sha3,
.ssbs,
.store_pair_suppress,
.v8_6a,
.zcm,
@ -2106,7 +2110,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -2116,7 +2119,6 @@ pub const cpu = struct {
.mte,
.perfmon,
.predictable_select_expensive,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -2149,7 +2151,6 @@ pub const cpu = struct {
.llvm_name = "cortex-a510",
.features = featureSet(&[_]Feature{
.bf16,
.ccidx,
.ete,
.fp16fml,
.fuse_adrp_add,
@ -2157,7 +2158,6 @@ pub const cpu = struct {
.i8mm,
.mte,
.perfmon,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -2167,14 +2167,12 @@ pub const cpu = struct {
.name = "cortex_a520",
.llvm_name = "cortex-a520",
.features = featureSet(&[_]Feature{
.ccidx,
.ete,
.fp16fml,
.fuse_adrp_add,
.fuse_aes,
.mte,
.perfmon,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2184,14 +2182,12 @@ pub const cpu = struct {
.name = "cortex_a520ae",
.llvm_name = "cortex-a520ae",
.features = featureSet(&[_]Feature{
.ccidx,
.ete,
.fp16fml,
.fuse_adrp_add,
.fuse_aes,
.mte,
.perfmon,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2294,7 +2290,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2305,7 +2300,6 @@ pub const cpu = struct {
.mte,
.perfmon,
.predictable_select_expensive,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -2317,7 +2311,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2329,7 +2322,6 @@ pub const cpu = struct {
.perfmon,
.predictable_select_expensive,
.spe,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -2357,7 +2349,6 @@ pub const cpu = struct {
.llvm_name = "cortex-a720",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2369,7 +2360,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2380,7 +2370,6 @@ pub const cpu = struct {
.llvm_name = "cortex-a720ae",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2392,7 +2381,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2403,7 +2391,6 @@ pub const cpu = struct {
.llvm_name = "cortex-a725",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2415,7 +2402,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2592,15 +2578,8 @@ pub const cpu = struct {
.llvm_name = "cortex-r82",
.features = featureSet(&[_]Feature{
.ccdp,
.complxnum,
.dotprod,
.fp16fml,
.jsconv,
.perfmon,
.predres,
.rdm,
.sb,
.ssbs,
.use_postra_scheduler,
.v8r,
}),
@ -2610,15 +2589,8 @@ pub const cpu = struct {
.llvm_name = "cortex-r82ae",
.features = featureSet(&[_]Feature{
.ccdp,
.complxnum,
.dotprod,
.fp16fml,
.jsconv,
.perfmon,
.predres,
.rdm,
.sb,
.ssbs,
.use_postra_scheduler,
.v8r,
}),
@ -2678,7 +2650,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2689,7 +2660,6 @@ pub const cpu = struct {
.mte,
.perfmon,
.predictable_select_expensive,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -2701,7 +2671,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -2712,7 +2681,6 @@ pub const cpu = struct {
.perfmon,
.predictable_select_expensive,
.spe,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -2723,7 +2691,6 @@ pub const cpu = struct {
.llvm_name = "cortex-x4",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -2734,7 +2701,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2745,7 +2711,6 @@ pub const cpu = struct {
.llvm_name = "cortex-x925",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -2756,7 +2721,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -2935,7 +2899,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -2948,7 +2911,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.rand,
.spe,
.ssbs,
.sve2_bitperm,
.use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler,
@ -2979,7 +2941,6 @@ pub const cpu = struct {
.alu_lsl_fast,
.bf16,
.ccdp,
.ccidx,
.enable_select_opt,
.fp16fml,
.fuse_adrp_add,
@ -3042,7 +3003,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -3052,7 +3012,6 @@ pub const cpu = struct {
.mte,
.perfmon,
.predictable_select_expensive,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9a,
@ -3063,7 +3022,6 @@ pub const cpu = struct {
.llvm_name = "neoverse-n3",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -3075,7 +3033,6 @@ pub const cpu = struct {
.rand,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -3090,7 +3047,6 @@ pub const cpu = struct {
.alu_lsl_fast,
.bf16,
.ccdp,
.ccidx,
.enable_select_opt,
.fp16fml,
.fuse_adrp_add,
@ -3115,7 +3071,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.bf16,
.ccidx,
.cmp_bcc_fusion,
.enable_select_opt,
.ete,
@ -3128,7 +3083,6 @@ pub const cpu = struct {
.predictable_select_expensive,
.rand,
.spe,
.ssbs,
.sve2_bitperm,
.use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler,
@ -3141,7 +3095,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.brbe,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -3152,10 +3105,8 @@ pub const cpu = struct {
.perfmon,
.predictable_select_expensive,
.rand,
.rme,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -3167,7 +3118,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.brbe,
.ccidx,
.enable_select_opt,
.ete,
.fp16fml,
@ -3178,10 +3128,8 @@ pub const cpu = struct {
.perfmon,
.predictable_select_expensive,
.rand,
.rme,
.spe,
.spe_eef,
.ssbs,
.sve2_bitperm,
.use_postra_scheduler,
.v9_2a,
@ -3192,7 +3140,6 @@ pub const cpu = struct {
.llvm_name = "oryon-1",
.features = featureSet(&[_]Feature{
.aes,
.ccidx,
.enable_select_opt,
.fp16fml,
.fuse_address,
@ -3204,7 +3151,6 @@ pub const cpu = struct {
.sha3,
.sm4,
.spe,
.ssbs,
.use_postra_scheduler,
.v8_6a,
}),
@ -3215,7 +3161,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.aes,
.alu_lsl_fast,
.ccidx,
.perfmon,
.predictable_select_expensive,
.sha2,
@ -3262,7 +3207,6 @@ pub const cpu = struct {
.aggressive_fma,
.arith_bcc_fusion,
.balance_fp_ops,
.ccidx,
.perfmon,
.predictable_select_expensive,
.sha2,

1
lib/std/Target/arm.zig
View File

@ -2254,7 +2254,6 @@ pub const cpu = struct {
.llvm_name = "cortex-m85",
.features = featureSet(&[_]Feature{
.dsp,
.trustzone,
.use_misched,
.v8_1m_main,
}),

23
tools/update_cpu_features.zig
View File

@ -61,10 +61,6 @@ const llvm_targets = [_]LlvmTarget{
.zig_name = "contextidr_el2",
.desc = "Enable RW operand Context ID Register (EL2)",
},
.{
.llvm_name = "v8a",
.extra_deps = &.{"neon"},
},
.{
.llvm_name = "neoversee1",
.flatten = true,
@ -487,7 +483,6 @@ const llvm_targets = [_]LlvmTarget{
.{
.llvm_name = "cortex-m85",
.omit_deps = &.{ "mve_fp", "pacbti", "fp_armv8d16" },
.extra_deps = &.{"trustzone"},
},
.{
.llvm_name = "cortex-x1c",
@ -1436,6 +1431,24 @@ fn processOneTarget(job: Job) anyerror!void {
try deps.append(other_zig_name);
}
}
// This is used by AArch64.
if (kv.value_ptr.object.get("DefaultExts")) |exts_val| {
for (exts_val.array.items) |ext| {
const other_key = ext.object.get("def").?.string;
const other_obj = &root_map.getPtr(other_key).?.object;
const other_llvm_name = other_obj.get("Name").?.string;
const other_zig_name = (try llvmFeatureNameToZigNameOmit(
arena,
llvm_target,
other_llvm_name,
)) orelse continue;
for (omit_deps) |omit_dep| {
if (mem.eql(u8, other_zig_name, omit_dep)) break;
} else {
try deps.append(other_zig_name);
}
}
}
for (extra_deps) |extra_dep| {
try deps.append(extra_dep);
}