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allow comptime_int in math.shl and math.shr
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parent
10e33b3536
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8e0670198b
16
std/math.zig
16
std/math.zig
@ -288,10 +288,8 @@ pub fn shl(comptime T: type, a: T, shift_amt: var) T {
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const abs_shift_amt = absCast(shift_amt);
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const casted_shift_amt = if (abs_shift_amt >= T.bit_count) return 0 else @intCast(Log2Int(T), abs_shift_amt);
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if (@typeOf(shift_amt).is_signed) {
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if (shift_amt >= 0) {
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return a << casted_shift_amt;
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} else {
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if (@typeOf(shift_amt) == comptime_int or @typeOf(shift_amt).is_signed) {
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if (shift_amt < 0) {
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return a >> casted_shift_amt;
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}
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}
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@ -304,6 +302,10 @@ test "math.shl" {
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testing.expect(shl(u8, 0b11111111, usize(8)) == 0);
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testing.expect(shl(u8, 0b11111111, usize(9)) == 0);
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testing.expect(shl(u8, 0b11111111, isize(-2)) == 0b00111111);
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testing.expect(shl(u8, 0b11111111, 3) == 0b11111000);
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testing.expect(shl(u8, 0b11111111, 8) == 0);
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testing.expect(shl(u8, 0b11111111, 9) == 0);
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testing.expect(shl(u8, 0b11111111, -2) == 0b00111111);
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}
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/// Shifts right. Overflowed bits are truncated.
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@ -312,7 +314,7 @@ pub fn shr(comptime T: type, a: T, shift_amt: var) T {
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const abs_shift_amt = absCast(shift_amt);
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const casted_shift_amt = if (abs_shift_amt >= T.bit_count) return 0 else @intCast(Log2Int(T), abs_shift_amt);
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if (@typeOf(shift_amt).is_signed) {
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if (@typeOf(shift_amt) == comptime_int or @typeOf(shift_amt).is_signed) {
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if (shift_amt >= 0) {
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return a >> casted_shift_amt;
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} else {
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@ -328,6 +330,10 @@ test "math.shr" {
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testing.expect(shr(u8, 0b11111111, usize(8)) == 0);
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testing.expect(shr(u8, 0b11111111, usize(9)) == 0);
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testing.expect(shr(u8, 0b11111111, isize(-2)) == 0b11111100);
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testing.expect(shr(u8, 0b11111111, 3) == 0b00011111);
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testing.expect(shr(u8, 0b11111111, 8) == 0);
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testing.expect(shr(u8, 0b11111111, 9) == 0);
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testing.expect(shr(u8, 0b11111111, -2) == 0b11111100);
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}
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/// Rotates right. Only unsigned values can be rotated.
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