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AstGen: preserve inferred ptr result loc for breaks
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@ -9915,7 +9915,7 @@ const GenZir = struct {
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.inferred_ptr => |ptr| {
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gz.rl_ty_inst = .none;
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gz.rl_ptr = ptr;
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gz.break_result_loc = .{ .block_ptr = gz };
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gz.break_result_loc = parent_rl;
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},
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.block_ptr => |parent_block_scope| {
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22
src/Sema.zig
22
src/Sema.zig
@ -2881,6 +2881,28 @@ fn zirResolveInferredAlloc(sema: *Sema, block: *Block, inst: Zir.Inst.Index) Com
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if (var_is_mut) {
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try sema.validateVarType(block, ty_src, final_elem_ty, false);
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// The value might have been bitcasted into a comptime only
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// pointer type such as `*@Type(.EnumLiteral)` so we must now
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// update all the stores to not give backends invalid AIR.
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var air_tags = sema.air_instructions.items(.tag);
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var air_data = sema.air_instructions.items(.data);
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var peer_inst_index: usize = 0;
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var i = ptr_inst;
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while (i < air_tags.len and peer_inst_index < peer_inst_list.len) : (i += 1) {
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if (air_tags[i] != .store) continue;
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if (air_data[i].bin_op.rhs == peer_inst_list[peer_inst_index]) {
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peer_inst_index += 1;
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_ = (try sema.resolveMaybeUndefVal(block, .unneeded, air_data[i].bin_op.rhs)) orelse continue;
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const coerced_val = try sema.coerce(block, final_elem_ty, air_data[i].bin_op.rhs, .unneeded);
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air_tags = sema.air_instructions.items(.tag);
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air_data = sema.air_instructions.items(.data);
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air_data[i].bin_op.lhs = ptr;
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air_data[i].bin_op.rhs = coerced_val;
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}
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}
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} else ct: {
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// Detect if the value is comptime known. In such case, the
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// last 3 AIR instructions of the block will look like this:
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@ -933,3 +933,15 @@ test "try in labeled block doesn't cast to wrong type" {
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};
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_ = s;
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}
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test "comptime int in switch in catch is casted to correct inferred type" {
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
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var a: error{ A, B }!u64 = 0;
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var b = a catch |err| switch (err) {
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error.A => 0,
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else => unreachable,
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};
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_ = b;
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}
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