From 89e107ee4ecdc888007958bd353e293856f0766f Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Mon, 20 Jan 2020 23:14:35 -0500 Subject: [PATCH] uncomment all the archs in target.zig --- BRANCH_TODO | 31 ---------------- lib/std/target.zig | 79 ++++++++++++++++++++-------------------- lib/std/target/riscv.zig | 19 ++++++++++ 3 files changed, 59 insertions(+), 70 deletions(-) diff --git a/BRANCH_TODO b/BRANCH_TODO index 2e92089e3a..5b5cf506f4 100644 --- a/BRANCH_TODO +++ b/BRANCH_TODO @@ -2,35 +2,4 @@ Finish these thigns before merging teh branch * zig targets - use non-reflection based cpu detection? - * finish refactoring target/arch/* - -const riscv32_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{ - &std.target.riscv.feature_a, - &std.target.riscv.feature_c, - &std.target.riscv.feature_d, - &std.target.riscv.feature_f, - &std.target.riscv.feature_m, - &std.target.riscv.feature_relax, -}; - -const riscv64_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{ - &std.target.riscv.feature_bit64, - &std.target.riscv.feature_a, - &std.target.riscv.feature_c, - &std.target.riscv.feature_d, - &std.target.riscv.feature_f, - &std.target.riscv.feature_m, - &std.target.riscv.feature_relax, -}; - -// Same as above but without sse. -const i386_default_features_freestanding: []*const std.target.Feature = &[_]*const std.target.Feature{ - &std.target.x86.feature_cmov, - &std.target.x86.feature_cx8, - &std.target.x86.feature_fxsr, - &std.target.x86.feature_mmx, - &std.target.x86.feature_nopl, - &std.target.x86.feature_slowUnalignedMem16, - &std.target.x86.feature_x87, -}; diff --git a/lib/std/target.zig b/lib/std/target.zig index d49d395dda..9b83384723 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -413,21 +413,21 @@ pub const Target = union(enum) { /// All CPU features Zig is aware of, sorted lexicographically by name. pub fn allFeaturesList(arch: Arch) []const Cpu.Feature { return switch (arch) { - // TODO .arm, .armeb, .thumb, .thumbeb => arm.all_features, + .arm, .armeb, .thumb, .thumbeb => arm.all_features, .aarch64, .aarch64_be, .aarch64_32 => &aarch64.all_features, - // TODO .avr => avr.all_features, - // TODO .bpfel, .bpfeb => bpf.all_features, - // TODO .hexagon => hexagon.all_features, - // TODO .mips, .mipsel, .mips64, .mips64el => mips.all_features, - // TODO .msp430 => msp430.all_features, - // TODO .powerpc, .powerpc64, .powerpc64le => powerpc.all_features, - // TODO .amdgcn => amdgpu.all_features, - // TODO .riscv32, .riscv64 => riscv.all_features, - // TODO .sparc, .sparcv9, .sparcel => sparc.all_features, - // TODO .s390x => systemz.all_features, + .avr => avr.all_features, + .bpfel, .bpfeb => bpf.all_features, + .hexagon => hexagon.all_features, + .mips, .mipsel, .mips64, .mips64el => mips.all_features, + .msp430 => msp430.all_features, + .powerpc, .powerpc64, .powerpc64le => powerpc.all_features, + .amdgcn => amdgpu.all_features, + .riscv32, .riscv64 => riscv.all_features, + .sparc, .sparcv9, .sparcel => sparc.all_features, + .s390x => systemz.all_features, .i386, .x86_64 => &x86.all_features, - // TODO .nvptx, .nvptx64 => nvptx.all_features, - // TODO .wasm32, .wasm64 => wasm.all_features, + .nvptx, .nvptx64 => nvptx.all_features, + .wasm32, .wasm64 => wasm.all_features, else => &[0]Cpu.Feature{}, }; @@ -437,22 +437,23 @@ pub const Target = union(enum) { /// of features that is expected to be supported on most available hardware. pub fn baselineFeatures(arch: Arch) Cpu.Feature.Set { return switch (arch) { - // TODO .arm, .armeb, .thumb, .thumbeb => arm.baseline_features, + .arm, .armeb, .thumb, .thumbeb => arm.cpu.generic.features, .aarch64, .aarch64_be, .aarch64_32 => aarch64.cpu.generic.features, - // TODO .avr => avr.baseline_features, - // TODO .bpfel, .bpfeb => bpf.baseline_features, - // TODO .hexagon => hexagon.baseline_features, - // TODO .mips, .mipsel, .mips64, .mips64el => mips.baseline_features, - // TODO .msp430 => msp430.baseline_features, - // TODO .powerpc, .powerpc64, .powerpc64le => powerpc.baseline_features, - // TODO .amdgcn => amdgpu.baseline_features, - // TODO .riscv32, .riscv64 => riscv.baseline_features, - // TODO .sparc, .sparcv9, .sparcel => sparc.baseline_features, - // TODO .s390x => systemz.baseline_features, + .avr => avr.cpu.generic.features, + .bpfel, .bpfeb => bpf.cpu.generic.features, + .hexagon => hexagon.cpu.generic.features, + .mips, .mipsel, .mips64, .mips64el => mips.cpu.generic.features, + .msp430 => msp430.cpu.generic.features, + .powerpc, .powerpc64, .powerpc64le => powerpc.cpu.generic.features, + .amdgcn => amdgpu.cpu.generic.features, + .riscv32 => riscv.baseline_32_features, + .riscv64 => riscv.baseline_64_features, + .sparc, .sparcv9, .sparcel => sparc.cpu.generic.features, + .s390x => systemz.cpu.generic.features, .i386 => x86.cpu.pentium4.features, .x86_64 => x86.cpu.x86_64.features, - // TODO .nvptx, .nvptx64 => nvptx.baseline_features, - // TODO .wasm32, .wasm64 => wasm.baseline_features, + .nvptx, .nvptx64 => nvptx.cpu.generic.features, + .wasm32, .wasm64 => wasm.cpu.generic.features, else => 0, }; @@ -461,21 +462,21 @@ pub const Target = union(enum) { /// All CPUs Zig is aware of, sorted lexicographically by name. pub fn allCpus(arch: Arch) []const *const Cpu { return switch (arch) { - // TODO .arm, .armeb, .thumb, .thumbeb => arm.all_cpus, + .arm, .armeb, .thumb, .thumbeb => arm.all_cpus, .aarch64, .aarch64_be, .aarch64_32 => aarch64.all_cpus, - // TODO .avr => avr.all_cpus, - // TODO .bpfel, .bpfeb => bpf.all_cpus, - // TODO .hexagon => hexagon.all_cpus, - // TODO .mips, .mipsel, .mips64, .mips64el => mips.all_cpus, - // TODO .msp430 => msp430.all_cpus, - // TODO .powerpc, .powerpc64, .powerpc64le => powerpc.all_cpus, - // TODO .amdgcn => amdgpu.all_cpus, - // TODO .riscv32, .riscv64 => riscv.all_cpus, - // TODO .sparc, .sparcv9, .sparcel => sparc.all_cpus, - // TODO .s390x => systemz.all_cpus, + .avr => avr.all_cpus, + .bpfel, .bpfeb => bpf.all_cpus, + .hexagon => hexagon.all_cpus, + .mips, .mipsel, .mips64, .mips64el => mips.all_cpus, + .msp430 => msp430.all_cpus, + .powerpc, .powerpc64, .powerpc64le => powerpc.all_cpus, + .amdgcn => amdgpu.all_cpus, + .riscv32, .riscv64 => riscv.all_cpus, + .sparc, .sparcv9, .sparcel => sparc.all_cpus, + .s390x => systemz.all_cpus, .i386, .x86_64 => x86.all_cpus, - // TODO .nvptx, .nvptx64 => nvptx.all_cpus, - // TODO .wasm32, .wasm64 => wasm.all_cpus, + .nvptx, .nvptx64 => nvptx.all_cpus, + .wasm32, .wasm64 => wasm.all_cpus, else => &[0]*const Cpu{}, }; diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig index 7181028cc2..dbe36e0fa1 100644 --- a/lib/std/target/riscv.zig +++ b/lib/std/target/riscv.zig @@ -101,3 +101,22 @@ pub const all_cpus = &[_]*const Cpu{ &cpu.generic_rv32, &cpu.generic_rv64, }; + +pub const baseline_32_features = featureSet(&[_]Feature{ + .a, + .c, + .d, + .f, + .m, + .relax, +}); + +pub const baseline_64_features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .f, + .m, + .relax, +});