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stage2: Default AVR generic cpu to avr2

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The avr1 target is a very minimal subset of the AVR ISA, quoting the GCC
manual:

> This ISA is implemented by the minimal AVR core and supported for
> assembler only.

Default to avr2 as GCC and Clang do.
This commit is contained in:
LemonBoy 2021-04-06 10:47:29 +02:00 committed by Andrew Kelley
parent 2bfc6d14d5
commit 89df41e5d8
1 changed files with 1 additions and 1 deletions
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lib/std/target.zig
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@ -1170,7 +1170,7 @@ pub const Target = struct {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
.aarch64, .aarch64_be, .aarch64_32 => &aarch64.cpu.generic,
.avr => &avr.cpu.avr1,
.avr => &avr.cpu.avr2,
.bpfel, .bpfeb => &bpf.cpu.generic,
.hexagon => &hexagon.cpu.generic,
.mips, .mipsel => &mips.cpu.mips32,