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https://github.com/ziglang/zig.git
synced 2026-02-21 16:54:52 +00:00
x86_64: enable mem dst bin ops, and fix uncovered bugs
This commit is contained in:
Jacob Young
parent
1de64dba23
commit
86625c5a75
@ -1628,7 +1628,7 @@ fn airAddSat(self: *Self, inst: Air.Inst.Index) !void {
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const reg_bits = self.regBitSize(ty);
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const cc: Condition = if (ty.isSignedInt()) cc: {
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try self.genSetReg(ty, limit_reg, dst_mcv);
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try self.genBinOpMir(.sar, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
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try self.genShiftBinOpMir(.sar, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
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try self.genBinOpMir(.xor, ty, limit_mcv, .{
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.immediate = (@as(u64, 1) << @intCast(u6, reg_bits - 1)) - 1,
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});
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@ -1681,7 +1681,7 @@ fn airSubSat(self: *Self, inst: Air.Inst.Index) !void {
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const reg_bits = self.regBitSize(ty);
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const cc: Condition = if (ty.isSignedInt()) cc: {
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try self.genSetReg(ty, limit_reg, dst_mcv);
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try self.genBinOpMir(.sar, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
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try self.genShiftBinOpMir(.sar, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
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try self.genBinOpMir(.xor, ty, limit_mcv, .{
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.immediate = (@as(u64, 1) << @intCast(u6, reg_bits - 1)) - 1,
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});
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@ -1735,7 +1735,7 @@ fn airMulSat(self: *Self, inst: Air.Inst.Index) !void {
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const cc: Condition = if (ty.isSignedInt()) cc: {
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try self.genSetReg(ty, limit_reg, lhs_mcv);
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try self.genBinOpMir(.xor, ty, limit_mcv, rhs_mcv);
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try self.genBinOpMir(.sar, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
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try self.genShiftBinOpMir(.sar, ty, limit_mcv, .{ .immediate = reg_bits - 1 });
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try self.genBinOpMir(.xor, ty, limit_mcv, .{
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.immediate = (@as(u64, 1) << @intCast(u6, reg_bits - 1)) - 1,
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});
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@ -2509,16 +2509,13 @@ fn airWrapErrUnionErr(self: *Self, inst: Air.Inst.Index) !void {
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fn airSlicePtr(self: *Self, inst: Air.Inst.Index) !void {
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const ty_op = self.air.instructions.items(.data)[inst].ty_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const operand = try self.resolveInst(ty_op.operand);
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const dst_mcv: MCValue = blk: {
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switch (operand) {
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.stack_offset => |off| {
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break :blk MCValue{ .stack_offset = off };
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},
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else => return self.fail("TODO implement slice_ptr for {}", .{operand}),
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}
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};
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const result = if (self.liveness.isUnused(inst)) .dead else result: {
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const src_mcv = try self.resolveInst(ty_op.operand);
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if (self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) break :result src_mcv;
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const dst_mcv = try self.allocRegOrMem(inst, true);
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const dst_ty = self.air.typeOfIndex(inst);
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try self.setRegOrMem(dst_ty, dst_mcv, src_mcv);
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break :result dst_mcv;
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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@ -4402,7 +4399,7 @@ fn genBinOp(
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else => {},
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}
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const is_commutative: bool = switch (tag) {
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const is_commutative = switch (tag) {
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.add,
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.addwrap,
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.bool_or,
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@ -4416,6 +4413,20 @@ fn genBinOp(
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else => false,
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};
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const needs_reg_dst = switch (tag) {
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.add,
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.addwrap,
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.sub,
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.subwrap,
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.mul,
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.div_float,
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.div_exact,
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.div_trunc,
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.div_floor,
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=> lhs_ty.isRuntimeFloat(),
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else => false,
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};
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const lhs_lock: ?RegisterLock = switch (lhs) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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@ -4432,10 +4443,10 @@ fn genBinOp(
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var flipped: bool = false;
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const dst_mcv: MCValue = blk: {
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if (maybe_inst) |inst| {
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if (lhs.isRegister() and self.reuseOperand(inst, lhs_air, 0, lhs)) {
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if ((!needs_reg_dst or lhs.isRegister()) and self.reuseOperand(inst, lhs_air, 0, lhs)) {
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break :blk lhs;
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}
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if (is_commutative and rhs.isRegister() and self.reuseOperand(inst, rhs_air, 1, rhs)) {
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if (is_commutative and (!needs_reg_dst or rhs.isRegister()) and self.reuseOperand(inst, rhs_air, 1, rhs)) {
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flipped = true;
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break :blk rhs;
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}
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@ -4485,33 +4496,37 @@ fn genBinOp(
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.div_float,
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.div_exact,
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=> try self.genBinOpMir(switch (lhs_ty.tag()) {
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.f32 => .divss,
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.f64 => .divsd,
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else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),
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}, lhs_ty, dst_mcv, src_mcv),
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.div_trunc,
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.div_floor,
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=> {
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try self.genBinOpMir(switch (lhs_ty.tag()) {
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.f32 => .divss,
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.f64 => .divsd,
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else => return self.fail("TODO implement genBinOp for {s} {}", .{ @tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?) }),
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else => return self.fail("TODO implement genBinOp for {s} {}", .{
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@tagName(tag), lhs_ty.fmt(self.bin_file.options.module.?),
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}),
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}, lhs_ty, dst_mcv, src_mcv);
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if (Target.x86.featureSetHas(self.target.cpu.features, .sse4_1)) {
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const abi_size = @intCast(u32, lhs_ty.abiSize(self.target.*));
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const dst_alias = registerAlias(dst_mcv.register, abi_size);
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try self.asmRegisterRegisterImmediate(switch (lhs_ty.tag()) {
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.f32 => .roundss,
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.f64 => .roundsd,
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else => unreachable,
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}, dst_alias, dst_alias, Immediate.u(switch (tag) {
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.div_trunc => 0b1_0_11,
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.div_floor => 0b1_0_01,
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else => unreachable,
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}));
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} else return self.fail("TODO implement round without sse4_1", .{});
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switch (tag) {
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.div_float,
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.div_exact,
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=> {},
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.div_trunc,
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.div_floor,
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=> if (Target.x86.featureSetHas(self.target.cpu.features, .sse4_1)) {
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const abi_size = @intCast(u32, lhs_ty.abiSize(self.target.*));
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const dst_alias = registerAlias(dst_mcv.register, abi_size);
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try self.asmRegisterRegisterImmediate(switch (lhs_ty.tag()) {
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.f32 => .roundss,
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.f64 => .roundsd,
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else => unreachable,
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}, dst_alias, dst_alias, Immediate.u(switch (tag) {
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.div_trunc => 0b1_0_11,
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.div_floor => 0b1_0_01,
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else => unreachable,
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}));
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} else return self.fail("TODO implement round without sse4_1", .{}),
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else => unreachable,
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}
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},
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.ptr_add,
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@ -4568,7 +4583,13 @@ fn genBinOp(
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};
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const abi_size = @intCast(u32, lhs_ty.abiSize(self.target.*));
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switch (dst_mcv) {
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const tmp_reg = switch (dst_mcv) {
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.register => |reg| reg,
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else => try self.copyToTmpRegister(lhs_ty, dst_mcv),
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};
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const tmp_lock = self.register_manager.lockReg(tmp_reg);
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defer if (tmp_lock) |lock| self.register_manager.unlockReg(lock);
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switch (mat_src_mcv) {
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.none,
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.undef,
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.dead,
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@ -4576,57 +4597,44 @@ fn genBinOp(
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.immediate,
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.eflags,
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.register_overflow,
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.stack_offset,
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.ptr_stack_offset,
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.memory,
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.linker_load,
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=> unreachable,
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.register => |dst_reg| switch (mat_src_mcv) {
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.none,
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.undef,
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.dead,
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.unreach,
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.immediate,
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.eflags,
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.register_overflow,
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.ptr_stack_offset,
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=> unreachable,
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.register => |src_reg| try self.asmCmovccRegisterRegister(
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registerAlias(dst_reg, abi_size),
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registerAlias(src_reg, abi_size),
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.register => |src_reg| try self.asmCmovccRegisterRegister(
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registerAlias(tmp_reg, abi_size),
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registerAlias(src_reg, abi_size),
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cc,
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),
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.stack_offset => |off| try self.asmCmovccRegisterMemory(
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registerAlias(tmp_reg, abi_size),
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .rbp,
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.disp = -off,
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}),
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cc,
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),
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.memory, .linker_load => {
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const addr_reg = (try self.register_manager.allocReg(null, gp)).to64();
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const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
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defer self.register_manager.unlockReg(addr_reg_lock);
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try self.loadMemPtrIntoRegister(addr_reg, Type.usize, mat_src_mcv);
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// To get the actual address of the value we want to modify we
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// we have to go through the GOT
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try self.asmRegisterMemory(
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.mov,
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addr_reg,
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Memory.sib(.qword, .{ .base = addr_reg }),
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);
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try self.asmCmovccRegisterMemory(
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registerAlias(tmp_reg, abi_size),
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = addr_reg }),
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cc,
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),
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.stack_offset => |off| try self.asmCmovccRegisterMemory(
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registerAlias(dst_reg, abi_size),
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .rbp,
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.disp = -off,
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}),
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cc,
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),
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.memory, .linker_load => {
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const addr_reg = (try self.register_manager.allocReg(null, gp)).to64();
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const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
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defer self.register_manager.unlockReg(addr_reg_lock);
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try self.loadMemPtrIntoRegister(addr_reg, Type.usize, dst_mcv);
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// To get the actual address of the value we want to modify we
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// we have to go through the GOT
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try self.asmRegisterMemory(
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.mov,
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addr_reg,
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Memory.sib(.qword, .{ .base = addr_reg }),
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);
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try self.asmCmovccRegisterMemory(
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registerAlias(dst_reg, abi_size),
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = addr_reg }),
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cc,
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);
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},
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);
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},
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}
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try self.setRegOrMem(lhs_ty, dst_mcv, .{ .register = tmp_reg });
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},
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.Float => try self.genBinOpMir(switch (lhs_ty.tag()) {
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.f32 => switch (tag) {
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@ -4649,8 +4657,8 @@ fn genBinOp(
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return dst_mcv;
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}
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fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
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const abi_size = @intCast(u32, dst_ty.abiSize(self.target.*));
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fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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switch (dst_mcv) {
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.none => unreachable,
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.undef => unreachable,
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@ -4667,12 +4675,12 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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const dst_reg_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);
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const reg = try self.copyToTmpRegister(dst_ty, src_mcv);
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return self.genBinOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
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const reg = try self.copyToTmpRegister(ty, src_mcv);
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return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = reg });
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},
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.register => |src_reg| switch (dst_ty.zigTypeTag()) {
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.register => |src_reg| switch (ty.zigTypeTag()) {
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.Float => {
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if (intrinsicsAllowed(self.target.*, dst_ty)) {
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if (intrinsicsAllowed(self.target.*, ty)) {
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return self.asmRegisterRegister(mir_tag, dst_reg.to128(), src_reg.to128());
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}
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@ -4685,7 +4693,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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),
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},
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.immediate => |imm| {
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switch (self.regBitSize(dst_ty)) {
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switch (self.regBitSize(ty)) {
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8, 16, 32 => {
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try self.asmRegisterImmediate(
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mir_tag,
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@ -4704,7 +4712,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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try self.asmRegisterRegister(
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mir_tag,
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registerAlias(dst_reg, abi_size),
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registerAlias(try self.copyToTmpRegister(dst_ty, src_mcv), abi_size),
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registerAlias(try self.copyToTmpRegister(ty, src_mcv), abi_size),
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);
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}
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},
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@ -4719,8 +4727,8 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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const dst_reg_lock = self.register_manager.lockReg(dst_reg);
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defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);
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const reg = try self.copyToTmpRegister(dst_ty, src_mcv);
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return self.genBinOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
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const reg = try self.copyToTmpRegister(ty, src_mcv);
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return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = reg });
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},
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.stack_offset => |off| {
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if (off > math.maxInt(i32)) {
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@ -4754,7 +4762,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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}), registerAlias(src_reg, abi_size));
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},
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.immediate => |imm| {
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switch (self.regBitSize(dst_ty)) {
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switch (self.regBitSize(ty)) {
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8, 16, 32 => {
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try self.asmMemoryImmediate(
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mir_tag,
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@ -4785,7 +4793,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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.base = .rbp,
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.disp = -off,
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}),
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registerAlias(try self.copyToTmpRegister(dst_ty, src_mcv), abi_size),
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registerAlias(try self.copyToTmpRegister(ty, src_mcv), abi_size),
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);
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}
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},
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@ -4793,16 +4801,18 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
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}
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},
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.memory,
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.linker_load,
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.stack_offset,
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.ptr_stack_offset,
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.eflags,
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=> {
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return self.fail("TODO implement x86 genBinOpMir source memory", .{});
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},
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.linker_load => {
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return self.fail("TODO implement x86 genBinOpMir source symbol at index in linker", .{});
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},
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.eflags => {
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return self.fail("TODO implement x86 genBinOpMir source eflags", .{});
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assert(abi_size <= 8);
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const tmp_reg = try self.copyToTmpRegister(ty, src_mcv);
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const tmp_lock = self.register_manager.lockReg(tmp_reg);
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defer if (tmp_lock) |lock| self.register_manager.unlockReg(lock);
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return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = tmp_reg });
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},
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}
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},
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@ -7151,7 +7161,15 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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fn airPtrToInt(self: *Self, inst: Air.Inst.Index) !void {
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const un_op = self.air.instructions.items(.data)[inst].un_op;
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const result = try self.resolveInst(un_op);
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const result = if (self.liveness.isUnused(inst)) .dead else result: {
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const src_mcv = try self.resolveInst(un_op);
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if (self.reuseOperand(inst, un_op, 0, src_mcv)) break :result src_mcv;
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const dst_mcv = try self.allocRegOrMem(inst, true);
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const dst_ty = self.air.typeOfIndex(inst);
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try self.setRegOrMem(dst_ty, dst_mcv, src_mcv);
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break :result dst_mcv;
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};
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return self.finishAir(inst, result, .{ un_op, .none, .none });
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}
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