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Merge pull request #23835 from alexrp/freebsd-libc

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Support dynamically-linked FreeBSD libc when cross-compiling
This commit is contained in:
Alex Rønne Petersen 2025-05-12 01:19:23 +02:00 committed by GitHub
commit 833d4c9ce4
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GPG Key ID: B5690EEEBB952194
1916 changed files with 369308 additions and 70 deletions
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15
CMakeLists.txt
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@ -586,11 +586,12 @@ set(ZIG_STAGE2_SOURCES
src/codegen/spirv/spec.zig
src/crash_report.zig
src/dev.zig
src/glibc.zig
src/libs/freebsd.zig
src/libs/glibc.zig
src/introspect.zig
src/libcxx.zig
src/libtsan.zig
src/libunwind.zig
src/libs/libcxx.zig
src/libs/libtsan.zig
src/libs/libunwind.zig
src/link.zig
src/link/C.zig
src/link/Coff.zig
@ -663,8 +664,8 @@ set(ZIG_STAGE2_SOURCES
src/link/tapi/yaml.zig
src/link/tapi/yaml/test.zig
src/main.zig
src/mingw.zig
src/musl.zig
src/libs/mingw.zig
src/libs/musl.zig
src/mutable_value.zig
src/print_air.zig
src/print_env.zig
@ -675,7 +676,7 @@ set(ZIG_STAGE2_SOURCES
src/target.zig
src/tracy.zig
src/translate_c.zig
src/wasi_libc.zig
src/libs/wasi_libc.zig
)
if(MSVC)

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lib/libc/freebsd/COPYRIGHT vendored Normal file
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@ -0,0 +1,125 @@
# @(#)COPYRIGHT 8.2 (Berkeley) 3/21/94
The compilation of software known as FreeBSD is distributed under the
following terms:
Copyright (c) 1992-2023 The FreeBSD Project.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
The 4.4BSD and 4.4BSD-Lite software is distributed under the following
terms:
All of the documentation and software included in the 4.4BSD and 4.4BSD-Lite
Releases is copyrighted by The Regents of the University of California.
Copyright 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
The Regents of the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement:
This product includes software developed by the University of
California, Berkeley and its contributors.
4. Neither the name of the University nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
The Institute of Electrical and Electronics Engineers and the American
National Standards Committee X3, on Information Processing Systems have
given us permission to reprint portions of their documentation.
In the following statement, the phrase ``this text'' refers to portions
of the system documentation.
Portions of this text are reprinted and reproduced in electronic form in
the second BSD Networking Software Release, from IEEE Std 1003.1-1988, IEEE
Standard Portable Operating System Interface for Computer Environments
(POSIX), copyright C 1988 by the Institute of Electrical and Electronics
Engineers, Inc. In the event of any discrepancy between these versions
and the original IEEE Standard, the original IEEE Standard is the referee
document.
In the following statement, the phrase ``This material'' refers to portions
of the system documentation.
This material is reproduced with permission from American National
Standards Committee X3, on Information Processing Systems. Computer and
Business Equipment Manufacturers Association (CBEMA), 311 First St., NW,
Suite 500, Washington, DC 20001-2178. The developmental work of
Programming Language C was completed by the X3J11 Technical Committee.
The views and conclusions contained in the software and documentation are
those of the authors and should not be interpreted as representing official
policies, either expressed or implied, of the Regents of the University
of California.
NOTE: The copyright of UC Berkeley's Berkeley Software Distribution ("BSD")
source has been updated. The copyright addendum may be found at
ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change and is
included below.
July 22, 1999
To All Licensees, Distributors of Any Version of BSD:
As you know, certain of the Berkeley Software Distribution ("BSD") source
code files require that further distributions of products containing all or
portions of the software, acknowledge within their advertising materials
that such products contain software developed by UC Berkeley and its
contributors.
Specifically, the provision reads:
" * 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors."
Effective immediately, licensees and distributors are no longer required to
include the acknowledgement within advertising materials. Accordingly, the
foregoing paragraph of those BSD Unix files containing it is hereby deleted
in its entirety.
William Hoskins
Director, Office of Technology Licensing
University of California, Berkeley

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lib/libc/freebsd/lib/csu/aarch64/crt.h vendored Normal file
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@ -0,0 +1 @@
/* Empty so we can include this unconditionally */

33
lib/libc/freebsd/lib/csu/aarch64/crt1_c.c vendored Normal file
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@ -0,0 +1,33 @@
/* LINTLIBRARY */
/*-
* Copyright 1996-1998 John D. Polstra.
* Copyright 2014 Andrew Turner.
* Copyright 2014-2015 The FreeBSD Foundation.
* All rights reserved.
*
* Portions of this software were developed by Andrew Turner
* under sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include "csu_common.h"

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@ -0,0 +1,68 @@
/* LINTLIBRARY */
/*-
* Copyright 1996-1998 John D. Polstra.
* Copyright 2014 Andrew Turner.
* Copyright 2014-2015 The FreeBSD Foundation.
* All rights reserved.
*
* Portions of this software were developed by Andrew Turner
* under sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <sys/elf_common.h>
/*
* The program entry point
* void _start(char **ap, void (*cleanup)(void)) __dead2
*/
ENTRY(_start)
.cfi_undefined x30
mov x3, x2 /* cleanup */
add x1, x0, #8 /* load argv */
ldr x0, [x0] /* load argc */
add x2, x1, x0, lsl #3 /* env is after argv */
add x2, x2, #8 /* argv is null terminated */
#ifdef PIC
adrp x4, :got:main
ldr x4, [x4, :got_lo12:main]
#else
ldr x4, =main
#endif
#ifdef GCRT
ldr x5, =eprol
ldr x6, =etext
/*
* __libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext)
*/
bl __libc_start1_gcrt
eprol:
#else
/* __libc_start1(argc, argv, env, cleanup, main) */
bl __libc_start1
#endif
END(_start)
.section .note.GNU-stack,"",@progbits
GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL)

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lib/libc/freebsd/lib/csu/amd64/crt.h vendored Normal file
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@ -0,0 +1,30 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2018 Andrew Turner
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CRT_H_
#define _CRT_H_
/* zig patch: no HAVE_CTORS */
#define INIT_CALL_SEQ(func) "call " __STRING(func)
#endif

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lib/libc/freebsd/lib/csu/amd64/crt1_c.c vendored Normal file
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@ -0,0 +1,30 @@
/* LINTLIBRARY */
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include "csu_common.h"

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lib/libc/freebsd/lib/csu/amd64/crt1_s.S vendored Normal file
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@ -0,0 +1,89 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (C) 2023 Dmitry Chagin <dchagin@FreeBSD.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <machine/asm.h>
.text
.align 8
/*
* The program entry point
* %rdi %rsi
* void _start(char **ap, void (*cleanup)(void)) __dead2
*/
.globl _start
.type _start, @function
_start:
.cfi_startproc
.cfi_undefined %rip /* Terminate call chain. */
pushq %rbp /* Align stack, terminate call chain. */
.cfi_def_cfa_offset 8
movq %rsp, %rbp
.cfi_offset %rbp, -16
.cfi_def_cfa_register %rbp
#ifdef GCRT
subq $16, %rsp
#endif
movq %rsi, %rcx
movq %rdi, %rsi /* argv = ap */
addq $8, %rsi /* argv += 1 */
movq %rdi, %rdx /* env = ap */
addq $16, %rdx /* env += 2 */
movslq (%rdi), %rax
movl %eax, %edi /* argc = *(long *)(void *)ap */
shlq $3, %rax
addq %rax, %rdx /* env += argc */
#ifdef PIC
/*
* XXX. %rip relative addressing is not intended for use in the
* large memory model due to the offset from %rip being limited
* to 32 bits.
*/
leaq main@plt(%rip), %r8
#else
movabsq $main, %r8
#endif
#ifdef GCRT
movabsq $eprol, %r9
movabsq $etext, %rax
movq %rax, (%rsp)
/*
* %edi %rsi %rdx %rcx %r8 %r9 (%rsp)
* __libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext)
*/
callq __libc_start1_gcrt
eprol:
#else
/* __libc_start1(argc, argv, env, cleanup, main) */
callq __libc_start1
#endif
int3
.cfi_endproc
.size _start, . - _start
.section .note.GNU-stack,"",%progbits

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/* Empty so we can include this unconditionally */

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/* LINTLIBRARY */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright 2001 David E. O'Brien.
* All rights reserved.
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
* Copyright (c) 1997 Jason R. Thorpe.
* Copyright (c) 1995 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the
* FreeBSD Project. See https://www.freebsd.org/ for
* information about FreeBSD.
* This product includes software developed for the
* NetBSD Project. See http://www.netbsd.org/ for
* information about NetBSD.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include <sys/param.h>
#include <sys/elf_common.h>
#include "libc_private.h"
#include "csu_common.h"
struct Struct_Obj_Entry;
struct ps_strings;
void _start(int, char **, char **, const struct Struct_Obj_Entry *,
void (*)(void), struct ps_strings *) __dead2;
struct ps_strings *__ps_strings;
void __start(int, char **, char **, struct ps_strings *,
const struct Struct_Obj_Entry *, void (*)(void)) __dead2;
void
__start(int argc, char **argv, char **env, struct ps_strings *ps_strings,
const struct Struct_Obj_Entry *obj __unused, void (*cleanup)(void))
{
if (ps_strings != (struct ps_strings *)0)
__ps_strings = ps_strings;
#ifdef GCRT
__libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext);
#else
__libc_start1(argc, argv, env, cleanup, main);
#endif
}
#ifdef GCRT
__asm__(".text");
__asm__("eprol:");
__asm__(".previous");
#endif

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@ -0,0 +1,77 @@
/* LINTLIBRARY */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright 2001 David E. O'Brien.
* All rights reserved.
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
* Copyright (c) 1997 Jason R. Thorpe.
* Copyright (c) 1995 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the
* FreeBSD Project. See https://www.freebsd.org/ for
* information about FreeBSD.
* This product includes software developed for the
* NetBSD Project. See http://www.netbsd.org/ for
* information about NetBSD.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <sys/param.h>
#include <sys/elf_common.h>
#include "notes.h"
ENTRY(_start)
mov r5, r2 /* cleanup */
mov r4, r1 /* obj_main */
mov r3, r0 /* ps_strings */
/* Get argc, argv, and envp from stack */
ldr r0, [sp, #0x0000]
add r1, sp, #0x0004
add r2, r1, r0, lsl #2
add r2, r2, #0x0004
/* Ensure the stack is properly aligned before calling C code. */
bic sp, sp, #7
sub sp, sp, #8
str r5, [sp, #4]
str r4, [sp, #0]
b __start
END(_start)
.section .note.tag,"a",%note
.p2align 2
.4byte 2f-1f
.4byte 4f-3f
.4byte NT_FREEBSD_ARCH_TAG
1: .asciz NOTE_FREEBSD_VENDOR
2: .p2align 2
3: .asciz MACHINE_ARCH
4:
.section .note.GNU-stack,"",%progbits

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/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2018 Andrew Turner
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include <sys/param.h>
#include "crt.h"
typedef void (*crt_func)(void);
extern void *__dso_handle __hidden;
#ifndef SHARED
void *__dso_handle = 0;
#else
void *__dso_handle = &__dso_handle;
void __cxa_finalize(void *) __weak_symbol;
/*
* Call __cxa_finalize with the dso handle in shared objects.
* When we have ctors/dtors call from the dtor handler before calling
* any dtors, otherwise use a destructor.
*/
#ifndef HAVE_CTORS
__attribute__((destructor))
#endif
static void
run_cxa_finalize(void)
{
if (__cxa_finalize != NULL)
__cxa_finalize(__dso_handle);
}
#endif
/*
* On some architectures and toolchains we may need to call the .dtors.
* These are called in the order they are in the ELF file.
*/
#ifdef HAVE_CTORS
static void __do_global_dtors_aux(void) __used;
static crt_func __CTOR_LIST__[] __section(".ctors") __used = {
(crt_func)-1
};
static crt_func __DTOR_LIST__[] __section(".dtors") __used = {
(crt_func)-1
};
static void
__do_global_dtors_aux(void)
{
crt_func fn;
int n;
#ifdef SHARED
run_cxa_finalize();
#endif
for (n = 1;; n++) {
fn = __DTOR_LIST__[n];
if (fn == (crt_func)0 || fn == (crt_func)-1)
break;
fn();
}
}
asm (
".pushsection .fini \n"
"\t" INIT_CALL_SEQ(__do_global_dtors_aux) "\n"
".popsection \n"
);
#endif
/* zig patch: remove gcj nonsense */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright 2000 David E. O'Brien, John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <sys/param.h>
#include <sys/elf_common.h>
#include "notes.h"
/*
* Special ".note.tag" entry specifying the ABI version. See
* http://www.netbsd.org/Documentation/kernel/elf-notes.html
* for more information.
*/
.section .note.tag,"aG",%note,.freebsd.noteG,comdat
.p2align 2
.4byte 2f-1f
.4byte 4f-3f
.4byte NT_FREEBSD_ABI_TAG
1: .asciz NOTE_FREEBSD_VENDOR
2: .p2align 2
/* zig patch: use __FreeBSD_version which is defined by the compiler */
3: .4byte __FreeBSD_version
4:
.section .note.GNU-stack,"",%progbits
#ifdef __aarch64__
/* This is needed in all objects for BTI to be used in the linked elf file */
GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL)
#endif

65
lib/libc/freebsd/lib/csu/common/crtend.c vendored Normal file
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@ -0,0 +1,65 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2018 Andrew Turner
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include "crt.h"
typedef void (*crt_func)(void);
/* zig patch: remove gcj nonsense */
#ifdef HAVE_CTORS
/*
* On some architectures and toolchains we may need to call the .ctors.
* These are called in the reverse order they are in the ELF file.
*/
static void __do_global_ctors_aux(void) __used;
static crt_func __CTOR_END__[] __section(".ctors") __used = {
(crt_func)0
};
static crt_func __DTOR_END__[] __section(".dtors") __used = {
(crt_func)0
};
static void
__do_global_ctors_aux(void)
{
crt_func fn;
int n;
for (n = 1;; n++) {
fn = __CTOR_END__[-n];
if (fn == (crt_func)0 || fn == (crt_func)-1)
break;
fn();
}
}
asm (
".pushsection .init \n"
"\t" INIT_CALL_SEQ(__do_global_ctors_aux) "\n"
".popsection \n"
);
#endif

50
lib/libc/freebsd/lib/csu/common/csu_common.h vendored Normal file
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@ -0,0 +1,50 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef _CSU_COMMON_H_
/*
* This file includes both definitions and declarations, it can be
* included only into one compilation unit for csu objects. We cannot
* practically check this, but at least guard against
* double-inclusion.
*/
#error "Include this file only once"
#else
#define _CSU_COMMON_H_
char **environ;
const char *__progname = "";
#ifdef GCRT
extern int eprol;
extern int etext;
#endif
int main(int, char **, char **);
#endif /* _CSU_COMMON_H_ */

47
lib/libc/freebsd/lib/csu/common/feature_note.S vendored Normal file
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@ -0,0 +1,47 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright 2000 David E. O'Brien, John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <sys/elf_common.h>
#include "notes.h"
.section .note.tag,"a",%note
.p2align 2
.4byte 2f-1f
.4byte 4f-3f
.4byte NT_FREEBSD_FEATURE_CTL
1: .asciz NOTE_FREEBSD_VENDOR
2: .p2align 2
3: .4byte 0
4:
.section .note.GNU-stack,"",%progbits
#ifdef __aarch64__
/* This is needed in all objects for BTI to be used in the linked elf file */
GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL)
#endif

48
lib/libc/freebsd/lib/csu/common/ignore_init_note.S vendored Normal file
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@ -0,0 +1,48 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2012 Konstantin Belousov <kib@FreeBSD.org>
* Copyright (c) 2018 The FreeBSD Foundation
*
* Parts of this software was developed by Konstantin Belousov
* <kib@FreeBSD.org> under sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
#include <sys/elf_common.h>
#include "notes.h"
.section .note.tag,"a",%note
.p2align 2
.4byte 2f-1f
.4byte 4f-3f
.4byte NT_FREEBSD_NOINIT_TAG
1: .asciz NOTE_FREEBSD_VENDOR
2: .p2align 2
3: .4byte 0
4:
.section .note.GNU-stack,"",%progbits
#ifdef __aarch64__
/* This is needed in all objects for BTI to be used in the linked elf file */
GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL)
#endif

32
lib/libc/freebsd/lib/csu/common/notes.h vendored Normal file
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@ -0,0 +1,32 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2012 Konstantin Belousov <kib@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CSU_COMMON_NOTES_H
#define CSU_COMMON_NOTES_H
#define NOTE_FREEBSD_VENDOR "FreeBSD"
#define NOTE_SECTION ".note.tag"
#endif

30
lib/libc/freebsd/lib/csu/i386/crt.h vendored Normal file
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@ -0,0 +1,30 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2018 Andrew Turner
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CRT_H_
#define _CRT_H_
/* zig patch: no HAVE_CTORS */
#define INIT_CALL_SEQ(func) "call " __STRING(func)
#endif

30
lib/libc/freebsd/lib/csu/i386/crt1_c.c vendored Normal file
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@ -0,0 +1,30 @@
/* LINTLIBRARY */
/*-
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include "csu_common.h"
void _start(char *, ...) __dead2;

91
lib/libc/freebsd/lib/csu/i386/crt1_s.S vendored Normal file
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@ -0,0 +1,91 @@
/*-
* Copyright 2009 Konstantin Belousov.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
.text
.align 4
.globl _start
.type _start, @function
_start:
.cfi_startproc
.cfi_undefined %eip
popl %esi # Pop argc
.cfi_def_cfa_offset -4
movl %esp,%edi # argv starts at stack top
xorl %ebp,%ebp
pushl %ebp
.cfi_def_cfa_offset 0
movl %esp,%ebp
.cfi_offset %ebp,-4
.cfi_def_cfa_register %ebp
andl $0xfffffff0,%esp # align stack
#ifdef GCRT
subl $4,%esp # Align stack for 7 arguments
pushl $etext
pushl $eprol
eprol:
#else
subl $12,%esp # Align stack for 5 arguments
#endif /* GCRT */
#ifdef PIC
calll 1f
1: popl %ebx
addl $_GLOBAL_OFFSET_TABLE_+[.-1b],%ebx
leal main@GOTOFF(%ebx),%eax
pushl %eax
#else
pushl $main
#endif /* PIC */
pushl %edx # rtld cleanup
/* env = argv + argc + 1 */
movl %edi,%eax # env = argv
movl %esi,%ecx
shll $2,%ecx # argc * 4
addl %ecx,%eax # env += argc
addl $4,%eax # env += 1
pushl %eax # env
pushl %edi # argv
pushl %esi # argc
#ifdef GCRT
/*
* __libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext);
*/
calll __libc_start1_gcrt
#else
/*
* __libc_start1(argc, argv, env, cleanup, main);
*/
#ifdef PIC
calll __libc_start1@PLT
#else
calll __libc_start1
#endif
#endif /* GCRT */
int3
.cfi_endproc
.size _start, . - _start
.section .note.GNU-stack,"",%progbits

31
lib/libc/freebsd/lib/csu/powerpc/crt.h vendored Normal file
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@ -0,0 +1,31 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2018 Andrew Turner
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CRT_H_
#define _CRT_H_
/* zig patch: no HAVE_CTORS */
#define CTORS_CONSTRUCTORS
#define INIT_CALL_SEQ(func) "bl " __STRING(func) "; nop"
#endif

89
lib/libc/freebsd/lib/csu/powerpc/crt1_c.c vendored Normal file
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@ -0,0 +1,89 @@
/* LINTLIBRARY */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright 2001 David E. O'Brien.
* All rights reserved.
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
* Copyright (c) 1997 Jason R. Thorpe.
* Copyright (c) 1995 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the
* FreeBSD Project. See https://www.freebsd.org/ for
* information about FreeBSD.
* This product includes software developed for the
* NetBSD Project. See http://www.netbsd.org/ for
* information about NetBSD.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include <stdlib.h>
#include "libc_private.h"
#include "csu_common.h"
struct Struct_Obj_Entry;
struct ps_strings;
struct ps_strings *__ps_strings;
void _start(int, char **, char **, const struct Struct_Obj_Entry *,
void (*)(void), struct ps_strings *) __dead2;
/* The entry function. */
/*
* First 5 arguments are specified by the PowerPC SVR4 ABI.
* The last argument, ps_strings, is a BSD extension.
*/
/* ARGSUSED */
void
_start(int argc, char **argv, char **env,
const struct Struct_Obj_Entry *obj __unused, void (*cleanup)(void),
struct ps_strings *ps_strings)
{
if (ps_strings != (struct ps_strings *)0)
__ps_strings = ps_strings;
#ifdef GCRT
__libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext);
#else
__libc_start1(argc, argv, env, cleanup, main);
#endif
}
#ifdef GCRT
__asm__(".text");
__asm__("eprol:");
__asm__(".previous");
#endif
#ifndef PIC
__asm__(".text\n"
"\t.global _GLOBAL_OFFSET_TABLE_\n"
"\t.reloc 0, R_PPC_NONE, _GLOBAL_OFFSET_TABLE_");
#endif

189
lib/libc/freebsd/lib/csu/powerpc/crtsavres.S vendored Normal file
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@ -0,0 +1,189 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2019 Justin Hibbits
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
.text
/*
* The PowerPC ABI spec requires the following save/restore functions to be
* provided:
*
* _savefpr_N
* _restfpr_N
* _restfpr_N_x
* _savegpr_N
* _restgpr_N
* _restgpr_N_x
*
* With N ranging from 14 to 31, to save the nonvolatile registers.
*/
#define _CRTENTRY(name) \
.text; \
.globl name; \
.type name,@function; \
name:
#define SAVEFPR(r) _CRTENTRY(__CONCAT(_savefpr_,r)) \
stfd r,(-256 + r * 8)(11)
SAVEFPR(14)
SAVEFPR(15)
SAVEFPR(16)
SAVEFPR(17)
SAVEFPR(18)
SAVEFPR(19)
SAVEFPR(20)
SAVEFPR(21)
SAVEFPR(22)
SAVEFPR(23)
SAVEFPR(24)
SAVEFPR(25)
SAVEFPR(26)
SAVEFPR(27)
SAVEFPR(28)
SAVEFPR(29)
SAVEFPR(30)
SAVEFPR(31)
blr
#define RESTFPR(r) _CRTENTRY(__CONCAT(_restfpr_,r)) \
lfd r,(-256 + r * 8)(11)
RESTFPR(14)
RESTFPR(15)
RESTFPR(16)
RESTFPR(17)
RESTFPR(18)
RESTFPR(19)
RESTFPR(20)
RESTFPR(21)
RESTFPR(22)
RESTFPR(23)
RESTFPR(24)
RESTFPR(25)
RESTFPR(26)
RESTFPR(27)
RESTFPR(28)
RESTFPR(29)
RESTFPR(30)
RESTFPR(31)
blr
#define SAVEGPR(r) _CRTENTRY(__CONCAT(_savegpr_,r)) \
stw r,(-128 + r * 4)(11)
SAVEGPR(14)
SAVEGPR(15)
SAVEGPR(16)
SAVEGPR(17)
SAVEGPR(18)
SAVEGPR(19)
SAVEGPR(20)
SAVEGPR(21)
SAVEGPR(22)
SAVEGPR(23)
SAVEGPR(24)
SAVEGPR(25)
SAVEGPR(26)
SAVEGPR(27)
SAVEGPR(28)
SAVEGPR(29)
SAVEGPR(30)
SAVEGPR(31)
blr
#define RESTGPR(r) _CRTENTRY(__CONCAT(_restgpr_,r)) \
lwz r,(-128 + r*4)(11)
RESTGPR(14)
RESTGPR(15)
RESTGPR(16)
RESTGPR(17)
RESTGPR(18)
RESTGPR(19)
RESTGPR(20)
RESTGPR(21)
RESTGPR(22)
RESTGPR(23)
RESTGPR(24)
RESTGPR(25)
RESTGPR(26)
RESTGPR(27)
RESTGPR(28)
RESTGPR(29)
RESTGPR(30)
RESTGPR(31)
blr
#define RESTFPR_X(r) _CRTENTRY(__CONCAT(__CONCAT(_restfpr_,r),_x)) \
lfd r,(-256 + r * 8)(11)
RESTFPR_X(14)
RESTFPR_X(15)
RESTFPR_X(16)
RESTFPR_X(17)
RESTFPR_X(18)
RESTFPR_X(19)
RESTFPR_X(20)
RESTFPR_X(21)
RESTFPR_X(22)
RESTFPR_X(23)
RESTFPR_X(24)
RESTFPR_X(25)
RESTFPR_X(26)
RESTFPR_X(27)
RESTFPR_X(28)
RESTFPR_X(29)
RESTFPR_X(30)
RESTFPR_X(31)
lwz 0,4(11)
mtlr 0
mr 1,11
blr
#define RESTGPR_X(r) _CRTENTRY(__CONCAT(__CONCAT(_restgpr_,r),_x)) \
lwz r,(-128 + r * 4)(11)
RESTGPR_X(14)
RESTGPR_X(15)
RESTGPR_X(16)
RESTGPR_X(17)
RESTGPR_X(18)
RESTGPR_X(19)
RESTGPR_X(20)
RESTGPR_X(21)
RESTGPR_X(22)
RESTGPR_X(23)
RESTGPR_X(24)
RESTGPR_X(25)
RESTGPR_X(26)
RESTGPR_X(27)
RESTGPR_X(28)
RESTGPR_X(29)
RESTGPR_X(30)
RESTGPR_X(31)
lwz 0,4(11)
mtlr 0
mr 1,11
blr

31
lib/libc/freebsd/lib/csu/powerpc64/crt.h vendored Normal file
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@ -0,0 +1,31 @@
/*-
* SPDX-License-Identifier: BSD-1-Clause
*
* Copyright 2018 Andrew Turner
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CRT_H_
#define _CRT_H_
/* zig patch: no HAVE_CTORS */
#define CTORS_CONSTRUCTORS
#define INIT_CALL_SEQ(func) "bl " __STRING(func) "; nop"
#endif

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/* LINTLIBRARY */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright 2001 David E. O'Brien.
* All rights reserved.
* Copyright 1996-1998 John D. Polstra.
* All rights reserved.
* Copyright (c) 1997 Jason R. Thorpe.
* Copyright (c) 1995 Christopher G. Demetriou
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the
* FreeBSD Project. See https://www.freebsd.org/ for
* information about FreeBSD.
* This product includes software developed for the
* NetBSD Project. See http://www.netbsd.org/ for
* information about NetBSD.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include <stdint.h>
#include <sys/elf.h>
#include "libc_private.h"
#include "csu_common.h"
struct Struct_Obj_Entry;
struct ps_strings;
void _start(int, char **, char **, const struct Struct_Obj_Entry *,
void (*)(void), struct ps_strings *) __dead2;
struct ps_strings *__ps_strings;
/* The entry function. */
/*
* First 5 arguments are specified by the PowerPC SVR4 ABI.
* The last argument, ps_strings, is a BSD extension.
*/
void
_start(int argc, char **argv, char **env,
const struct Struct_Obj_Entry *obj __unused, void (*cleanup)(void),
struct ps_strings *ps_strings)
{
if (ps_strings != (struct ps_strings *)0)
__ps_strings = ps_strings;
#ifdef GCRT
__libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext);
#else
__libc_start1(argc, argv, env, cleanup, main);
#endif
}
#ifdef GCRT
__asm__(".text");
__asm__("eprol:");
__asm__(".previous");
#endif

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#ifndef _CRT_H_
#define _CRT_H_
/* zig patch: no HAVE_CTORS */
#define INIT_CALL_SEQ(func) "call " __STRING(func)
#endif

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/* LINTLIBRARY */
/*-
* Copyright 1996-1998 John D. Polstra.
* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
* University of Cambridge Computer Laboratory under DARPA/AFRL contract
* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Portions of this software were developed by the University of Cambridge
* Computer Laboratory as part of the CTSRD Project, with support from the
* UK Higher Education Innovation Fund (HEIF).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#include "libc_private.h"
#include "csu_common.h"
void __start(int argc, char **argv, char **env, void (*cleanup)(void)) __dead2;
void
__start(int argc, char **argv, char **env, void (*cleanup)(void))
{
#ifdef GCRT
__libc_start1_gcrt(argc, argv, env, cleanup, main, &eprol, &etext);
__asm__("eprol:");
#else
__libc_start1(argc, argv, env, cleanup, main);
#endif
}

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/* LINTLIBRARY */
/*-
* Copyright 1996-1998 John D. Polstra.
* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
* University of Cambridge Computer Laboratory under DARPA/AFRL contract
* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Portions of this software were developed by the University of Cambridge
* Computer Laboratory as part of the CTSRD Project, with support from the
* UK Higher Education Innovation Fund (HEIF).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/asm.h>
ENTRY(_start)
mv a3, a2 # cleanup
addi a1, a0, 8 # get argv
ld a0, 0(a0) # load argc
slli t0, a0, 3 # mult by arg size
add a2, a1, t0 # env is after argv
addi a2, a2, 8 # argv is null terminated
.option push
.option norelax
lla gp, __global_pointer$
.option pop
call __start
END(_start)
.section .note.GNU-stack,"",%progbits

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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1998 John Birrell <jb@cimlogic.com.au>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Private definitions for libc, libc_r and libpthread.
*
*/
#ifndef _LIBC_PRIVATE_H_
#define _LIBC_PRIVATE_H_
#include <sys/_types.h>
#include <sys/_pthreadtypes.h>
extern char **environ;
/*
* The kernel doesn't expose PID_MAX to the user space. Save it here
* to allow to run a newer world on a pre-1400079 kernel.
*/
#define _PID_MAX 99999
/*
* This global flag is non-zero when a process has created one
* or more threads. It is used to avoid calling locking functions
* when they are not required.
*/
#ifndef __LIBC_ISTHREADED_DECLARED
#define __LIBC_ISTHREADED_DECLARED
extern int __isthreaded;
#endif
/*
* Elf_Auxinfo *__elf_aux_vector, the pointer to the ELF aux vector
* provided by kernel. Either set for us by rtld, or found at runtime
* on stack for static binaries.
*
* Type is void to avoid polluting whole libc with ELF types.
*/
extern void *__elf_aux_vector;
/*
* libc should use libc_dlopen internally, which respects a global
* flag where loading of new shared objects can be restricted.
*/
void *libc_dlopen(const char *, int);
/*
* For dynamic linker.
*/
void _rtld_error(const char *fmt, ...);
/*
* File lock contention is difficult to diagnose without knowing
* where locks were set. Allow a debug library to be built which
* records the source file and line number of each lock call.
*/
#ifdef _FLOCK_DEBUG
#define _FLOCKFILE(x) _flockfile_debug(x, __FILE__, __LINE__)
#else
#define _FLOCKFILE(x) _flockfile(x)
#endif
/*
* Macros for locking and unlocking FILEs. These test if the
* process is threaded to avoid locking when not required.
*/
#define FLOCKFILE(fp) if (__isthreaded) _FLOCKFILE(fp)
#define FUNLOCKFILE(fp) if (__isthreaded) _funlockfile(fp)
struct _spinlock;
extern struct _spinlock __stdio_thread_lock __hidden;
#define STDIO_THREAD_LOCK() \
do { \
if (__isthreaded) \
_SPINLOCK(&__stdio_thread_lock); \
} while (0)
#define STDIO_THREAD_UNLOCK() \
do { \
if (__isthreaded) \
_SPINUNLOCK(&__stdio_thread_lock); \
} while (0)
void __libc_spinlock_stub(struct _spinlock *);
void __libc_spinunlock_stub(struct _spinlock *);
/*
* Indexes into the pthread jump table.
*
* Warning! If you change this type, you must also change the threads
* libraries that reference it (libc_r, libpthread).
*/
typedef enum {
PJT_ATFORK,
PJT_ATTR_DESTROY,
PJT_ATTR_GETDETACHSTATE,
PJT_ATTR_GETGUARDSIZE,
PJT_ATTR_GETINHERITSCHED,
PJT_ATTR_GETSCHEDPARAM,
PJT_ATTR_GETSCHEDPOLICY,
PJT_ATTR_GETSCOPE,
PJT_ATTR_GETSTACKADDR,
PJT_ATTR_GETSTACKSIZE,
PJT_ATTR_INIT,
PJT_ATTR_SETDETACHSTATE,
PJT_ATTR_SETGUARDSIZE,
PJT_ATTR_SETINHERITSCHED,
PJT_ATTR_SETSCHEDPARAM,
PJT_ATTR_SETSCHEDPOLICY,
PJT_ATTR_SETSCOPE,
PJT_ATTR_SETSTACKADDR,
PJT_ATTR_SETSTACKSIZE,
PJT_CANCEL,
PJT_CLEANUP_POP,
PJT_CLEANUP_PUSH,
PJT_COND_BROADCAST,
PJT_COND_DESTROY,
PJT_COND_INIT,
PJT_COND_SIGNAL,
PJT_COND_TIMEDWAIT,
PJT_COND_WAIT,
PJT_DETACH,
PJT_EQUAL,
PJT_EXIT,
PJT_GETSPECIFIC,
PJT_JOIN,
PJT_KEY_CREATE,
PJT_KEY_DELETE,
PJT_KILL,
PJT_MAIN_NP,
PJT_MUTEXATTR_DESTROY,
PJT_MUTEXATTR_INIT,
PJT_MUTEXATTR_SETTYPE,
PJT_MUTEX_DESTROY,
PJT_MUTEX_INIT,
PJT_MUTEX_LOCK,
PJT_MUTEX_TRYLOCK,
PJT_MUTEX_UNLOCK,
PJT_ONCE,
PJT_RWLOCK_DESTROY,
PJT_RWLOCK_INIT,
PJT_RWLOCK_RDLOCK,
PJT_RWLOCK_TRYRDLOCK,
PJT_RWLOCK_TRYWRLOCK,
PJT_RWLOCK_UNLOCK,
PJT_RWLOCK_WRLOCK,
PJT_SELF,
PJT_SETCANCELSTATE,
PJT_SETCANCELTYPE,
PJT_SETSPECIFIC,
PJT_SIGMASK,
PJT_TESTCANCEL,
PJT_CLEANUP_POP_IMP,
PJT_CLEANUP_PUSH_IMP,
PJT_CANCEL_ENTER,
PJT_CANCEL_LEAVE,
PJT_MUTEX_CONSISTENT,
PJT_MUTEXATTR_GETROBUST,
PJT_MUTEXATTR_SETROBUST,
PJT_GETTHREADID_NP,
PJT_ATTR_GET_NP,
PJT_GETNAME_NP,
PJT_MAX
} pjt_index_t;
typedef int (*pthread_func_t)(void);
typedef pthread_func_t pthread_func_entry_t[2];
extern pthread_func_entry_t __thr_jtable[];
void __set_error_selector(int *(*arg)(void));
int _pthread_mutex_init_calloc_cb_stub(pthread_mutex_t *mutex,
void *(calloc_cb)(__size_t, __size_t));
typedef int (*interpos_func_t)(void);
interpos_func_t *__libc_interposing_slot(int interposno);
extern interpos_func_t __libc_interposing[] __hidden;
enum {
INTERPOS_accept,
INTERPOS_accept4,
INTERPOS_aio_suspend,
INTERPOS_close,
INTERPOS_connect,
INTERPOS_fcntl,
INTERPOS_fsync,
INTERPOS_fork,
INTERPOS_msync,
INTERPOS_nanosleep,
INTERPOS_openat,
INTERPOS_poll,
INTERPOS_pselect,
INTERPOS_recvfrom,
INTERPOS_recvmsg,
INTERPOS_select,
INTERPOS_sendmsg,
INTERPOS_sendto,
INTERPOS_setcontext,
INTERPOS_sigaction,
INTERPOS_sigprocmask,
INTERPOS_sigsuspend,
INTERPOS_sigwait,
INTERPOS_sigtimedwait,
INTERPOS_sigwaitinfo,
INTERPOS_swapcontext,
INTERPOS_system,
INTERPOS_tcdrain,
INTERPOS_read,
INTERPOS_readv,
INTERPOS_wait4,
INTERPOS_write,
INTERPOS_writev,
INTERPOS__pthread_mutex_init_calloc_cb,
INTERPOS_spinlock,
INTERPOS_spinunlock,
INTERPOS_kevent,
INTERPOS_wait6,
INTERPOS_ppoll,
INTERPOS_map_stacks_exec,
INTERPOS_fdatasync,
INTERPOS_clock_nanosleep,
INTERPOS_distribute_static_tls,
INTERPOS_pdfork,
INTERPOS_MAX
};
/*
* yplib internal interfaces
*/
#ifdef YP
int _yp_check(char **);
#endif
void __libc_start1(int, char *[], char *[],
void (*)(void), int (*)(int, char *[], char *[])) __dead2;
void __libc_start1_gcrt(int, char *[], char *[],
void (*)(void), int (*)(int, char *[], char *[]),
int *, int *) __dead2;
/*
* Initialise TLS for static programs
*/
void _init_tls(void);
/*
* Provides pthread_once()-like functionality for both single-threaded
* and multi-threaded applications.
*/
int _once(pthread_once_t *, void (*)(void));
/*
* This is a pointer in the C run-time startup code. It is used
* by getprogname() and setprogname().
*/
extern const char *__progname;
/*
* This function is used by the threading libraries to notify malloc that a
* thread is exiting.
*/
void _malloc_thread_cleanup(void);
/*
* This function is used by the threading libraries to notify libc that a
* thread is exiting, so its thread-local dtors should be called.
*/
void __cxa_thread_call_dtors(void);
int __cxa_thread_atexit_hidden(void (*dtor_func)(void *), void *obj,
void *dso_symbol) __hidden;
/*
* These functions are used by the threading libraries in order to protect
* malloc across fork().
*/
void _malloc_prefork(void);
void _malloc_postfork(void);
void _malloc_first_thread(void);
/*
* Function to clean up streams, called from abort() and exit().
*/
extern void (*__cleanup)(void) __hidden;
/*
* Get kern.osreldate to detect ABI revisions. Explicitly
* ignores value of $OSVERSION and caches result.
*/
int __getosreldate(void);
#include <sys/_types.h>
#include <sys/_sigset.h>
struct aiocb;
struct fd_set;
struct iovec;
struct kevent;
struct msghdr;
struct pollfd;
struct rusage;
struct sigaction;
struct sockaddr;
struct stat;
struct statfs;
struct timespec;
struct timeval;
struct timezone;
struct __siginfo;
struct __ucontext;
struct __wrusage;
enum idtype;
int __sys_aio_suspend(const struct aiocb * const[], int,
const struct timespec *);
int __sys_accept(int, struct sockaddr *, __socklen_t *);
int __sys_accept4(int, struct sockaddr *, __socklen_t *, int);
int __sys_clock_gettime(__clockid_t, struct timespec *ts);
int __sys_clock_nanosleep(__clockid_t, int,
const struct timespec *, struct timespec *);
int __sys_close(int);
int __sys_close_range(unsigned, unsigned, int);
int __sys_connect(int, const struct sockaddr *, __socklen_t);
int __sys_fcntl(int, int, ...);
int __sys_fdatasync(int);
int __sys_fstat(int fd, struct stat *);
int __sys_fstatfs(int fd, struct statfs *);
int __sys_fstatat(int, const char *, struct stat *, int);
int __sys_fsync(int);
__pid_t __sys_fork(void);
int __sys_ftruncate(int, __off_t);
__ssize_t __sys_getdirentries(int, char *, __size_t, __off_t *);
int __sys_getfsstat(struct statfs *, long, int);
int __sys_gettimeofday(struct timeval *, struct timezone *);
int __sys_kevent(int, const struct kevent *, int, struct kevent *,
int, const struct timespec *);
__off_t __sys_lseek(int, __off_t, int);
void *__sys_mmap(void *, __size_t, int, int, int, __off_t);
int __sys_msync(void *, __size_t, int);
int __sys_nanosleep(const struct timespec *, struct timespec *);
int __sys_open(const char *, int, ...);
int __sys_openat(int, const char *, int, ...);
int __sys_pdfork(int *, int);
int __sys_pselect(int, struct fd_set *, struct fd_set *,
struct fd_set *, const struct timespec *,
const __sigset_t *);
int __sys_ptrace(int, __pid_t, char *, int);
int __sys_poll(struct pollfd *, unsigned, int);
int __sys_ppoll(struct pollfd *, unsigned, const struct timespec *,
const __sigset_t *);
__ssize_t __sys_pread(int, void *, __size_t, __off_t);
__ssize_t __sys_pwrite(int, const void *, __size_t, __off_t);
__ssize_t __sys_read(int, void *, __size_t);
__ssize_t __sys_readv(int, const struct iovec *, int);
__ssize_t __sys_recv(int, void *, __size_t, int);
__ssize_t __sys_recvfrom(int, void *, __size_t, int, struct sockaddr *,
__socklen_t *);
__ssize_t __sys_recvmsg(int, struct msghdr *, int);
int __sys_sched_getcpu(void);
int __sys_select(int, struct fd_set *, struct fd_set *,
struct fd_set *, struct timeval *);
__ssize_t __sys_sendmsg(int, const struct msghdr *, int);
__ssize_t __sys_sendto(int, const void *, __size_t, int,
const struct sockaddr *, __socklen_t);
int __sys_setcontext(const struct __ucontext *);
int __sys_sigaction(int, const struct sigaction *,
struct sigaction *);
int __sys_sigprocmask(int, const __sigset_t *, __sigset_t *);
int __sys_sigsuspend(const __sigset_t *);
int __sys_sigtimedwait(const __sigset_t *, struct __siginfo *,
const struct timespec *);
int __sys_sigwait(const __sigset_t *, int *);
int __sys_sigwaitinfo(const __sigset_t *, struct __siginfo *);
int __sys___specialfd(int, const void *, __size_t);
int __sys_statfs(const char *, struct statfs *);
int __sys_swapcontext(struct __ucontext *,
const struct __ucontext *);
int __sys_thr_kill(long, int);
int __sys_thr_self(long *);
int __sys_truncate(const char *, __off_t);
__pid_t __sys_wait4(__pid_t, int *, int, struct rusage *);
__pid_t __sys_wait6(enum idtype, __id_t, int *, int,
struct __wrusage *, struct __siginfo *);
__ssize_t __sys_write(int, const void *, __size_t);
__ssize_t __sys_writev(int, const struct iovec *, int);
int __sys_shm_open2(const char *, int, __mode_t, int, const char *);
int __libc_sigaction(int, const struct sigaction *,
struct sigaction *) __hidden;
int __libc_sigprocmask(int, const __sigset_t *, __sigset_t *)
__hidden;
int __libc_sigsuspend(const __sigset_t *) __hidden;
int __libc_sigwait(const __sigset_t * __restrict,
int * restrict sig);
int __libc_system(const char *);
int __libc_tcdrain(int);
int __fcntl_compat(int fd, int cmd, ...);
int __sys_futimens(int fd, const struct timespec *times) __hidden;
int __sys_utimensat(int fd, const char *path,
const struct timespec *times, int flag) __hidden;
int _elf_aux_info(int aux, void *buf, int buflen);
struct dl_phdr_info;
int __elf_phdr_match_addr(struct dl_phdr_info *, void *);
void __init_elf_aux_vector(void);
void __libc_map_stacks_exec(void);
void __libc_distribute_static_tls(__size_t, void *, __size_t, __size_t);
__uintptr_t __libc_static_tls_base(__size_t);
void _pthread_cancel_enter(int);
void _pthread_cancel_leave(int);
struct _pthread_cleanup_info;
void ___pthread_cleanup_push_imp(void (*)(void *), void *,
struct _pthread_cleanup_info *);
void ___pthread_cleanup_pop_imp(int);
void __throw_constraint_handler_s(const char * restrict msg, int error);
struct __nl_cat_d;
struct _xlocale;
struct __nl_cat_d *__catopen_l(const char *name, int type,
struct _xlocale *locale);
int __strerror_rl(int errnum, char *strerrbuf, __size_t buflen,
struct _xlocale *locale);
#endif /* _LIBC_PRIVATE_H_ */

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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2001 David E. O'Brien
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)param.h 5.8 (Berkeley) 6/28/91
*/
#ifndef _ARM_INCLUDE__ALIGN_H_
#define _ARM_INCLUDE__ALIGN_H_
/*
* Round p (pointer or byte index) up to the hardware-required alignment which
* is sufficient for any data type, pointer or numeric. The resulting type
* is equivelent to arm's uintptr_t (but is purposely spelled "unsigned" here).
*/
#define _ALIGNBYTES (sizeof(int) - 1)
#define _ALIGN(p) (((unsigned)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
#endif /* !_ARM_INCLUDE__ALIGN_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* From: $NetBSD: int_fmtio.h,v 1.2 2001/04/26 16:25:21 kleink Exp $
*/
#ifndef _MACHINE_INTTYPES_H_
#define _MACHINE_INTTYPES_H_
/*
* Macros for format specifiers.
*/
/* fprintf(3) macros for signed integers. */
#define PRId8 "d" /* int8_t */
#define PRId16 "d" /* int16_t */
#define PRId32 "d" /* int32_t */
#define PRId64 "lld" /* int64_t */
#define PRIdLEAST8 "d" /* int_least8_t */
#define PRIdLEAST16 "d" /* int_least16_t */
#define PRIdLEAST32 "d" /* int_least32_t */
#define PRIdLEAST64 "lld" /* int_least64_t */
#define PRIdFAST8 "d" /* int_fast8_t */
#define PRIdFAST16 "d" /* int_fast16_t */
#define PRIdFAST32 "d" /* int_fast32_t */
#define PRIdFAST64 "lld" /* int_fast64_t */
#define PRIdMAX "jd" /* intmax_t */
#define PRIdPTR "d" /* intptr_t */
#define PRIi8 "i" /* int8_t */
#define PRIi16 "i" /* int16_t */
#define PRIi32 "i" /* int32_t */
#define PRIi64 "lli" /* int64_t */
#define PRIiLEAST8 "i" /* int_least8_t */
#define PRIiLEAST16 "i" /* int_least16_t */
#define PRIiLEAST32 "i" /* int_least32_t */
#define PRIiLEAST64 "lli" /* int_least64_t */
#define PRIiFAST8 "i" /* int_fast8_t */
#define PRIiFAST16 "i" /* int_fast16_t */
#define PRIiFAST32 "i" /* int_fast32_t */
#define PRIiFAST64 "lli" /* int_fast64_t */
#define PRIiMAX "ji" /* intmax_t */
#define PRIiPTR "i" /* intptr_t */
/* fprintf(3) macros for unsigned integers. */
#define PRIo8 "o" /* uint8_t */
#define PRIo16 "o" /* uint16_t */
#define PRIo32 "o" /* uint32_t */
#define PRIo64 "llo" /* uint64_t */
#define PRIoLEAST8 "o" /* uint_least8_t */
#define PRIoLEAST16 "o" /* uint_least16_t */
#define PRIoLEAST32 "o" /* uint_least32_t */
#define PRIoLEAST64 "llo" /* uint_least64_t */
#define PRIoFAST8 "o" /* uint_fast8_t */
#define PRIoFAST16 "o" /* uint_fast16_t */
#define PRIoFAST32 "o" /* uint_fast32_t */
#define PRIoFAST64 "llo" /* uint_fast64_t */
#define PRIoMAX "jo" /* uintmax_t */
#define PRIoPTR "o" /* uintptr_t */
#define PRIu8 "u" /* uint8_t */
#define PRIu16 "u" /* uint16_t */
#define PRIu32 "u" /* uint32_t */
#define PRIu64 "llu" /* uint64_t */
#define PRIuLEAST8 "u" /* uint_least8_t */
#define PRIuLEAST16 "u" /* uint_least16_t */
#define PRIuLEAST32 "u" /* uint_least32_t */
#define PRIuLEAST64 "llu" /* uint_least64_t */
#define PRIuFAST8 "u" /* uint_fast8_t */
#define PRIuFAST16 "u" /* uint_fast16_t */
#define PRIuFAST32 "u" /* uint_fast32_t */
#define PRIuFAST64 "llu" /* uint_fast64_t */
#define PRIuMAX "ju" /* uintmax_t */
#define PRIuPTR "u" /* uintptr_t */
#define PRIx8 "x" /* uint8_t */
#define PRIx16 "x" /* uint16_t */
#define PRIx32 "x" /* uint32_t */
#define PRIx64 "llx" /* uint64_t */
#define PRIxLEAST8 "x" /* uint_least8_t */
#define PRIxLEAST16 "x" /* uint_least16_t */
#define PRIxLEAST32 "x" /* uint_least32_t */
#define PRIxLEAST64 "llx" /* uint_least64_t */
#define PRIxFAST8 "x" /* uint_fast8_t */
#define PRIxFAST16 "x" /* uint_fast16_t */
#define PRIxFAST32 "x" /* uint_fast32_t */
#define PRIxFAST64 "llx" /* uint_fast64_t */
#define PRIxMAX "jx" /* uintmax_t */
#define PRIxPTR "x" /* uintptr_t */
#define PRIX8 "X" /* uint8_t */
#define PRIX16 "X" /* uint16_t */
#define PRIX32 "X" /* uint32_t */
#define PRIX64 "llX" /* uint64_t */
#define PRIXLEAST8 "X" /* uint_least8_t */
#define PRIXLEAST16 "X" /* uint_least16_t */
#define PRIXLEAST32 "X" /* uint_least32_t */
#define PRIXLEAST64 "llX" /* uint_least64_t */
#define PRIXFAST8 "X" /* uint_fast8_t */
#define PRIXFAST16 "X" /* uint_fast16_t */
#define PRIXFAST32 "X" /* uint_fast32_t */
#define PRIXFAST64 "llX" /* uint_fast64_t */
#define PRIXMAX "jX" /* uintmax_t */
#define PRIXPTR "X" /* uintptr_t */
/* fscanf(3) macros for signed integers. */
#define SCNd8 "hhd" /* int8_t */
#define SCNd16 "hd" /* int16_t */
#define SCNd32 "d" /* int32_t */
#define SCNd64 "lld" /* int64_t */
#define SCNdLEAST8 "hhd" /* int_least8_t */
#define SCNdLEAST16 "hd" /* int_least16_t */
#define SCNdLEAST32 "d" /* int_least32_t */
#define SCNdLEAST64 "lld" /* int_least64_t */
#define SCNdFAST8 "d" /* int_fast8_t */
#define SCNdFAST16 "d" /* int_fast16_t */
#define SCNdFAST32 "d" /* int_fast32_t */
#define SCNdFAST64 "lld" /* int_fast64_t */
#define SCNdMAX "jd" /* intmax_t */
#define SCNdPTR "d" /* intptr_t */
#define SCNi8 "hhi" /* int8_t */
#define SCNi16 "hi" /* int16_t */
#define SCNi32 "i" /* int32_t */
#define SCNi64 "lli" /* int64_t */
#define SCNiLEAST8 "hhi" /* int_least8_t */
#define SCNiLEAST16 "hi" /* int_least16_t */
#define SCNiLEAST32 "i" /* int_least32_t */
#define SCNiLEAST64 "lli" /* int_least64_t */
#define SCNiFAST8 "i" /* int_fast8_t */
#define SCNiFAST16 "i" /* int_fast16_t */
#define SCNiFAST32 "i" /* int_fast32_t */
#define SCNiFAST64 "lli" /* int_fast64_t */
#define SCNiMAX "ji" /* intmax_t */
#define SCNiPTR "i" /* intptr_t */
/* fscanf(3) macros for unsigned integers. */
#define SCNo8 "hho" /* uint8_t */
#define SCNo16 "ho" /* uint16_t */
#define SCNo32 "o" /* uint32_t */
#define SCNo64 "llo" /* uint64_t */
#define SCNoLEAST8 "hho" /* uint_least8_t */
#define SCNoLEAST16 "ho" /* uint_least16_t */
#define SCNoLEAST32 "o" /* uint_least32_t */
#define SCNoLEAST64 "llo" /* uint_least64_t */
#define SCNoFAST8 "o" /* uint_fast8_t */
#define SCNoFAST16 "o" /* uint_fast16_t */
#define SCNoFAST32 "o" /* uint_fast32_t */
#define SCNoFAST64 "llo" /* uint_fast64_t */
#define SCNoMAX "jo" /* uintmax_t */
#define SCNoPTR "o" /* uintptr_t */
#define SCNu8 "hhu" /* uint8_t */
#define SCNu16 "hu" /* uint16_t */
#define SCNu32 "u" /* uint32_t */
#define SCNu64 "llu" /* uint64_t */
#define SCNuLEAST8 "hhu" /* uint_least8_t */
#define SCNuLEAST16 "hu" /* uint_least16_t */
#define SCNuLEAST32 "u" /* uint_least32_t */
#define SCNuLEAST64 "llu" /* uint_least64_t */
#define SCNuFAST8 "u" /* uint_fast8_t */
#define SCNuFAST16 "u" /* uint_fast16_t */
#define SCNuFAST32 "u" /* uint_fast32_t */
#define SCNuFAST64 "llu" /* uint_fast64_t */
#define SCNuMAX "ju" /* uintmax_t */
#define SCNuPTR "u" /* uintptr_t */
#define SCNx8 "hhx" /* uint8_t */
#define SCNx16 "hx" /* uint16_t */
#define SCNx32 "x" /* uint32_t */
#define SCNx64 "llx" /* uint64_t */
#define SCNxLEAST8 "hhx" /* uint_least8_t */
#define SCNxLEAST16 "hx" /* uint_least16_t */
#define SCNxLEAST32 "x" /* uint_least32_t */
#define SCNxLEAST64 "llx" /* uint_least64_t */
#define SCNxFAST8 "x" /* uint_fast8_t */
#define SCNxFAST16 "x" /* uint_fast16_t */
#define SCNxFAST32 "x" /* uint_fast32_t */
#define SCNxFAST64 "llx" /* uint_fast64_t */
#define SCNxMAX "jx" /* uintmax_t */
#define SCNxPTR "x" /* uintptr_t */
#endif /* !_MACHINE_INTTYPES_H_ */

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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1988, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)limits.h 8.3 (Berkeley) 1/4/94
*/
#ifndef _MACHINE__LIMITS_H_
#define _MACHINE__LIMITS_H_
/*
* According to ANSI (section 2.2.4.2), the values below must be usable by
* #if preprocessing directives. Additionally, the expression must have the
* same type as would an expression that is an object of the corresponding
* type converted according to the integral promotions. The subtraction for
* INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an
* unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2).
*/
#define __CHAR_BIT 8 /* number of bits in a char */
#define __SCHAR_MAX 0x7f /* max value for a signed char */
#define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */
#define __UCHAR_MAX 0xff /* max value for an unsigned char */
#define __USHRT_MAX 0xffff /* max value for an unsigned short */
#define __SHRT_MAX 0x7fff /* max value for a short */
#define __SHRT_MIN (-0x7fff - 1) /* min value for a short */
#define __UINT_MAX 0xffffffff /* max value for an unsigned int */
#define __INT_MAX 0x7fffffff /* max value for an int */
#define __INT_MIN (-0x7fffffff - 1) /* min value for an int */
#define __ULONG_MAX 0xffffffffUL /* max value for an unsigned long */
#define __LONG_MAX 0x7fffffffL /* max value for a long */
#define __LONG_MIN (-0x7fffffffL - 1) /* min value for a long */
/* max value for an unsigned long long */
#define __ULLONG_MAX 0xffffffffffffffffULL
#define __LLONG_MAX 0x7fffffffffffffffLL /* max value for a long long */
#define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */
#define __SSIZE_MAX __INT_MAX /* max value for a ssize_t */
#define __SIZE_T_MAX __UINT_MAX /* max value for a size_t */
#define __OFF_MAX __LLONG_MAX /* max value for a off_t */
#define __OFF_MIN __LLONG_MIN /* min value for a off_t */
/* Quads and long longs are the same size. Ensure they stay in sync. */
#define __UQUAD_MAX __ULLONG_MAX /* max value for a uquad_t */
#define __QUAD_MAX __LLONG_MAX /* max value for a quad_t */
#define __QUAD_MIN __LLONG_MIN /* min value for a quad_t */
#define __LONG_BIT 32
#define __WORD_BIT 32
/* Minimum signal stack size. */
#define __MINSIGSTKSZ (1024 * 4)
#endif /* !_MACHINE__LIMITS_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
#define INT8_C(c) (c)
#define INT16_C(c) (c)
#define INT32_C(c) (c)
#define INT64_C(c) (c ## LL)
#define UINT8_C(c) (c)
#define UINT16_C(c) (c)
#define UINT32_C(c) (c ## U)
#define UINT64_C(c) (c ## ULL)
#define INTMAX_C(c) INT64_C(c)
#define UINTMAX_C(c) UINT64_C(c)
#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */
#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
/*
* ISO/IEC 9899:1999
* 7.18.2.1 Limits of exact-width integer types
*/
/* Minimum values of exact-width signed integer types. */
#define INT8_MIN (-0x7f-1)
#define INT16_MIN (-0x7fff-1)
#define INT32_MIN (-0x7fffffff-1)
#define INT64_MIN (-0x7fffffffffffffffLL-1)
/* Maximum values of exact-width signed integer types. */
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#define INT64_MAX 0x7fffffffffffffffLL
/* Maximum values of exact-width unsigned integer types. */
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffULL
/*
* ISO/IEC 9899:1999
* 7.18.2.2 Limits of minimum-width integer types
*/
/* Minimum values of minimum-width signed integer types. */
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST16_MIN INT16_MIN
#define INT_LEAST32_MIN INT32_MIN
#define INT_LEAST64_MIN INT64_MIN
/* Maximum values of minimum-width signed integer types. */
#define INT_LEAST8_MAX INT8_MAX
#define INT_LEAST16_MAX INT16_MAX
#define INT_LEAST32_MAX INT32_MAX
#define INT_LEAST64_MAX INT64_MAX
/* Maximum values of minimum-width unsigned integer types. */
#define UINT_LEAST8_MAX UINT8_MAX
#define UINT_LEAST16_MAX UINT16_MAX
#define UINT_LEAST32_MAX UINT32_MAX
#define UINT_LEAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.3 Limits of fastest minimum-width integer types
*/
/* Minimum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MIN INT32_MIN
#define INT_FAST16_MIN INT32_MIN
#define INT_FAST32_MIN INT32_MIN
#define INT_FAST64_MIN INT64_MIN
/* Maximum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MAX INT32_MAX
#define INT_FAST16_MAX INT32_MAX
#define INT_FAST32_MAX INT32_MAX
#define INT_FAST64_MAX INT64_MAX
/* Maximum values of fastest minimum-width unsigned integer types. */
#define UINT_FAST8_MAX UINT32_MAX
#define UINT_FAST16_MAX UINT32_MAX
#define UINT_FAST32_MAX UINT32_MAX
#define UINT_FAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.4 Limits of integer types capable of holding object pointers
*/
#define INTPTR_MIN INT32_MIN
#define INTPTR_MAX INT32_MAX
#define UINTPTR_MAX UINT32_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.5 Limits of greatest-width integer types
*/
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.3 Limits of other integer types
*/
/* Limits of ptrdiff_t. */
#define PTRDIFF_MIN INT32_MIN
#define PTRDIFF_MAX INT32_MAX
/* Limits of sig_atomic_t. */
#define SIG_ATOMIC_MIN INT32_MIN
#define SIG_ATOMIC_MAX INT32_MAX
/* Limit of size_t. */
#define SIZE_MAX UINT32_MAX
/* Limits of wint_t. */
#define WINT_MIN INT32_MIN
#define WINT_MAX INT32_MAX
#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */
#endif /* !_MACHINE__STDINT_H_ */

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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
* From: @(#)types.h 8.3 (Berkeley) 1/5/94
*/
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#ifndef _SYS__TYPES_H_
#error do not include this header, use sys/_types.h
#endif
/*
* Standard type definitions.
*/
typedef __uint32_t __clock_t; /* clock()... */
typedef __int32_t __critical_t;
#ifndef _STANDALONE
typedef double __double_t;
typedef float __float_t;
#endif
typedef __int32_t __int_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __int64_t __int_fast64_t;
typedef __int32_t __register_t;
typedef __int32_t __segsz_t; /* segment size (in pages) */
typedef __int64_t __time_t; /* time()... */
typedef __uint32_t __uint_fast8_t;
typedef __uint32_t __uint_fast16_t;
typedef __uint32_t __uint_fast32_t;
typedef __uint64_t __uint_fast64_t;
typedef __uint32_t __u_register_t;
typedef __uint32_t __vm_paddr_t;
typedef unsigned int ___wchar_t;
#define __WCHAR_MIN 0 /* min value for a wchar_t */
#define __WCHAR_MAX __UINT_MAX /* max value for a wchar_t */
#endif /* !_MACHINE__TYPES_H_ */

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/*
* Copyright (c) 2014 ARM Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the company may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARM_ARCH
/* ACLE standardises a set of pre-defines that describe the ARM architecture.
These were mostly implemented in GCC around GCC-4.8; older versions
have no, or only partial support. To provide a level of backwards
compatibility we try to work out what the definitions should be, given
the older pre-defines that GCC did produce. This isn't complete, but
it should be enough for use by routines that depend on this header. */
/* No need to handle ARMv8, GCC had ACLE support before that. */
#define __ARM_ACLE 101
# ifdef __ARM_ARCH_7__
/* The common subset of ARMv7 in all profiles. */
# define __ARM_ARCH 7
# define __ARM_ARCH_ISA_THUMB 2
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_LDREX 7
# define __ARM_FEATURE_UNALIGNED
# endif
# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)
# define __ARM_ARCH 7
# define __ARM_ARCH_ISA_THUMB 2
# define __ARM_ARCH_ISA_ARM
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_SIMD32
# define __ARM_FEATURE_DSP
# define __ARM_FEATURE_QBIT
# define __ARM_FEATURE_SAT
# define __ARM_FEATURE_LDREX 15
# define __ARM_FEATURE_UNALIGNED
# ifdef __ARM_ARCH_7A__
# define __ARM_ARCH_PROFILE 'A'
# else
# define __ARM_ARCH_PROFILE 'R'
# endif
# endif
# ifdef __ARM_ARCH_7EM__
# define __ARM_ARCH 7
# define __ARM_ARCH_ISA_THUMB 2
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_SIMD32
# define __ARM_FEATURE_DSP
# define __ARM_FEATURE_QBIT
# define __ARM_FEATURE_SAT
# define __ARM_FEATURE_LDREX 7
# define __ARM_FEATURE_UNALIGNED
# define __ARM_ARCH_PROFILE 'M'
# endif
# ifdef __ARM_ARCH_7M__
# define __ARM_ARCH 7
# define __ARM_ARCH_ISA_THUMB 2
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_QBIT
# define __ARM_FEATURE_SAT
# define __ARM_FEATURE_LDREX 7
# define __ARM_FEATURE_UNALIGNED
# define __ARM_ARCH_PROFILE 'M'
# endif
# ifdef __ARM_ARCH_6T2__
# define __ARM_ARCH 6
# define __ARM_ARCH_ISA_THUMB 2
# define __ARM_ARCH_ISA_ARM
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_SIMD32
# define __ARM_FEATURE_DSP
# define __ARM_FEATURE_QBIT
# define __ARM_FEATURE_SAT
# define __ARM_FEATURE_LDREX 4
# define __ARM_FEATURE_UNALIGNED
# endif
# ifdef __ARM_ARCH_6M__
# define __ARM_ARCH 6
# define __ARM_ARCH_ISA_THUMB 1
# define __ARM_ARCH_PROFILE 'M'
# endif
# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
|| defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
|| defined (__ARM_ARCH_6ZK__)
# define __ARM_ARCH 6
# define __ARM_ARCH_ISA_THUMB 1
# define __ARM_ARCH_ISA_ARM
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_SIMD32
# define __ARM_FEATURE_DSP
# define __ARM_FEATURE_QBIT
# define __ARM_FEATURE_SAT
# define __ARM_FEATURE_UNALIGNED
# ifndef __thumb__
# if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
# define __ARM_FEATURE_LDREX 15
# else
# define __ARM_FEATURE_LDREX 4
# endif
# endif
# endif
# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)
# define __ARM_ARCH 5
# define __ARM_ARCH_ISA_ARM
# ifdef __ARM_ARCH_5TE__
# define __ARM_ARCH_ISA_THUMB 1
# endif
# define __ARM_FEATURE_CLZ
# define __ARM_FEATURE_DSP
# endif
# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)
# define __ARM_ARCH 5
# define __ARM_ARCH_ISA_ARM
# ifdef __ARM_ARCH_5TE__
# define __ARM_ARCH_ISA_THUMB 1
# endif
# define __ARM_FEATURE_CLZ
# endif
# ifdef __ARM_ARCH_4T__
# define __ARM_ARCH 4
# define __ARM_ARCH_ISA_ARM
# define __ARM_ARCH_ISA_THUMB 1
# endif
# ifdef __ARM_ARCH_4__
# define __ARM_ARCH 4
# define __ARM_ARCH_ISA_ARM
# endif
# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)
# define __ARM_ARCH 3
# define __ARM_ARCH_ISA_ARM
# endif
# ifdef __ARM_ARCH_2__
# define __ARM_ARCH 2
# define __ARM_ARCH_ISA_ARM
# endif
# ifdef __ARMEB__
# define __ARM_BIG_ENDIAN
# endif
/* If we still don't know what the target architecture is, then we're
probably not using GCC. */
# ifndef __ARM_ARCH
# error Unable to determine architecture version.
# endif
#endif /* __ARM_ARCH */

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/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1998, 2001 Ben Harris
* Copyright (c) 1994-1996 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef MACHINE_ARMREG_H
#define MACHINE_ARMREG_H
#define PSR_MODE 0x0000001f /* mode mask */
#define PSR_USR32_MODE 0x00000010
#define PSR_FIQ32_MODE 0x00000011
#define PSR_IRQ32_MODE 0x00000012
#define PSR_SVC32_MODE 0x00000013
#define PSR_MON32_MODE 0x00000016
#define PSR_ABT32_MODE 0x00000017
#define PSR_HYP32_MODE 0x0000001a
#define PSR_UND32_MODE 0x0000001b
#define PSR_SYS32_MODE 0x0000001f
#define PSR_32_MODE 0x00000010
#define PSR_T 0x00000020 /* Instruction set bit */
#define PSR_F 0x00000040 /* FIQ disable bit */
#define PSR_I 0x00000080 /* IRQ disable bit */
#define PSR_A 0x00000100 /* Imprecise abort bit */
#define PSR_E 0x00000200 /* Data endianess bit */
#define PSR_GE 0x000f0000 /* Greater than or equal to bits */
#define PSR_J 0x01000000 /* Java bit */
#define PSR_Q 0x08000000 /* Sticky overflow bit */
#define PSR_V 0x10000000 /* Overflow bit */
#define PSR_C 0x20000000 /* Carry bit */
#define PSR_Z 0x40000000 /* Zero bit */
#define PSR_N 0x80000000 /* Negative bit */
#define PSR_FLAGS 0xf0000000 /* Flags mask. */
/* The high-order byte is always the implementor */
#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
#define CPU_ID_DEC 0x44000000 /* 'D' */
#define CPU_ID_MOTOROLA 0x4D000000 /* 'M' */
#define CPU_ID_QUALCOM 0x51000000 /* 'Q' */
#define CPU_ID_TI 0x54000000 /* 'T' */
#define CPU_ID_MARVELL 0x56000000 /* 'V' */
#define CPU_ID_INTEL 0x69000000 /* 'i' */
#define CPU_ID_FARADAY 0x66000000 /* 'f' */
#define CPU_ID_VARIANT_SHIFT 20
#define CPU_ID_VARIANT_MASK 0x00f00000
/* How to decide what format the CPUID is in. */
#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
/* On recent ARMs this byte holds the architecture and variant (sub-model) */
#define CPU_ID_ARCH_MASK 0x000f0000
#define CPU_ID_ARCH_V3 0x00000000
#define CPU_ID_ARCH_V4 0x00010000
#define CPU_ID_ARCH_V4T 0x00020000
#define CPU_ID_ARCH_V5 0x00030000
#define CPU_ID_ARCH_V5T 0x00040000
#define CPU_ID_ARCH_V5TE 0x00050000
#define CPU_ID_ARCH_V5TEJ 0x00060000
#define CPU_ID_ARCH_V6 0x00070000
#define CPU_ID_CPUID_SCHEME 0x000f0000
/* Next three nybbles are part number */
#define CPU_ID_PARTNO_MASK 0x0000fff0
/* Intel XScale has sub fields in part number */
#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
/* And finally, the revision number. */
#define CPU_ID_REVISION_MASK 0x0000000f
/* Individual CPUs are probably best IDed by everything but the revision. */
#define CPU_ID_CPU_MASK 0xfffffff0
/* ARM9 and later CPUs */
#define CPU_ID_ARM920T 0x41129200
#define CPU_ID_ARM920T_ALT 0x41009200
#define CPU_ID_ARM922T 0x41029220
#define CPU_ID_ARM926EJS 0x41069260
#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
#define CPU_ID_ARM1022ES 0x4105a220
#define CPU_ID_ARM1026EJS 0x4106a260
#define CPU_ID_ARM1136JS 0x4107b360
#define CPU_ID_ARM1136JSR1 0x4117b360
#define CPU_ID_ARM1176JZS 0x410fb760
/* CPUs that follow the CPUID scheme */
#define CPU_ID_SCHEME_MASK \
(CPU_ID_IMPLEMENTOR_MASK | CPU_ID_ARCH_MASK | CPU_ID_PARTNO_MASK)
#define CPU_ID_CORTEXA5 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc050)
#define CPU_ID_CORTEXA7 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc070)
#define CPU_ID_CORTEXA8 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc080)
#define CPU_ID_CORTEXA8R1 (CPU_ID_CORTEXA8 | (1 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA8R2 (CPU_ID_CORTEXA8 | (2 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA8R3 (CPU_ID_CORTEXA8 | (3 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA9 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc090)
#define CPU_ID_CORTEXA9R1 (CPU_ID_CORTEXA9 | (1 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA9R2 (CPU_ID_CORTEXA9 | (2 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA9R3 (CPU_ID_CORTEXA9 | (3 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA9R4 (CPU_ID_CORTEXA9 | (4 << CPU_ID_VARIANT_SHIFT))
/* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */
#define CPU_ID_CORTEXA12 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0)
#define CPU_ID_CORTEXA12R0 (CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA15 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0)
#define CPU_ID_CORTEXA15R0 (CPU_ID_CORTEXA15 | (0 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA15R1 (CPU_ID_CORTEXA15 | (1 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA15R2 (CPU_ID_CORTEXA15 | (2 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA15R3 (CPU_ID_CORTEXA15 | (3 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_CORTEXA53 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd030)
#define CPU_ID_CORTEXA57 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd070)
#define CPU_ID_CORTEXA72 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd080)
#define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME | 0x06f0)
/* Snapdragon S4 Pro/APQ8064 */
#define CPU_ID_KRAIT300R0 (CPU_ID_KRAIT300 | (0 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_KRAIT300R1 (CPU_ID_KRAIT300 | (1 << CPU_ID_VARIANT_SHIFT))
#define CPU_ID_TI925T 0x54029250
#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */
#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
/*
* LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported
* L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID.
*/
#ifdef SOC_MV_LOKIPLUS
#define CPU_ID_MV88FR571_41 0x00000000
#else
#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
#endif
#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
/* Marvell's CPUIDs with ARM ID in implementor field */
#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
#define CPU_ID_FA526 0x66015260
#define CPU_ID_FA626TE 0x66056260
#define CPU_ID_80200 0x69052000
#define CPU_ID_PXA250 0x69052100 /* sans core revision */
#define CPU_ID_PXA210 0x69052120
#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
#define CPU_ID_PXA27X 0x69054110
#define CPU_ID_80321_400 0x69052420
#define CPU_ID_80321_600 0x69052430
#define CPU_ID_80321_400_B0 0x69052c20
#define CPU_ID_80321_600_B0 0x69052c30
#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */
#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */
#define CPU_ID_81342 0x69056810
#define CPU_ID_IXP425 0x690541c0
#define CPU_ID_IXP425_533 0x690541c0
#define CPU_ID_IXP425_400 0x690541d0
#define CPU_ID_IXP425_266 0x690541f0
#define CPU_ID_IXP435 0x69054040
#define CPU_ID_IXP465 0x69054200
/* CPUID registers */
#define ARM_PFR0_ARM_ISA_MASK 0x0000000f
#define ARM_PFR0_THUMB_MASK 0x000000f0
#define ARM_PFR0_THUMB 0x10
#define ARM_PFR0_THUMB2 0x30
#define ARM_PFR0_JAZELLE_MASK 0x00000f00
#define ARM_PFR0_THUMBEE_MASK 0x0000f000
#define ARM_PFR1_ARMV4_MASK 0x0000000f
#define ARM_PFR1_SEC_EXT_MASK 0x000000f0
#define ARM_PFR1_MICROCTRL_MASK 0x00000f00
/*
* Post-ARM3 CP15 registers:
*
* 1 Control register
*
* 2 Translation Table Base
*
* 3 Domain Access Control
*
* 4 Reserved
*
* 5 Fault Status
*
* 6 Fault Address
*
* 7 Cache/write-buffer Control
*
* 8 TLB Control
*
* 9 Cache Lockdown
*
* 10 TLB Lockdown
*
* 11 Reserved
*
* 12 Reserved
*
* 13 Process ID (for FCSE)
*
* 14 Reserved
*
* 15 Implementation Dependent
*/
/* Some of the definitions below need cleaning up for V3/V4 architectures */
/* CPU control register (CP15 register 1) */
#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */
#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */
#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/
#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */
#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */
#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */
#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */
#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
/* This is an undocumented flag
* used to work around a cache bug
* in r0 steppings. See errata
* 364296.
*/
/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
/* Note: XSCale core 3 uses those for LLR DCcahce attributes */
#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
#define XSCALE_AUXCTL_MD_MASK 0x00000030
/* Xscale Core 3 only */
#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */
/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */
#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */
#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */
#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */
#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */
#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */
#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */
#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */
#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */
#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */
/* Cache type register definitions */
#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
#define CPU_CT_S (1U << 24) /* split cache */
#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
#define CPU_CT_FORMAT(x) ((x) >> 29)
/* Cache type register definitions for ARM v7 */
#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */
#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */
#define CPU_CT_CTYPE_WT 0 /* write-through */
#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
#define CPU_CT_ARMV7 0x4
/* ARM v7 Cache type definitions */
#define CPUV7_CT_CTYPE_WT (1U << 31)
#define CPUV7_CT_CTYPE_WB (1 << 30)
#define CPUV7_CT_CTYPE_RA (1 << 29)
#define CPUV7_CT_CTYPE_WA (1 << 28)
#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */
#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */
#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */
#define CPUV7_L2CTLR_NPROC_SHIFT 24
#define CPUV7_L2CTLR_NPROC(r) ((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1)
#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7)
#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7)
#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7)
#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7)
#define CACHE_ICACHE 1
#define CACHE_DCACHE 2
#define CACHE_SEP_CACHE 3
#define CACHE_UNI_CACHE 4
/* Fault status register definitions */
#define FAULT_USER 0x10
#define FAULT_ALIGN 0x001 /* Alignment Fault */
#define FAULT_DEBUG 0x002 /* Debug Event */
#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */
#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */
#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */
#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */
#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */
#define FAULT_EA_PREC 0x008 /* External Abort */
#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */
#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */
#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */
#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */
#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */
#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */
#define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */
#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */
#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */
#define FAULT_PARITY 0x019 /* Parity Error */
#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */
#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */
#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \
((((fsr) & (1 << 10)) >> (10 - 4))))
#define FSR_LPAE (1 << 9) /* LPAE indicator */
#define FSR_WNR (1 << 11) /* Write-not-Read access */
#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
#define FSR_CM (1 << 13) /* Cache maintenance fault */
/*
* Address of the vector page, low and high versions.
*/
#ifndef __ASSEMBLER__
#define ARM_VECTORS_LOW 0x00000000U
#define ARM_VECTORS_HIGH 0xffff0000U
#else
#define ARM_VECTORS_LOW 0
#define ARM_VECTORS_HIGH 0xffff0000
#endif
/*
* ARM Instructions
*
* 3 3 2 2 2
* 1 0 9 8 7 0
* +-------+-------------------------------------------------------+
* | cond | instruction dependant |
* |c c c c| |
* +-------+-------------------------------------------------------+
*/
#define INSN_SIZE 4 /* Always 4 bytes */
#define INSN_COND_MASK 0xf0000000 /* Condition mask */
#define INSN_COND_AL 0xe0000000 /* Always condition */
/* ARM register defines */
#define ARM_REG_SIZE 4
#define ARM_REG_NUM_PC 15
#define ARM_REG_NUM_LR 14
#define ARM_REG_NUM_SP 13
#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
/* ARM Hypervisor Related Defines */
#define ARM_CP15_HDCR_HPMN 0x0000001f
#endif /* !MACHINE_ARMREG_H */

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/* $NetBSD: asm.h,v 1.5 2003/08/07 16:26:53 agc Exp $ */
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)asm.h 5.5 (Berkeley) 5/7/91
*/
#ifndef _MACHINE_ASM_H_
#define _MACHINE_ASM_H_
#include <sys/cdefs.h>
#define _C_LABEL(x) x
#define _ASM_LABEL(x) x
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 2
#endif
#ifndef _STANDALONE
#define STOP_UNWINDING .cantunwind
#define _FNSTART .fnstart
#define _FNEND .fnend
#define _SAVE(...) .save __VA_ARGS__
#else
#define STOP_UNWINDING
#define _FNSTART
#define _FNEND
#define _SAVE(...)
#endif
/*
* gas/arm uses @ as a single comment character and thus cannot be used here.
* It recognises the # instead of an @ symbol in .type directives.
*/
#define _ASM_TYPE_FUNCTION #function
#define _ASM_TYPE_OBJECT #object
/*
* EENTRY()/EEND() mark "extra" entry/exit points from a function.
* LEENTRY()/LEEND() are the same for local symbols.
* The unwind info cannot handle the concept of a nested function, or a function
* with multiple .fnstart directives, but some of our assembler code is written
* with multiple labels to allow entry at several points. The EENTRY() macro
* defines such an extra entry point without a new .fnstart, so that it's
* basically just a label that you can jump to. The EEND() macro does nothing
* at all, except document the exit point associated with the same-named entry.
*/
#define GLOBAL(x) .global x
#ifdef __thumb__
#define _FUNC_MODE .code 16; .thumb_func
#else
#define _FUNC_MODE .code 32
#endif
#define _LEENTRY(x) .type x,_ASM_TYPE_FUNCTION; _FUNC_MODE; x:
#define _LEEND(x) /* nothing */
#define _EENTRY(x) GLOBAL(x); _LEENTRY(x)
#define _EEND(x) _LEEND(x)
#define _LENTRY(x) .text; _ALIGN_TEXT; _LEENTRY(x); _FNSTART
#define _LEND(x) .size x, . - x; _FNEND
#define _ENTRY(x) .text; _ALIGN_TEXT; _EENTRY(x); _FNSTART
#define _END(x) _LEND(x)
#define ENTRY(y) _ENTRY(_C_LABEL(y));
#define EENTRY(y) _EENTRY(_C_LABEL(y));
#define ENTRY_NP(y) _ENTRY(_C_LABEL(y))
#define EENTRY_NP(y) _EENTRY(_C_LABEL(y))
#define END(y) _END(_C_LABEL(y))
#define EEND(y) _EEND(_C_LABEL(y))
#define ASENTRY(y) _ENTRY(_ASM_LABEL(y));
#define ASLENTRY(y) _LENTRY(_ASM_LABEL(y));
#define ASEENTRY(y) _EENTRY(_ASM_LABEL(y));
#define ASLEENTRY(y) _LEENTRY(_ASM_LABEL(y));
#define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y))
#define ASLENTRY_NP(y) _LENTRY(_ASM_LABEL(y))
#define ASEENTRY_NP(y) _EENTRY(_ASM_LABEL(y))
#define ASLEENTRY_NP(y) _LEENTRY(_ASM_LABEL(y))
#define ASEND(y) _END(_ASM_LABEL(y))
#define ASLEND(y) _LEND(_ASM_LABEL(y))
#define ASEEND(y) _EEND(_ASM_LABEL(y))
#define ASLEEND(y) _LEEND(_ASM_LABEL(y))
#define ASMSTR .asciz
#if defined(PIC)
#define PLT_SYM(x) PIC_SYM(x, PLT)
#define GOT_SYM(x) PIC_SYM(x, GOT)
#define GOT_GET(x,got,sym) \
ldr x, sym; \
ldr x, [x, got]
#define GOT_INIT(got,gotsym,pclabel) \
ldr got, gotsym; \
pclabel: add got, pc
#ifdef __thumb__
#define GOT_INITSYM(gotsym,pclabel) \
.align 2; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+4)
#else
#define GOT_INITSYM(gotsym,pclabel) \
.align 2; \
gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) - (pclabel+8)
#endif
#ifdef __STDC__
#define PIC_SYM(x,y) x ## ( ## y ## )
#else
#define PIC_SYM(x,y) x/**/(/**/y/**/)
#endif
#else
#define PLT_SYM(x) x
#define GOT_SYM(x) x
#define GOT_GET(x,got,sym) \
ldr x, sym;
#define GOT_INIT(got,gotsym,pclabel)
#define GOT_INITSYM(gotsym,pclabel)
#define PIC_SYM(x,y) x
#endif /* PIC */
#undef __FBSDID
#if !defined(lint) && !defined(STRIP_FBSDID)
#define __FBSDID(s) .ident s
#else
#define __FBSDID(s) /* nothing */
#endif
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
#ifdef __STDC__
#define WARN_REFERENCES(sym,msg) \
.stabs msg ## ,30,0,0,0 ; \
.stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0
#else
#define WARN_REFERENCES(sym,msg) \
.stabs msg,30,0,0,0 ; \
.stabs __STRING(sym),1,0,0,0
#endif /* __STDC__ */
# define RET bx lr
# define RETeq bxeq lr
# define RETne bxne lr
# define RETc(c) bx##c lr
#if __ARM_ARCH >= 7
#define ISB isb
#define DSB dsb
#define DMB dmb
#define WFI wfi
#if defined(__ARM_ARCH_7VE__) || defined(__clang__)
#define MSR_ELR_HYP(regnum) msr elr_hyp, lr
#define ERET eret
#else
#define MSR_ELR_HYP(regnum) .word (0xe12ef300 | regnum)
#define ERET .word 0xe160006e
#endif
#elif __ARM_ARCH == 6
#include <machine/sysreg.h>
#define ISB mcr CP15_CP15ISB
#define DSB mcr CP15_CP15DSB
#define DMB mcr CP15_CP15DMB
#define WFI mcr CP15_CP15WFI
#endif
#endif /* !_MACHINE_ASM_H_ */

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/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_
#include <machine/_bus.h>
/*
* int bus_space_map (bus_space_tag_t t, bus_addr_t addr,
* bus_size_t size, int flags, bus_space_handle_t *bshp);
*
* Map a region of bus space.
*/
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_LINEAR 0x02
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
/*
* Bus space for ARM.
*
* The functions used most often are grouped together at the beginning to ensure
* that all the data fits into a single cache line. The inline implementations
* of single read/write access these values a lot.
*/
struct bus_space {
/* Read/write single and barrier: the most commonly used functions. */
uint8_t (*bs_r_1)(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint32_t (*bs_r_4)(bus_space_tag_t, bus_space_handle_t, bus_size_t);
void (*bs_w_1)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t);
void (*bs_w_4)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t);
void (*bs_barrier)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, int);
/* Backlink to parent (if copied), and implementation private data. */
struct bus_space *bs_parent;
void *bs_privdata;
/* mapping/unmapping */
int (*bs_map) (bus_space_tag_t, bus_addr_t, bus_size_t,
int, bus_space_handle_t *);
void (*bs_unmap) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
int (*bs_subregion) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
/* allocation/deallocation */
int (*bs_alloc) (bus_space_tag_t, bus_addr_t, bus_addr_t,
bus_size_t, bus_size_t, bus_size_t, int,
bus_addr_t *, bus_space_handle_t *);
void (*bs_free) (bus_space_tag_t, bus_space_handle_t,
bus_size_t);
/* Read single, the less commonly used functions. */
uint16_t (*bs_r_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint64_t (*bs_r_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
/* read multiple */
void (*bs_rm_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint8_t *, bus_size_t);
void (*bs_rm_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint16_t *, bus_size_t);
void (*bs_rm_4) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rm_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* read region */
void (*bs_rr_1) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rr_2) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rr_4) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rr_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* Write single, the less commonly used functions. */
void (*bs_w_2) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t);
void (*bs_w_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t);
/* write multiple */
void (*bs_wm_1) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wm_2) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wm_4) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wm_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
/* write region */
void (*bs_wr_1) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wr_2) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wr_4) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wr_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
/* set multiple */
void (*bs_sm_1) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t, bus_size_t);
void (*bs_sm_2) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t, bus_size_t);
void (*bs_sm_4) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t, bus_size_t);
void (*bs_sm_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t, bus_size_t);
/* set region */
void (*bs_sr_1) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t, bus_size_t);
void (*bs_sr_2) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t, bus_size_t);
void (*bs_sr_4) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t, bus_size_t);
void (*bs_sr_8) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t, bus_size_t);
/* copy */
void (*bs_c_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
/* read stream (single) */
uint8_t (*bs_r_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint16_t (*bs_r_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint32_t (*bs_r_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint64_t (*bs_r_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t);
/* read multiple stream */
void (*bs_rm_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint8_t *, bus_size_t);
void (*bs_rm_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint16_t *, bus_size_t);
void (*bs_rm_4_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rm_8_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* read region stream */
void (*bs_rr_1_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t *, bus_size_t);
void (*bs_rr_2_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t *, bus_size_t);
void (*bs_rr_4_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t *, bus_size_t);
void (*bs_rr_8_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t *, bus_size_t);
/* write stream (single) */
void (*bs_w_1_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint8_t);
void (*bs_w_2_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint16_t);
void (*bs_w_4_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint32_t);
void (*bs_w_8_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, uint64_t);
/* write multiple stream */
void (*bs_wm_1_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wm_2_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wm_4_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wm_8_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
/* write region stream */
void (*bs_wr_1_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint8_t *, bus_size_t);
void (*bs_wr_2_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint16_t *, bus_size_t);
void (*bs_wr_4_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint32_t *, bus_size_t);
void (*bs_wr_8_s) (bus_space_tag_t, bus_space_handle_t,
bus_size_t, const uint64_t *, bus_size_t);
};
/*
* Utility macros; INTERNAL USE ONLY.
*/
#define __bs_c(a,b) __CONCAT(a,b)
#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size)
#define __bs_nonsingle(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname(type,sz))((t), h, o, a, c)
#define __bs_set(type, sz, t, h, o, v, c) \
(*(t)->__bs_opname(type,sz))((t), h, o, v, c)
#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \
(*(t)->__bs_opname(c,sz))((t), h1, o1, h2, o2, cnt)
#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s)
#define __bs_rs_s(sz, t, h, o) \
(*(t)->__bs_opname_s(r,sz))((t), h, o)
#define __bs_ws_s(sz, t, h, o, v) \
(*(t)->__bs_opname_s(w,sz))((t), h, o, v)
#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname_s(type,sz))((t), h, o, a, c)
#define __generate_inline_bs_rs(IFN, MBR, TYP) \
static inline TYP \
IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) \
{ \
\
if (__predict_true(t->MBR == NULL)) \
return (*(volatile TYP *)(h + o)); \
else \
return (t->MBR(t, h, o)); \
}
#define __generate_inline_bs_ws(IFN, MBR, TYP) \
static inline void \
IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, TYP v)\
{ \
\
if (__predict_true(t->MBR == NULL)) \
*(volatile TYP *)(h + o) = v; \
else \
t->MBR(t, h, o, v); \
}
/*
* Mapping and unmapping operations.
*/
#define bus_space_map(t, a, s, c, hp) \
(*(t)->bs_map)((t), (a), (s), (c), (hp))
#define bus_space_unmap(t, h, s) \
(*(t)->bs_unmap)((t), (h), (s))
#define bus_space_subregion(t, h, o, s, hp) \
(*(t)->bs_subregion)((t), (h), (o), (s), (hp))
/*
* Allocation and deallocation operations.
*/
#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \
(*(t)->bs_alloc)((t), (rs), (re), (s), (a), (b), \
(c), (ap), (hp))
#define bus_space_free(t, h, s) \
(*(t)->bs_free)((t), (h), (s))
/*
* Bus barrier operations.
*/
#define bus_space_barrier(t, h, o, l, f) \
(*(t)->bs_barrier)((t), (h), (o), (l), (f))
#define BUS_SPACE_BARRIER_READ 0x01
#define BUS_SPACE_BARRIER_WRITE 0x02
/*
* Bus read (single) operations.
*/
__generate_inline_bs_rs(bus_space_read_1, bs_r_1, uint8_t);
__generate_inline_bs_rs(bus_space_read_2, bs_r_2, uint16_t);
__generate_inline_bs_rs(bus_space_read_4, bs_r_4, uint32_t);
__generate_inline_bs_rs(bus_space_read_8, bs_r_8, uint64_t);
__generate_inline_bs_rs(bus_space_read_stream_1, bs_r_1_s, uint8_t);
__generate_inline_bs_rs(bus_space_read_stream_2, bs_r_2_s, uint16_t);
__generate_inline_bs_rs(bus_space_read_stream_4, bs_r_4_s, uint32_t);
__generate_inline_bs_rs(bus_space_read_stream_8, bs_r_8_s, uint64_t);
/*
* Bus read multiple operations.
*/
#define bus_space_read_multi_1(t, h, o, a, c) \
__bs_nonsingle(rm,1,(t),(h),(o),(a),(c))
#define bus_space_read_multi_2(t, h, o, a, c) \
__bs_nonsingle(rm,2,(t),(h),(o),(a),(c))
#define bus_space_read_multi_4(t, h, o, a, c) \
__bs_nonsingle(rm,4,(t),(h),(o),(a),(c))
#define bus_space_read_multi_8(t, h, o, a, c) \
__bs_nonsingle(rm,8,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
/*
* Bus read region operations.
*/
#define bus_space_read_region_1(t, h, o, a, c) \
__bs_nonsingle(rr,1,(t),(h),(o),(a),(c))
#define bus_space_read_region_2(t, h, o, a, c) \
__bs_nonsingle(rr,2,(t),(h),(o),(a),(c))
#define bus_space_read_region_4(t, h, o, a, c) \
__bs_nonsingle(rr,4,(t),(h),(o),(a),(c))
#define bus_space_read_region_8(t, h, o, a, c) \
__bs_nonsingle(rr,8,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
/*
* Bus write (single) operations.
*/
__generate_inline_bs_ws(bus_space_write_1, bs_w_1, uint8_t);
__generate_inline_bs_ws(bus_space_write_2, bs_w_2, uint16_t);
__generate_inline_bs_ws(bus_space_write_4, bs_w_4, uint32_t);
__generate_inline_bs_ws(bus_space_write_8, bs_w_8, uint64_t);
__generate_inline_bs_ws(bus_space_write_stream_1, bs_w_1_s, uint8_t);
__generate_inline_bs_ws(bus_space_write_stream_2, bs_w_2_s, uint16_t);
__generate_inline_bs_ws(bus_space_write_stream_4, bs_w_4_s, uint32_t);
__generate_inline_bs_ws(bus_space_write_stream_8, bs_w_8_s, uint64_t);
/*
* Bus write multiple operations.
*/
#define bus_space_write_multi_1(t, h, o, a, c) \
__bs_nonsingle(wm,1,(t),(h),(o),(a),(c))
#define bus_space_write_multi_2(t, h, o, a, c) \
__bs_nonsingle(wm,2,(t),(h),(o),(a),(c))
#define bus_space_write_multi_4(t, h, o, a, c) \
__bs_nonsingle(wm,4,(t),(h),(o),(a),(c))
#define bus_space_write_multi_8(t, h, o, a, c) \
__bs_nonsingle(wm,8,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
/*
* Bus write region operations.
*/
#define bus_space_write_region_1(t, h, o, a, c) \
__bs_nonsingle(wr,1,(t),(h),(o),(a),(c))
#define bus_space_write_region_2(t, h, o, a, c) \
__bs_nonsingle(wr,2,(t),(h),(o),(a),(c))
#define bus_space_write_region_4(t, h, o, a, c) \
__bs_nonsingle(wr,4,(t),(h),(o),(a),(c))
#define bus_space_write_region_8(t, h, o, a, c) \
__bs_nonsingle(wr,8,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
/*
* Set multiple operations.
*/
#define bus_space_set_multi_1(t, h, o, v, c) \
__bs_set(sm,1,(t),(h),(o),(v),(c))
#define bus_space_set_multi_2(t, h, o, v, c) \
__bs_set(sm,2,(t),(h),(o),(v),(c))
#define bus_space_set_multi_4(t, h, o, v, c) \
__bs_set(sm,4,(t),(h),(o),(v),(c))
#define bus_space_set_multi_8(t, h, o, v, c) \
__bs_set(sm,8,(t),(h),(o),(v),(c))
/*
* Set region operations.
*/
#define bus_space_set_region_1(t, h, o, v, c) \
__bs_set(sr,1,(t),(h),(o),(v),(c))
#define bus_space_set_region_2(t, h, o, v, c) \
__bs_set(sr,2,(t),(h),(o),(v),(c))
#define bus_space_set_region_4(t, h, o, v, c) \
__bs_set(sr,4,(t),(h),(o),(v),(c))
#define bus_space_set_region_8(t, h, o, v, c) \
__bs_set(sr,8,(t),(h),(o),(v),(c))
/*
* Copy operations.
*/
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
__bs_copy(1, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
__bs_copy(2, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
__bs_copy(4, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
__bs_copy(8, t, h1, o1, h2, o2, c)
/*
* Macros to provide prototypes for all the functions used in the
* bus_space structure
*/
#define bs_map_proto(f) \
int __bs_c(f,_bs_map) (bus_space_tag_t t, bus_addr_t addr, \
bus_size_t size, int cacheable, bus_space_handle_t *bshp);
#define bs_unmap_proto(f) \
void __bs_c(f,_bs_unmap) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t size);
#define bs_subregion_proto(f) \
int __bs_c(f,_bs_subregion) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, bus_size_t size, \
bus_space_handle_t *nbshp);
#define bs_alloc_proto(f) \
int __bs_c(f,_bs_alloc) (bus_space_tag_t t, bus_addr_t rstart, \
bus_addr_t rend, bus_size_t size, bus_size_t align, \
bus_size_t boundary, int cacheable, bus_addr_t *addrp, \
bus_space_handle_t *bshp);
#define bs_free_proto(f) \
void __bs_c(f,_bs_free) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t size);
#define bs_mmap_proto(f) \
int __bs_c(f,_bs_mmap) (struct cdev *, vm_offset_t, vm_paddr_t *, int);
#define bs_barrier_proto(f) \
void __bs_c(f,_bs_barrier) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, bus_size_t len, int flags);
#define bs_r_1_proto(f) \
uint8_t __bs_c(f,_bs_r_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_2_proto(f) \
uint16_t __bs_c(f,_bs_r_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_4_proto(f) \
uint32_t __bs_c(f,_bs_r_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_8_proto(f) \
uint64_t __bs_c(f,_bs_r_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_1_s_proto(f) \
uint8_t __bs_c(f,_bs_r_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_2_s_proto(f) \
uint16_t __bs_c(f,_bs_r_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_r_4_s_proto(f) \
uint32_t __bs_c(f,_bs_r_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset);
#define bs_w_1_proto(f) \
void __bs_c(f,_bs_w_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value);
#define bs_w_2_proto(f) \
void __bs_c(f,_bs_w_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value);
#define bs_w_4_proto(f) \
void __bs_c(f,_bs_w_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value);
#define bs_w_8_proto(f) \
void __bs_c(f,_bs_w_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value);
#define bs_w_1_s_proto(f) \
void __bs_c(f,_bs_w_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value);
#define bs_w_2_s_proto(f) \
void __bs_c(f,_bs_w_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value);
#define bs_w_4_s_proto(f) \
void __bs_c(f,_bs_w_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value);
#define bs_rm_1_proto(f) \
void __bs_c(f,_bs_rm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t *addr, bus_size_t count);
#define bs_rm_2_proto(f) \
void __bs_c(f,_bs_rm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t *addr, bus_size_t count);
#define bs_rm_4_proto(f) \
void __bs_c(f,_bs_rm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t *addr, bus_size_t count);
#define bs_rm_8_proto(f) \
void __bs_c(f,_bs_rm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t *addr, bus_size_t count);
#define bs_wm_1_proto(f) \
void __bs_c(f,_bs_wm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint8_t *addr, bus_size_t count);
#define bs_wm_2_proto(f) \
void __bs_c(f,_bs_wm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint16_t *addr, bus_size_t count);
#define bs_wm_4_proto(f) \
void __bs_c(f,_bs_wm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint32_t *addr, bus_size_t count);
#define bs_wm_8_proto(f) \
void __bs_c(f,_bs_wm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint64_t *addr, bus_size_t count);
#define bs_rr_1_proto(f) \
void __bs_c(f, _bs_rr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t *addr, bus_size_t count);
#define bs_rr_2_proto(f) \
void __bs_c(f, _bs_rr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t *addr, bus_size_t count);
#define bs_rr_4_proto(f) \
void __bs_c(f, _bs_rr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t *addr, bus_size_t count);
#define bs_rr_8_proto(f) \
void __bs_c(f, _bs_rr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t *addr, bus_size_t count);
#define bs_wr_1_proto(f) \
void __bs_c(f, _bs_wr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint8_t *addr, bus_size_t count);
#define bs_wr_2_proto(f) \
void __bs_c(f, _bs_wr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint16_t *addr, bus_size_t count);
#define bs_wr_4_proto(f) \
void __bs_c(f, _bs_wr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint32_t *addr, bus_size_t count);
#define bs_wr_8_proto(f) \
void __bs_c(f, _bs_wr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, const uint64_t *addr, bus_size_t count);
#define bs_sm_1_proto(f) \
void __bs_c(f,_bs_sm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value, bus_size_t count);
#define bs_sm_2_proto(f) \
void __bs_c(f,_bs_sm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value, bus_size_t count);
#define bs_sm_4_proto(f) \
void __bs_c(f,_bs_sm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value, bus_size_t count);
#define bs_sm_8_proto(f) \
void __bs_c(f,_bs_sm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value, bus_size_t count);
#define bs_sr_1_proto(f) \
void __bs_c(f,_bs_sr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint8_t value, bus_size_t count);
#define bs_sr_2_proto(f) \
void __bs_c(f,_bs_sr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint16_t value, bus_size_t count);
#define bs_sr_4_proto(f) \
void __bs_c(f,_bs_sr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint32_t value, bus_size_t count);
#define bs_sr_8_proto(f) \
void __bs_c(f,_bs_sr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \
bus_size_t offset, uint64_t value, bus_size_t count);
#define bs_c_1_proto(f) \
void __bs_c(f,_bs_c_1) (bus_space_tag_t t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_c_2_proto(f) \
void __bs_c(f,_bs_c_2) (bus_space_tag_t t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_c_4_proto(f) \
void __bs_c(f,_bs_c_4) (bus_space_tag_t t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_c_8_proto(f) \
void __bs_c(f,_bs_c_8) (bus_space_tag_t t, bus_space_handle_t bsh1, \
bus_size_t offset1, bus_space_handle_t bsh2, \
bus_size_t offset2, bus_size_t count);
#define bs_protos(f) \
bs_map_proto(f); \
bs_unmap_proto(f); \
bs_subregion_proto(f); \
bs_alloc_proto(f); \
bs_free_proto(f); \
bs_mmap_proto(f); \
bs_barrier_proto(f); \
bs_r_1_proto(f); \
bs_r_2_proto(f); \
bs_r_4_proto(f); \
bs_r_8_proto(f); \
bs_r_1_s_proto(f); \
bs_r_2_s_proto(f); \
bs_r_4_s_proto(f); \
bs_w_1_proto(f); \
bs_w_2_proto(f); \
bs_w_4_proto(f); \
bs_w_8_proto(f); \
bs_w_1_s_proto(f); \
bs_w_2_s_proto(f); \
bs_w_4_s_proto(f); \
bs_rm_1_proto(f); \
bs_rm_2_proto(f); \
bs_rm_4_proto(f); \
bs_rm_8_proto(f); \
bs_wm_1_proto(f); \
bs_wm_2_proto(f); \
bs_wm_4_proto(f); \
bs_wm_8_proto(f); \
bs_rr_1_proto(f); \
bs_rr_2_proto(f); \
bs_rr_4_proto(f); \
bs_rr_8_proto(f); \
bs_wr_1_proto(f); \
bs_wr_2_proto(f); \
bs_wr_4_proto(f); \
bs_wr_8_proto(f); \
bs_sm_1_proto(f); \
bs_sm_2_proto(f); \
bs_sm_4_proto(f); \
bs_sm_8_proto(f); \
bs_sr_1_proto(f); \
bs_sr_2_proto(f); \
bs_sr_4_proto(f); \
bs_sr_8_proto(f); \
bs_c_1_proto(f); \
bs_c_2_proto(f); \
bs_c_4_proto(f); \
bs_c_8_proto(f);
void generic_bs_unimplemented(void);
#define BS_UNIMPLEMENTED (void *)generic_bs_unimplemented
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXADDR 0xFFFFFFFF
#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
#define BUS_SPACE_MAXSIZE 0xFFFFFFFF
#define BUS_SPACE_UNRESTRICTED (~0)
#define BUS_PEEK_FUNC(width, type) \
static inline int \
bus_space_peek_##width(bus_space_tag_t tag, \
bus_space_handle_t hnd, bus_size_t offset, type *value) \
{ \
type tmp; \
tmp = bus_space_read_##width(tag, hnd, offset); \
*value = (type)tmp; \
return (0); \
}
BUS_PEEK_FUNC(1, uint8_t)
BUS_PEEK_FUNC(2, uint16_t)
BUS_PEEK_FUNC(4, uint32_t)
BUS_PEEK_FUNC(8, uint64_t)
#define BUS_POKE_FUNC(width, type) \
static inline int \
bus_space_poke_##width(bus_space_tag_t tag, \
bus_space_handle_t hnd, bus_size_t offset, type value) \
{ \
bus_space_write_##width(tag, hnd, offset, value); \
return (0); \
}
BUS_POKE_FUNC(1, uint8_t)
BUS_POKE_FUNC(2, uint16_t)
BUS_POKE_FUNC(4, uint32_t)
BUS_POKE_FUNC(8, uint64_t)
#include <machine/bus_dma.h>
/*
* Get the physical address of a bus space memory-mapped resource.
* Doing this as a macro is a temporary solution until a more robust fix is
* designed. It also serves to mark the locations needing that fix.
*/
#define BUS_SPACE_PHYSADDR(res, offs) \
((u_int)(rman_get_start(res)+(offs)))
#endif /* _MACHINE_BUS_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2012 Konstantin Belousov <kib@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __MACHINE_COUNTER_H__
#define __MACHINE_COUNTER_H__
#include <sys/pcpu.h>
#include <machine/atomic.h>
#define EARLY_COUNTER &__pcpu[0].pc_early_dummy_counter
#define counter_enter() do {} while (0)
#define counter_exit() do {} while (0)
#ifdef IN_SUBR_COUNTER_C
static inline uint64_t
counter_u64_read_one(uint64_t *p, int cpu)
{
return (atomic_load_64((uint64_t *)zpcpu_get_cpu(p, cpu)));
}
static inline uint64_t
counter_u64_fetch_inline(uint64_t *p)
{
uint64_t r;
int i;
r = 0;
CPU_FOREACH(i)
r += counter_u64_read_one((uint64_t *)p, i);
return (r);
}
static void
counter_u64_zero_one_cpu(void *arg)
{
atomic_store_64((uint64_t *)zpcpu_get(arg), 0);
}
static inline void
counter_u64_zero_inline(counter_u64_t c)
{
smp_rendezvous(smp_no_rendezvous_barrier, counter_u64_zero_one_cpu,
smp_no_rendezvous_barrier, c);
}
#endif
#define counter_u64_add_protected(c, inc) counter_u64_add(c, inc)
static inline void
counter_u64_add(counter_u64_t c, int64_t inc)
{
atomic_add_64((uint64_t *)zpcpu_get(c), inc);
}
#endif /* ! __MACHINE_COUNTER_H__ */

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/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */
#ifndef MACHINE_CPU_H
#define MACHINE_CPU_H
#include <machine/armreg.h>
#include <machine/frame.h>
void cpu_halt(void);
#ifdef _KERNEL
#include <machine/atomic.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/sysreg.h>
/*
* Some kernel modules (dtrace all for example) are compiled
* unconditionally with -DSMP. Although it looks like a bug,
* handle this case here and in #elif condition in ARM_SMP_UP macro.
*/
#if __ARM_ARCH <= 6 && defined(SMP) && !defined(KLD_MODULE)
#error SMP option is not supported on ARMv6
#endif
#if __ARM_ARCH <= 6 && defined(SMP_ON_UP)
#error SMP_ON_UP option is only supported on ARMv7+ CPUs
#endif
#if !defined(SMP) && defined(SMP_ON_UP)
#error SMP option must be defined for SMP_ON_UP option
#endif
#define CPU_ASID_KERNEL 0
#if defined(SMP_ON_UP)
#define ARM_SMP_UP(smp_code, up_code) \
do { \
if (cpuinfo.mp_ext != 0) { \
smp_code; \
} else { \
up_code; \
} \
} while (0)
#elif defined(SMP) && __ARM_ARCH > 6
#define ARM_SMP_UP(smp_code, up_code) \
do { \
smp_code; \
} while (0)
#else
#define ARM_SMP_UP(smp_code, up_code) \
do { \
up_code; \
} while (0)
#endif
void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
#ifdef DEV_PMU
#include <sys/pcpu.h>
#define PMU_OVSR_C 0x80000000 /* Cycle Counter */
extern uint32_t ccnt_hi[MAXCPU];
extern int pmu_attched;
#endif /* DEV_PMU */
#define sev() __asm __volatile("sev" : : : "memory")
#define wfe() __asm __volatile("wfe" : : : "memory")
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
#define _FX(s...) #s
#define _RF0(fname, aname...) \
static __inline uint32_t \
fname(void) \
{ \
uint32_t reg; \
__asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _R64F0(fname, aname) \
static __inline uint64_t \
fname(void) \
{ \
uint64_t reg; \
__asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _WF0(fname, aname...) \
static __inline void \
fname(void) \
{ \
__asm __volatile("mcr\t" _FX(aname)); \
}
#define _WF1(fname, aname...) \
static __inline void \
fname(uint32_t reg) \
{ \
__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
}
#define _W64F1(fname, aname...) \
static __inline void \
fname(uint64_t reg) \
{ \
__asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \
}
/*
* Raw CP15 maintenance operations
* !!! not for external use !!!
*/
/* TLB */
_WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */
#if __ARM_ARCH >= 7 && defined(SMP)
_WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */
#endif
_WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */
#if __ARM_ARCH >= 7 && defined(SMP)
_WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */
#endif
_WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */
#if __ARM_ARCH >= 7 && defined(SMP)
_WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */
#endif
_WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */
_WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
/* Cache and Branch predictor */
_WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */
#if __ARM_ARCH >= 7 && defined(SMP)
_WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */
#endif
_WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */
_WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */
_WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */
_WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */
#if __ARM_ARCH >= 7
_WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */
#endif
_WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */
_WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */
_WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */
_WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */
#if __ARM_ARCH >= 7 && defined(SMP)
_WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */
#endif
_WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */
/*
* Publicly accessible functions
*/
/* CP14 Debug Registers */
_RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0))
_RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0))
_RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0))
_RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0))
_RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0))
_WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0))
_WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0))
_WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0))
_WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0))
/* Various control registers */
_RF0(cp15_cpacr_get, CP15_CPACR(%0))
_WF1(cp15_cpacr_set, CP15_CPACR(%0))
_RF0(cp15_dfsr_get, CP15_DFSR(%0))
_RF0(cp15_ifsr_get, CP15_IFSR(%0))
_WF1(cp15_prrr_set, CP15_PRRR(%0))
_WF1(cp15_nmrr_set, CP15_NMRR(%0))
_RF0(cp15_ttbr_get, CP15_TTBR0(%0))
_RF0(cp15_dfar_get, CP15_DFAR(%0))
#if __ARM_ARCH >= 7
_RF0(cp15_ifar_get, CP15_IFAR(%0))
_RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0))
#endif
_RF0(cp15_actlr_get, CP15_ACTLR(%0))
_WF1(cp15_actlr_set, CP15_ACTLR(%0))
_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
_WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
_WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0))
_WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0))
_RF0(cp15_par_get, CP15_PAR(%0))
_RF0(cp15_sctlr_get, CP15_SCTLR(%0))
/*CPU id registers */
_RF0(cp15_midr_get, CP15_MIDR(%0))
_RF0(cp15_ctr_get, CP15_CTR(%0))
_RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
_RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
_RF0(cp15_mpidr_get, CP15_MPIDR(%0))
_RF0(cp15_revidr_get, CP15_REVIDR(%0))
_RF0(cp15_ccsidr_get, CP15_CCSIDR(%0))
_RF0(cp15_clidr_get, CP15_CLIDR(%0))
_RF0(cp15_aidr_get, CP15_AIDR(%0))
_WF1(cp15_csselr_set, CP15_CSSELR(%0))
_RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
_RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
_RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
_RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
_RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
_RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
_RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
_RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
_RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
_RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
_RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
_RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
_RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
_RF0(cp15_cbar_get, CP15_CBAR(%0))
/* Performance Monitor registers */
#if __ARM_ARCH == 6 && defined(CPU_ARM1176)
_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
_RF0(cp15_pmcr_get, CP15_PMCR(%0))
_WF1(cp15_pmcr_set, CP15_PMCR(%0))
_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
#elif __ARM_ARCH > 6
_RF0(cp15_pmcr_get, CP15_PMCR(%0))
_WF1(cp15_pmcr_set, CP15_PMCR(%0))
_RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
_WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
_WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
_RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
_WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
_WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
_RF0(cp15_pmselr_get, CP15_PMSELR(%0))
_WF1(cp15_pmselr_set, CP15_PMSELR(%0))
_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
_RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
_WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
_RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
_WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
_RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
_WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
_WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
#endif
_RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0))
_WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
_RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0))
_WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
_RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0))
_WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
/* Generic Timer registers - only use when you know the hardware is available */
_RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0))
_WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
_RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0))
_WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
_RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0))
_WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
_RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0))
_WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
_RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0))
_WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
_RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0))
_WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
_RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0))
_WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
_RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0))
_WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
_RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0))
_WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
_R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0))
_R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0))
_R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0))
_W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0))
_R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0))
_W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0))
_R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0))
_W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0))
_R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0))
_W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
#undef _FX
#undef _RF0
#undef _WF0
#undef _WF1
/*
* TLB maintenance operations.
*/
/* Local (i.e. not broadcasting ) operations. */
/* Flush all TLB entries (even global). */
static __inline void
tlb_flush_all_local(void)
{
dsb();
_CP15_TLBIALL();
dsb();
}
/* Flush all not global TLB entries. */
static __inline void
tlb_flush_all_ng_local(void)
{
dsb();
_CP15_TLBIASID(CPU_ASID_KERNEL);
dsb();
}
/* Flush single TLB entry (even global). */
static __inline void
tlb_flush_local(vm_offset_t va)
{
KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
dsb();
_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
dsb();
}
/* Flush range of TLB entries (even global). */
static __inline void
tlb_flush_range_local(vm_offset_t va, vm_size_t size)
{
vm_offset_t eva = va + size;
KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
size));
dsb();
for (; va < eva; va += PAGE_SIZE)
_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
dsb();
}
/* Broadcasting operations. */
#if __ARM_ARCH >= 7 && defined(SMP)
static __inline void
tlb_flush_all(void)
{
dsb();
ARM_SMP_UP(
_CP15_TLBIALLIS(),
_CP15_TLBIALL()
);
dsb();
}
static __inline void
tlb_flush_all_ng(void)
{
dsb();
ARM_SMP_UP(
_CP15_TLBIASIDIS(CPU_ASID_KERNEL),
_CP15_TLBIASID(CPU_ASID_KERNEL)
);
dsb();
}
static __inline void
tlb_flush(vm_offset_t va)
{
KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
dsb();
ARM_SMP_UP(
_CP15_TLBIMVAAIS(va),
_CP15_TLBIMVA(va | CPU_ASID_KERNEL)
);
dsb();
}
static __inline void
tlb_flush_range(vm_offset_t va, vm_size_t size)
{
vm_offset_t eva = va + size;
KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__,
size));
dsb();
ARM_SMP_UP(
{
for (; va < eva; va += PAGE_SIZE)
_CP15_TLBIMVAAIS(va);
},
{
for (; va < eva; va += PAGE_SIZE)
_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
}
);
dsb();
}
#else /* __ARM_ARCH < 7 */
#define tlb_flush_all() tlb_flush_all_local()
#define tlb_flush_all_ng() tlb_flush_all_ng_local()
#define tlb_flush(va) tlb_flush_local(va)
#define tlb_flush_range(va, size) tlb_flush_range_local(va, size)
#endif /* __ARM_ARCH < 7 */
/*
* Cache maintenance operations.
*/
/* Sync I and D caches to PoU */
static __inline void
icache_sync(vm_offset_t va, vm_size_t size)
{
vm_offset_t eva = va + size;
dsb();
va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
#if __ARM_ARCH >= 7
_CP15_DCCMVAU(va);
#else
_CP15_DCCMVAC(va);
#endif
}
dsb();
ARM_SMP_UP(
_CP15_ICIALLUIS(),
_CP15_ICIALLU()
);
dsb();
isb();
}
/* Invalidate I cache */
static __inline void
icache_inv_all(void)
{
ARM_SMP_UP(
_CP15_ICIALLUIS(),
_CP15_ICIALLU()
);
dsb();
isb();
}
/* Invalidate branch predictor buffer */
static __inline void
bpb_inv_all(void)
{
ARM_SMP_UP(
_CP15_BPIALLIS(),
_CP15_BPIALL()
);
dsb();
isb();
}
/* Write back D-cache to PoU */
static __inline void
dcache_wb_pou(vm_offset_t va, vm_size_t size)
{
vm_offset_t eva = va + size;
dsb();
va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
#if __ARM_ARCH >= 7
_CP15_DCCMVAU(va);
#else
_CP15_DCCMVAC(va);
#endif
}
dsb();
}
/*
* Invalidate D-cache to PoC
*
* Caches are invalidated from outermost to innermost as fresh cachelines
* flow in this direction. In given range, if there was no dirty cacheline
* in any cache before, no stale cacheline should remain in them after this
* operation finishes.
*/
static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t eva = va + size;
dsb();
/* invalidate L2 first */
cpu_l2cache_inv_range(pa, size);
/* then L1 */
va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCIMVAC(va);
}
dsb();
}
/*
* Discard D-cache lines to PoC, prior to overwrite by DMA engine.
*
* Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't
* flow into L1 while invalidating. This routine is intended to be used only
* when invalidating a buffer before a DMA operation loads new data into memory.
* The concern in this case is that dirty lines are not evicted to main memory,
* overwriting the DMA data. For that reason, the L1 is done first to ensure
* that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned.
*/
static __inline void
dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t eva = va + size;
/* invalidate L1 first */
dsb();
va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCIMVAC(va);
}
dsb();
/* then L2 */
cpu_l2cache_inv_range(pa, size);
}
/*
* Write back D-cache to PoC
*
* Caches are written back from innermost to outermost as dirty cachelines
* flow in this direction. In given range, no dirty cacheline should remain
* in any cache after this operation finishes.
*/
static __inline void
dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t eva = va + size;
dsb();
va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCCMVAC(va);
}
dsb();
cpu_l2cache_wb_range(pa, size);
}
/* Write back and invalidate D-cache to PoC */
static __inline void
dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
/* write back L1 first */
va = sva & ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCCMVAC(va);
}
dsb();
/* then write back and invalidate L2 */
cpu_l2cache_wbinv_range(pa, size);
/* then invalidate L1 */
va = sva & ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) {
_CP15_DCIMVAC(va);
}
dsb();
}
/* Set TTB0 register */
static __inline void
cp15_ttbr_set(uint32_t reg)
{
dsb();
_CP15_TTB_SET(reg);
dsb();
_CP15_BPIALL();
dsb();
isb();
tlb_flush_all_ng_local();
}
/*
* Functions for address checking:
*
* cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access
* cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access
* cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access
* cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access
*
* They must be called while interrupts are disabled to get consistent result.
*/
static __inline int
cp15_ats1cpr_check(vm_offset_t addr)
{
cp15_ats1cpr_set(addr);
isb();
return (cp15_par_get() & 0x01 ? EFAULT : 0);
}
static __inline int
cp15_ats1cpw_check(vm_offset_t addr)
{
cp15_ats1cpw_set(addr);
isb();
return (cp15_par_get() & 0x01 ? EFAULT : 0);
}
static __inline int
cp15_ats1cur_check(vm_offset_t addr)
{
cp15_ats1cur_set(addr);
isb();
return (cp15_par_get() & 0x01 ? EFAULT : 0);
}
static __inline int
cp15_ats1cuw_check(vm_offset_t addr)
{
cp15_ats1cuw_set(addr);
isb();
return (cp15_par_get() & 0x01 ? EFAULT : 0);
}
static __inline uint64_t
get_cyclecount(void)
{
#if __ARM_ARCH > 6 || (__ARM_ARCH == 6 && defined(CPU_ARM1176))
#if (__ARM_ARCH > 6) && defined(DEV_PMU)
if (pmu_attched) {
u_int cpu;
uint64_t h, h2;
uint32_t l, r;
cpu = PCPU_GET(cpuid);
h = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]);
l = cp15_pmccntr_get();
/* In case interrupts are disabled we need to check for overflow. */
r = cp15_pmovsr_get();
if (r & PMU_OVSR_C) {
atomic_add_32(&ccnt_hi[cpu], 1);
/* Clear the event. */
cp15_pmovsr_set(PMU_OVSR_C);
}
/* Make sure there was no wrap-around while we read the lo half. */
h2 = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]);
if (h != h2)
l = cp15_pmccntr_get();
return (h2 << 32 | l);
} else
#endif
return cp15_pmccntr_get();
#else /* No performance counters, so use nanotime(9). */
struct timespec tv;
nanotime(&tv);
return (tv.tv_sec * (uint64_t)1000000000ull + tv.tv_nsec);
#endif
}
#endif
#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
#define TRAPF_PC(tfp) ((tfp)->tf_pc)
#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp)
#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp))
#define cpu_spinwait() /* nothing */
#define cpu_lock_delay() DELAY(1)
#define ARM_NVEC 8
#define ARM_VEC_ALL 0xffffffff
extern vm_offset_t vector_page;
/*
* Params passed into initarm. If you change the size of this you will
* need to update locore.S to allocate more memory on the stack before
* it calls initarm.
*/
struct arm_boot_params {
register_t abp_size; /* Size of this structure */
register_t abp_r0; /* r0 from the boot loader */
register_t abp_r1; /* r1 from the boot loader */
register_t abp_r2; /* r2 from the boot loader */
register_t abp_r3; /* r3 from the boot loader */
vm_offset_t abp_physaddr; /* The kernel physical address */
vm_offset_t abp_pagetable; /* The early page table */
};
void arm_vector_init(vm_offset_t, int);
void fork_trampoline(void);
void identify_arm_cpu(void);
void *initarm(struct arm_boot_params *);
extern char btext[];
extern char etext[];
int badaddr_read(void *, size_t, void *);
#endif /* !MACHINE_CPU_H */

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/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Causality Limited.
* 4. The name of Causality Limited may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpufunc.h
*
* Prototypes for cpu, mmu and tlb related functions.
*/
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#ifdef _KERNEL
#include <sys/types.h>
#include <machine/armreg.h>
static __inline void
breakpoint(void)
{
__asm("udf 0xffff");
}
struct cpu_functions {
/* CPU functions */
void (*cf_l2cache_wbinv_all) (void);
void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
void (*cf_l2cache_drain_writebuf) (void);
/* Other functions */
void (*cf_sleep) (int mode);
void (*cf_setup) (void);
};
extern struct cpu_functions cpufuncs;
extern u_int cputype;
#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
#define cpu_setup() cpufuncs.cf_setup()
int set_cpufuncs (void);
#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
void cpufunc_nullop (void);
u_int cpufunc_control (u_int clear, u_int bic);
#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
void armv7_cpu_sleep (int);
#endif
#if defined(CPU_MV_PJ4B)
void pj4b_config (void);
#endif
#if defined(CPU_ARM1176)
void arm11x6_sleep (int); /* no ref. for errata */
#endif
/*
* Macros for manipulating CPU interrupts
*/
#define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A)
static __inline uint32_t
__set_cpsr(uint32_t bic, uint32_t eor)
{
uint32_t tmp, ret;
__asm __volatile(
"mrs %0, cpsr\n" /* Get the CPSR */
"bic %1, %0, %2\n" /* Clear bits */
"eor %1, %1, %3\n" /* XOR bits */
"msr cpsr_xc, %1\n" /* Set the CPSR */
: "=&r" (ret), "=&r" (tmp)
: "r" (bic), "r" (eor) : "memory");
return ret;
}
static __inline uint32_t
disable_interrupts(uint32_t mask)
{
return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS));
}
static __inline uint32_t
enable_interrupts(uint32_t mask)
{
return (__set_cpsr(mask & __ARM_INTR_BITS, 0));
}
static __inline uint32_t
restore_interrupts(uint32_t old_cpsr)
{
return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS));
}
static __inline register_t
intr_disable(void)
{
return (disable_interrupts(PSR_I | PSR_F));
}
static __inline void
intr_restore(register_t s)
{
restore_interrupts(s);
}
#undef __ARM_INTR_BITS
/*
* Functions to manipulate cpu r13
* (in arm/arm32/setstack.S)
*/
void set_stackptr (u_int mode, u_int address);
u_int get_stackptr (u_int mode);
/*
* CPU functions from locore.S
*/
void cpu_reset (void) __attribute__((__noreturn__));
/*
* Cache info variables.
*/
/* PRIMARY CACHE VARIABLES */
extern unsigned int arm_dcache_align;
extern unsigned int arm_dcache_align_mask;
#else /* !_KERNEL */
static __inline void
breakpoint(void)
{
/*
* This matches the instruction used by GDB for software
* breakpoints.
*/
__asm("udf 0xfdee");
}
#endif /* _KERNEL */
#endif /* _MACHINE_CPUFUNC_H_ */
/* End of cpufunc.h */

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/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_CPUINFO_H_
#define _MACHINE_CPUINFO_H_
#include <sys/types.h>
#define CPU_IMPLEMENTER_ARM 0x41
#define CPU_IMPLEMENTER_QCOM 0x51
#define CPU_IMPLEMENTER_MRVL 0x56
/* ARM */
#define CPU_ARCH_ARM1176 0xB76
#define CPU_ARCH_CORTEX_A5 0xC05
#define CPU_ARCH_CORTEX_A7 0xC07
#define CPU_ARCH_CORTEX_A8 0xC08
#define CPU_ARCH_CORTEX_A9 0xC09
#define CPU_ARCH_CORTEX_A12 0xC0D
#define CPU_ARCH_CORTEX_A15 0xC0F
#define CPU_ARCH_CORTEX_A17 0xC11
#define CPU_ARCH_CORTEX_A53 0xD03
#define CPU_ARCH_CORTEX_A57 0xD07
#define CPU_ARCH_CORTEX_A72 0xD08
#define CPU_ARCH_CORTEX_A73 0xD09
#define CPU_ARCH_CORTEX_A75 0xD0A
/* QCOM */
#define CPU_ARCH_KRAIT_300 0x06F
/* MRVL */
#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */
#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */
struct cpuinfo {
/* raw id registers */
uint32_t midr;
uint32_t ctr;
uint32_t tcmtr;
uint32_t tlbtr;
uint32_t mpidr;
uint32_t revidr;
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_dfr0;
uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_isar0;
uint32_t id_isar1;
uint32_t id_isar2;
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
uint32_t cbar;
uint32_t ccsidr;
uint32_t clidr;
/* Parsed bits of above registers... */
/* midr */
int implementer;
int revision;
int architecture;
int part_number;
int patch;
/* id_mmfr0 */
int outermost_shareability;
int shareability_levels;
int auxiliary_registers;
int innermost_shareability;
/* id_mmfr1 */
int mem_barrier;
/* id_mmfr3 */
int coherent_walk;
int maintenance_broadcast;
/* id_pfr1 */
int generic_timer_ext;
int virtualization_ext;
int security_ext;
/* L1 cache info */
int dcache_line_size;
int dcache_line_mask;
int icache_line_size;
int icache_line_mask;
/* mpidr */
int mp_ext;
};
extern struct cpuinfo cpuinfo;
void cpuinfo_init(void);
void cpuinfo_init_bp_hardening(void);
void cpuinfo_reinit_mmu(uint32_t ttb);
#endif /* _MACHINE_CPUINFO_H_ */

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/*-
* This file is in the public domain since it's just boilerplate.
*/
#ifndef __ARM_INCLUDE_EFI_H_
#define __ARM_INCLUDE_EFI_H_
#define EFIABI_ATTR
#endif /* __ARM_INCLUDE_EFI_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2001 David E. O'Brien
* Copyright (c) 1996-1997 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_ELF_H_
#define _MACHINE_ELF_H_ 1
/*
* EABI ELF definitions for the StrongARM architecture.
* See "ARM ELF", document no. `SWS ESPC 0003 A-08' for details.
*/
#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */
#define __ELF_WORD_SIZE 32 /* Used by <sys/elf_generic.h> */
#include <sys/elf_generic.h>
typedef struct { /* Auxiliary vector entry on initial stack */
int a_type; /* Entry type. */
union {
long a_val; /* Integer value. */
void *a_ptr; /* Address. */
void (*a_fcn)(void); /* Function pointer (not used). */
} a_un;
} Elf32_Auxinfo;
__ElfType(Auxinfo);
#define ELF_ARCH EM_ARM
#define ELF_MACHINE_OK(x) ((x) == EM_ARM)
/*
* Relocation types.
*/
#define R_ARM_COUNT 33 /* Count of defined relocation types. */
/* Define "machine" characteristics */
#define ELF_TARG_CLASS ELFCLASS32
#ifdef __ARMEB__
#define ELF_TARG_DATA ELFDATA2MSB
#else
#define ELF_TARG_DATA ELFDATA2LSB
#endif
#define ELF_TARG_MACH EM_ARM
#define ELF_TARG_VER 1
/* Defines specific for arm headers */
#define EF_ARM_EABI_FREEBSD_MIN EF_ARM_EABI_VER4
#define ET_DYN_LOAD_ADDR 0x01001000
/* Flags passed in AT_HWCAP. */
#define HWCAP_SWP 0x00000001 /* Unsupported, never set. */
#define HWCAP_HALF 0x00000002 /* Always set. */
#define HWCAP_THUMB 0x00000004
#define HWCAP_26BIT 0x00000008 /* Unsupported, never set. */
#define HWCAP_FAST_MULT 0x00000010 /* Always set. */
#define HWCAP_FPA 0x00000020 /* Unsupported, never set. */
#define HWCAP_VFP 0x00000040
#define HWCAP_EDSP 0x00000080 /* Always set for ARMv6+. */
#define HWCAP_JAVA 0x00000100 /* Unsupported, never set. */
#define HWCAP_IWMMXT 0x00000200 /* Unsupported, never set. */
#define HWCAP_CRUNCH 0x00000400 /* Unsupported, never set. */
#define HWCAP_THUMBEE 0x00000800
#define HWCAP_NEON 0x00001000
#define HWCAP_VFPv3 0x00002000
#define HWCAP_VFPv3D16 0x00004000
#define HWCAP_TLS 0x00008000 /* Always set for ARMv6+. */
#define HWCAP_VFPv4 0x00010000
#define HWCAP_IDIVA 0x00020000
#define HWCAP_IDIVT 0x00040000
#define HWCAP_VFPD32 0x00080000
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
#define HWCAP_LPAE 0x00100000
#define HWCAP_EVTSTRM 0x00200000 /* Not implemented yet. */
/* Flags passed in AT_HWCAP2. */
#define HWCAP2_AES 0x00000001
#define HWCAP2_PMULL 0x00000002
#define HWCAP2_SHA1 0x00000004
#define HWCAP2_SHA2 0x00000008
#define HWCAP2_CRC32 0x00000010
#endif /* !_MACHINE_ELF_H_ */

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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2001 David E. O'Brien
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_EXEC_H_
#define _MACHINE_EXEC_H_
#define __LDPGSZ 4096
#endif /* !_MACHINE_EXEC_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _FENV_H_
#define _FENV_H_
#include <sys/_types.h>
#ifndef __fenv_static
#define __fenv_static static
#endif
typedef __uint32_t fenv_t;
typedef __uint32_t fexcept_t;
/* Exception flags */
#define FE_INVALID 0x0001
#define FE_DIVBYZERO 0x0002
#define FE_OVERFLOW 0x0004
#define FE_UNDERFLOW 0x0008
#define FE_INEXACT 0x0010
#ifdef __ARM_PCS_VFP
#define FE_DENORMAL 0x0080
#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW | FE_DENORMAL)
#else
#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
#endif
/* Rounding modes */
#define VFP_FE_TONEAREST 0x00000000
#define VFP_FE_UPWARD 0x00400000
#define VFP_FE_DOWNWARD 0x00800000
#define VFP_FE_TOWARDZERO 0x00c00000
#ifdef __ARM_PCS_VFP
#define FE_TONEAREST VFP_FE_TONEAREST
#define FE_UPWARD VFP_FE_UPWARD
#define FE_DOWNWARD VFP_FE_DOWNWARD
#define FE_TOWARDZERO VFP_FE_TOWARDZERO
#else
#define FE_TONEAREST 0x0000
#define FE_TOWARDZERO 0x0001
#define FE_UPWARD 0x0002
#define FE_DOWNWARD 0x0003
#endif
#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
FE_UPWARD | FE_TOWARDZERO)
__BEGIN_DECLS
/* Default floating-point environment */
extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV (&__fe_dfl_env)
/* We need to be able to map status flag positions to mask flag positions */
#ifndef __ARM_PCS_VFP
#define _FPUSW_SHIFT 16
#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
#endif
#ifndef __ARM_PCS_VFP
int feclearexcept(int __excepts);
int fegetexceptflag(fexcept_t *__flagp, int __excepts);
int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
int feraiseexcept(int __excepts);
int fetestexcept(int __excepts);
int fegetround(void);
int fesetround(int __round);
int fegetenv(fenv_t *__envp);
int feholdexcept(fenv_t *__envp);
int fesetenv(const fenv_t *__envp);
int feupdateenv(const fenv_t *__envp);
#if __BSD_VISIBLE
int feenableexcept(int __mask);
int fedisableexcept(int __mask);
int fegetexcept(void);
#endif
#else /* __ARM_PCS_VFP */
#define vmrs_fpscr(__r) __asm __volatile("vmrs %0, fpscr" : "=&r"(__r))
#define vmsr_fpscr(__r) __asm __volatile("vmsr fpscr, %0" : : "r"(__r))
#define _FPU_MASK_SHIFT 8
__fenv_static inline int
feclearexcept(int __excepts)
{
fexcept_t __fpsr;
vmrs_fpscr(__fpsr);
__fpsr &= ~__excepts;
vmsr_fpscr(__fpsr);
return (0);
}
__fenv_static inline int
fegetexceptflag(fexcept_t *__flagp, int __excepts)
{
fexcept_t __fpsr;
vmrs_fpscr(__fpsr);
*__flagp = __fpsr & __excepts;
return (0);
}
__fenv_static inline int
fesetexceptflag(const fexcept_t *__flagp, int __excepts)
{
fexcept_t __fpsr;
vmrs_fpscr(__fpsr);
__fpsr &= ~__excepts;
__fpsr |= *__flagp & __excepts;
vmsr_fpscr(__fpsr);
return (0);
}
__fenv_static inline int
feraiseexcept(int __excepts)
{
fexcept_t __ex = __excepts;
fesetexceptflag(&__ex, __excepts); /* XXX */
return (0);
}
__fenv_static inline int
fetestexcept(int __excepts)
{
fexcept_t __fpsr;
vmrs_fpscr(__fpsr);
return (__fpsr & __excepts);
}
__fenv_static inline int
fegetround(void)
{
fenv_t __fpsr;
vmrs_fpscr(__fpsr);
return (__fpsr & _ROUND_MASK);
}
__fenv_static inline int
fesetround(int __round)
{
fenv_t __fpsr;
vmrs_fpscr(__fpsr);
__fpsr &= ~(_ROUND_MASK);
__fpsr |= __round;
vmsr_fpscr(__fpsr);
return (0);
}
__fenv_static inline int
fegetenv(fenv_t *__envp)
{
vmrs_fpscr(*__envp);
return (0);
}
__fenv_static inline int
feholdexcept(fenv_t *__envp)
{
fenv_t __env;
vmrs_fpscr(__env);
*__envp = __env;
__env &= ~(FE_ALL_EXCEPT);
vmsr_fpscr(__env);
return (0);
}
__fenv_static inline int
fesetenv(const fenv_t *__envp)
{
vmsr_fpscr(*__envp);
return (0);
}
__fenv_static inline int
feupdateenv(const fenv_t *__envp)
{
fexcept_t __fpsr;
vmrs_fpscr(__fpsr);
vmsr_fpscr(*__envp);
feraiseexcept(__fpsr & FE_ALL_EXCEPT);
return (0);
}
#if __BSD_VISIBLE
/* We currently provide no external definitions of the functions below. */
__fenv_static inline int
feenableexcept(int __mask)
{
fenv_t __old_fpsr, __new_fpsr;
vmrs_fpscr(__old_fpsr);
__new_fpsr = __old_fpsr |
((__mask & FE_ALL_EXCEPT) << _FPU_MASK_SHIFT);
vmsr_fpscr(__new_fpsr);
return ((__old_fpsr >> _FPU_MASK_SHIFT) & FE_ALL_EXCEPT);
}
__fenv_static inline int
fedisableexcept(int __mask)
{
fenv_t __old_fpsr, __new_fpsr;
vmrs_fpscr(__old_fpsr);
__new_fpsr = __old_fpsr &
~((__mask & FE_ALL_EXCEPT) << _FPU_MASK_SHIFT);
vmsr_fpscr(__new_fpsr);
return ((__old_fpsr >> _FPU_MASK_SHIFT) & FE_ALL_EXCEPT);
}
__fenv_static inline int
fegetexcept(void)
{
fenv_t __fpsr;
vmrs_fpscr(__fpsr);
return (__fpsr & FE_ALL_EXCEPT);
}
#endif /* __BSD_VISIBLE */
#endif /* __ARM_PCS_VFP */
__END_DECLS
#endif /* !_FENV_H_ */

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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1989 Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)float.h 7.1 (Berkeley) 5/8/90
*/
#ifndef _MACHINE_FLOAT_H_
#define _MACHINE_FLOAT_H_ 1
#include <sys/cdefs.h>
__BEGIN_DECLS
extern int __flt_rounds(void);
__END_DECLS
#define FLT_RADIX 2 /* b */
#ifndef _ARM_HARD_FLOAT
#define FLT_ROUNDS __flt_rounds()
#else
#define FLT_ROUNDS (-1)
#endif
#if __ISO_C_VISIBLE >= 1999
#define FLT_EVAL_METHOD 0
#define DECIMAL_DIG 17 /* max precision in decimal digits */
#endif
#define FLT_MANT_DIG 24 /* p */
#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */
#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
#define FLT_MIN_EXP (-125) /* emin */
#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */
#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
#define FLT_MAX_EXP 128 /* emax */
#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
#if __ISO_C_VISIBLE >= 2011
#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */
#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */
#define FLT_HAS_SUBNORM 1
#endif /* __ISO_C_VISIBLE >= 2011 */
#define DBL_MANT_DIG 53
#define DBL_EPSILON 2.2204460492503131E-16
#define DBL_DIG 15
#define DBL_MIN_EXP (-1021)
#define DBL_MIN 2.2250738585072014E-308
#define DBL_MIN_10_EXP (-307)
#define DBL_MAX_EXP 1024
#define DBL_MAX 1.7976931348623157E+308
#define DBL_MAX_10_EXP 308
#if __ISO_C_VISIBLE >= 2011
#define DBL_TRUE_MIN 4.9406564584124654E-324
#define DBL_DECIMAL_DIG 17
#define DBL_HAS_SUBNORM 1
#endif /* __ISO_C_VISIBLE >= 2011 */
#define LDBL_MANT_DIG DBL_MANT_DIG
#define LDBL_EPSILON ((long double)DBL_EPSILON)
#define LDBL_DIG DBL_DIG
#define LDBL_MIN_EXP DBL_MIN_EXP
#define LDBL_MIN ((long double)DBL_MIN)
#define LDBL_MIN_10_EXP DBL_MIN_10_EXP
#define LDBL_MAX_EXP DBL_MAX_EXP
#define LDBL_MAX ((long double)DBL_MAX)
#define LDBL_MAX_10_EXP DBL_MAX_10_EXP
#if __ISO_C_VISIBLE >= 2011
#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN)
#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG
#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM
#endif /* __ISO_C_VISIBLE >= 2011 */
#endif /* _MACHINE_FLOAT_H_ */

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/* $NetBSD: frame.h,v 1.5 2002/10/19 00:10:54 bjh21 Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1994-1997 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* frame.h
*
* Stack frames structures
*
* Created : 30/09/94
*
*/
#ifndef _MACHINE_FRAME_H_
#define _MACHINE_FRAME_H_
#ifndef _LOCORE
#include <sys/signal.h>
#include <sys/ucontext.h>
/*
* Trap frame. Pushed onto the kernel stack on a trap (synchronous exception).
*/
struct trapframe {
register_t tf_spsr;
register_t tf_r0;
register_t tf_r1;
register_t tf_r2;
register_t tf_r3;
register_t tf_r4;
register_t tf_r5;
register_t tf_r6;
register_t tf_r7;
register_t tf_r8;
register_t tf_r9;
register_t tf_r10;
register_t tf_r11;
register_t tf_r12;
register_t tf_usr_sp;
register_t tf_usr_lr;
register_t tf_svc_sp;
register_t tf_svc_lr;
register_t tf_pc;
register_t tf_pad;
};
/* Register numbers */
#define tf_r13 tf_usr_sp
#define tf_r14 tf_usr_lr
#define tf_r15 tf_pc
/*
* Signal frame. Pushed onto user stack before calling sigcode.
* The pointers are used in the trampoline code to locate the ucontext.
*/
struct sigframe {
siginfo_t sf_si; /* actual saved siginfo */
ucontext_t sf_uc; /* actual saved ucontext */
mcontext_vfp_t sf_vfp; /* actual saved VFP context */
};
/*
* Switch frame.
*
* It is important this is a multiple of 8 bytes so the stack is correctly
* aligned when we create new threads.
*/
struct switchframe
{
register_t sf_r4;
register_t sf_r5;
register_t sf_r6;
register_t sf_r7;
register_t sf_r8;
register_t sf_r9;
register_t sf_r10;
register_t sf_r11;
register_t sf_r12;
register_t sf_sp;
register_t sf_lr;
register_t sf_pc;
register_t sf_tpidrurw;
register_t sf_spare0;
};
/*
* Stack frame. Used during stack traces (db_trace.c)
*/
struct frame {
u_int fr_fp;
u_int fr_sp;
u_int fr_lr;
u_int fr_pc;
};
#endif /* !_LOCORE */
#endif /* _MACHINE_FRAME_H_ */

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/* $NetBSD: ieeefp.h,v 1.1 2001/01/10 19:02:06 bjh21 Exp $ */
/*-
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _MACHINE_IEEEFP_H_
#define _MACHINE_IEEEFP_H_
/* Deprecated historical FPU control interface */
/* FP exception codes */
#define FP_EXCEPT_INV 0
#define FP_EXCEPT_DZ 1
#define FP_EXCEPT_OFL 2
#define FP_EXCEPT_UFL 3
#define FP_EXCEPT_IMP 4
/* Exception type (used by fpsetmask() et al.) */
typedef int fp_except;
/* Bit defines for fp_except */
#define FP_X_INV (1 << FP_EXCEPT_INV) /* invalid operation exception */
#define FP_X_DZ (1 << FP_EXCEPT_DZ) /* divide-by-zero exception */
#define FP_X_OFL (1 << FP_EXCEPT_OFL) /* overflow exception */
#define FP_X_UFL (1 << FP_EXCEPT_UFL) /* underflow exception */
#define FP_X_IMP (1 << FP_EXCEPT_IMP) /* imprecise (loss of precision; "inexact") */
/* Rounding modes */
typedef enum {
FP_RN=0, /* round to nearest representable number */
FP_RP=1, /* round toward positive infinity */
FP_RM=2, /* round toward negative infinity */
FP_RZ=3 /* round to zero (truncate) */
} fp_rnd_t;
/*
* FP precision modes
*/
typedef enum {
FP_PS=0, /* 24 bit (single-precision) */
FP_PRS, /* reserved */
FP_PD, /* 53 bit (double-precision) */
FP_PE /* 64 bit (extended-precision) */
} fp_prec_t;
#define fp_except_t int
#endif /* _MACHINE_IEEEFP_H_ */

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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2001 David E. O'Brien
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)param.h 5.8 (Berkeley) 6/28/91
*/
#ifndef _ARM_INCLUDE_PARAM_H_
#define _ARM_INCLUDE_PARAM_H_
/*
* Machine dependent constants for StrongARM
*/
#include <machine/_align.h>
#define STACKALIGNBYTES (8 - 1)
#define STACKALIGN(p) ((u_int)(p) & ~STACKALIGNBYTES)
#define __PCI_REROUTE_INTERRUPT
#ifndef MACHINE
#define MACHINE "arm"
#endif
#ifndef MACHINE_ARCH
#if __ARM_ARCH >= 7
#define MACHINE_ARCH "armv7"
#else
#define MACHINE_ARCH "armv6"
#endif
#endif
#ifdef SMP
#ifndef MAXCPU
#define MAXCPU 4
#endif
#else
#define MAXCPU 1
#endif
#ifndef MAXMEMDOM
#define MAXMEMDOM 1
#endif
#define ALIGNBYTES _ALIGNBYTES
#define ALIGN(p) _ALIGN(p)
/*
* ALIGNED_POINTER is a boolean macro that checks whether an address
* is valid to fetch data elements of type t from on this architecture.
* This does not reflect the optimal alignment, just the possibility
* (within reasonable limits).
*
* armv4 and v5 require alignment to the type's size. armv6 requires 8-byte
* alignment for the ldrd/strd instructions, but otherwise follows armv7 rules.
* armv7 requires that an 8-byte type be aligned to at least a 4-byte boundary;
* access to smaller types can be unaligned, except that the compiler may
* optimize access to adjacent uint32_t values into a single load/store-multiple
* instruction which requires 4-byte alignment, so we must provide the most-
* pessimistic answer possible even on armv7.
*/
#define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0)
/*
* CACHE_LINE_SIZE is the compile-time maximum cache line size for an
* architecture. It should be used with appropriate caution.
*/
#define CACHE_LINE_SHIFT 6
#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
#define PAGE_SHIFT 12
#define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */
#define PAGE_MASK (PAGE_SIZE - 1)
#define PDR_SHIFT 20 /* log2(NBPDR) */
#define NBPDR (1 << PDR_SHIFT)
#define PDRMASK (NBPDR - 1)
#define NPDEPG (1 << (32 - PDR_SHIFT))
#define MAXPAGESIZES 2 /* maximum number of supported page sizes */
#ifndef KSTACK_PAGES
#define KSTACK_PAGES 2
#endif /* !KSTACK_PAGES */
#ifndef FPCONTEXTSIZE
#define FPCONTEXTSIZE (0x100)
#endif
#ifndef KSTACK_GUARD_PAGES
#define KSTACK_GUARD_PAGES 1
#endif /* !KSTACK_GUARD_PAGES */
#define USPACE_SVC_STACK_TOP (kstack_pages * PAGE_SIZE)
/*
* Mach derived conversion macros
*/
#define trunc_page(x) ((x) & ~PAGE_MASK)
#define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK)
#define trunc_1mpage(x) ((unsigned)(x) & ~PDRMASK)
#define round_1mpage(x) ((((unsigned)(x)) + PDRMASK) & ~PDRMASK)
#define atop(x) ((unsigned)(x) >> PAGE_SHIFT)
#define ptoa(x) ((unsigned)(x) << PAGE_SHIFT)
#define arm32_btop(x) ((unsigned)(x) >> PAGE_SHIFT)
#define arm32_ptob(x) ((unsigned)(x) << PAGE_SHIFT)
#define pgtok(x) ((x) * (PAGE_SIZE / 1024))
#endif /* !_ARM_INCLUDE_PARAM_H_ */

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/* $NetBSD: pcb.h,v 1.10 2003/10/13 21:46:39 scw Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2001 Matt Thomas <matt@3am-software.com>.
* Copyright (c) 1994 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the RiscBSD team.
* 4. The name "RiscBSD" nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_PCB_H_
#define _MACHINE_PCB_H_
#include <machine/frame.h>
#include <machine/vfp.h>
/*
* WARNING!
* Keep pcb_regs first for faster access in switch.S
*/
struct pcb {
struct switchframe pcb_regs; /* CPU state */
u_int pcb_flags;
#define PCB_OWNFPU 0x00000001
#define PCB_NOALIGNFLT 0x00000002
caddr_t pcb_onfault; /* On fault handler */
vm_offset_t pcb_pagedir; /* TTB0 value */
/*
* XXX:
* Variables pcb_pl1vec, pcb_l1vec, pcb_dacr are used solely
* by old PMAP. Keep them here for PCB binary compatibility
* between old and new PMAP.
*/
uint32_t *pcb_pl1vec; /* PTR to vector_base L1 entry*/
uint32_t pcb_l1vec; /* Value to stuff on ctx sw */
u_int pcb_dacr; /* Domain Access Control Reg */
struct vfp_state pcb_vfpstate; /* VP/NEON state */
u_int pcb_vfpcpu; /* VP/NEON last cpu */
#define PCB_FP_STARTED 0x01
#define PCB_FP_KERN 0x02
#define PCB_FP_NOSAVE 0x04
struct vfp_state *pcb_vfpsaved; /* VP/NEON state */
int pcb_fpflags;
} __aligned(8); /*
* We need the PCB to be aligned on 8 bytes, as we may
* access it using ldrd/strd, and ARM ABI require it
* to by aligned on 8 bytes.
*/
/*
* No additional data for core dumps.
*/
struct md_coredump {
int md_empty;
};
void makectx(struct trapframe *tf, struct pcb *pcb);
#ifdef _KERNEL
void savectx(struct pcb *) __returns_twice;
#endif /* _KERNEL */
#endif /* !_MACHINE_PCB_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: FreeBSD: src/sys/i386/include/globaldata.h,v 1.27 2001/04/27
*/
#ifndef _MACHINE_PCPU_H_
#define _MACHINE_PCPU_H_
#ifdef _KERNEL
#include <sys/_lock.h>
#include <sys/_mutex.h>
struct vmspace;
#endif /* _KERNEL */
/* Branch predictor hardening method */
#define PCPU_BP_HARDEN_KIND_NONE 0
#define PCPU_BP_HARDEN_KIND_BPIALL 1
#define PCPU_BP_HARDEN_KIND_ICIALLU 2
#define PCPU_MD_FIELDS \
unsigned int pc_vfpsid; \
unsigned int pc_vfpmvfr0; \
unsigned int pc_vfpmvfr1; \
struct pmap *pc_curpmap; \
struct mtx pc_cmap_lock; \
void *pc_cmap1_pte2p; \
void *pc_cmap2_pte2p; \
caddr_t pc_cmap1_addr; \
caddr_t pc_cmap2_addr; \
vm_offset_t pc_qmap_addr; \
void *pc_qmap_pte2p; \
unsigned int pc_dbreg[32]; \
int pc_dbreg_cmd; \
int pc_bp_harden_kind; \
uint32_t pc_original_actlr; \
uint64_t pc_clock; \
uint32_t pc_mpidr; \
char __pad[135]
#ifdef _KERNEL
#define PC_DBREG_CMD_NONE 0
#define PC_DBREG_CMD_LOAD 1
struct pcb;
struct pcpu;
extern struct pcpu *pcpup;
#define CPU_MASK (0xf)
#ifndef SMP
#define get_pcpu() (pcpup)
#else
#define get_pcpu() __extension__ ({ \
int id; \
__asm __volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (id)); \
(pcpup + (id & CPU_MASK)); \
})
#endif
static inline struct thread *
get_curthread(void)
{
void *ret;
__asm __volatile("mrc p15, 0, %0, c13, c0, 4" : "=r" (ret));
return (ret);
}
static inline void
set_curthread(struct thread *td)
{
__asm __volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (td));
}
static inline void *
get_tls(void)
{
void *tls;
/* TPIDRURW contains the authoritative value. */
__asm __volatile("mrc p15, 0, %0, c13, c0, 2" : "=r" (tls));
return (tls);
}
static inline void
set_tls(void *tls)
{
/*
* Update both TPIDRURW and TPIDRURO. TPIDRURW needs to be written
* first to ensure that a context switch between the two writes will
* still give the desired result of updating both.
*/
__asm __volatile(
"mcr p15, 0, %0, c13, c0, 2\n"
"mcr p15, 0, %0, c13, c0, 3\n"
: : "r" (tls));
}
#define curthread get_curthread()
#define PCPU_GET(member) (get_pcpu()->pc_ ## member)
#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value))
#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member)
#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value))
#define PCPU_GET_MPIDR(pc) ((pc)->pc_mpidr)
void pcpu0_init(void);
#endif /* _KERNEL */
#endif /* !_MACHINE_PCPU_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2019 The FreeBSD Foundation
*
* This software was developed by Konstantin Belousov <kib@FreeBSD.org>
* under sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_PCPU_AUX_H_
#define _MACHINE_PCPU_AUX_H_
#ifndef _KERNEL
#error "Not for userspace"
#endif
#ifndef _SYS_PCPU_H_
#error "Do not include machine/pcpu_aux.h directly"
#endif
/*
* To minimize memory waste in per-cpu UMA zones, the page size should
* be a multiple of the size of struct pcpu.
*/
_Static_assert(PAGE_SIZE % sizeof(struct pcpu) == 0, "fix pcpu size");
extern struct pcpu __pcpu[];
#endif /* _MACHINE_PCPU_AUX_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2014,2016 Svatopluk Kraus <onwahe@gmail.com>
* Copyright (c) 2014,2016 Michal Meloun <meloun@miracle.cz>
* Copyright (c) 1991 Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and William Jolitz of UUNET Technologies Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The ARM version of this file was more or less based on the i386 version,
* which has the following provenance...
*
* Derived from hp300 version by Mike Hibler, this version by William
* Jolitz uses a recursive map [a pde points to the page directory] to
* map the page tables using the pagetables themselves. This is done to
* reduce the impact on kernel virtual memory for lots of sparse address
* space, and to reduce the cost of memory to each process.
*
* from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
* from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
* from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
*/
#ifndef _MACHINE_PMAP_H_
#define _MACHINE_PMAP_H_
#include <sys/systm.h>
#include <sys/queue.h>
#include <sys/_cpuset.h>
#include <sys/_lock.h>
#include <sys/_mutex.h>
#include <sys/_pv_entry.h>
typedef uint32_t pt1_entry_t; /* L1 table entry */
typedef uint32_t pt2_entry_t; /* L2 table entry */
typedef uint32_t ttb_entry_t; /* TTB entry */
#ifdef _KERNEL
#if 0
#define PMAP_PTE_NOCACHE // Use uncached page tables
#endif
/*
* (1) During pmap bootstrap, physical pages for L2 page tables are
* allocated in advance which are used for KVA continuous mapping
* starting from KERNBASE. This makes things more simple.
* (2) During vm subsystem initialization, only vm subsystem itself can
* allocate physical memory safely. As pmap_map() is called during
* this initialization, we must be prepared for that and have some
* preallocated physical pages for L2 page tables.
*
* Note that some more pages for L2 page tables are preallocated too
* for mappings laying above VM_MAX_KERNEL_ADDRESS.
*/
#ifndef NKPT2PG
/*
* The optimal way is to define this in board configuration as
* definition here must be safe enough. It means really big.
*
* 1 GB KVA <=> 256 kernel L2 page table pages
*
* From real platforms:
* 1 GB physical memory <=> 10 pages is enough
* 2 GB physical memory <=> 21 pages is enough
*/
#define NKPT2PG 32
#endif
#endif /* _KERNEL */
/*
* Pmap stuff
*/
struct md_page {
TAILQ_HEAD(,pv_entry) pv_list;
uint16_t pt2_wirecount[4];
vm_memattr_t pat_mode;
};
struct pmap {
struct mtx pm_mtx;
pt1_entry_t *pm_pt1; /* KVA of pt1 */
pt2_entry_t *pm_pt2tab; /* KVA of pt2 pages table */
TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */
cpuset_t pm_active; /* active on cpus */
struct pmap_statistics pm_stats; /* pmap statictics */
LIST_ENTRY(pmap) pm_list; /* List of all pmaps */
};
typedef struct pmap *pmap_t;
#ifdef _KERNEL
extern struct pmap kernel_pmap_store;
#define kernel_pmap (&kernel_pmap_store)
#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
#define PMAP_LOCK_ASSERT(pmap, type) \
mtx_assert(&(pmap)->pm_mtx, (type))
#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
NULL, MTX_DEF | MTX_DUPOK)
#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx)
#define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
extern ttb_entry_t pmap_kern_ttb; /* TTB for kernel pmap */
#define pmap_page_get_memattr(m) ((m)->md.pat_mode)
/*
* Only the following functions or macros may be used before pmap_bootstrap()
* is called: pmap_kenter(), pmap_kextract(), pmap_kremove(), vtophys(), and
* vtopte2().
*/
void pmap_bootstrap(vm_offset_t);
void pmap_kenter(vm_offset_t, vm_paddr_t);
void pmap_kremove(vm_offset_t);
boolean_t pmap_page_is_mapped(vm_page_t);
bool pmap_ps_enabled(pmap_t pmap);
void pmap_tlb_flush(pmap_t, vm_offset_t);
void pmap_tlb_flush_range(pmap_t, vm_offset_t, vm_size_t);
vm_paddr_t pmap_dump_kextract(vm_offset_t, pt2_entry_t *);
int pmap_fault(pmap_t, vm_offset_t, uint32_t, int, bool);
void pmap_set_tex(void);
/*
* Pre-bootstrap epoch functions set.
*/
void pmap_bootstrap_prepare(vm_paddr_t);
vm_paddr_t pmap_preboot_get_pages(u_int);
void pmap_preboot_map_pages(vm_paddr_t, vm_offset_t, u_int);
vm_offset_t pmap_preboot_reserve_pages(u_int);
vm_offset_t pmap_preboot_get_vpages(u_int);
void pmap_preboot_map_attr(vm_paddr_t, vm_offset_t, vm_size_t, vm_prot_t,
vm_memattr_t);
void pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr);
extern char *_tmppt; /* poor name! */
extern vm_offset_t virtual_avail;
extern vm_offset_t virtual_end;
void *pmap_kenter_temporary(vm_paddr_t, int);
#define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0)
void pmap_page_set_memattr(vm_page_t, vm_memattr_t);
#define pmap_map_delete(pmap, sva, eva) pmap_remove(pmap, sva, eva)
void *pmap_mapdev(vm_paddr_t, vm_size_t);
void pmap_unmapdev(void *, vm_size_t);
static inline void *
pmap_mapdev_attr(vm_paddr_t addr __unused, vm_size_t size __unused,
int attr __unused)
{
panic("%s is not implemented yet!\n", __func__);
}
struct pcb;
void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
void pmap_kenter_device(vm_offset_t, vm_size_t, vm_paddr_t);
void pmap_kremove_device(vm_offset_t, vm_size_t);
vm_paddr_t pmap_kextract(vm_offset_t);
#define vtophys(va) pmap_kextract((vm_offset_t)(va))
static inline int
pmap_vmspace_copy(pmap_t dst_pmap __unused, pmap_t src_pmap __unused)
{
return (0);
}
#define PMAP_ENTER_QUICK_LOCKED 0x10000000
#define pmap_vm_page_alloc_check(m)
#endif /* _KERNEL */
#endif /* !_MACHINE_PMAP_H_ */

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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1991 Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)proc.h 7.1 (Berkeley) 5/15/91
* from: FreeBSD: src/sys/i386/include/proc.h,v 1.11 2001/06/29
*/
#ifndef _MACHINE_PROC_H_
#define _MACHINE_PROC_H_
struct mdthread {
int md_spinlock_count; /* (k) */
register_t md_saved_cspr; /* (k) */
register_t md_spurflt_addr; /* (k) Spurious page fault address. */
int md_ptrace_instr;
int md_ptrace_addr;
int md_ptrace_instr_alt;
int md_ptrace_addr_alt;
};
struct mdproc {
long md_dummy;
};
#define KINFO_PROC_SIZE 816
#endif /* !_MACHINE_PROC_H_ */

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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)profile.h 8.1 (Berkeley) 6/11/93
*/
#ifndef _MACHINE_PROFILE_H_
#define _MACHINE_PROFILE_H_
/*
* Config generates something to tell the compiler to align functions on 32
* byte boundaries. A strict alignment is good for keeping the tables small.
*/
#define FUNCTION_ALIGNMENT 16
#define _MCOUNT_DECL void mcount
typedef u_long fptrdiff_t;
/*
* Cannot implement mcount in C as GCC will trash the ip register when it
* pushes a trapframe. Pity we cannot insert assembly before the function
* prologue.
*/
#ifndef PLTSYM
#define PLTSYM
#endif
#define MCOUNT \
__asm__(".text"); \
__asm__(".align 2"); \
__asm__(".type __mcount ,%function"); \
__asm__(".global __mcount"); \
__asm__("__mcount:"); \
/* \
* Preserve registers that are trashed during mcount \
*/ \
__asm__("stmfd sp!, {r0-r3, ip, lr}"); \
/* \
* find the return address for mcount, \
* and the return address for mcount's caller. \
* \
* frompcindex = pc pushed by call into self. \
*/ \
__asm__("mov r0, ip"); \
/* \
* selfpc = pc pushed by mcount call \
*/ \
__asm__("mov r1, lr"); \
/* \
* Call the real mcount code \
*/ \
__asm__("bl mcount"); \
/* \
* Restore registers that were trashed during mcount \
*/ \
__asm__("ldmfd sp!, {r0-r3, lr}"); \
/* \
* Return to the caller. Loading lr and pc in one instruction \
* is deprecated on ARMv7 so we need this on its own. \
*/ \
__asm__("ldmfd sp!, {pc}");
void bintr(void);
void btrap(void);
void eintr(void);
void user(void);
#define MCOUNT_FROMPC_USER(pc) \
((pc < (uintfptr_t)VM_MAXUSER_ADDRESS) ? (uintfptr_t)user : pc)
#define MCOUNT_FROMPC_INTR(pc) \
((pc >= (uintfptr_t)btrap && pc < (uintfptr_t)eintr) ? \
((pc >= (uintfptr_t)bintr) ? (uintfptr_t)bintr : \
(uintfptr_t)btrap) : ~0U)
#ifdef _KERNEL
#define MCOUNT_DECL(s) register_t s;
#include <machine/asm.h>
#include <machine/cpufunc.h>
#define MCOUNT_ENTER(s) {s = intr_disable(); } /* kill IRQ */
#define MCOUNT_EXIT(s) {intr_restore(s); } /* restore old value */
void mcount(uintfptr_t frompc, uintfptr_t selfpc);
#else
typedef u_int uintfptr_t;
#endif /* _KERNEL */
#endif /* !_MACHINE_PROFILE_H_ */

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/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_PTE_V6_H_
#define _MACHINE_PTE_V6_H_
/*
* Domain Types for the Domain Access Control Register.
*/
#define DOMAIN_FAULT 0x00 /* no access */
#define DOMAIN_CLIENT 0x01 /* client */
#define DOMAIN_RESERVED 0x02 /* reserved */
#define DOMAIN_MANAGER 0x03 /* manager */
/*
* TEX remap registers attributes
*/
#define PRRR_SO 0 /* Strongly ordered memory */
#define PRRR_DEV 1 /* Device memory */
#define PRRR_MEM 2 /* Normal memory */
#define PRRR_DS0 (1 << 16) /* Shared bit for Device, S = 0 */
#define PRRR_DS1 (1 << 17) /* Shared bit for Device, S = 1 */
#define PRRR_NS0 (1 << 18) /* Shared bit for Normal, S = 0 */
#define PRRR_NS1 (1 << 19) /* Shared bit for Normal, S = 1 */
#define PRRR_NOS_SHIFT 24 /* base shif for Not Outer Shared bits */
#define NMRR_NC 0 /* Noncachable*/
#define NMRR_WB_WA 1 /* Write Back, Write Allocate */
#define NMRR_WT 2 /* Write Through, Non-Write Allocate */
#define NMRR_WB 3 /* Write Back, Non-Write Allocate */
/*
*
* The ARM MMU is capable of mapping memory in the following chunks:
*
* 16M Supersections (L1 table)
*
* 1M Sections (L1 table)
*
* 64K Large Pages (L2 table)
*
* 4K Small Pages (L2 table)
*
*
* Coarse Tables can map Large and Small Pages.
* Coarse Tables are 1K in length.
*
* The Translation Table Base register holds the pointer to the
* L1 Table. The L1 Table is a 16K contiguous chunk of memory
* aligned to a 16K boundary. Each entry in the L1 Table maps
* 1M of virtual address space, either via a Section mapping or
* via an L2 Table.
*
*/
#define L1_TABLE_SIZE 0x4000 /* 16K */
#define L1_ENTRIES 0x1000 /* 4K */
#define L2_TABLE_SIZE 0x0400 /* 1K */
#define L2_ENTRIES 0x0100 /* 256 */
/* ARMv6 super-sections. */
#define L1_SUP_SIZE 0x01000000 /* 16M */
#define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
#define L1_SUP_FRAME (~L1_SUP_OFFSET)
#define L1_SUP_SHIFT 24
#define L1_S_SIZE 0x00100000 /* 1M */
#define L1_S_OFFSET (L1_S_SIZE - 1)
#define L1_S_FRAME (~L1_S_OFFSET)
#define L1_S_SHIFT 20
#define L2_L_SIZE 0x00010000 /* 64K */
#define L2_L_OFFSET (L2_L_SIZE - 1)
#define L2_L_FRAME (~L2_L_OFFSET)
#define L2_L_SHIFT 16
#define L2_S_SIZE 0x00001000 /* 4K */
#define L2_S_OFFSET (L2_S_SIZE - 1)
#define L2_S_FRAME (~L2_S_OFFSET)
#define L2_S_SHIFT 12
/*
* ARM MMU L1 Descriptors
*/
#define L1_TYPE_INV 0x00 /* Invalid (fault) */
#define L1_TYPE_C 0x01 /* Coarse L2 */
#define L1_TYPE_S 0x02 /* Section */
#define L1_TYPE_MASK 0x03 /* Mask of type bits */
/* L1 Section Descriptor */
#define L1_S_B 0x00000004 /* bufferable Section */
#define L1_S_C 0x00000008 /* cacheable Section */
#define L1_S_NX 0x00000010 /* not executeable */
#define L1_S_DOM(x) ((x) << 5) /* domain */
#define L1_S_DOM_MASK L1_S_DOM(0xf)
#define L1_S_P 0x00000200 /* ECC enable for this section */
#define L1_S_AP(x) ((x) << 10) /* access permissions */
#define L1_S_AP0 0x00000400 /* access permissions bit 0 */
#define L1_S_AP1 0x00000800 /* access permissions bit 1 */
#define L1_S_TEX(x) ((x) << 12) /* type extension */
#define L1_S_TEX0 0x00001000 /* type extension bit 0 */
#define L1_S_TEX1 0x00002000 /* type extension bit 1 */
#define L1_S_TEX2 0x00004000 /* type extension bit 2 */
#define L1_S_AP2 0x00008000 /* access permissions bit 2 */
#define L1_S_SHARED 0x00010000 /* shared */
#define L1_S_NG 0x00020000 /* not global */
#define L1_S_SUPERSEC 0x00040000 /* Section is a super-section. */
#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
/* L1 Coarse Descriptor */
#define L1_C_DOM(x) ((x) << 5) /* domain */
#define L1_C_DOM_MASK L1_C_DOM(0xf)
#define L1_C_P 0x00000200 /* ECC enable for this section */
#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
/*
* ARM MMU L2 Descriptors
*/
#define L2_TYPE_INV 0x00 /* Invalid (fault) */
#define L2_TYPE_L 0x01 /* Large Page - 64k - not used yet*/
#define L2_TYPE_S 0x02 /* Small Page - 4 */
#define L2_TYPE_MASK 0x03
#define L2_NX 0x00000001 /* Not executable */
#define L2_B 0x00000004 /* Bufferable page */
#define L2_C 0x00000008 /* Cacheable page */
#define L2_CB_SHIFT 2 /* C,B bit field shift */
#define L2_AP(x) ((x) << 4)
#define L2_AP0 0x00000010 /* access permissions bit 0*/
#define L2_AP1 0x00000020 /* access permissions bit 1*/
#define L2_TEX_SHIFT 6 /* type extension field shift */
#define L2_TEX(x) ((x) << L2_TEX_SHIFT) /* type extension */
#define L2_TEX0 0x00000040 /* type extension bit 0 */
#define L2_TEX1 0x00000080 /* type extension bit 1 */
#define L2_TEX2 0x00000100 /* type extension bit 2 */
#define L2_AP2 0x00000200 /* access permissions bit 2*/
#define L2_SHARED 0x00000400 /* shared */
#define L2_NG 0x00000800 /* not global */
/*
* TEX classes encoding
*/
#define TEX1_CLASS_0 ( 0)
#define TEX1_CLASS_1 ( L1_S_B)
#define TEX1_CLASS_2 ( L1_S_C )
#define TEX1_CLASS_3 ( L1_S_C | L1_S_B)
#define TEX1_CLASS_4 (L1_S_TEX0 )
#define TEX1_CLASS_5 (L1_S_TEX0 | L1_S_B)
#define TEX1_CLASS_6 (L1_S_TEX0 | L1_S_C ) /* Reserved for ARM11 */
#define TEX1_CLASS_7 (L1_S_TEX0 | L1_S_C | L1_S_B)
#define TEX2_CLASS_0 ( 0)
#define TEX2_CLASS_1 ( L2_B)
#define TEX2_CLASS_2 ( L2_C )
#define TEX2_CLASS_3 ( L2_C | L2_B)
#define TEX2_CLASS_4 (L2_TEX0 )
#define TEX2_CLASS_5 (L2_TEX0 | L2_B)
#define TEX2_CLASS_6 (L2_TEX0 | L2_C ) /* Reserved for ARM11 */
#define TEX2_CLASS_7 (L2_TEX0 | L2_C | L2_B)
/* L1 table definitions. */
#define NB_IN_PT1 L1_TABLE_SIZE
#define NPTE1_IN_PT1 L1_ENTRIES
/* L2 table definitions. */
#define NB_IN_PT2 L2_TABLE_SIZE
#define NPTE2_IN_PT2 L2_ENTRIES
/*
* Map memory attributes to TEX classes
*/
#define PTE2_ATTR_WB_WA TEX2_CLASS_0
#define PTE2_ATTR_NOCACHE TEX2_CLASS_1
#define PTE2_ATTR_DEVICE TEX2_CLASS_2
#define PTE2_ATTR_SO TEX2_CLASS_3
#define PTE2_ATTR_WT TEX2_CLASS_4
/*
* Software defined bits for L1 descriptors
* - L1_AP0 is used as page accessed bit
* - L1_AP2 (RO / not RW) is used as page not modified bit
* - L1_TEX0 is used as software emulated RO bit
*/
#define PTE1_V L1_TYPE_S /* Valid bit */
#define PTE1_A L1_S_AP0 /* Accessed - software emulated */
#define PTE1_NM L1_S_AP2 /* not modified bit - software emulated
* used as real write enable bit */
#define PTE1_M 0 /* Modified (dummy) */
#define PTE1_S L1_S_SHARED /* Shared */
#define PTE1_NG L1_S_NG /* Not global */
#define PTE1_G 0 /* Global (dummy) */
#define PTE1_NX L1_S_NX /* Not executable */
#define PTE1_X 0 /* Executable (dummy) */
#define PTE1_RO L1_S_TEX1 /* Read Only */
#define PTE1_RW 0 /* Read-Write (dummy) */
#define PTE1_U L1_S_AP1 /* User */
#define PTE1_NU 0 /* Not user (kernel only) (dummy) */
#define PTE1_W L1_S_TEX2 /* Wired */
#define PTE1_SHIFT L1_S_SHIFT
#define PTE1_SIZE L1_S_SIZE
#define PTE1_OFFSET L1_S_OFFSET
#define PTE1_FRAME L1_S_FRAME
#define PTE1_ATTR_MASK (L1_S_TEX0 | L1_S_C | L1_S_B)
#define PTE1_AP_KR (PTE1_RO | PTE1_NM)
#define PTE1_AP_KRW 0
#define PTE1_AP_KRUR (PTE1_RO | PTE1_NM | PTE1_U)
#define PTE1_AP_KRWURW PTE1_U
/*
* PTE1 descriptors creation macros.
*/
#define PTE1_PA(pa) ((pa) & PTE1_FRAME)
#define PTE1_AP_COMMON (PTE1_V | PTE1_S)
#define PTE1(pa, ap, attr) (PTE1_PA(pa) | (ap) | (attr) | PTE1_AP_COMMON)
#define PTE1_KERN(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_G, attr)
#define PTE1_KERN_NG(pa, ap, attr) PTE1(pa, (ap) | PTE1_A | PTE1_NG, attr)
#define PTE1_LINK(pa) (((pa) & L1_C_ADDR_MASK) | L1_TYPE_C)
/*
* Software defined bits for L2 descriptors
* - L2_AP0 is used as page accessed bit
* - L2_AP2 (RO / not RW) is used as page not modified bit
* - L2_TEX0 is used as software emulated RO bit
*/
#define PTE2_V L2_TYPE_S /* Valid bit */
#define PTE2_A L2_AP0 /* Accessed - software emulated */
#define PTE2_NM L2_AP2 /* not modified bit - software emulated
* used as real write enable bit */
#define PTE2_M 0 /* Modified (dummy) */
#define PTE2_S L2_SHARED /* Shared */
#define PTE2_NG L2_NG /* Not global */
#define PTE2_G 0 /* Global (dummy) */
#define PTE2_NX L2_NX /* Not executable */
#define PTE2_X 0 /* Not executable (dummy) */
#define PTE2_RO L2_TEX1 /* Read Only */
#define PTE2_U L2_AP1 /* User */
#define PTE2_NU 0 /* Not user (kernel only) (dummy) */
#define PTE2_W L2_TEX2 /* Wired */
#define PTE2_SHIFT L2_S_SHIFT
#define PTE2_SIZE L2_S_SIZE
#define PTE2_OFFSET L2_S_OFFSET
#define PTE2_FRAME L2_S_FRAME
#define PTE2_ATTR_MASK (L2_TEX0 | L2_C | L2_B)
/* PTE2 attributes to TEX class index: (TEX0 C B) */
#define PTE2_ATTR2IDX(attr) \
((((attr) & (L2_C | L2_B)) >> L2_CB_SHIFT) | \
(((attr) & L2_TEX0) >> (L2_TEX_SHIFT - L2_CB_SHIFT)))
#define PTE2_AP_KR (PTE2_RO | PTE2_NM)
#define PTE2_AP_KRW 0
#define PTE2_AP_KRUR (PTE2_RO | PTE2_NM | PTE2_U)
#define PTE2_AP_KRWURW PTE2_U
/*
* PTE2 descriptors creation macros.
*/
#define PTE2_PA(pa) ((pa) & PTE2_FRAME)
#define PTE2_AP_COMMON (PTE2_V | PTE2_S)
#define PTE2(pa, ap, attr) (PTE2_PA(pa) | (ap) | (attr) | PTE2_AP_COMMON)
#define PTE2_KERN(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_G, attr)
#define PTE2_KERN_NG(pa, ap, attr) PTE2(pa, (ap) | PTE2_A | PTE2_NG, attr)
#endif /* !_MACHINE_PTE_V6_H_ */

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/* $NetBSD: reg.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */
#ifndef MACHINE_REG_H
#define MACHINE_REG_H
#include <sys/_types.h>
struct reg {
unsigned int r[13];
unsigned int r_sp;
unsigned int r_lr;
unsigned int r_pc;
unsigned int r_cpsr;
};
struct fpreg {
__uint64_t fpr_r[32];
__uint32_t fpr_fpscr;
};
struct dbreg {
#define ARM_WR_MAX 16 /* Maximum number of watchpoint registers */
unsigned int dbg_wcr[ARM_WR_MAX]; /* Watchpoint Control Registers */
unsigned int dbg_wvr[ARM_WR_MAX]; /* Watchpoint Value Registers */
};
#endif /* !MACHINE_REG_H */

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lib/libc/include/aarch64-freebsd-none/arm/reloc.h vendored Normal file
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/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)reloc.h 8.1 (Berkeley) 6/10/93
*/
#ifndef _MACHINE_RELOC_H_
#define _MACHINE_RELOC_H_
/* Relocation format. */
struct relocation_info {
int r_address; /* offset in text or data segment */
unsigned int r_symbolnum : 24, /* ordinal number of add symbol */
r_pcrel : 1, /* 1 if value should be pc-relative */
r_length : 2, /* log base 2 of value's width */
r_extern : 1, /* 1 if need to add symbol to value */
r_baserel : 1, /* linkage table relative */
r_jmptable : 1, /* relocate to jump table */
r_relative : 1, /* load address relative */
r_copy : 1; /* run time copy */
};
#endif

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/*-
* Copyright 1998 Massachusetts Institute of Technology
*
* Permission to use, copy, modify, and distribute this software and
* its documentation for any purpose and without fee is hereby
* granted, provided that both the above copyright notice and this
* permission notice appear in all copies, that both the above
* copyright notice and this permission notice appear in all
* supporting documentation, and that the name of M.I.T. not be used
* in advertising or publicity pertaining to distribution of the
* software without specific, written prior permission. M.I.T. makes
* no representations about the suitability of this software for any
* purpose. It is provided "as is" without express or implied
* warranty.
*
* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_RESOURCE_H_
#define _MACHINE_RESOURCE_H_ 1
/*
* Definitions of resource types for Intel Architecture machines
* with support for legacy ISA devices and drivers.
*/
#define SYS_RES_IRQ 1 /* interrupt lines */
#define SYS_RES_DRQ 2 /* isa dma lines */
#define SYS_RES_MEMORY 3 /* i/o memory */
#define SYS_RES_IOPORT 4 /* i/o ports */
#define SYS_RES_GPIO 5 /* general purpose i/o */
#ifdef NEW_PCIB
#define PCI_RES_BUS 6 /* PCI bus numbers */
#endif
#endif /* !_MACHINE_RESOURCE_H_ */

46
lib/libc/include/aarch64-freebsd-none/arm/runq.h vendored Normal file
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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2001 Jake Burkholder <jake@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_RUNQ_H_
#define _MACHINE_RUNQ_H_
#define RQB_LEN (2) /* Number of priority status words. */
#define RQB_L2BPW (5) /* Log2(sizeof(rqb_word_t) * NBBY)). */
#define RQB_BPW (1<<RQB_L2BPW) /* Bits in an rqb_word_t. */
#define RQB_BIT(pri) (1 << ((pri) & (RQB_BPW - 1)))
#define RQB_WORD(pri) ((pri) >> RQB_L2BPW)
#define RQB_FFS(word) (ffs(word) - 1)
/*
* Type of run queue status word.
*/
typedef u_int32_t rqb_word_t;
#endif

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/* $NetBSD: setjmp.h,v 1.5 2013/01/11 13:56:32 matt Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
*/
#ifndef _MACHINE_SETJMP_H_
#define _MACHINE_SETJMP_H_
#define _JBLEN 64 /* size, in longs, of a jmp_buf */
/*
* NOTE: The internal structure of a jmp_buf is *PRIVATE*
* This information is provided as there is software
* that fiddles with this with obtain the stack pointer
* (yes really ! and its commercial !).
*
* Description of the setjmp buffer
*
* word 0 magic number (dependent on creator)
* 13 fpscr vfp status control register
* 14 r4 register 4
* 15 r5 register 5
* 16 r6 register 6
* 17 r7 register 7
* 18 r8 register 8
* 19 r9 register 9
* 20 r10 register 10 (sl)
* 21 r11 register 11 (fp)
* 22 r12 register 12 (ip)
* 23 r13 register 13 (sp)
* 24 r14 register 14 (lr)
* 25 signal mask (dependent on magic)
* 26 (con't)
* 27 (con't)
* 28 (con't)
* 32-33 d8 (vfp register d8)
* 34-35 d9 (vfp register d9)
* 36-37 d10 (vfp register d10)
* 38-39 d11 (vfp register d11)
* 40-41 d12 (vfp register d12)
* 42-43 d13 (vfp register d13)
* 44-45 d14 (vfp register d14)
* 46-47 d15 (vfp register d15)
*
* The magic number identifies the jmp_buf and
* how the buffer was created as well as providing
* a sanity check
*
* A side note I should mention - Please do not tamper
* with the floating point fields. While they are
* always saved and restored at the moment this cannot
* be garenteed especially if the compiler happens
* to be generating soft-float code so no fp
* registers will be used.
*
* Whilst this can be seen an encouraging people to
* use the setjmp buffer in this way I think that it
* is for the best then if changes occur compiles will
* break rather than just having new builds falling over
* mysteriously.
*/
#define _JB_MAGIC__SETJMP 0x4278f500
#define _JB_MAGIC_SETJMP 0x4278f501
#define _JB_MAGIC__SETJMP_VFP 0x4278f502
#define _JB_MAGIC_SETJMP_VFP 0x4278f503
/* Valid for all jmp_buf's */
#define _JB_MAGIC 0
#define _JB_REG_FPSCR 13
#define _JB_REG_R4 14
#define _JB_REG_R5 15
#define _JB_REG_R6 16
#define _JB_REG_R7 17
#define _JB_REG_R8 18
#define _JB_REG_R9 19
#define _JB_REG_R10 20
#define _JB_REG_R11 21
#define _JB_REG_R12 22
#define _JB_REG_R13 23
#define _JB_REG_R14 24
/* Only valid with the _JB_MAGIC_SETJMP magic */
#define _JB_SIGMASK 25
#define _JB_REG_D8 32
#define _JB_REG_D9 34
#define _JB_REG_D10 36
#define _JB_REG_D11 38
#define _JB_REG_D12 40
#define _JB_REG_D13 42
#define _JB_REG_D14 44
#define _JB_REG_D15 46
#ifndef __ASSEMBLER__
#if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE
typedef struct _sigjmp_buf { int _sjb[_JBLEN + 1]; } sigjmp_buf[1];
#endif
typedef struct _jmp_buf { int _jb[_JBLEN + 1]; } jmp_buf[1];
#endif
#endif /* !_MACHINE_SETJMP_H_ */

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lib/libc/include/aarch64-freebsd-none/arm/sf_buf.h vendored Normal file
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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2003 Alan L. Cox <alc@cs.rice.edu>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_SF_BUF_H_
#define _MACHINE_SF_BUF_H_
static inline void
sf_buf_map(struct sf_buf *sf, int flags)
{
pmap_qenter(sf->kva, &(sf->m), 1);
}
static inline int
sf_buf_unmap(struct sf_buf *sf)
{
pmap_qremove(sf->kva, 1);
return (1);
}
#endif /* !_MACHINE_SF_BUF_H_ */

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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1986, 1989, 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)signal.h 8.1 (Berkeley) 6/11/93
* from: FreeBSD: src/sys/i386/include/signal.h,v 1.13 2000/11/09
* from: FreeBSD: src/sys/sparc64/include/signal.h,v 1.6 2001/09/30 18:52:17
*/
#ifndef _MACHINE_SIGNAL_H_
#define _MACHINE_SIGNAL_H_
#include <sys/cdefs.h>
typedef long sig_atomic_t;
#if __BSD_VISIBLE
struct sigcontext {
int _dummy;
};
#endif
#endif /* !_MACHINE_SIGNAL_H_ */

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lib/libc/include/aarch64-freebsd-none/arm/sysarch.h vendored Normal file
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/* $NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1996-1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _ARM_SYSARCH_H_
#define _ARM_SYSARCH_H_
#include <machine/armreg.h>
#ifndef LOCORE
#ifndef __ASSEMBLER__
/*
* Pickup definition of various __types.
*/
#include <sys/_types.h>
/*
* Architecture specific syscalls (arm)
*/
#define ARM_SYNC_ICACHE 0
#define ARM_DRAIN_WRITEBUF 1
#define ARM_SET_TP 2
#define ARM_GET_TP 3
#define ARM_GET_VFPSTATE 4
struct arm_sync_icache_args {
__uintptr_t addr; /* Virtual start address */
__size_t len; /* Region size */
};
struct arm_get_vfpstate_args {
__size_t mc_vfp_size;
void *mc_vfp;
};
#ifndef _KERNEL
__BEGIN_DECLS
int arm_sync_icache(unsigned int, int);
int arm_drain_writebuf(void);
int sysarch(int, void *);
__END_DECLS
#endif
#endif /* __ASSEMBLER__ */
#endif /* LOCORE */
#endif /* !_ARM_SYSARCH_H_ */

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lib/libc/include/aarch64-freebsd-none/arm/sysreg.h vendored Normal file
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/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Macros to make working with the System Control Registers simpler.
*
* Note that when register r0 is hard-coded in these definitions it means the
* cp15 operation neither reads nor writes the register, and r0 is used only
* because some syntatically-valid register name has to appear at that point to
* keep the asm parser happy.
*/
#ifndef MACHINE_SYSREG_H
#define MACHINE_SYSREG_H
/*
* CP14 registers
*/
#define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */
#define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */
#define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */
#define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */
#define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */
#define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */
#define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */
#define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */
#define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */
/*
* CP15 C0 registers
*/
#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */
#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */
#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */
#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */
#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */
#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */
#define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */
#define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */
#define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */
#define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */
#define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */
#define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */
#define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */
#define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */
#define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */
#define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */
#define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */
#define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */
#define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */
#define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */
#define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */
#define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */
#define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */
#define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */
#define CP15_VPIDR(rr) p15, 4, rr, c0, c0, 0 /* Virtualization Processor ID Register */
#define CP15_VMPIDR(rr) p15, 4, rr, c0, c0, 5 /* Virtualization Multiprocessor ID Register */
/*
* CP15 C1 registers
*/
#define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */
#define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */
#define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */
#define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */
#define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */
#define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */
#define CP15_HSCTLR(rr) p15, 4, rr, c1, c0, 0 /* Hyp System Control Register */
#define CP15_HCR(rr) p15, 4, rr, c1, c1, 0 /* Hyp Configuration Register */
#define CP15_HDCR(rr) p15, 4, rr, c1, c1, 1 /* Hyp Debug Configuration Register */
#define CP15_HCPTR(rr) p15, 4, rr, c1, c1, 2 /* Hyp Coprocessor Trap Register */
#define CP15_HSTR(rr) p15, 4, rr, c1, c1, 3 /* Hyp System Trap Register */
/*
* CP15 C2 registers
*/
#define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */
#define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */
#define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */
#define CP15_HTCR(rr) p15, 4, rr, c2, c0, 2 /* Hyp Translation Control Register */
#define CP15_VTCR(rr) p15, 4, rr, c2, c1, 2 /* Virtualization Translation Control Register */
/*
* CP15 C3 registers
*/
#define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */
/*
* CP15 C5 registers
*/
#define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */
#define CP15_HSR(rr) p15, 4, rr, c5, c2, 0 /* Hyp Syndrome Register */
/* From ARMv6: */
#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */
#if __ARM_ARCH >= 7
/* From ARMv7: */
#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */
#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */
#endif
/*
* CP15 C6 registers
*/
#define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */
#define CP15_HDFAR(rr) p15, 4, rr, c6, c0, 0 /* Hyp Data Fault Address Register */
#define CP15_HIFAR(rr) p15, 4, rr, c6, c0, 2 /* Hyp Instruction Fault Address Register */
#define CP15_HPFAR(rr) p15, 4, rr, c6, c0, 4 /* Hyp IPA Fault Address Register */
/* From ARMv6k: */
#define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */
/*
* CP15 C7 registers
*/
#if __ARM_ARCH >= 7 && defined(SMP)
/* From ARMv7: */
#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */
#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */
#endif
#define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */
#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */
#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */
#if __ARM_ARCH == 6
/* Deprecated in ARMv7 */
#define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */
#endif
#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */
#define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */
#if __ARM_ARCH == 6
/* Only ARMv6: */
#define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */
#endif
#define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */
#define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */
#define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */
#define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */
#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */
#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */
#if __ARM_ARCH >= 7
/* From ARMv7: */
#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */
#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */
#define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */
#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */
#endif
#if __ARM_ARCH == 6
/* Only ARMv6: */
#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */
#endif
#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */
#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */
#if __ARM_ARCH == 6
/* Only ARMv6: */
#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */
#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */
#define CP15_CP15WFI p15, 0, r0, c7, c0, 4 /* WFI */
#endif
#if __ARM_ARCH >= 7
/* From ARMv7: */
#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */
#endif
#if __ARM_ARCH == 6
/* Only ARMv6: */
#define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */
#endif
#define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */
#define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */
/*
* CP15 C8 registers
*/
#if __ARM_ARCH >= 7 && defined(SMP)
/* From ARMv7: */
#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */
#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */
#define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */
#define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */
#endif
#define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */
#define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */
#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */
#define CP15_TLBIALLH(rr) p15, 4, rr, c8, c7, 0 /* Invalidate Entire Hyp Unified TLB */
/* From ARMv6: */
#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */
/*
* CP15 C9 registers
*/
#if __ARM_ARCH == 6 && defined(CPU_ARM1176)
#define CP15_PMUSERENR(rr) p15, 0, rr, c15, c9, 0 /* Access Validation Control Register */
#define CP15_PMCR(rr) p15, 0, rr, c15, c12, 0 /* Performance Monitor Control Register */
#define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */
#else
#define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */
#define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */
#define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */
#define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */
#define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */
#define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */
#define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */
#define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */
#define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */
#define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */
#define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */
#define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */
#define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */
#endif
/*
* CP15 C10 registers
*/
/* Without LPAE this is PRRR, with LPAE it's MAIR0 */
#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */
#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */
/* Without LPAE this is NMRR, with LPAE it's MAIR1 */
#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */
#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */
#define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */
#define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */
#define CP15_HMAIR0(rr) p15, 4, rr, c10, c2, 0 /* Hyp Memory Attribute Indirection Register 0 */
#define CP15_HMAIR1(rr) p15, 4, rr, c10, c2, 1 /* Hyp Memory Attribute Indirection Register 1 */
/*
* CP15 C12 registers
*/
#define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */
#define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */
#define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */
#define CP15_HVBAR(rr) p15, 4, rr, c12, c0, 0 /* Hyp Vector Base Address Register*/
/*
* CP15 C13 registers
*/
#define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */
#define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */
#define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */
#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */
#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
#define CP15_HTPIDR(rr) p15, 4, rr, c13, c0, 2 /* Hyp Software Thread ID Register */
/*
* CP15 C14 registers
* These are the Generic Timer registers and may be unallocated on some SoCs.
* Only use these when you know the Generic Timer is available.
*/
#define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */
#define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */
#define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */
#define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */
#define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */
#define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */
#define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */
#define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */
#define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */
/* 64-bit registers for use with mcrr/mrrc */
#define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */
#define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */
#define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */
#define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */
#define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */
#define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */
#define CP15_VTTBR(rq, rr) p15, 6, rq, rr, c2 /* Virtualization Translation Table Base Register */
#define CP15_HTTBR(rq, rr) p15, 4, rq, rr, c2 /* Hyp Translation Table Base Register */
#define CP15_TTBR0_2(rq, rr) p15, 0, rq, rr, c2 /* Translation Table Base Register 0 */
#define CP15_TTBR1_2(rq, rr) p15, 1, rq, rr, c2 /* Translation Table Base Register 1 */
#define CP15_PAR_2(rq, rr) p15, 0, rq, rr, c7 /* Physical Address Register */
/*
* CP15 C15 registers
*/
#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */
#endif /* !MACHINE_SYSREG_H */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2005 David Xu <davidxu@freebsd.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_TLS_H_
#define _MACHINE_TLS_H_
#include <sys/_tls_variant_i.h>
#include <machine/sysarch.h>
#define TLS_DTV_OFFSET 0
#define TLS_TCB_ALIGN 8
#define TLS_TP_OFFSET 0
static __inline void
_tcb_set(struct tcb *tcb)
{
sysarch(ARM_SET_TP, tcb);
}
static __inline struct tcb *
_tcb_get(void)
{
struct tcb *tcb;
__asm __volatile("mrc p15, 0, %0, c13, c0, 3" \
: "=r" (tcb));
return (tcb);
}
#endif /* !_MACHINE_TLS_H_ */

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/* $NetBSD: mcontext.h,v 1.4 2003/10/08 22:43:01 thorpej Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein and by Jason R. Thorpe of Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_MCONTEXT_H_
#define _MACHINE_MCONTEXT_H_
/*
* General register state
*/
#define _NGREG 17
typedef unsigned int __greg_t;
typedef __greg_t __gregset_t[_NGREG];
#define _REG_R0 0
#define _REG_R1 1
#define _REG_R2 2
#define _REG_R3 3
#define _REG_R4 4
#define _REG_R5 5
#define _REG_R6 6
#define _REG_R7 7
#define _REG_R8 8
#define _REG_R9 9
#define _REG_R10 10
#define _REG_R11 11
#define _REG_R12 12
#define _REG_R13 13
#define _REG_R14 14
#define _REG_R15 15
#define _REG_CPSR 16
/* Convenience synonyms */
#define _REG_FP _REG_R11
#define _REG_SP _REG_R13
#define _REG_LR _REG_R14
#define _REG_PC _REG_R15
/*
* Floating point register state
*/
typedef struct {
__uint64_t mcv_reg[32];
__uint32_t mcv_fpscr;
} mcontext_vfp_t;
typedef struct {
__gregset_t __gregs;
/*
* Originally, rest of this structure was named __fpu, 35 * 4 bytes
* long, never accessed from kernel.
*/
__size_t mc_vfp_size;
void *mc_vfp_ptr;
unsigned int mc_spare[33];
} mcontext_t;
#define UC_
#endif /* !_MACHINE_MCONTEXT_H_ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright 2012 Konstantin Belousov <kib@FreeBSD.ORG>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_VDSO_H
#define _ARM_VDSO_H
#define VDSO_TIMEHANDS_MD \
uint32_t th_physical; \
uint32_t th_res[7];
#define VDSO_TH_ALGO_ARM_GENTIM VDSO_TH_ALGO_1
#endif

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2012 Mark Tinguely
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE__VFP_H_
#define _MACHINE__VFP_H_
/* fpsid, fpscr, fpexc are defined in the newer gas */
#define VFPSID cr0
#define VFPSCR cr1
#define VMVFR1 cr6
#define VMVFR0 cr7
#define VFPEXC cr8
#define VFPINST cr9 /* vfp 1 and 2 except instruction */
#define VFPINST2 cr10 /* vfp 2? */
/* VFPSID */
#define VFPSID_IMPLEMENTOR_OFF 24
#define VFPSID_IMPLEMENTOR_MASK (0xff000000)
#define VFPSID_HARDSOFT_IMP (0x00800000)
#define VFPSID_SINGLE_PREC 20 /* version 1 and 2 */
#define VFPSID_SUBVERSION_OFF 16
#define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
#define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
#define VFP_ARCH1 0x0
#define VFP_ARCH2 0x1
#define VFP_ARCH3 0x2
#define VFPSID_PARTNUMBER_OFF 8
#define VFPSID_PARTNUMBER_MASK (0x0000ff00)
#define VFPSID_VARIANT_OFF 4
#define VFPSID_VARIANT_MASK (0x000000f0)
#define VFPSID_REVISION_MASK 0x0f
/* VFPSCR */
#define VFPSCR_CC_N (0x80000000) /* comparison less than */
#define VFPSCR_CC_Z (0x40000000) /* comparison equal */
#define VFPSCR_CC_C (0x20000000) /* comparison = > unordered */
#define VFPSCR_CC_V (0x10000000) /* comparison unordered */
#define VFPSCR_QC (0x08000000) /* saturation cululative */
#define VFPSCR_DN (0x02000000) /* default NaN enable */
#define VFPSCR_FZ (0x01000000) /* flush to zero enabled */
#define VFPSCR_RMODE_OFF 22 /* rounding mode offset */
#define VFPSCR_RMODE_MASK (0x00c00000) /* rounding mode mask */
#define VFPSCR_RMODE_RN (0x00000000) /* round nearest */
#define VFPSCR_RMODE_RPI (0x00400000) /* round to plus infinity */
#define VFPSCR_RMODE_RNI (0x00800000) /* round to neg infinity */
#define VFPSCR_RMODE_RM (0x00c00000) /* round to zero */
#define VFPSCR_STRIDE_OFF 20 /* vector stride -1 */
#define VFPSCR_STRIDE_MASK (0x00300000)
#define VFPSCR_LEN_OFF 16 /* vector length -1 */
#define VFPSCR_LEN_MASK (0x00070000)
#define VFPSCR_IDE (0x00008000) /* input subnormal exc enable */
#define VFPSCR_IXE (0x00001000) /* inexact exception enable */
#define VFPSCR_UFE (0x00000800) /* underflow exception enable */
#define VFPSCR_OFE (0x00000400) /* overflow exception enable */
#define VFPSCR_DNZ (0x00000200) /* div by zero exception en */
#define VFPSCR_IOE (0x00000100) /* invalid op exec enable */
#define VFPSCR_IDC (0x00000080) /* input subnormal cumul */
#define VFPSCR_IXC (0x00000010) /* Inexact cumulative flag */
#define VFPSCR_UFC (0x00000008) /* underflow cumulative flag */
#define VFPSCR_OFC (0x00000004) /* overflow cumulative flag */
#define VFPSCR_DZC (0x00000002) /* division by zero flag */
#define VFPSCR_IOC (0x00000001) /* invalid operation cumul */
/* VFPEXC */
#define VFPEXC_EX (0x80000000) /* exception v1 v2 */
#define VFPEXC_EN (0x40000000) /* vfp enable */
#define VFPEXC_DEX (0x20000000) /* Synchronous exception */
#define VFPEXC_FP2V (0x10000000) /* FPINST2 valid */
#define VFPEXC_INV (0x00000080) /* Input exception */
#define VFPEXC_UFC (0x00000008) /* Underflow exception */
#define VFPEXC_OFC (0x00000004) /* Overflow exception */
#define VFPEXC_IOC (0x00000001) /* Invlaid operation */
/* version 3 registers */
/* VMVFR0 */
#define VMVFR0_RM_OFF 28
#define VMVFR0_RM_MASK (0xf0000000) /* VFP rounding modes */
#define VMVFR0_SV_OFF 24
#define VMVFR0_SV_MASK (0x0f000000) /* VFP short vector supp */
#define VMVFR0_SR_OFF 20
#define VMVFR0_SR (0x00f00000) /* VFP hw sqrt supp */
#define VMVFR0_D_OFF 16
#define VMVFR0_D_MASK (0x000f0000) /* VFP divide supp */
#define VMVFR0_TE_OFF 12
#define VMVFR0_TE_MASK (0x0000f000) /* VFP trap exception supp */
#define VMVFR0_DP_OFF 8
#define VMVFR0_DP_MASK (0x00000f00) /* VFP double prec support */
#define VMVFR0_SP_OFF 4
#define VMVFR0_SP_MASK (0x000000f0) /* VFP single prec support */
#define VMVFR0_RB_MASK (0x0000000f) /* VFP 64 bit media support */
/* VMVFR1 */
#define VMVFR1_FMAC_OFF 28
#define VMVFR1_FMAC_MASK (0xf0000000) /* Neon FMAC support */
#define VMVFR1_VFP_HP_OFF 24
#define VMVFR1_VFP_HP_MASK (0x0f000000) /* VFP half prec support */
#define VMVFR1_HP_OFF 20
#define VMVFR1_HP_MASK (0x00f00000) /* Neon half prec support */
#define VMVFR1_SP_OFF 16
#define VMVFR1_SP_MASK (0x000f0000) /* Neon single prec support */
#define VMVFR1_I_OFF 12
#define VMVFR1_I_MASK (0x0000f000) /* Neon integer support */
#define VMVFR1_LS_OFF 8
#define VMVFR1_LS_MASK (0x00000f00) /* Neon ld/st instr support */
#define VMVFR1_DN_OFF 4
#define VMVFR1_DN_MASK (0x000000f0) /* Neon prop NaN support */
#define VMVFR1_FZ_MASK (0x0000000f) /* Neon denormal arith supp */
#define COPROC10 (0x3 << 20)
#define COPROC11 (0x3 << 22)
#define FPU_KERN_NORMAL 0x0000
#define FPU_KERN_NOWAIT 0x0001
#define FPU_KERN_KTHR 0x0002
#define FPU_KERN_NOCTX 0x0004
#ifndef LOCORE
struct vfp_state {
uint64_t reg[32];
uint32_t fpscr;
uint32_t fpexec;
uint32_t fpinst;
uint32_t fpinst2;
};
#ifdef _KERNEL
void get_vfpcontext(struct thread *, mcontext_vfp_t *);
void set_vfpcontext(struct thread *, mcontext_vfp_t *);
void vfp_init(void);
void vfp_new_thread(struct thread*, struct thread*, bool);
void vfp_store(struct vfp_state *, boolean_t);
void vfp_discard(struct thread *);
void vfp_restore_state(void);
void vfp_save_state(struct thread *, struct pcb *);
struct fpu_kern_ctx;
struct fpu_kern_ctx *fpu_kern_alloc_ctx(u_int);
void fpu_kern_free_ctx(struct fpu_kern_ctx *);
void fpu_kern_enter(struct thread *, struct fpu_kern_ctx *, u_int);
int fpu_kern_leave(struct thread *, struct fpu_kern_ctx *);
int fpu_kern_thread(u_int);
int is_fpu_kern_thread(u_int);
#endif /* _KERNEL */
#endif /* LOCORE */
#endif

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/* $NetBSD: vmparam.h,v 1.26 2003/08/07 16:27:47 agc Exp $ */
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1988 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_VMPARAM_H_
#define _MACHINE_VMPARAM_H_
/*
* Machine dependent constants for ARM.
*/
/*
* Virtual memory related constants, all in bytes
*/
#ifndef MAXTSIZ
#define MAXTSIZ (256UL*1024*1024) /* max text size */
#endif
#ifndef DFLDSIZ
#define DFLDSIZ (128UL*1024*1024) /* initial data size limit */
#endif
#ifndef MAXDSIZ
#define MAXDSIZ (512UL*1024*1024) /* max data size */
#endif
#ifndef DFLSSIZ
#define DFLSSIZ (4UL*1024*1024) /* initial stack size limit */
#endif
#ifndef MAXSSIZ
#define MAXSSIZ (64UL*1024*1024) /* max stack size */
#endif
#ifndef SGROWSIZ
#define SGROWSIZ (128UL*1024) /* amount to grow stack */
#endif
/*
* Address space constants
*/
/*
* The line between user space and kernel space
* Mappings >= KERNEL_BASE are constant across all processes
*/
#ifndef KERNBASE
#define KERNBASE 0xc0000000
#endif
/*
* The virtual address the kernel is linked to run at. For armv4/5 platforms
* the low-order 30 bits of this must match the low-order bits of the physical
* address the kernel is loaded at, so the value is most often provided as a
* kernel config option in the std.platform file. For armv6/7 the kernel can
* be loaded at any 2MB boundary, and KERNVIRTADDR can also be set to any 2MB
* boundary. It is typically overridden in the std.platform file only when
* KERNBASE is also set to a lower address to provide more KVA.
*/
#ifndef KERNVIRTADDR
#define KERNVIRTADDR 0xc0000000
#endif
/*
* max number of non-contig chunks of physical RAM you can have
*/
#define VM_PHYSSEG_MAX 32
/*
* The physical address space may be sparsely populated on some ARM systems.
*/
#define VM_PHYSSEG_SPARSE
/*
* Create one free page pool. Since the ARM kernel virtual address
* space does not include a mapping onto the machine's entire physical
* memory, VM_FREEPOOL_DIRECT is defined as an alias for the default
* pool, VM_FREEPOOL_DEFAULT.
*/
#define VM_NFREEPOOL 1
#define VM_FREEPOOL_DEFAULT 0
#define VM_FREEPOOL_DIRECT 0
/*
* We need just one free list: DEFAULT.
*/
#define VM_NFREELIST 1
#define VM_FREELIST_DEFAULT 0
/*
* The largest allocation size is 1MB.
*/
#define VM_NFREEORDER 9
/*
* Enable superpage reservations: 1 level.
*/
#ifndef VM_NRESERVLEVEL
#define VM_NRESERVLEVEL 1
#endif
/*
* Level 0 reservations consist of 256 pages.
*/
#ifndef VM_LEVEL_0_ORDER
#define VM_LEVEL_0_ORDER 8
#endif
#define VM_MIN_ADDRESS (0x00001000)
#ifndef VM_MAXUSER_ADDRESS
#define VM_MAXUSER_ADDRESS (KERNBASE - 0x00400000) /* !!! PT2MAP_SIZE */
#endif
#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
#define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE)
#define USRSTACK SHAREDPAGE
/* initial pagein size of beginning of executable file */
#ifndef VM_INITIAL_PAGEIN
#define VM_INITIAL_PAGEIN 16
#endif
#ifndef VM_MIN_KERNEL_ADDRESS
#define VM_MIN_KERNEL_ADDRESS KERNBASE
#endif
#define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address)
/*
* How many physical pages per kmem arena virtual page.
*/
#ifndef VM_KMEM_SIZE_SCALE
#define VM_KMEM_SIZE_SCALE (3)
#endif
/*
* Optional floor (in bytes) on the size of the kmem arena.
*/
#ifndef VM_KMEM_SIZE_MIN
#define VM_KMEM_SIZE_MIN (12 * 1024 * 1024)
#endif
/*
* Optional ceiling (in bytes) on the size of the kmem arena: 40% of the
* kernel map.
*/
#ifndef VM_KMEM_SIZE_MAX
#define VM_KMEM_SIZE_MAX ((vm_max_kernel_address - \
VM_MIN_KERNEL_ADDRESS + 1) * 2 / 5)
#endif
extern vm_offset_t vm_max_kernel_address;
#define ZERO_REGION_SIZE (64 * 1024) /* 64KB */
#ifndef VM_MAX_AUTOTUNE_MAXUSERS
#define VM_MAX_AUTOTUNE_MAXUSERS 384
#endif
#define SFBUF
#define SFBUF_MAP
#define PMAP_HAS_DMAP 0
#define PHYS_TO_DMAP(x) ({ panic("No direct map exists"); 0; })
#define DMAP_TO_PHYS(x) ({ panic("No direct map exists"); 0; })
#define DEVMAP_MAX_VADDR ARM_VECTORS_HIGH
/*
* No non-transparent large page support in the pmap.
*/
#define PMAP_HAS_LARGEPAGES 0
/*
* Need a page dump array for minidump.
*/
#define MINIDUMP_PAGE_TRACKING 1
#endif /* _MACHINE_VMPARAM_H_ */

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/*-
* Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef __arm__
#include <arm/fenv.h>
#else /* __arm__ */
#ifndef _FENV_H_
#define _FENV_H_
#include <sys/_types.h>
#ifndef __fenv_static
#define __fenv_static static
#endif
/* The high 32 bits contain fpcr, low 32 contain fpsr. */
typedef __uint64_t fenv_t;
typedef __uint64_t fexcept_t;
/* Exception flags */
#define FE_INVALID 0x00000001
#define FE_DIVBYZERO 0x00000002
#define FE_OVERFLOW 0x00000004
#define FE_UNDERFLOW 0x00000008
#define FE_INEXACT 0x00000010
#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
/*
* Rounding modes
*
* We can't just use the hardware bit values here, because that would
* make FE_UPWARD and FE_DOWNWARD negative, which is not allowed.
*/
#define FE_TONEAREST 0x0
#define FE_UPWARD 0x1
#define FE_DOWNWARD 0x2
#define FE_TOWARDZERO 0x3
#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
FE_UPWARD | FE_TOWARDZERO)
#define _ROUND_SHIFT 22
__BEGIN_DECLS
/* Default floating-point environment */
extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV (&__fe_dfl_env)
/* We need to be able to map status flag positions to mask flag positions */
#define _FPUSW_SHIFT 8
#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT)
#define __mrs_fpcr(__r) __asm __volatile("mrs %0, fpcr" : "=r" (__r))
#define __msr_fpcr(__r) __asm __volatile("msr fpcr, %0" : : "r" (__r))
#define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r))
#define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r))
__fenv_static __inline int
feclearexcept(int __excepts)
{
fexcept_t __r;
__mrs_fpsr(__r);
__r &= ~__excepts;
__msr_fpsr(__r);
return (0);
}
__fenv_static inline int
fegetexceptflag(fexcept_t *__flagp, int __excepts)
{
fexcept_t __r;
__mrs_fpsr(__r);
*__flagp = __r & __excepts;
return (0);
}
__fenv_static inline int
fesetexceptflag(const fexcept_t *__flagp, int __excepts)
{
fexcept_t __r;
__mrs_fpsr(__r);
__r &= ~__excepts;
__r |= *__flagp & __excepts;
__msr_fpsr(__r);
return (0);
}
__fenv_static inline int
feraiseexcept(int __excepts)
{
fexcept_t __r;
__mrs_fpsr(__r);
__r |= __excepts;
__msr_fpsr(__r);
return (0);
}
__fenv_static inline int
fetestexcept(int __excepts)
{
fexcept_t __r;
__mrs_fpsr(__r);
return (__r & __excepts);
}
__fenv_static inline int
fegetround(void)
{
fenv_t __r;
__mrs_fpcr(__r);
return ((__r >> _ROUND_SHIFT) & _ROUND_MASK);
}
__fenv_static inline int
fesetround(int __round)
{
fenv_t __r;
if (__round & ~_ROUND_MASK)
return (-1);
__mrs_fpcr(__r);
__r &= ~(_ROUND_MASK << _ROUND_SHIFT);
__r |= __round << _ROUND_SHIFT;
__msr_fpcr(__r);
return (0);
}
__fenv_static inline int
fegetenv(fenv_t *__envp)
{
__uint64_t fpcr;
__uint64_t fpsr;
__mrs_fpcr(fpcr);
__mrs_fpsr(fpsr);
*__envp = fpsr | (fpcr << 32);
return (0);
}
__fenv_static inline int
feholdexcept(fenv_t *__envp)
{
fenv_t __r;
__mrs_fpcr(__r);
*__envp = __r << 32;
__r &= ~(_ENABLE_MASK);
__msr_fpcr(__r);
__mrs_fpsr(__r);
*__envp |= (__uint32_t)__r;
__r &= ~(_ENABLE_MASK);
__msr_fpsr(__r);
return (0);
}
__fenv_static inline int
fesetenv(const fenv_t *__envp)
{
__msr_fpcr((*__envp) >> 32);
__msr_fpsr((fenv_t)(__uint32_t)*__envp);
return (0);
}
__fenv_static inline int
feupdateenv(const fenv_t *__envp)
{
fexcept_t __r;
__mrs_fpsr(__r);
fesetenv(__envp);
feraiseexcept(__r & FE_ALL_EXCEPT);
return (0);
}
#if __BSD_VISIBLE
/* We currently provide no external definitions of the functions below. */
static inline int
feenableexcept(int __mask)
{
fenv_t __old_r, __new_r;
__mrs_fpcr(__old_r);
__new_r = __old_r | ((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
__msr_fpcr(__new_r);
return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
}
static inline int
fedisableexcept(int __mask)
{
fenv_t __old_r, __new_r;
__mrs_fpcr(__old_r);
__new_r = __old_r & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT);
__msr_fpcr(__new_r);
return ((__old_r >> _FPUSW_SHIFT) & FE_ALL_EXCEPT);
}
static inline int
fegetexcept(void)
{
fenv_t __r;
__mrs_fpcr(__r);
return ((__r & _ENABLE_MASK) >> _FPUSW_SHIFT);
}
#endif /* __BSD_VISIBLE */
__END_DECLS
#endif /* !_FENV_H_ */
#endif /* __arm__ */

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/*-
* Copyright (c) 1989 Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)float.h 7.1 (Berkeley) 5/8/90
*/
#ifdef __arm__
#include <arm/float.h>
#else /* !__arm__ */
#ifndef _MACHINE_FLOAT_H_
#define _MACHINE_FLOAT_H_
#include <sys/cdefs.h>
__BEGIN_DECLS
extern int __flt_rounds(void);
__END_DECLS
#define FLT_RADIX 2 /* b */
#define FLT_ROUNDS __flt_rounds()
#if __ISO_C_VISIBLE >= 1999
#define FLT_EVAL_METHOD 0
#define DECIMAL_DIG 17 /* max precision in decimal digits */
#endif
#define FLT_MANT_DIG 24 /* p */
#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */
#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
#define FLT_MIN_EXP (-125) /* emin */
#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */
#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
#define FLT_MAX_EXP 128 /* emax */
#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
#if __ISO_C_VISIBLE >= 2011
#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */
#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */
#define FLT_HAS_SUBNORM 1
#endif /* __ISO_C_VISIBLE >= 2011 */
#define DBL_MANT_DIG 53
#define DBL_EPSILON 2.2204460492503131E-16
#define DBL_DIG 15
#define DBL_MIN_EXP (-1021)
#define DBL_MIN 2.2250738585072014E-308
#define DBL_MIN_10_EXP (-307)
#define DBL_MAX_EXP 1024
#define DBL_MAX 1.7976931348623157E+308
#define DBL_MAX_10_EXP 308
#if __ISO_C_VISIBLE >= 2011
#define DBL_TRUE_MIN 4.9406564584124654E-324
#define DBL_DECIMAL_DIG 17
#define DBL_HAS_SUBNORM 1
#endif /* __ISO_C_VISIBLE >= 2011 */
#define LDBL_MANT_DIG 113
#define LDBL_EPSILON 1.925929944387235853055977942584927319E-34L
#define LDBL_DIG 33
#define LDBL_MIN_EXP (-16381)
#define LDBL_MIN 3.362103143112093506262677817321752603E-4932L
#define LDBL_MIN_10_EXP (-4931)
#define LDBL_MAX_EXP (+16384)
#define LDBL_MAX 1.189731495357231765085759326628007016E+4932L
#define LDBL_MAX_10_EXP (+4932)
#if __ISO_C_VISIBLE >= 2011
#define LDBL_TRUE_MIN 6.475175119438025110924438958227646552E-4966L
#define LDBL_DECIMAL_DIG 36
#define LDBL_HAS_SUBNORM 1
#endif /* __ISO_C_VISIBLE >= 2011 */
#endif /* _MACHINE_FLOAT_H_ */
#endif /* !__arm__ */

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#include <machine/ieeefp.h>

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/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)param.h 5.8 (Berkeley) 6/28/91
*/
#ifdef __arm__
#include <arm/_align.h>
#else /* !__arm__ */
#ifndef _MACHINE__ALIGN_H_
#define _MACHINE__ALIGN_H_
/*
* Round p (pointer or byte index) up to a correctly-aligned value
* for all data types (int, long, ...). The result is unsigned int
* and must be cast to any desired pointer type.
*/
#define _ALIGNBYTES (sizeof(long long) - 1)
#define _ALIGN(p) (((u_long)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
#endif /* !_MACHINE__ALIGN_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 2005 M. Warner Losh <imp@FreeBSD.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE__BUS_H_
#define _MACHINE__BUS_H_
/*
* Addresses (in bus space).
*/
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
/*
* Access methods for bus space.
*/
typedef u_long bus_space_handle_t;
typedef struct bus_space *bus_space_tag_t;
#endif /* !_MACHINE__BUS_H_ */

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/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* From: $NetBSD: int_fmtio.h,v 1.4 2008/04/28 20:23:36 martin Exp $
*/
#ifdef __arm__
#include <arm/_inttypes.h>
#else /* !__arm__ */
#ifndef _MACHINE__INTTYPES_H_
#define _MACHINE__INTTYPES_H_
/*
* Macros for format specifiers.
*/
/* fprintf(3) macros for signed integers. */
#define PRId8 "d" /* int8_t */
#define PRId16 "d" /* int16_t */
#define PRId32 "d" /* int32_t */
#define PRId64 "ld" /* int64_t */
#define PRIdLEAST8 "d" /* int_least8_t */
#define PRIdLEAST16 "d" /* int_least16_t */
#define PRIdLEAST32 "d" /* int_least32_t */
#define PRIdLEAST64 "ld" /* int_least64_t */
#define PRIdFAST8 "d" /* int_fast8_t */
#define PRIdFAST16 "d" /* int_fast16_t */
#define PRIdFAST32 "d" /* int_fast32_t */
#define PRIdFAST64 "ld" /* int_fast64_t */
#define PRIdMAX "jd" /* intmax_t */
#define PRIdPTR "ld" /* intptr_t */
#define PRIi8 "i" /* int8_t */
#define PRIi16 "i" /* int16_t */
#define PRIi32 "i" /* int32_t */
#define PRIi64 "li" /* int64_t */
#define PRIiLEAST8 "i" /* int_least8_t */
#define PRIiLEAST16 "i" /* int_least16_t */
#define PRIiLEAST32 "i" /* int_least32_t */
#define PRIiLEAST64 "li" /* int_least64_t */
#define PRIiFAST8 "i" /* int_fast8_t */
#define PRIiFAST16 "i" /* int_fast16_t */
#define PRIiFAST32 "i" /* int_fast32_t */
#define PRIiFAST64 "li" /* int_fast64_t */
#define PRIiMAX "ji" /* intmax_t */
#define PRIiPTR "li" /* intptr_t */
/* fprintf(3) macros for unsigned integers. */
#define PRIo8 "o" /* uint8_t */
#define PRIo16 "o" /* uint16_t */
#define PRIo32 "o" /* uint32_t */
#define PRIo64 "lo" /* uint64_t */
#define PRIoLEAST8 "o" /* uint_least8_t */
#define PRIoLEAST16 "o" /* uint_least16_t */
#define PRIoLEAST32 "o" /* uint_least32_t */
#define PRIoLEAST64 "lo" /* uint_least64_t */
#define PRIoFAST8 "o" /* uint_fast8_t */
#define PRIoFAST16 "o" /* uint_fast16_t */
#define PRIoFAST32 "o" /* uint_fast32_t */
#define PRIoFAST64 "lo" /* uint_fast64_t */
#define PRIoMAX "jo" /* uintmax_t */
#define PRIoPTR "lo" /* uintptr_t */
#define PRIu8 "u" /* uint8_t */
#define PRIu16 "u" /* uint16_t */
#define PRIu32 "u" /* uint32_t */
#define PRIu64 "lu" /* uint64_t */
#define PRIuLEAST8 "u" /* uint_least8_t */
#define PRIuLEAST16 "u" /* uint_least16_t */
#define PRIuLEAST32 "u" /* uint_least32_t */
#define PRIuLEAST64 "lu" /* uint_least64_t */
#define PRIuFAST8 "u" /* uint_fast8_t */
#define PRIuFAST16 "u" /* uint_fast16_t */
#define PRIuFAST32 "u" /* uint_fast32_t */
#define PRIuFAST64 "lu" /* uint_fast64_t */
#define PRIuMAX "ju" /* uintmax_t */
#define PRIuPTR "lu" /* uintptr_t */
#define PRIx8 "x" /* uint8_t */
#define PRIx16 "x" /* uint16_t */
#define PRIx32 "x" /* uint32_t */
#define PRIx64 "lx" /* uint64_t */
#define PRIxLEAST8 "x" /* uint_least8_t */
#define PRIxLEAST16 "x" /* uint_least16_t */
#define PRIxLEAST32 "x" /* uint_least32_t */
#define PRIxLEAST64 "lx" /* uint_least64_t */
#define PRIxFAST8 "x" /* uint_fast8_t */
#define PRIxFAST16 "x" /* uint_fast16_t */
#define PRIxFAST32 "x" /* uint_fast32_t */
#define PRIxFAST64 "lx" /* uint_fast64_t */
#define PRIxMAX "jx" /* uintmax_t */
#define PRIxPTR "lx" /* uintptr_t */
#define PRIX8 "X" /* uint8_t */
#define PRIX16 "X" /* uint16_t */
#define PRIX32 "X" /* uint32_t */
#define PRIX64 "lX" /* uint64_t */
#define PRIXLEAST8 "X" /* uint_least8_t */
#define PRIXLEAST16 "X" /* uint_least16_t */
#define PRIXLEAST32 "X" /* uint_least32_t */
#define PRIXLEAST64 "lX" /* uint_least64_t */
#define PRIXFAST8 "X" /* uint_fast8_t */
#define PRIXFAST16 "X" /* uint_fast16_t */
#define PRIXFAST32 "X" /* uint_fast32_t */
#define PRIXFAST64 "lX" /* uint_fast64_t */
#define PRIXMAX "jX" /* uintmax_t */
#define PRIXPTR "lX" /* uintptr_t */
/* fscanf(3) macros for signed integers. */
#define SCNd8 "hhd" /* int8_t */
#define SCNd16 "hd" /* int16_t */
#define SCNd32 "d" /* int32_t */
#define SCNd64 "ld" /* int64_t */
#define SCNdLEAST8 "hhd" /* int_least8_t */
#define SCNdLEAST16 "hd" /* int_least16_t */
#define SCNdLEAST32 "d" /* int_least32_t */
#define SCNdLEAST64 "ld" /* int_least64_t */
#define SCNdFAST8 "d" /* int_fast8_t */
#define SCNdFAST16 "d" /* int_fast16_t */
#define SCNdFAST32 "d" /* int_fast32_t */
#define SCNdFAST64 "ld" /* int_fast64_t */
#define SCNdMAX "jd" /* intmax_t */
#define SCNdPTR "ld" /* intptr_t */
#define SCNi8 "hhi" /* int8_t */
#define SCNi16 "hi" /* int16_t */
#define SCNi32 "i" /* int32_t */
#define SCNi64 "li" /* int64_t */
#define SCNiLEAST8 "hhi" /* int_least8_t */
#define SCNiLEAST16 "hi" /* int_least16_t */
#define SCNiLEAST32 "i" /* int_least32_t */
#define SCNiLEAST64 "li" /* int_least64_t */
#define SCNiFAST8 "i" /* int_fast8_t */
#define SCNiFAST16 "i" /* int_fast16_t */
#define SCNiFAST32 "i" /* int_fast32_t */
#define SCNiFAST64 "li" /* int_fast64_t */
#define SCNiMAX "ji" /* intmax_t */
#define SCNiPTR "li" /* intptr_t */
/* fscanf(3) macros for unsigned integers. */
#define SCNo8 "hho" /* uint8_t */
#define SCNo16 "ho" /* uint16_t */
#define SCNo32 "o" /* uint32_t */
#define SCNo64 "lo" /* uint64_t */
#define SCNoLEAST8 "hho" /* uint_least8_t */
#define SCNoLEAST16 "ho" /* uint_least16_t */
#define SCNoLEAST32 "o" /* uint_least32_t */
#define SCNoLEAST64 "lo" /* uint_least64_t */
#define SCNoFAST8 "o" /* uint_fast8_t */
#define SCNoFAST16 "o" /* uint_fast16_t */
#define SCNoFAST32 "o" /* uint_fast32_t */
#define SCNoFAST64 "lo" /* uint_fast64_t */
#define SCNoMAX "jo" /* uintmax_t */
#define SCNoPTR "lo" /* uintptr_t */
#define SCNu8 "hhu" /* uint8_t */
#define SCNu16 "hu" /* uint16_t */
#define SCNu32 "u" /* uint32_t */
#define SCNu64 "lu" /* uint64_t */
#define SCNuLEAST8 "hhu" /* uint_least8_t */
#define SCNuLEAST16 "hu" /* uint_least16_t */
#define SCNuLEAST32 "u" /* uint_least32_t */
#define SCNuLEAST64 "lu" /* uint_least64_t */
#define SCNuFAST8 "u" /* uint_fast8_t */
#define SCNuFAST16 "u" /* uint_fast16_t */
#define SCNuFAST32 "u" /* uint_fast32_t */
#define SCNuFAST64 "lu" /* uint_fast64_t */
#define SCNuMAX "ju" /* uintmax_t */
#define SCNuPTR "lu" /* uintptr_t */
#define SCNx8 "hhx" /* uint8_t */
#define SCNx16 "hx" /* uint16_t */
#define SCNx32 "x" /* uint32_t */
#define SCNx64 "lx" /* uint64_t */
#define SCNxLEAST8 "hhx" /* uint_least8_t */
#define SCNxLEAST16 "hx" /* uint_least16_t */
#define SCNxLEAST32 "x" /* uint_least32_t */
#define SCNxLEAST64 "lx" /* uint_least64_t */
#define SCNxFAST8 "x" /* uint_fast8_t */
#define SCNxFAST16 "x" /* uint_fast16_t */
#define SCNxFAST32 "x" /* uint_fast32_t */
#define SCNxFAST64 "lx" /* uint_fast64_t */
#define SCNxMAX "jx" /* uintmax_t */
#define SCNxPTR "lx" /* uintptr_t */
#endif /* !_MACHINE__INTTYPES_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 1988, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)limits.h 8.3 (Berkeley) 1/4/94
*/
#ifdef __arm__
#include <arm/_limits.h>
#else /* !__arm__ */
#ifndef _MACHINE__LIMITS_H_
#define _MACHINE__LIMITS_H_
/*
* According to ANSI (section 2.2.4.2), the values below must be usable by
* #if preprocessing directives. Additionally, the expression must have the
* same type as would an expression that is an object of the corresponding
* type converted according to the integral promotions. The subtraction for
* INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an
* unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2).
*/
#define __CHAR_BIT 8 /* number of bits in a char */
#define __SCHAR_MAX 0x7f /* max value for a signed char */
#define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */
#define __UCHAR_MAX 0xff /* max value for an unsigned char */
#define __USHRT_MAX 0xffff /* max value for an unsigned short */
#define __SHRT_MAX 0x7fff /* max value for a short */
#define __SHRT_MIN (-0x7fff - 1) /* min value for a short */
#define __UINT_MAX 0xffffffff /* max value for an unsigned int */
#define __INT_MAX 0x7fffffff /* max value for an int */
#define __INT_MIN (-0x7fffffff - 1) /* min value for an int */
#define __ULONG_MAX 0xffffffffffffffffUL /* max for an unsigned long */
#define __LONG_MAX 0x7fffffffffffffffL /* max for a long */
#define __LONG_MIN (-0x7fffffffffffffffL - 1) /* min for a long */
/* Long longs have the same size but not the same type as longs. */
/* max for an unsigned long long */
#define __ULLONG_MAX 0xffffffffffffffffULL
#define __LLONG_MAX 0x7fffffffffffffffLL /* max for a long long */
#define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */
#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */
#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */
#define __OFF_MAX __LONG_MAX /* max value for an off_t */
#define __OFF_MIN __LONG_MIN /* min value for an off_t */
/* Quads and longs are the same size. Ensure they stay in sync. */
#define __UQUAD_MAX (__ULONG_MAX) /* max value for a uquad_t */
#define __QUAD_MAX (__LONG_MAX) /* max value for a quad_t */
#define __QUAD_MIN (__LONG_MIN) /* min value for a quad_t */
#define __LONG_BIT 64
#define __WORD_BIT 32
/* Minimum signal stack size. */
#define __MINSIGSTKSZ (1024 * 4)
#endif /* !_MACHINE__LIMITS_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Klaus Klein.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef __arm__
#include <arm/_stdint.h>
#else /* !__arm__ */
#ifndef _MACHINE__STDINT_H_
#define _MACHINE__STDINT_H_
#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS)
#define INT8_C(c) (c)
#define INT16_C(c) (c)
#define INT32_C(c) (c)
#define INT64_C(c) (c ## L)
#define UINT8_C(c) (c)
#define UINT16_C(c) (c)
#define UINT32_C(c) (c ## U)
#define UINT64_C(c) (c ## UL)
#define INTMAX_C(c) INT64_C(c)
#define UINTMAX_C(c) UINT64_C(c)
#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */
#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS)
/*
* ISO/IEC 9899:1999
* 7.18.2.1 Limits of exact-width integer types
*/
/* Minimum values of exact-width signed integer types. */
#define INT8_MIN (-0x7f-1)
#define INT16_MIN (-0x7fff-1)
#define INT32_MIN (-0x7fffffff-1)
#define INT64_MIN (-0x7fffffffffffffffL-1)
/* Maximum values of exact-width signed integer types. */
#define INT8_MAX 0x7f
#define INT16_MAX 0x7fff
#define INT32_MAX 0x7fffffff
#define INT64_MAX 0x7fffffffffffffffL
/* Maximum values of exact-width unsigned integer types. */
#define UINT8_MAX 0xff
#define UINT16_MAX 0xffff
#define UINT32_MAX 0xffffffffU
#define UINT64_MAX 0xffffffffffffffffUL
/*
* ISO/IEC 9899:1999
* 7.18.2.2 Limits of minimum-width integer types
*/
/* Minimum values of minimum-width signed integer types. */
#define INT_LEAST8_MIN INT8_MIN
#define INT_LEAST16_MIN INT16_MIN
#define INT_LEAST32_MIN INT32_MIN
#define INT_LEAST64_MIN INT64_MIN
/* Maximum values of minimum-width signed integer types. */
#define INT_LEAST8_MAX INT8_MAX
#define INT_LEAST16_MAX INT16_MAX
#define INT_LEAST32_MAX INT32_MAX
#define INT_LEAST64_MAX INT64_MAX
/* Maximum values of minimum-width unsigned integer types. */
#define UINT_LEAST8_MAX UINT8_MAX
#define UINT_LEAST16_MAX UINT16_MAX
#define UINT_LEAST32_MAX UINT32_MAX
#define UINT_LEAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.3 Limits of fastest minimum-width integer types
*/
/* Minimum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MIN INT32_MIN
#define INT_FAST16_MIN INT32_MIN
#define INT_FAST32_MIN INT32_MIN
#define INT_FAST64_MIN INT64_MIN
/* Maximum values of fastest minimum-width signed integer types. */
#define INT_FAST8_MAX INT32_MAX
#define INT_FAST16_MAX INT32_MAX
#define INT_FAST32_MAX INT32_MAX
#define INT_FAST64_MAX INT64_MAX
/* Maximum values of fastest minimum-width unsigned integer types. */
#define UINT_FAST8_MAX UINT32_MAX
#define UINT_FAST16_MAX UINT32_MAX
#define UINT_FAST32_MAX UINT32_MAX
#define UINT_FAST64_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.4 Limits of integer types capable of holding object pointers
*/
#define INTPTR_MIN INT64_MIN
#define INTPTR_MAX INT64_MAX
#define UINTPTR_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.2.5 Limits of greatest-width integer types
*/
#define INTMAX_MIN INT64_MIN
#define INTMAX_MAX INT64_MAX
#define UINTMAX_MAX UINT64_MAX
/*
* ISO/IEC 9899:1999
* 7.18.3 Limits of other integer types
*/
/* Limits of ptrdiff_t. */
#define PTRDIFF_MIN INT64_MIN
#define PTRDIFF_MAX INT64_MAX
/* Limits of sig_atomic_t. */
#define SIG_ATOMIC_MIN INT64_MIN
#define SIG_ATOMIC_MAX INT64_MAX
/* Limit of size_t. */
#define SIZE_MAX UINT64_MAX
/* Limits of wint_t. */
#define WINT_MIN INT32_MIN
#define WINT_MAX INT32_MAX
#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */
#endif /* !_MACHINE__STDINT_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* From: @(#)ansi.h 8.2 (Berkeley) 1/4/94
* From: @(#)types.h 8.3 (Berkeley) 1/5/94
*/
#ifdef __arm__
#include <arm/_types.h>
#else /* !__arm__ */
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#ifndef _SYS__TYPES_H_
#error do not include this header, use sys/_types.h
#endif
/*
* Standard type definitions.
*/
typedef __int32_t __clock_t; /* clock()... */
typedef __int64_t __critical_t;
#ifndef _STANDALONE
typedef double __double_t;
typedef float __float_t;
#endif
typedef __int32_t __int_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __int64_t __int_fast64_t;
typedef __int64_t __register_t;
typedef __int64_t __segsz_t; /* segment size (in pages) */
typedef __int64_t __time_t; /* time()... */
typedef __uint32_t __uint_fast8_t;
typedef __uint32_t __uint_fast16_t;
typedef __uint32_t __uint_fast32_t;
typedef __uint64_t __uint_fast64_t;
typedef __uint64_t __u_register_t;
typedef __uint64_t __vm_paddr_t;
typedef unsigned int ___wchar_t;
#define __WCHAR_MIN 0 /* min value for a wchar_t */
#define __WCHAR_MAX __UINT_MAX /* max value for a wchar_t */
#endif /* !_MACHINE__TYPES_H_ */
#endif /* !__arm__ */

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#ifdef __arm__
#include <arm/acle-compat.h>
#else /* !__arm__ */
#error Do not include this header, used only for 32-bit compatibility
#endif /* !__arm__ */

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/*-
* Copyright (c) 2002 Mitsuru IWASAKI
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/******************************************************************************
*
* Name: acpica_machdep.h - arch-specific defines, etc.
* $Revision$
*
*****************************************************************************/
#ifndef __ACPICA_MACHDEP_H__
#define __ACPICA_MACHDEP_H__
#ifdef _KERNEL
#include <machine/_bus.h>
/* Only use the reduced hardware model */
#define ACPI_REDUCED_HARDWARE 1
/* Section 5.2.10.1: global lock acquire/release functions */
int acpi_acquire_global_lock(volatile uint32_t *);
int acpi_release_global_lock(volatile uint32_t *);
void *acpi_map_table(vm_paddr_t pa, const char *sig);
void acpi_unmap_table(void *table);
vm_paddr_t acpi_find_table(const char *sig);
struct acpi_generic_address;
int acpi_map_addr(struct acpi_generic_address *, bus_space_tag_t *,
bus_space_handle_t *, bus_size_t);
extern int (*apei_nmi)(void);
#endif /* _KERNEL */
#endif /* __ACPICA_MACHDEP_H__ */

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020 The FreeBSD Foundation
*
* This software was developed by Mark Johnston under sponsorship from the
* FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_ASAN_H_
#define _MACHINE_ASAN_H_
#ifdef KASAN
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_page.h>
#include <machine/vmparam.h>
static inline vm_offset_t
kasan_md_addr_to_shad(vm_offset_t addr)
{
return (((addr - VM_MIN_KERNEL_ADDRESS) >> KASAN_SHADOW_SCALE_SHIFT) +
KASAN_MIN_ADDRESS);
}
static inline bool
kasan_md_unsupported(vm_offset_t addr)
{
return (addr < VM_MIN_KERNEL_ADDRESS || addr >= virtual_end);
}
static inline void
kasan_md_init(void)
{
}
static inline void
kasan_md_init_early(vm_offset_t bootstack, size_t size)
{
kasan_shadow_map(bootstack, size);
}
#endif /* KASAN */
#endif /* !_MACHINE_ASAN_H_ */

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/*-
* Copyright (c) 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef __arm__
#include <arm/asm.h>
#else /* !__arm__ */
#ifndef _MACHINE_ASM_H_
#define _MACHINE_ASM_H_
#undef __FBSDID
#if !defined(lint) && !defined(STRIP_FBSDID)
#define __FBSDID(s) .ident s
#else
#define __FBSDID(s) /* nothing */
#endif
#define _C_LABEL(x) x
#ifdef KDTRACE_HOOKS
#define DTRACE_NOP nop
#else
#define DTRACE_NOP
#endif
#define LENTRY(sym) \
.text; .align 2; .type sym,#function; sym: \
.cfi_startproc; BTI_C; DTRACE_NOP
#define ENTRY(sym) \
.globl sym; LENTRY(sym)
#define EENTRY(sym) \
.globl sym; .text; .align 2; .type sym,#function; sym:
#define LEND(sym) .ltorg; .cfi_endproc; .size sym, . - sym
#define END(sym) LEND(sym)
#define EEND(sym)
#define WEAK_REFERENCE(sym, alias) \
.weak alias; \
.set alias,sym
#define UINT64_C(x) (x)
#if defined(PIC)
#define PIC_SYM(x,y) x ## @ ## y
#else
#define PIC_SYM(x,y) x
#endif
/* Alias for link register x30 */
#define lr x30
/*
* Sets the trap fault handler. The exception handler will return to the
* address in the handler register on a data abort or the xzr register to
* clear the handler. The tmp parameter should be a register able to hold
* the temporary data.
*/
#define SET_FAULT_HANDLER(handler, tmp) \
ldr tmp, [x18, #PC_CURTHREAD]; /* Load curthread */ \
ldr tmp, [tmp, #TD_PCB]; /* Load the pcb */ \
str handler, [tmp, #PCB_ONFAULT] /* Set the handler */
#define ENTER_USER_ACCESS(reg, tmp) \
ldr tmp, =has_pan; /* Get the addr of has_pan */ \
ldr reg, [tmp]; /* Read it */ \
cbz reg, 997f; /* If no PAN skip */ \
.inst 0xd500409f | (0 << 8); /* Clear PAN */ \
997:
#define EXIT_USER_ACCESS(reg) \
cbz reg, 998f; /* If no PAN skip */ \
.inst 0xd500409f | (1 << 8); /* Set PAN */ \
998:
#define EXIT_USER_ACCESS_CHECK(reg, tmp) \
ldr tmp, =has_pan; /* Get the addr of has_pan */ \
ldr reg, [tmp]; /* Read it */ \
cbz reg, 999f; /* If no PAN skip */ \
.inst 0xd500409f | (1 << 8); /* Set PAN */ \
999:
/*
* Some AArch64 CPUs speculate past an eret instruction. As the user may
* control the registers at this point add a speculation barrier usable on
* all AArch64 CPUs after the eret instruction.
* TODO: ARMv8.5 adds a specific instruction for this, we could use that
* if we know we are running on something that supports it.
*/
#define ERET \
eret; \
dsb sy; \
isb
/*
* When a CPU that implements FEAT_BTI uses a BR/BLR instruction (or the
* pointer authentication variants, e.g. BLRAA) and the target location
* has the GP attribute in its page table, then the target of the BR/BLR
* needs to be a valid BTI landing pad.
*
* BTI_C should be used at the start of a function and is used in the
* ENTRY macro. It can be replaced by PACIASP or PACIBSP, however these
* also need an appropriate authenticate instruction before returning.
*
* BTI_J should be used as the target instruction when branching with a
* BR instruction within a function.
*
* When using a BR to branch to a new function, e.g. a tail call, then
* the target register should be x16 or x17 so it is compatible with
* the BRI_C instruction.
*
* As these instructions are in the hint space they are a NOP when
* the CPU doesn't implement FEAT_BTI so are safe to use.
*/
#ifdef __ARM_FEATURE_BTI_DEFAULT
#define BTI_C hint #34
#define BTI_J hint #36
#else
#define BTI_C
#define BTI_J
#endif
/*
* To help protect against ROP attacks we can use Pointer Authentication
* to sign the return address before pushing it to the stack.
*
* PAC_LR_SIGN can be used at the start of a function to sign the link
* register with the stack pointer as the modifier. As this is in the hint
* space it is safe to use on CPUs that don't implement pointer
* authentication. It can be used in place of the BTI_C instruction above as
* a valid BTI landing pad instruction.
*
* PAC_LR_AUTH is used to authenticate the link register using the stack
* pointer as the modifier. It should be used in any function that uses
* PAC_LR_SIGN. The stack pointer must be identical in each case.
*/
#ifdef __ARM_FEATURE_PAC_DEFAULT
#define PAC_LR_SIGN hint #25 /* paciasp */
#define PAC_LR_AUTH hint #29 /* autiasp */
#else
#define PAC_LR_SIGN
#define PAC_LR_AUTH
#endif
/*
* GNU_PROPERTY_AARCH64_FEATURE_1_NOTE can be used to insert a note that
* the current assembly file is built with Pointer Authentication (PAC) or
* Branch Target Identification support (BTI). As the linker requires all
* object files in an executable or library to have the GNU property
* note to emit it in the created elf file we need to add a note to all
* assembly files that support BTI so the kernel and dynamic linker can
* mark memory used by the file as guarded.
*
* The GNU_PROPERTY_AARCH64_FEATURE_1_VAL macro encodes the combination
* of PAC and BTI that have been enabled. It can be used as follows:
* GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL);
*
* To use this you need to include <sys/elf_common.h> for
* GNU_PROPERTY_AARCH64_FEATURE_1_*
*/
#if defined(__ARM_FEATURE_BTI_DEFAULT)
#if defined(__ARM_FEATURE_PAC_DEFAULT)
/* BTI, PAC */
#define GNU_PROPERTY_AARCH64_FEATURE_1_VAL \
(GNU_PROPERTY_AARCH64_FEATURE_1_BTI | GNU_PROPERTY_AARCH64_FEATURE_1_PAC)
#else
/* BTI, no PAC */
#define GNU_PROPERTY_AARCH64_FEATURE_1_VAL \
(GNU_PROPERTY_AARCH64_FEATURE_1_BTI)
#endif
#elif defined(__ARM_FEATURE_PAC_DEFAULT)
/* No BTI, PAC */
#define GNU_PROPERTY_AARCH64_FEATURE_1_VAL \
(GNU_PROPERTY_AARCH64_FEATURE_1_PAC)
#else
/* No BTI, no PAC */
#define GNU_PROPERTY_AARCH64_FEATURE_1_VAL 0
#endif
#if defined(__ARM_FEATURE_BTI_DEFAULT) || defined(__ARM_FEATURE_PAC_DEFAULT)
#define GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(x) \
.section .note.gnu.property, "a"; \
.balign 8; \
.4byte 0x4; /* sizeof(vendor) */ \
.4byte 0x10; /* sizeof(note data) */ \
.4byte (NT_GNU_PROPERTY_TYPE_0); \
.asciz "GNU"; /* vendor */ \
/* note data: */ \
.4byte (GNU_PROPERTY_AARCH64_FEATURE_1_AND); \
.4byte 0x4; /* sizeof(property) */ \
.4byte (x); /* property */ \
.4byte 0
#else
#define GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(x)
#endif
#endif /* _MACHINE_ASM_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 2013 Andrew Turner <andrew@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef __arm__
#include <arm/atomic.h>
#else /* !__arm__ */
#ifndef _MACHINE_ATOMIC_H_
#define _MACHINE_ATOMIC_H_
#define isb() __asm __volatile("isb" : : : "memory")
/*
* Options for DMB and DSB:
* oshld Outer Shareable, load
* oshst Outer Shareable, store
* osh Outer Shareable, all
* nshld Non-shareable, load
* nshst Non-shareable, store
* nsh Non-shareable, all
* ishld Inner Shareable, load
* ishst Inner Shareable, store
* ish Inner Shareable, all
* ld Full system, load
* st Full system, store
* sy Full system, all
*/
#define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory")
#define dmb(opt) __asm __volatile("dmb " __STRING(opt) : : : "memory")
#define mb() dmb(sy) /* Full system memory barrier all */
#define wmb() dmb(st) /* Full system memory barrier store */
#define rmb() dmb(ld) /* Full system memory barrier load */
#ifdef _KERNEL
extern _Bool lse_supported;
#endif
#if defined(SAN_NEEDS_INTERCEPTORS) && !defined(SAN_RUNTIME)
#include <sys/atomic_san.h>
#else
#include <sys/atomic_common.h>
#if defined(__ARM_FEATURE_ATOMICS)
#define _ATOMIC_LSE_SUPPORTED 1
#elif defined(_KERNEL)
#ifdef LSE_ATOMICS
#define _ATOMIC_LSE_SUPPORTED 1
#else
#define _ATOMIC_LSE_SUPPORTED lse_supported
#endif
#else
#define _ATOMIC_LSE_SUPPORTED 0
#endif
#define _ATOMIC_OP_PROTO(t, op, bar, flav) \
static __inline void \
atomic_##op##_##bar##t##flav(volatile uint##t##_t *p, uint##t##_t val)
#define _ATOMIC_OP_IMPL(t, w, s, op, llsc_asm_op, lse_asm_op, pre, bar, a, l) \
_ATOMIC_OP_PROTO(t, op, bar, _llsc) \
{ \
uint##t##_t tmp; \
int res; \
\
pre; \
__asm __volatile( \
"1: ld"#a"xr"#s" %"#w"0, [%2]\n" \
" "#llsc_asm_op" %"#w"0, %"#w"0, %"#w"3\n" \
" st"#l"xr"#s" %w1, %"#w"0, [%2]\n" \
" cbnz %w1, 1b\n" \
: "=&r"(tmp), "=&r"(res) \
: "r" (p), "r" (val) \
: "memory" \
); \
} \
\
_ATOMIC_OP_PROTO(t, op, bar, _lse) \
{ \
uint##t##_t tmp; \
\
pre; \
__asm __volatile( \
".arch_extension lse\n" \
"ld"#lse_asm_op#a#l#s" %"#w"2, %"#w"0, [%1]\n" \
".arch_extension nolse\n" \
: "=r" (tmp) \
: "r" (p), "r" (val) \
: "memory" \
); \
} \
\
_ATOMIC_OP_PROTO(t, op, bar, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
atomic_##op##_##bar##t##_lse(p, val); \
else \
atomic_##op##_##bar##t##_llsc(p, val); \
}
#define __ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, bar, a, l) \
_ATOMIC_OP_IMPL(8, w, b, op, llsc_asm_op, lse_asm_op, pre, \
bar, a, l) \
_ATOMIC_OP_IMPL(16, w, h, op, llsc_asm_op, lse_asm_op, pre, \
bar, a, l) \
_ATOMIC_OP_IMPL(32, w, , op, llsc_asm_op, lse_asm_op, pre, \
bar, a, l) \
_ATOMIC_OP_IMPL(64, , , op, llsc_asm_op, lse_asm_op, pre, \
bar, a, l)
#define _ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre) \
__ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, , , ) \
__ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, acq_, a, ) \
__ATOMIC_OP(op, llsc_asm_op, lse_asm_op, pre, rel_, , l)
_ATOMIC_OP(add, add, add, )
_ATOMIC_OP(clear, bic, clr, )
_ATOMIC_OP(set, orr, set, )
_ATOMIC_OP(subtract, add, add, val = -val)
#define _ATOMIC_CMPSET_PROTO(t, bar, flav) \
static __inline int \
atomic_cmpset_##bar##t##flav(volatile uint##t##_t *p, \
uint##t##_t cmpval, uint##t##_t newval)
#define _ATOMIC_FCMPSET_PROTO(t, bar, flav) \
static __inline int \
atomic_fcmpset_##bar##t##flav(volatile uint##t##_t *p, \
uint##t##_t *cmpval, uint##t##_t newval)
#define _ATOMIC_CMPSET_IMPL(t, w, s, bar, a, l) \
_ATOMIC_CMPSET_PROTO(t, bar, _llsc) \
{ \
uint##t##_t tmp; \
int res; \
\
__asm __volatile( \
"1: mov %w1, #1\n" \
" ld"#a"xr"#s" %"#w"0, [%2]\n" \
" cmp %"#w"0, %"#w"3\n" \
" b.ne 2f\n" \
" st"#l"xr"#s" %w1, %"#w"4, [%2]\n" \
" cbnz %w1, 1b\n" \
"2:" \
: "=&r"(tmp), "=&r"(res) \
: "r" (p), "r" (cmpval), "r" (newval) \
: "cc", "memory" \
); \
\
return (!res); \
} \
\
_ATOMIC_CMPSET_PROTO(t, bar, _lse) \
{ \
uint##t##_t oldval; \
int res; \
\
oldval = cmpval; \
__asm __volatile( \
".arch_extension lse\n" \
"cas"#a#l#s" %"#w"1, %"#w"4, [%3]\n" \
"cmp %"#w"1, %"#w"2\n" \
"cset %w0, eq\n" \
".arch_extension nolse\n" \
: "=r" (res), "+&r" (cmpval) \
: "r" (oldval), "r" (p), "r" (newval) \
: "cc", "memory" \
); \
\
return (res); \
} \
\
_ATOMIC_CMPSET_PROTO(t, bar, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
return (atomic_cmpset_##bar##t##_lse(p, cmpval, \
newval)); \
else \
return (atomic_cmpset_##bar##t##_llsc(p, cmpval, \
newval)); \
} \
\
_ATOMIC_FCMPSET_PROTO(t, bar, _llsc) \
{ \
uint##t##_t _cmpval, tmp; \
int res; \
\
_cmpval = *cmpval; \
__asm __volatile( \
" mov %w1, #1\n" \
" ld"#a"xr"#s" %"#w"0, [%2]\n" \
" cmp %"#w"0, %"#w"3\n" \
" b.ne 1f\n" \
" st"#l"xr"#s" %w1, %"#w"4, [%2]\n" \
"1:" \
: "=&r"(tmp), "=&r"(res) \
: "r" (p), "r" (_cmpval), "r" (newval) \
: "cc", "memory" \
); \
*cmpval = tmp; \
\
return (!res); \
} \
\
_ATOMIC_FCMPSET_PROTO(t, bar, _lse) \
{ \
uint##t##_t _cmpval, tmp; \
int res; \
\
_cmpval = tmp = *cmpval; \
__asm __volatile( \
".arch_extension lse\n" \
"cas"#a#l#s" %"#w"1, %"#w"4, [%3]\n" \
"cmp %"#w"1, %"#w"2\n" \
"cset %w0, eq\n" \
".arch_extension nolse\n" \
: "=r" (res), "+&r" (tmp) \
: "r" (_cmpval), "r" (p), "r" (newval) \
: "cc", "memory" \
); \
*cmpval = tmp; \
\
return (res); \
} \
\
_ATOMIC_FCMPSET_PROTO(t, bar, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
return (atomic_fcmpset_##bar##t##_lse(p, cmpval, \
newval)); \
else \
return (atomic_fcmpset_##bar##t##_llsc(p, cmpval, \
newval)); \
}
#define _ATOMIC_CMPSET(bar, a, l) \
_ATOMIC_CMPSET_IMPL(8, w, b, bar, a, l) \
_ATOMIC_CMPSET_IMPL(16, w, h, bar, a, l) \
_ATOMIC_CMPSET_IMPL(32, w, , bar, a, l) \
_ATOMIC_CMPSET_IMPL(64, , , bar, a, l)
#define atomic_cmpset_8 atomic_cmpset_8
#define atomic_fcmpset_8 atomic_fcmpset_8
#define atomic_cmpset_16 atomic_cmpset_16
#define atomic_fcmpset_16 atomic_fcmpset_16
_ATOMIC_CMPSET( , , )
_ATOMIC_CMPSET(acq_, a, )
_ATOMIC_CMPSET(rel_, ,l)
#define _ATOMIC_FETCHADD_PROTO(t, flav) \
static __inline uint##t##_t \
atomic_fetchadd_##t##flav(volatile uint##t##_t *p, uint##t##_t val)
#define _ATOMIC_FETCHADD_IMPL(t, w) \
_ATOMIC_FETCHADD_PROTO(t, _llsc) \
{ \
uint##t##_t ret, tmp; \
int res; \
\
__asm __volatile( \
"1: ldxr %"#w"2, [%3]\n" \
" add %"#w"0, %"#w"2, %"#w"4\n" \
" stxr %w1, %"#w"0, [%3]\n" \
" cbnz %w1, 1b\n" \
: "=&r" (tmp), "=&r" (res), "=&r" (ret) \
: "r" (p), "r" (val) \
: "memory" \
); \
\
return (ret); \
} \
\
_ATOMIC_FETCHADD_PROTO(t, _lse) \
{ \
uint##t##_t ret; \
\
__asm __volatile( \
".arch_extension lse\n" \
"ldadd %"#w"2, %"#w"0, [%1]\n" \
".arch_extension nolse\n" \
: "=r" (ret) \
: "r" (p), "r" (val) \
: "memory" \
); \
\
return (ret); \
} \
\
_ATOMIC_FETCHADD_PROTO(t, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
return (atomic_fetchadd_##t##_lse(p, val)); \
else \
return (atomic_fetchadd_##t##_llsc(p, val)); \
}
_ATOMIC_FETCHADD_IMPL(32, w)
_ATOMIC_FETCHADD_IMPL(64, )
#define _ATOMIC_SWAP_PROTO(t, flav) \
static __inline uint##t##_t \
atomic_swap_##t##flav(volatile uint##t##_t *p, uint##t##_t val)
#define _ATOMIC_READANDCLEAR_PROTO(t, flav) \
static __inline uint##t##_t \
atomic_readandclear_##t##flav(volatile uint##t##_t *p)
#define _ATOMIC_SWAP_IMPL(t, w, zreg) \
_ATOMIC_SWAP_PROTO(t, _llsc) \
{ \
uint##t##_t ret; \
int res; \
\
__asm __volatile( \
"1: ldxr %"#w"1, [%2]\n" \
" stxr %w0, %"#w"3, [%2]\n" \
" cbnz %w0, 1b\n" \
: "=&r" (res), "=&r" (ret) \
: "r" (p), "r" (val) \
: "memory" \
); \
\
return (ret); \
} \
\
_ATOMIC_SWAP_PROTO(t, _lse) \
{ \
uint##t##_t ret; \
\
__asm __volatile( \
".arch_extension lse\n" \
"swp %"#w"2, %"#w"0, [%1]\n" \
".arch_extension nolse\n" \
: "=r" (ret) \
: "r" (p), "r" (val) \
: "memory" \
); \
\
return (ret); \
} \
\
_ATOMIC_SWAP_PROTO(t, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
return (atomic_swap_##t##_lse(p, val)); \
else \
return (atomic_swap_##t##_llsc(p, val)); \
} \
\
_ATOMIC_READANDCLEAR_PROTO(t, _llsc) \
{ \
uint##t##_t ret; \
int res; \
\
__asm __volatile( \
"1: ldxr %"#w"1, [%2]\n" \
" stxr %w0, "#zreg", [%2]\n" \
" cbnz %w0, 1b\n" \
: "=&r" (res), "=&r" (ret) \
: "r" (p) \
: "memory" \
); \
\
return (ret); \
} \
\
_ATOMIC_READANDCLEAR_PROTO(t, _lse) \
{ \
return (atomic_swap_##t##_lse(p, 0)); \
} \
\
_ATOMIC_READANDCLEAR_PROTO(t, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
return (atomic_readandclear_##t##_lse(p)); \
else \
return (atomic_readandclear_##t##_llsc(p)); \
}
_ATOMIC_SWAP_IMPL(32, w, wzr)
_ATOMIC_SWAP_IMPL(64, , xzr)
#define _ATOMIC_TEST_OP_PROTO(t, op, bar, flav) \
static __inline int \
atomic_testand##op##_##bar##t##flav(volatile uint##t##_t *p, u_int val)
#define _ATOMIC_TEST_OP_IMPL(t, w, op, llsc_asm_op, lse_asm_op, bar, a) \
_ATOMIC_TEST_OP_PROTO(t, op, bar, _llsc) \
{ \
uint##t##_t mask, old, tmp; \
int res; \
\
mask = ((uint##t##_t)1) << (val & (t - 1)); \
__asm __volatile( \
"1: ld"#a"xr %"#w"2, [%3]\n" \
" "#llsc_asm_op" %"#w"0, %"#w"2, %"#w"4\n" \
" stxr %w1, %"#w"0, [%3]\n" \
" cbnz %w1, 1b\n" \
: "=&r" (tmp), "=&r" (res), "=&r" (old) \
: "r" (p), "r" (mask) \
: "memory" \
); \
\
return ((old & mask) != 0); \
} \
\
_ATOMIC_TEST_OP_PROTO(t, op, bar, _lse) \
{ \
uint##t##_t mask, old; \
\
mask = ((uint##t##_t)1) << (val & (t - 1)); \
__asm __volatile( \
".arch_extension lse\n" \
"ld"#lse_asm_op#a" %"#w"2, %"#w"0, [%1]\n" \
".arch_extension nolse\n" \
: "=r" (old) \
: "r" (p), "r" (mask) \
: "memory" \
); \
\
return ((old & mask) != 0); \
} \
\
_ATOMIC_TEST_OP_PROTO(t, op, bar, ) \
{ \
if (_ATOMIC_LSE_SUPPORTED) \
return (atomic_testand##op##_##bar##t##_lse(p, val)); \
else \
return (atomic_testand##op##_##bar##t##_llsc(p, val)); \
}
#define _ATOMIC_TEST_OP(op, llsc_asm_op, lse_asm_op) \
_ATOMIC_TEST_OP_IMPL(32, w, op, llsc_asm_op, lse_asm_op, , ) \
_ATOMIC_TEST_OP_IMPL(32, w, op, llsc_asm_op, lse_asm_op, acq_, a) \
_ATOMIC_TEST_OP_IMPL(64, , op, llsc_asm_op, lse_asm_op, , ) \
_ATOMIC_TEST_OP_IMPL(64, , op, llsc_asm_op, lse_asm_op, acq_, a)
_ATOMIC_TEST_OP(clear, bic, clr)
_ATOMIC_TEST_OP(set, orr, set)
#define _ATOMIC_LOAD_ACQ_IMPL(t, w, s) \
static __inline uint##t##_t \
atomic_load_acq_##t(volatile uint##t##_t *p) \
{ \
uint##t##_t ret; \
\
__asm __volatile( \
"ldar"#s" %"#w"0, [%1]\n" \
: "=&r" (ret) \
: "r" (p) \
: "memory"); \
\
return (ret); \
}
#define atomic_load_acq_8 atomic_load_acq_8
#define atomic_load_acq_16 atomic_load_acq_16
_ATOMIC_LOAD_ACQ_IMPL(8, w, b)
_ATOMIC_LOAD_ACQ_IMPL(16, w, h)
_ATOMIC_LOAD_ACQ_IMPL(32, w, )
_ATOMIC_LOAD_ACQ_IMPL(64, , )
#define _ATOMIC_STORE_REL_IMPL(t, w, s) \
static __inline void \
atomic_store_rel_##t(volatile uint##t##_t *p, uint##t##_t val) \
{ \
__asm __volatile( \
"stlr"#s" %"#w"0, [%1]\n" \
: \
: "r" (val), "r" (p) \
: "memory"); \
}
_ATOMIC_STORE_REL_IMPL(8, w, b)
_ATOMIC_STORE_REL_IMPL(16, w, h)
_ATOMIC_STORE_REL_IMPL(32, w, )
_ATOMIC_STORE_REL_IMPL(64, , )
#define atomic_add_char atomic_add_8
#define atomic_fcmpset_char atomic_fcmpset_8
#define atomic_clear_char atomic_clear_8
#define atomic_cmpset_char atomic_cmpset_8
#define atomic_fetchadd_char atomic_fetchadd_8
#define atomic_readandclear_char atomic_readandclear_8
#define atomic_set_char atomic_set_8
#define atomic_swap_char atomic_swap_8
#define atomic_subtract_char atomic_subtract_8
#define atomic_testandclear_char atomic_testandclear_8
#define atomic_testandset_char atomic_testandset_8
#define atomic_add_acq_char atomic_add_acq_8
#define atomic_fcmpset_acq_char atomic_fcmpset_acq_8
#define atomic_clear_acq_char atomic_clear_acq_8
#define atomic_cmpset_acq_char atomic_cmpset_acq_8
#define atomic_load_acq_char atomic_load_acq_8
#define atomic_set_acq_char atomic_set_acq_8
#define atomic_subtract_acq_char atomic_subtract_acq_8
#define atomic_testandset_acq_char atomic_testandset_acq_8
#define atomic_add_rel_char atomic_add_rel_8
#define atomic_fcmpset_rel_char atomic_fcmpset_rel_8
#define atomic_clear_rel_char atomic_clear_rel_8
#define atomic_cmpset_rel_char atomic_cmpset_rel_8
#define atomic_set_rel_char atomic_set_rel_8
#define atomic_subtract_rel_char atomic_subtract_rel_8
#define atomic_store_rel_char atomic_store_rel_8
#define atomic_add_short atomic_add_16
#define atomic_fcmpset_short atomic_fcmpset_16
#define atomic_clear_short atomic_clear_16
#define atomic_cmpset_short atomic_cmpset_16
#define atomic_fetchadd_short atomic_fetchadd_16
#define atomic_readandclear_short atomic_readandclear_16
#define atomic_set_short atomic_set_16
#define atomic_swap_short atomic_swap_16
#define atomic_subtract_short atomic_subtract_16
#define atomic_testandclear_short atomic_testandclear_16
#define atomic_testandset_short atomic_testandset_16
#define atomic_add_acq_short atomic_add_acq_16
#define atomic_fcmpset_acq_short atomic_fcmpset_acq_16
#define atomic_clear_acq_short atomic_clear_acq_16
#define atomic_cmpset_acq_short atomic_cmpset_acq_16
#define atomic_load_acq_short atomic_load_acq_16
#define atomic_set_acq_short atomic_set_acq_16
#define atomic_subtract_acq_short atomic_subtract_acq_16
#define atomic_testandset_acq_short atomic_testandset_acq_16
#define atomic_add_rel_short atomic_add_rel_16
#define atomic_fcmpset_rel_short atomic_fcmpset_rel_16
#define atomic_clear_rel_short atomic_clear_rel_16
#define atomic_cmpset_rel_short atomic_cmpset_rel_16
#define atomic_set_rel_short atomic_set_rel_16
#define atomic_subtract_rel_short atomic_subtract_rel_16
#define atomic_store_rel_short atomic_store_rel_16
#define atomic_add_int atomic_add_32
#define atomic_fcmpset_int atomic_fcmpset_32
#define atomic_clear_int atomic_clear_32
#define atomic_cmpset_int atomic_cmpset_32
#define atomic_fetchadd_int atomic_fetchadd_32
#define atomic_readandclear_int atomic_readandclear_32
#define atomic_set_int atomic_set_32
#define atomic_swap_int atomic_swap_32
#define atomic_subtract_int atomic_subtract_32
#define atomic_testandclear_int atomic_testandclear_32
#define atomic_testandset_int atomic_testandset_32
#define atomic_add_acq_int atomic_add_acq_32
#define atomic_fcmpset_acq_int atomic_fcmpset_acq_32
#define atomic_clear_acq_int atomic_clear_acq_32
#define atomic_cmpset_acq_int atomic_cmpset_acq_32
#define atomic_load_acq_int atomic_load_acq_32
#define atomic_set_acq_int atomic_set_acq_32
#define atomic_subtract_acq_int atomic_subtract_acq_32
#define atomic_testandset_acq_int atomic_testandset_acq_32
#define atomic_add_rel_int atomic_add_rel_32
#define atomic_fcmpset_rel_int atomic_fcmpset_rel_32
#define atomic_clear_rel_int atomic_clear_rel_32
#define atomic_cmpset_rel_int atomic_cmpset_rel_32
#define atomic_set_rel_int atomic_set_rel_32
#define atomic_subtract_rel_int atomic_subtract_rel_32
#define atomic_store_rel_int atomic_store_rel_32
#define atomic_add_long atomic_add_64
#define atomic_fcmpset_long atomic_fcmpset_64
#define atomic_clear_long atomic_clear_64
#define atomic_cmpset_long atomic_cmpset_64
#define atomic_fetchadd_long atomic_fetchadd_64
#define atomic_readandclear_long atomic_readandclear_64
#define atomic_set_long atomic_set_64
#define atomic_swap_long atomic_swap_64
#define atomic_subtract_long atomic_subtract_64
#define atomic_testandclear_long atomic_testandclear_64
#define atomic_testandset_long atomic_testandset_64
#define atomic_add_ptr atomic_add_64
#define atomic_fcmpset_ptr atomic_fcmpset_64
#define atomic_clear_ptr atomic_clear_64
#define atomic_cmpset_ptr atomic_cmpset_64
#define atomic_fetchadd_ptr atomic_fetchadd_64
#define atomic_readandclear_ptr atomic_readandclear_64
#define atomic_set_ptr atomic_set_64
#define atomic_swap_ptr atomic_swap_64
#define atomic_subtract_ptr atomic_subtract_64
#define atomic_add_acq_long atomic_add_acq_64
#define atomic_fcmpset_acq_long atomic_fcmpset_acq_64
#define atomic_clear_acq_long atomic_clear_acq_64
#define atomic_cmpset_acq_long atomic_cmpset_acq_64
#define atomic_load_acq_long atomic_load_acq_64
#define atomic_set_acq_long atomic_set_acq_64
#define atomic_subtract_acq_long atomic_subtract_acq_64
#define atomic_testandset_acq_long atomic_testandset_acq_64
#define atomic_add_acq_ptr atomic_add_acq_64
#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_64
#define atomic_clear_acq_ptr atomic_clear_acq_64
#define atomic_cmpset_acq_ptr atomic_cmpset_acq_64
#define atomic_load_acq_ptr atomic_load_acq_64
#define atomic_set_acq_ptr atomic_set_acq_64
#define atomic_subtract_acq_ptr atomic_subtract_acq_64
#define atomic_add_rel_long atomic_add_rel_64
#define atomic_fcmpset_rel_long atomic_fcmpset_rel_64
#define atomic_clear_rel_long atomic_clear_rel_64
#define atomic_cmpset_rel_long atomic_cmpset_rel_64
#define atomic_set_rel_long atomic_set_rel_64
#define atomic_subtract_rel_long atomic_subtract_rel_64
#define atomic_store_rel_long atomic_store_rel_64
#define atomic_add_rel_ptr atomic_add_rel_64
#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_64
#define atomic_clear_rel_ptr atomic_clear_rel_64
#define atomic_cmpset_rel_ptr atomic_cmpset_rel_64
#define atomic_set_rel_ptr atomic_set_rel_64
#define atomic_subtract_rel_ptr atomic_subtract_rel_64
#define atomic_store_rel_ptr atomic_store_rel_64
static __inline void
atomic_thread_fence_acq(void)
{
dmb(ld);
}
static __inline void
atomic_thread_fence_rel(void)
{
dmb(sy);
}
static __inline void
atomic_thread_fence_acq_rel(void)
{
dmb(sy);
}
static __inline void
atomic_thread_fence_seq_cst(void)
{
dmb(sy);
}
#endif /* KCSAN && !KCSAN_RUNTIME */
#endif /* _MACHINE_ATOMIC_H_ */
#endif /* !__arm__ */

527
lib/libc/include/aarch64-freebsd-none/machine/bus.h vendored Normal file
View File

@ -0,0 +1,527 @@
/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
* NASA Ames Research Center.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christopher G. Demetriou
* for the NetBSD Project.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* From: sys/arm/include/bus.h
*/
#ifdef __arm__
#include <arm/bus.h>
#else /* !__arm__ */
#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_
#include <machine/_bus.h>
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFFUL
#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFFUL
#define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFUL
#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFFUL
#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFFUL
#define BUS_SPACE_MAXSIZE_40BIT 0xFFFFFFFFFFUL
#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFUL
#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFFUL
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_LINEAR 0x02
#define BUS_SPACE_MAP_PREFETCHABLE 0x04
#define BUS_SPACE_MAP_NONPOSTED 0x08
#define BUS_SPACE_UNRESTRICTED (~0)
#define BUS_SPACE_BARRIER_READ 0x01
#define BUS_SPACE_BARRIER_WRITE 0x02
struct bus_space {
/* cookie */
void *bs_cookie;
/* mapping/unmapping */
int (*bs_map) (void *, bus_addr_t, bus_size_t,
int, bus_space_handle_t *);
void (*bs_unmap) (void *, bus_space_handle_t, bus_size_t);
int (*bs_subregion) (void *, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
/* allocation/deallocation */
int (*bs_alloc) (void *, bus_addr_t, bus_addr_t,
bus_size_t, bus_size_t, bus_size_t, int,
bus_addr_t *, bus_space_handle_t *);
void (*bs_free) (void *, bus_space_handle_t,
bus_size_t);
/* get kernel virtual address */
/* barrier */
void (*bs_barrier) (void *, bus_space_handle_t,
bus_size_t, bus_size_t, int);
/* read single */
u_int8_t (*bs_r_1) (void *, bus_space_handle_t, bus_size_t);
u_int16_t (*bs_r_2) (void *, bus_space_handle_t, bus_size_t);
u_int32_t (*bs_r_4) (void *, bus_space_handle_t, bus_size_t);
u_int64_t (*bs_r_8) (void *, bus_space_handle_t, bus_size_t);
/* read multiple */
void (*bs_rm_1) (void *, bus_space_handle_t, bus_size_t,
u_int8_t *, bus_size_t);
void (*bs_rm_2) (void *, bus_space_handle_t, bus_size_t,
u_int16_t *, bus_size_t);
void (*bs_rm_4) (void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
void (*bs_rm_8) (void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
/* read region */
void (*bs_rr_1) (void *, bus_space_handle_t,
bus_size_t, u_int8_t *, bus_size_t);
void (*bs_rr_2) (void *, bus_space_handle_t,
bus_size_t, u_int16_t *, bus_size_t);
void (*bs_rr_4) (void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
void (*bs_rr_8) (void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
/* write single */
void (*bs_w_1) (void *, bus_space_handle_t,
bus_size_t, u_int8_t);
void (*bs_w_2) (void *, bus_space_handle_t,
bus_size_t, u_int16_t);
void (*bs_w_4) (void *, bus_space_handle_t,
bus_size_t, u_int32_t);
void (*bs_w_8) (void *, bus_space_handle_t,
bus_size_t, u_int64_t);
/* write multiple */
void (*bs_wm_1) (void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
void (*bs_wm_2) (void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
void (*bs_wm_4) (void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
void (*bs_wm_8) (void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
/* write region */
void (*bs_wr_1) (void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
void (*bs_wr_2) (void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
void (*bs_wr_4) (void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
void (*bs_wr_8) (void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
/* set multiple */
void (*bs_sm_1) (void *, bus_space_handle_t,
bus_size_t, u_int8_t, bus_size_t);
void (*bs_sm_2) (void *, bus_space_handle_t,
bus_size_t, u_int16_t, bus_size_t);
void (*bs_sm_4) (void *, bus_space_handle_t,
bus_size_t, u_int32_t, bus_size_t);
void (*bs_sm_8) (void *, bus_space_handle_t,
bus_size_t, u_int64_t, bus_size_t);
/* set region */
void (*bs_sr_1) (void *, bus_space_handle_t,
bus_size_t, u_int8_t, bus_size_t);
void (*bs_sr_2) (void *, bus_space_handle_t,
bus_size_t, u_int16_t, bus_size_t);
void (*bs_sr_4) (void *, bus_space_handle_t,
bus_size_t, u_int32_t, bus_size_t);
void (*bs_sr_8) (void *, bus_space_handle_t,
bus_size_t, u_int64_t, bus_size_t);
/* copy */
void (*bs_c_1) (void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_2) (void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_4) (void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t,
bus_space_handle_t, bus_size_t, bus_size_t);
/* read single stream */
u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t);
u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t);
u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t);
u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t);
/* read multiple stream */
void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t,
u_int8_t *, bus_size_t);
void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t,
u_int16_t *, bus_size_t);
void (*bs_rm_4_s) (void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
void (*bs_rm_8_s) (void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
/* read region stream */
void (*bs_rr_1_s) (void *, bus_space_handle_t,
bus_size_t, u_int8_t *, bus_size_t);
void (*bs_rr_2_s) (void *, bus_space_handle_t,
bus_size_t, u_int16_t *, bus_size_t);
void (*bs_rr_4_s) (void *, bus_space_handle_t,
bus_size_t, u_int32_t *, bus_size_t);
void (*bs_rr_8_s) (void *, bus_space_handle_t,
bus_size_t, u_int64_t *, bus_size_t);
/* write single stream */
void (*bs_w_1_s) (void *, bus_space_handle_t,
bus_size_t, u_int8_t);
void (*bs_w_2_s) (void *, bus_space_handle_t,
bus_size_t, u_int16_t);
void (*bs_w_4_s) (void *, bus_space_handle_t,
bus_size_t, u_int32_t);
void (*bs_w_8_s) (void *, bus_space_handle_t,
bus_size_t, u_int64_t);
/* write multiple stream */
void (*bs_wm_1_s) (void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
void (*bs_wm_2_s) (void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
void (*bs_wm_4_s) (void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
void (*bs_wm_8_s) (void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
/* write region stream */
void (*bs_wr_1_s) (void *, bus_space_handle_t,
bus_size_t, const u_int8_t *, bus_size_t);
void (*bs_wr_2_s) (void *, bus_space_handle_t,
bus_size_t, const u_int16_t *, bus_size_t);
void (*bs_wr_4_s) (void *, bus_space_handle_t,
bus_size_t, const u_int32_t *, bus_size_t);
void (*bs_wr_8_s) (void *, bus_space_handle_t,
bus_size_t, const u_int64_t *, bus_size_t);
/* peek */
int (*bs_peek_1)(void *, bus_space_handle_t,
bus_size_t , uint8_t *);
int (*bs_peek_2)(void *, bus_space_handle_t,
bus_size_t , uint16_t *);
int (*bs_peek_4)(void *, bus_space_handle_t,
bus_size_t , uint32_t *);
int (*bs_peek_8)(void *, bus_space_handle_t,
bus_size_t , uint64_t *);
/* poke */
int (*bs_poke_1)(void *, bus_space_handle_t,
bus_size_t, uint8_t);
int (*bs_poke_2)(void *, bus_space_handle_t,
bus_size_t, uint16_t);
int (*bs_poke_4)(void *, bus_space_handle_t,
bus_size_t, uint32_t);
int (*bs_poke_8)(void *, bus_space_handle_t,
bus_size_t, uint64_t);
};
#if defined(SAN_NEEDS_INTERCEPTORS) && !defined(SAN_RUNTIME)
#include <sys/bus_san.h>
#else
/*
* Utility macros; INTERNAL USE ONLY.
*/
#define __bs_c(a,b) __CONCAT(a,b)
#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size)
#define __bs_rs(sz, t, h, o) \
(*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o)
#define __bs_ws(sz, t, h, o, v) \
(*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v)
#define __bs_nonsingle(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c)
#define __bs_set(type, sz, t, h, o, v, c) \
(*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c)
#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \
(*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt)
#define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s)
#define __bs_rs_s(sz, t, h, o) \
(*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o)
#define __bs_ws_s(sz, t, h, o, v) \
(*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v)
#define __bs_peek(sz, t, h, o, vp) \
(*(t)->__bs_opname(peek, sz))((t)->bs_cookie, h, o, vp)
#define __bs_poke(sz, t, h, o, v) \
(*(t)->__bs_opname(poke, sz))((t)->bs_cookie, h, o, v)
#define __bs_nonsingle_s(type, sz, t, h, o, a, c) \
(*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c)
/*
* Mapping and unmapping operations.
*/
#define bus_space_map(t, a, s, c, hp) \
(*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp))
#define bus_space_unmap(t, h, s) \
(*(t)->bs_unmap)((t)->bs_cookie, (h), (s))
#define bus_space_subregion(t, h, o, s, hp) \
(*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp))
/*
* Allocation and deallocation operations.
*/
#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \
(*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \
(c), (ap), (hp))
#define bus_space_free(t, h, s) \
(*(t)->bs_free)((t)->bs_cookie, (h), (s))
/*
* Bus barrier operations.
*/
#define bus_space_barrier(t, h, o, l, f) \
(*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f))
/*
* Bus read (single) operations.
*/
#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o))
#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o))
#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o))
#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o))
#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o))
#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o))
#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o))
#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,(t), (h), (o))
/*
* Bus read multiple operations.
*/
#define bus_space_read_multi_1(t, h, o, a, c) \
__bs_nonsingle(rm,1,(t),(h),(o),(a),(c))
#define bus_space_read_multi_2(t, h, o, a, c) \
__bs_nonsingle(rm,2,(t),(h),(o),(a),(c))
#define bus_space_read_multi_4(t, h, o, a, c) \
__bs_nonsingle(rm,4,(t),(h),(o),(a),(c))
#define bus_space_read_multi_8(t, h, o, a, c) \
__bs_nonsingle(rm,8,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c))
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c))
/*
* Bus read region operations.
*/
#define bus_space_read_region_1(t, h, o, a, c) \
__bs_nonsingle(rr,1,(t),(h),(o),(a),(c))
#define bus_space_read_region_2(t, h, o, a, c) \
__bs_nonsingle(rr,2,(t),(h),(o),(a),(c))
#define bus_space_read_region_4(t, h, o, a, c) \
__bs_nonsingle(rr,4,(t),(h),(o),(a),(c))
#define bus_space_read_region_8(t, h, o, a, c) \
__bs_nonsingle(rr,8,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c))
#define bus_space_read_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c))
/*
* Bus write (single) operations.
*/
#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v))
#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v))
#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v))
#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v))
#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v))
#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v))
#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v))
#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v))
/*
* Bus write multiple operations.
*/
#define bus_space_write_multi_1(t, h, o, a, c) \
__bs_nonsingle(wm,1,(t),(h),(o),(a),(c))
#define bus_space_write_multi_2(t, h, o, a, c) \
__bs_nonsingle(wm,2,(t),(h),(o),(a),(c))
#define bus_space_write_multi_4(t, h, o, a, c) \
__bs_nonsingle(wm,4,(t),(h),(o),(a),(c))
#define bus_space_write_multi_8(t, h, o, a, c) \
__bs_nonsingle(wm,8,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c))
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c))
/*
* Bus write region operations.
*/
#define bus_space_write_region_1(t, h, o, a, c) \
__bs_nonsingle(wr,1,(t),(h),(o),(a),(c))
#define bus_space_write_region_2(t, h, o, a, c) \
__bs_nonsingle(wr,2,(t),(h),(o),(a),(c))
#define bus_space_write_region_4(t, h, o, a, c) \
__bs_nonsingle(wr,4,(t),(h),(o),(a),(c))
#define bus_space_write_region_8(t, h, o, a, c) \
__bs_nonsingle(wr,8,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_1(t, h, o, a, c) \
__bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_2(t, h, o, a, c) \
__bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_4(t, h, o, a, c) \
__bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c))
#define bus_space_write_region_stream_8(t, h, o, a, c) \
__bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c))
/*
* Set multiple operations.
*/
#define bus_space_set_multi_1(t, h, o, v, c) \
__bs_set(sm,1,(t),(h),(o),(v),(c))
#define bus_space_set_multi_2(t, h, o, v, c) \
__bs_set(sm,2,(t),(h),(o),(v),(c))
#define bus_space_set_multi_4(t, h, o, v, c) \
__bs_set(sm,4,(t),(h),(o),(v),(c))
#define bus_space_set_multi_8(t, h, o, v, c) \
__bs_set(sm,8,(t),(h),(o),(v),(c))
#define bus_space_set_multi_stream_1(t, h, o, v, c) \
bus_space_set_multi_1((t), (h), (o), (v), (c))
#define bus_space_set_multi_stream_2(t, h, o, v, c) \
bus_space_set_multi_2((t), (h), (o), (v), (c))
#define bus_space_set_multi_stream_4(t, h, o, v, c) \
bus_space_set_multi_4((t), (h), (o), (v), (c))
#define bus_space_set_multi_stream_8(t, h, o, v, c) \
bus_space_set_multi_8((t), (h), (o), (v), (c))
/*
* Set region operations.
*/
#define bus_space_set_region_1(t, h, o, v, c) \
__bs_set(sr,1,(t),(h),(o),(v),(c))
#define bus_space_set_region_2(t, h, o, v, c) \
__bs_set(sr,2,(t),(h),(o),(v),(c))
#define bus_space_set_region_4(t, h, o, v, c) \
__bs_set(sr,4,(t),(h),(o),(v),(c))
#define bus_space_set_region_8(t, h, o, v, c) \
__bs_set(sr,8,(t),(h),(o),(v),(c))
#define bus_space_set_region_stream_1(t, h, o, v, c) \
bus_space_set_region_1((t), (h), (o), (v), (c))
#define bus_space_set_region_stream_2(t, h, o, v, c) \
bus_space_set_region_2((t), (h), (o), (v), (c))
#define bus_space_set_region_stream_4(t, h, o, v, c) \
bus_space_set_region_4((t), (h), (o), (v), (c))
#define bus_space_set_region_stream_8(t, h, o, v, c) \
bus_space_set_region_8((t), (h), (o), (v), (c))
/*
* Copy operations.
*/
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
__bs_copy(1, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
__bs_copy(2, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
__bs_copy(4, t, h1, o1, h2, o2, c)
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
__bs_copy(8, t, h1, o1, h2, o2, c)
/*
* Poke (checked write) operations.
*/
#define bus_space_poke_1(t, h, o, v) __bs_poke(1, (t), (h), (o), (v))
#define bus_space_poke_2(t, h, o, v) __bs_poke(2, (t), (h), (o), (v))
#define bus_space_poke_4(t, h, o, v) __bs_poke(4, (t), (h), (o), (v))
#define bus_space_poke_8(t, h, o, v) __bs_poke(8, (t), (h), (o), (v))
/*
* Peek (checked read) operations.
*/
#define bus_space_peek_1(t, h, o, vp) __bs_peek(1, (t), (h), (o), (vp))
#define bus_space_peek_2(t, h, o, vp) __bs_peek(2, (t), (h), (o), (vp))
#define bus_space_peek_4(t, h, o, vp) __bs_peek(4, (t), (h), (o), (vp))
#define bus_space_peek_8(t, h, o, vp) __bs_peek(8, (t), (h), (o), (vp))
#endif /* !SAN_NEEDS_INTERCEPTORS */
#include <machine/bus_dma.h>
#endif /* _MACHINE_BUS_H_ */
#endif /* !__arm__ */

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#ifndef _MACHINE_BUS_DMA_H_
#define _MACHINE_BUS_DMA_H_
#define WANT_INLINE_DMAMAP
#include <sys/bus_dma.h>
#include <machine/bus_dma_impl.h>
/*
* Is DMA address 1:1 mapping of physical address
*/
static inline bool
bus_dma_id_mapped(bus_dma_tag_t dmat, vm_paddr_t buf, bus_size_t buflen)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->id_mapped(dmat, buf, buflen));
}
/*
* Allocate a handle for mapping from kva/uva/physical
* address space into bus device space.
*/
static inline int
bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->map_create(dmat, flags, mapp));
}
/*
* Destroy a handle for mapping from kva/uva/physical
* address space into bus device space.
*/
static inline int
bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->map_destroy(dmat, map));
}
/*
* Allocate a piece of memory that can be efficiently mapped into
* bus device space based on the constraints listed in the dma tag.
* A dmamap to for use with dmamap_load is also allocated.
*/
static inline int
bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
bus_dmamap_t *mapp)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->mem_alloc(dmat, vaddr, flags, mapp));
}
/*
* Free a piece of memory and it's allociated dmamap, that was allocated
* via bus_dmamem_alloc. Make the same choice for free/contigfree.
*/
static inline void
bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
tc->impl->mem_free(dmat, vaddr, map);
}
/*
* Release the mapping held by map.
*/
static inline void
bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
tc->impl->map_unload(dmat, map);
}
static inline void
bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
tc->impl->map_sync(dmat, map, op);
}
static inline int
_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map, vm_paddr_t buf,
bus_size_t buflen, int flags, bus_dma_segment_t *segs, int *segp)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->load_phys(dmat, map, buf, buflen, flags, segs,
segp));
}
static inline int
_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map, struct vm_page **ma,
bus_size_t tlen, int ma_offs, int flags, bus_dma_segment_t *segs,
int *segp)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->load_ma(dmat, map, ma, tlen, ma_offs, flags,
segs, segp));
}
static inline int
_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf,
bus_size_t buflen, struct pmap *pmap, int flags, bus_dma_segment_t *segs,
int *segp)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->load_buffer(dmat, map, buf, buflen, pmap, flags, segs,
segp));
}
static inline void
_bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map,
struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
tc->impl->map_waitok(dmat, map, mem, callback, callback_arg);
}
static inline bus_dma_segment_t *
_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map,
bus_dma_segment_t *segs, int nsegs, int error)
{
struct bus_dma_tag_common *tc;
tc = (struct bus_dma_tag_common *)dmat;
return (tc->impl->map_complete(dmat, map, segs, nsegs, error));
}
#endif /* !_MACHINE_BUS_DMA_H_ */

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/*-
* Copyright (c) 2013 The FreeBSD Foundation
*
* This software was developed by Konstantin Belousov <kib@FreeBSD.org>
* under sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_BUS_DMA_IMPL_H_
#define _MACHINE_BUS_DMA_IMPL_H_
struct bus_dma_tag_common {
struct bus_dma_impl *impl;
struct bus_dma_tag_common *parent;
bus_size_t alignment;
bus_addr_t boundary;
bus_addr_t lowaddr;
bus_addr_t highaddr;
bus_dma_filter_t *filter;
void *filterarg;
bus_size_t maxsize;
u_int nsegments;
bus_size_t maxsegsz;
int flags;
bus_dma_lock_t *lockfunc;
void *lockfuncarg;
int ref_count;
int domain;
};
struct bus_dma_impl {
int (*tag_create)(bus_dma_tag_t parent,
bus_size_t alignment, bus_addr_t boundary, bus_addr_t lowaddr,
bus_addr_t highaddr, bus_dma_filter_t *filter,
void *filterarg, bus_size_t maxsize, int nsegments,
bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
void *lockfuncarg, bus_dma_tag_t *dmat);
int (*tag_destroy)(bus_dma_tag_t dmat);
int (*tag_set_domain)(bus_dma_tag_t);
bool (*id_mapped)(bus_dma_tag_t, vm_paddr_t, bus_size_t);
int (*map_create)(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp);
int (*map_destroy)(bus_dma_tag_t dmat, bus_dmamap_t map);
int (*mem_alloc)(bus_dma_tag_t dmat, void** vaddr, int flags,
bus_dmamap_t *mapp);
void (*mem_free)(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map);
int (*load_ma)(bus_dma_tag_t dmat, bus_dmamap_t map,
struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags,
bus_dma_segment_t *segs, int *segp);
int (*load_phys)(bus_dma_tag_t dmat, bus_dmamap_t map,
vm_paddr_t buf, bus_size_t buflen, int flags,
bus_dma_segment_t *segs, int *segp);
int (*load_buffer)(bus_dma_tag_t dmat, bus_dmamap_t map,
void *buf, bus_size_t buflen, struct pmap *pmap, int flags,
bus_dma_segment_t *segs, int *segp);
void (*map_waitok)(bus_dma_tag_t dmat, bus_dmamap_t map,
struct memdesc *mem, bus_dmamap_callback_t *callback,
void *callback_arg);
bus_dma_segment_t *(*map_complete)(bus_dma_tag_t dmat, bus_dmamap_t map,
bus_dma_segment_t *segs, int nsegs, int error);
void (*map_unload)(bus_dma_tag_t dmat, bus_dmamap_t map);
void (*map_sync)(bus_dma_tag_t dmat, bus_dmamap_t map,
bus_dmasync_op_t op);
};
int bus_dma_run_filter(struct bus_dma_tag_common *dmat, bus_addr_t paddr);
int common_bus_dma_tag_create(struct bus_dma_tag_common *parent,
bus_size_t alignment,
bus_addr_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr,
bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize,
int nsegments, bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc,
void *lockfuncarg, size_t sz, void **dmat);
extern struct bus_dma_impl bus_dma_bounce_impl;
#endif

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/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2021 ARM Ltd
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_CMN600_REG_H_
#define _MACHINE_CMN600_REG_H_
#define CMN600_COUNTERS_N 8
#define CMN600_UNIT_MAX 4
#define CMN600_PMU_DEFAULT_UNITS_N 2
#define CMN600_COMMON_PMU_EVENT_SEL 0x2000 /* rw */
#define CMN600_COMMON_PMU_EVENT_SEL_OCC_SHIFT 32
#define CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK (0x7UL << 32)
struct cmn600_pmc {
void *arg;
int domain;
};
int cmn600_pmc_nunits(void);
int cmn600_pmc_getunit(int unit, void **arg, int *domain);
int cmn600_pmu_intr_cb(void *arg, int (*handler)(struct trapframe *tf,
int unit, int i));
int pmu_cmn600_alloc_localpmc(void *arg, int nodeid, int node_type,
int *local_counter);
int pmu_cmn600_free_localpmc(void *arg, int nodeid, int node_type,
int local_counter);
int pmu_cmn600_rev(void *arg);
uint32_t pmu_cmn600_rd4(void *arg, int nodeid, int node_type, off_t reg);
int pmu_cmn600_wr4(void *arg, int nodeid, int node_type, off_t reg,
uint32_t val);
uint64_t pmu_cmn600_rd8(void *arg, int nodeid, int node_type, off_t reg);
int pmu_cmn600_wr8(void *arg, int nodeid, int node_type, off_t reg,
uint64_t val);
int pmu_cmn600_set8(void *arg, int nodeid, int node_type, off_t reg,
uint64_t val);
int pmu_cmn600_clr8(void *arg, int nodeid, int node_type, off_t reg,
uint64_t val);
int pmu_cmn600_md8(void *arg, int nodeid, int node_type, off_t reg,
uint64_t mask, uint64_t val);
/* Configuration master registers */
#define POR_CFGM_NODE_INFO 0x0000 /* ro */
#define POR_CFGM_NODE_INFO_LOGICAL_ID_MASK 0xffff00000000UL
#define POR_CFGM_NODE_INFO_LOGICAL_ID_SHIFT 32
#define POR_CFGM_NODE_INFO_NODE_ID_MASK 0xffff0000
#define POR_CFGM_NODE_INFO_NODE_ID_SHIFT 16
#define POR_CFGM_NODE_INFO_NODE_TYPE_MASK 0xffff
#define POR_CFGM_NODE_INFO_NODE_TYPE_SHIFT 0
#define NODE_ID_SUB_MASK 0x3
#define NODE_ID_SUB_SHIFT 0
#define NODE_ID_PORT_MASK 0x4
#define NODE_ID_PORT_SHIFT 2
#define NODE_ID_X2B_MASK (0x3 << 3)
#define NODE_ID_X2B_SHIFT 3
#define NODE_ID_Y2B_MASK (0x3 << 5)
#define NODE_ID_Y2B_SHIFT 5
#define NODE_ID_X3B_MASK (0x7 << 3)
#define NODE_ID_X3B_SHIFT 3
#define NODE_ID_Y3B_MASK (0x7 << 6)
#define NODE_ID_Y3B_SHIFT 6
#define NODE_TYPE_INVALID 0x000
#define NODE_TYPE_DVM 0x001
#define NODE_TYPE_CFG 0x002
#define NODE_TYPE_DTC 0x003
#define NODE_TYPE_HN_I 0x004
#define NODE_TYPE_HN_F 0x005
#define NODE_TYPE_XP 0x006
#define NODE_TYPE_SBSX 0x007
#define NODE_TYPE_RN_I 0x00A
#define NODE_TYPE_RN_D 0x00D
#define NODE_TYPE_RN_SAM 0x00F
#define NODE_TYPE_CXRA 0x100
#define NODE_TYPE_CXHA 0x101
#define NODE_TYPE_CXLA 0x102
#define POR_CFGM_PERIPH_ID_0_PERIPH_ID_1 0x0008 /* ro */
#define POR_CFGM_PERIPH_ID_2_PERIPH_ID_3 0x0010 /* ro */
#define POR_CFGM_PERIPH_ID_2_REV_SHIFT 4
#define POR_CFGM_PERIPH_ID_2_REV_MASK 0xf0
#define POR_CFGM_PERIPH_ID_2_REV_R1P0 0
#define POR_CFGM_PERIPH_ID_2_REV_R1P1 1
#define POR_CFGM_PERIPH_ID_2_REV_R1P2 2
#define POR_CFGM_PERIPH_ID_2_REV_R1P3 3
#define POR_CFGM_PERIPH_ID_2_REV_R2P0 4
#define POR_CFGM_PERIPH_ID_4_PERIPH_ID_5 0x0018 /* ro */
#define POR_CFGM_PERIPH_ID_6_PERIPH_ID_7 0x0020 /* ro */
#define POR_CFGM_PERIPH_ID_32(x) (0x0008 + ((x) * 4)) /* ro 32 */
#define POR_CFGM_COMPONENT_ID_0_COMPONENT_ID_1 0x0028 /* ro */
#define POR_CFGM_COMPONENT_ID_2_COMPONENT_ID_3 0x0030 /* ro */
#define POR_CFGM_CHILD_INFO 0x0080 /* ro */
#define POR_CFGM_CHILD_INFO_CHILD_PTR_OFFSET_MASK 0xffff0000
#define POR_CFGM_CHILD_INFO_CHILD_PTR_OFFSET_SHIFT 16
#define POR_CFGM_CHILD_INFO_CHILD_COUNT_MASK 0x0000ffff
#define POR_CFGM_CHILD_INFO_CHILD_COUNT_SHIFT 0
#define POR_CFGM_SECURE_ACCESS 0x0980 /* rw */
#define POR_CFGM_ERRGSR0 0x3000 /* ro */
#define POR_CFGM_ERRGSR1 0x3008 /* ro */
#define POR_CFGM_ERRGSR2 0x3010 /* ro */
#define POR_CFGM_ERRGSR3 0x3018 /* ro */
#define POR_CFGM_ERRGSR4 0x3020 /* ro */
#define POR_CFGM_ERRGSR5 0x3080 /* ro */
#define POR_CFGM_ERRGSR6 0x3088 /* ro */
#define POR_CFGM_ERRGSR7 0x3090 /* ro */
#define POR_CFGM_ERRGSR8 0x3098 /* ro */
#define POR_CFGM_ERRGSR9 0x30a0 /* ro */
#define POR_CFGM_ERRGSR(x) (0x3000 + ((x) * 8)) /* ro */
#define POR_CFGM_ERRGSR0_ns 0x3100 /* ro */
#define POR_CFGM_ERRGSR1_ns 0x3108 /* ro */
#define POR_CFGM_ERRGSR2_ns 0x3110 /* ro */
#define POR_CFGM_ERRGSR3_ns 0x3118 /* ro */
#define POR_CFGM_ERRGSR4_ns 0x3120 /* ro */
#define POR_CFGM_ERRGSR5_ns 0x3180 /* ro */
#define POR_CFGM_ERRGSR6_ns 0x3188 /* ro */
#define POR_CFGM_ERRGSR7_ns 0x3190 /* ro */
#define POR_CFGM_ERRGSR8_ns 0x3198 /* ro */
#define POR_CFGM_ERRGSR9_ns 0x31a0 /* ro */
#define POR_CFGM_ERRGSR_ns(x) (0x3100 + ((x) * 8)) /* ro */
#define POR_CFGM_ERRDEVAFF 0x3fa8 /* ro */
#define POR_CFGM_ERRDEVARCH 0x3fb8 /* ro */
#define POR_CFGM_ERRIDR 0x3fc8 /* ro */
#define POR_CFGM_ERRPIDR45 0x3fd0 /* ro */
#define POR_CFGM_ERRPIDR67 0x3fd8 /* ro */
#define POR_CFGM_ERRPIDR01 0x3fe0 /* ro */
#define POR_CFGM_ERRPIDR23 0x3fe8 /* ro */
#define POR_CFGM_ERRCIDR01 0x3ff0 /* ro */
#define POR_CFGM_ERRCIDR23 0x3ff8 /* ro */
#define POR_INFO_GLOBAL 0x0900 /* ro */
#define POR_INFO_GLOBAL_CHIC_MODE_EN (1UL << 49) /* CHI-C mode enable */
#define POR_INFO_GLOBAL_R2_ENABLE (1UL << 48) /* CMN R2 feature enable */
#define POR_INFO_GLOBAL_RNSAM_NUM_ADD_HASHED_TGT_SHIFT 36 /* Number of additional hashed target ID's supported by the RN SAM, beyond the local HNF count */
#define POR_INFO_GLOBAL_RNSAM_NUM_ADD_HASHED_TGT_MASK (0x3fUL << 36)
#define POR_INFO_GLOBAL_NUM_REMOTE_RNF_SHIFT 28 /* Number of remote RN-F devices in the system when the CML feature is enabled */
#define POR_INFO_GLOBAL_NUM_REMOTE_RNF_MASK (0xffUL << 28)
#define POR_INFO_GLOBAL_FLIT_PARITY_EN (1 << 25) /* Indicates whether parity checking is enabled in the transport layer on all flits sent on the interconnect */
#define POR_INFO_GLOBAL_DATACHECK_EN (1 << 24) /* Indicates whether datacheck feature is enabled for CHI DAT flit */
#define POR_INFO_GLOBAL_PHYSICAL_ADDRESS_WIDTH_SHIFT 16 /* Physical address width */
#define POR_INFO_GLOBAL_PHYSICAL_ADDRESS_WIDTH_MASK (0xff << 16)
#define POR_INFO_GLOBAL_CHI_REQ_ADDR_WIDTH_SHIFT 8 /* REQ address width */
#define POR_INFO_GLOBAL_CHI_REQ_ADDR_WIDTH_MASK (0xff << 8)
#define POR_INFO_GLOBAL_CHI_REQ_RSVDC_WIDTH_SHIFT 0 /* RSVDC field width in CHI REQ flit */
#define POR_INFO_GLOBAL_CHI_REQ_RSVDC_WIDTH_MASK 0xff
#define POR_PPU_INT_ENABLE 0x1000 /* rw */
#define POR_PPU_INT_STATUS 0x1008 /* w1c */
#define POR_PPU_QACTIVE_HYST 0x1010 /* rw */
#define POR_CFGM_CHILD_POINTER_0 0x0100 /* ro */
#define POR_CFGM_CHILD_POINTER(x) (POR_CFGM_CHILD_POINTER_0 + ((x) * 8))
#define POR_CFGM_CHILD_POINTER_EXT (1 << 31)
#define POR_CFGM_CHILD_POINTER_BASE_MASK 0x0fffffffUL
/* DN registers */
#define POR_DN_NODE_INFO 0x0000 /* ro */
#define POR_DN_CHILD_INFO 0x0080 /* ro */
#define POR_DN_BUILD_INFO 0x0900 /* ro */
#define POR_DN_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_DN_AUX_CTL 0x0a00 /* rw */
#define POR_DN_VMF0_CTRL 0x0c00 /* rw */
#define POR_DN_VMF0_RNF0 0x0c08 /* rw */
#define POR_DN_VMF0_RND 0x0c10 /* rw */
#define POR_DN_VMF0_CXRA 0x0c18 /* rw */
#define POR_DN_VMF1_CTRL 0x0c20 /* rw */
#define POR_DN_VMF1_RNF0 0x0c28 /* rw */
#define POR_DN_VMF1_RND 0x0c30 /* rw */
#define POR_DN_VMF1_CXRA 0x0c38 /* rw */
#define POR_DN_VMF2_CTRL 0x0c40 /* rw */
#define POR_DN_VMF2_RNF0 0x0c48 /* rw */
#define POR_DN_VMF2_RND 0x0c50 /* rw */
#define POR_DN_VMF2_CXRA 0x0c58 /* rw */
#define POR_DN_VMF3_CTRL 0x0c60 /* rw */
#define POR_DN_VMF3_RNF0 0x0c68 /* rw */
#define POR_DN_VMF3_RND 0x0c70 /* rw */
#define POR_DN_VMF3_CXRA 0x0c78 /* rw */
#define POR_DN_VMF4_CTRL 0x0c80 /* rw */
#define POR_DN_VMF4_RNF0 0x0c88 /* rw */
#define POR_DN_VMF4_RND 0x0c90 /* rw */
#define POR_DN_VMF4_CXRA 0x0c98 /* rw */
#define POR_DN_VMF5_CTRL 0x0ca0 /* rw */
#define POR_DN_VMF5_RNF0 0x0ca8 /* rw */
#define POR_DN_VMF5_RND 0x0cb0 /* rw */
#define POR_DN_VMF5_CXRA 0x0cb8 /* rw */
#define POR_DN_VMF6_CTRL 0x0cc0 /* rw */
#define POR_DN_VMF6_RNF0 0x0cc8 /* rw */
#define POR_DN_VMF6_RND 0x0cd0 /* rw */
#define POR_DN_VMF6_CXRA 0x0cd8 /* rw */
#define POR_DN_VMF7_CTRL 0x0ce0 /* rw */
#define POR_DN_VMF7_RNF0 0x0ce8 /* rw */
#define POR_DN_VMF7_RND 0x0cf0 /* rw */
#define POR_DN_VMF7_CXRA 0x0cf8 /* rw */
#define POR_DN_VMF8_CTRL 0x0d00 /* rw */
#define POR_DN_VMF8_RNF0 0x0d08 /* rw */
#define POR_DN_VMF8_RND 0x0d10 /* rw */
#define POR_DN_VMF8_CXRA 0x0d18 /* rw */
#define POR_DN_VMF9_CTRL 0x0d20 /* rw */
#define POR_DN_VMF9_RNF0 0x0d28 /* rw */
#define POR_DN_VMF9_RND 0x0d30 /* rw */
#define POR_DN_VMF9_CXRA 0x0d38 /* rw */
#define POR_DN_VMF10_CTRL 0x0d40 /* rw */
#define POR_DN_VMF10_RNF0 0x0d48 /* rw */
#define POR_DN_VMF10_RND 0x0d50 /* rw */
#define POR_DN_VMF10_CXRA 0x0d58 /* rw */
#define POR_DN_VMF11_CTRL 0x0d60 /* rw */
#define POR_DN_VMF11_RNF0 0x0d68 /* rw */
#define POR_DN_VMF11_RND 0x0d70 /* rw */
#define POR_DN_VMF11_CXRA 0x0d78 /* rw */
#define POR_DN_VMF12_CTRL 0x0d80 /* rw */
#define POR_DN_VMF12_RNF0 0x0d88 /* rw */
#define POR_DN_VMF12_RND 0x0d90 /* rw */
#define POR_DN_VMF12_CXRA 0x0d98 /* rw */
#define POR_DN_VMF13_CTRL 0x0da0 /* rw */
#define POR_DN_VMF13_RNF0 0x0da8 /* rw */
#define POR_DN_VMF13_RND 0x0db0 /* rw */
#define POR_DN_VMF13_CXRA 0x0db8 /* rw */
#define POR_DN_VMF14_CTRL 0x0dc0 /* rw */
#define POR_DN_VMF14_RNF0 0x0dc8 /* rw */
#define POR_DN_VMF14_RND 0x0dd0 /* rw */
#define POR_DN_VMF14_CXRA 0x0dd8 /* rw */
#define POR_DN_VMF15_CTRL 0x0de0 /* rw */
#define POR_DN_VMF15_RNF0 0x0de8 /* rw */
#define POR_DN_VMF15_RND 0x0df0 /* rw */
#define POR_DN_VMF15_CXRA 0x0df8 /* rw */
#define POR_DN_PMU_EVENT_SEL 0x2000 /* rw */
#define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_SHIFT 32
#define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_MASK (0xf << 32)
#define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_ALL 0
#define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_DVM_OPS 1
#define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_DVM_SYNCS 2
#define POR_DN_PMU_EVENT_SEL_EVENT_ID3_SHIFT 24
#define POR_DN_PMU_EVENT_SEL_EVENT_ID3_MASK (0x3f << 24)
#define POR_DN_PMU_EVENT_SEL_EVENT_ID2_SHIFT 16
#define POR_DN_PMU_EVENT_SEL_EVENT_ID2_MASK (0x3f << 16)
#define POR_DN_PMU_EVENT_SEL_EVENT_ID1_SHIFT 8
#define POR_DN_PMU_EVENT_SEL_EVENT_ID1_MASK (0x3f << 8)
#define POR_DN_PMU_EVENT_SEL_EVENT_ID0_SHIFT 0
#define POR_DN_PMU_EVENT_SEL_EVENT_ID0_MASK 0x3f
/* Debug and trace register */
#define POR_DT_NODE_INFO 0x0000 /* ro */
#define POR_DT_CHILD_INFO 0x0080 /* ro */
#define POR_DT_SECURE_ACCESS 0x0980 /* rw */
#define POR_DT_DTC_CTL 0x0a00 /* rw */
#define POR_DT_DTC_CTL_DT_EN (1 << 0)
#define POR_DT_TRIGGER_STATUS 0x0a10 /* ro */
#define POR_DT_TRIGGER_STATUS_CLR 0x0a20 /* wo */
#define POR_DT_TRACE_CONTROL 0x0a30 /* rw */
#define POR_DT_TRACEID 0x0a48 /* rw */
#define POR_DT_PMEVCNTAB 0x2000 /* rw */
#define POR_DT_PMEVCNTCD 0x2010 /* rw */
#define POR_DT_PMEVCNTEF 0x2020 /* rw */
#define POR_DT_PMEVCNTGH 0x2030 /* rw */
#define POR_DT_PMEVCNT(x) (0x2000 + ((x) * 0x10))
#define POR_DT_PMEVCNT_EVENCNT_SHIFT 0
#define POR_DT_PMEVCNT_ODDCNT_SHIFT 32
#define POR_DT_PMCCNTR 0x2040 /* rw */
#define POR_DT_PMEVCNTSRAB 0x2050 /* rw */
#define POR_DT_PMEVCNTSRCD 0x2060 /* rw */
#define POR_DT_PMEVCNTSREF 0x2070 /* rw */
#define POR_DT_PMEVCNTSRGH 0x2080 /* rw */
#define POR_DT_PMCCNTRSR 0x2090 /* rw */
#define POR_DT_PMCR 0x2100 /* rw */
#define POR_DT_PMCR_OVFL_INTR_EN (1 << 6)
#define POR_DT_PMCR_CNTR_RST (1 << 5)
#define POR_DT_PMCR_CNTCFG_SHIFT 1
#define POR_DT_PMCR_CNTCFG_MASK (0xf << POR_DT_PMCR_CNTCFG_SHIFT)
#define POR_DT_PMCR_PMU_EN (1 << 0)
#define POR_DT_PMOVSR 0x2118 /* ro */
#define POR_DT_PMOVSR_CLR 0x2120 /* wo */
#define POR_DT_PMOVSR_EVENT_COUNTERS 0xffUL
#define POR_DT_PMOVSR_CYCLE_COUNTER 0x100UL
#define POR_DT_PMOVSR_ALL \
(POR_DT_PMOVSR_EVENT_COUNTERS | POR_DT_PMOVSR_CYCLE_COUNTER)
#define POR_DT_PMSSR 0x2128 /* ro */
#define POR_DT_PMSRR 0x2130 /* wo */
#define POR_DT_CLAIM 0x2da0 /* rw */
#define POR_DT_DEVAFF 0x2da8 /* ro */
#define POR_DT_LSR 0x2db0 /* ro */
#define POR_DT_AUTHSTATUS_DEVARCH 0x2db8 /* ro */
#define POR_DT_DEVID 0x2dc0 /* ro */
#define POR_DT_DEVTYPE 0x2dc8 /* ro */
#define POR_DT_PIDR45 0x2dd0 /* ro */
#define POR_DT_PIDR67 0x2dd8 /* ro */
#define POR_DT_PIDR01 0x2de0 /* ro */
#define POR_DT_PIDR23 0x2de8 /* ro */
#define POR_DT_CIDR01 0x2df0 /* ro */
#define POR_DT_CIDR23 0x2df8 /* ro */
/* HN-F registers */
#define POR_HNF_NODE_INFO 0x0000 /* ro */
#define POR_HNF_CHILD_INFO 0x0080 /* ro */
#define POR_HNF_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_HNF_UNIT_INFO 0x0900 /* ro */
#define POR_HNF_CFG_CTL 0x0a00 /* rw */
#define POR_HNF_AUX_CTL 0x0a08 /* rw */
#define POR_HNF_R2_AUX_CTL 0x0a10 /* rw */
#define POR_HNF_PPU_PWPR 0x1000 /* rw */
#define POR_HNF_PPU_PWSR 0x1008 /* ro */
#define POR_HNF_PPU_MISR 0x1014 /* ro */
#define POR_HNF_PPU_IDR0 0x1fb0 /* ro */
#define POR_HNF_PPU_IDR1 0x1fb4 /* ro */
#define POR_HNF_PPU_IIDR 0x1fc8 /* ro */
#define POR_HNF_PPU_AIDR 0x1fcc /* ro */
#define POR_HNF_PPU_DYN_RET_THRESHOLD 0x1100 /* rw */
#define POR_HNF_QOS_BAND 0x0a80 /* ro */
#define POR_HNF_QOS_RESERVATION 0x0a88 /* rw */
#define POR_HNF_RN_STARVATION 0x0a90 /* rw */
#define POR_HNF_ERRFR 0x3000 /* ro */
#define POR_HNF_ERRCTLR 0x3008 /* rw */
#define POR_HNF_ERRSTATUS 0x3010 /* w1c */
#define POR_HNF_ERRADDR 0x3018 /* rw */
#define POR_HNF_ERRMISC 0x3020 /* rw */
#define POR_HNF_ERR_INJ 0x3030 /* rw */
#define POR_HNF_BYTE_PAR_ERR_INJ 0x3038 /* wo */
#define POR_HNF_ERRFR_NS 0x3100 /* ro */
#define POR_HNF_ERRCTLR_NS 0x3108 /* rw */
#define POR_HNF_ERRSTATUS_NS 0x3110 /* w1c */
#define POR_HNF_ERRADDR_NS 0x3118 /* rw */
#define POR_HNF_ERRMISC_NS 0x3120 /* rw */
#define POR_HNF_SLC_LOCK_WAYS 0x0c00 /* rw */
#define POR_HNF_SLC_LOCK_BASE0 0x0c08 /* rw */
#define POR_HNF_SLC_LOCK_BASE1 0x0c10 /* rw */
#define POR_HNF_SLC_LOCK_BASE2 0x0c18 /* rw */
#define POR_HNF_SLC_LOCK_BASE3 0x0c20 /* rw */
#define POR_HNF_RNF_REGION_VEC1 0x0c28 /* rw */
#define POR_HNF_RNI_REGION_VEC 0x0c30 /* rw */
#define POR_HNF_RNF_REGION_VEC 0x0c38 /* rw */
#define POR_HNF_RND_REGION_VEC 0x0c40 /* rw */
#define POR_HNF_SLCWAY_PARTITION0_RNF_VEC 0x0c48 /* rw */
#define POR_HNF_SLCWAY_PARTITION1_RNF_VEC 0x0c50 /* rw */
#define POR_HNF_SLCWAY_PARTITION2_RNF_VEC 0x0c58 /* rw */
#define POR_HNF_SLCWAY_PARTITION3_RNF_VEC 0x0c60 /* rw */
#define POR_HNF_SLCWAY_PARTITION0_RNF_VEC1 0x0cb0 /* rw */
#define POR_HNF_SLCWAY_PARTITION1_RNF_VEC1 0x0cb8 /* rw */
#define POR_HNF_SLCWAY_PARTITION2_RNF_VEC1 0x0cc0 /* rw */
#define POR_HNF_SLCWAY_PARTITION3_RNF_VEC1 0x0cc8 /* rw */
#define POR_HNF_SLCWAY_PARTITION0_RNI_VEC 0x0c68 /* rw */
#define POR_HNF_SLCWAY_PARTITION1_RNI_VEC 0x0c70 /* rw */
#define POR_HNF_SLCWAY_PARTITION2_RNI_VEC 0x0c78 /* rw */
#define POR_HNF_SLCWAY_PARTITION3_RNI_VEC 0x0c80 /* rw */
#define POR_HNF_SLCWAY_PARTITION0_RND_VEC 0x0c88 /* rw */
#define POR_HNF_SLCWAY_PARTITION1_RND_VEC 0x0c90 /* rw */
#define POR_HNF_SLCWAY_PARTITION2_RND_VEC 0x0c98 /* rw */
#define POR_HNF_SLCWAY_PARTITION3_RND_VEC 0x0ca0 /* rw */
#define POR_HNF_RN_REGION_LOCK 0x0ca8 /* rw */
#define POR_HNF_SAM_CONTROL 0x0d00 /* rw */
#define POR_HNF_SAM_MEMREGION0 0x0d08 /* rw */
#define POR_HNF_SAM_MEMREGION1 0x0d10 /* rw */
#define POR_HNF_SAM_SN_PROPERTIES 0x0d18 /* rw */
#define POR_HNF_SAM_6SN_NODEID 0x0d20 /* rw */
#define POR_HNF_RN_PHYS_ID(x) (0x0d28 + 8 * (x)) /* rw */
#define POR_HNF_RN_PHYS_ID63 0x0f90 /* rw */
#define POR_HNF_SF_CXG_BLOCKED_WAYS 0x0f00 /* rw */
#define POR_HNF_CML_PORT_AGGR_GRP0_ADD_MASK 0x0f10 /* rw */
#define POR_HNF_CML_PORT_AGGR_GRP1_ADD_MASK 0x0f18 /* rw */
#define POR_HNF_CML_PORT_AGGR_GRP0_REG 0x0f28 /* rw */
#define POR_HNF_CML_PORT_AGGR_GRP1_REG 0x0f30 /* rw */
#define HN_SAM_HASH_ADDR_MASK_REG 0x0f40 /* rw */
#define HN_SAM_REGION_CMP_ADDR_MASK_REG 0x0f48 /* rw */
#define POR_HNF_ABF_LO_ADDR 0x0f50 /* rw */
#define POR_HNF_ABF_HI_ADDR 0x0f58 /* rw */
#define POR_HNF_ABF_PR 0x0f60 /* rw */
#define POR_HNF_ABF_SR 0x0f68 /* ro */
#define POR_HNF_LDID_MAP_TABLE_REG0 0x0f98 /* rw */
#define POR_HNF_LDID_MAP_TABLE_REG1 0x0fa0 /* rw */
#define POR_HNF_LDID_MAP_TABLE_REG2 0x0fa8 /* rw */
#define POR_HNF_LDID_MAP_TABLE_REG3 0x0fb0 /* rw */
#define POR_HNF_CFG_SLCSF_DBGRD 0x0b80 /* wo */
#define POR_HNF_SLC_CACHE_ACCESS_SLC_TAG 0x0b88 /* ro */
#define POR_HNF_SLC_CACHE_ACCESS_SLC_DATA 0x0b90 /* ro */
#define POR_HNF_SLC_CACHE_ACCESS_SF_TAG 0x0b98 /* ro */
#define POR_HNF_SLC_CACHE_ACCESS_SF_TAG1 0x0ba0 /* ro */
#define POR_HNF_SLC_CACHE_ACCESS_SF_TAG2 0x0ba8 /* ro */
#define POR_HNF_PMU_EVENT_SEL 0x2000 /* rw */
/* HN-I registers */
#define POR_HNI_NODE_INFO 0x0000 /* ro */
#define POR_HNI_CHILD_INFO 0x0080 /* ro */
#define POR_HNI_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_HNI_UNIT_INFO 0x0900 /* ro */
#define POR_HNI_SAM_ADDRREGION0_CFG 0x0c00 /* rw */
#define POR_HNI_SAM_ADDRREGION1_CFG 0x0c08 /* rw */
#define POR_HNI_SAM_ADDRREGION2_CFG 0x0c10 /* rw */
#define POR_HNI_SAM_ADDRREGION3_CFG 0x0c18 /* rw */
#define POR_HNI_CFG_CTL 0x0a00 /* rw */
#define POR_HNI_AUX_CTL 0x0a08 /* rw */
#define POR_HNI_ERRFR 0x3000 /* ro */
#define POR_HNI_ERRCTLR 0x3008 /* rw */
#define POR_HNI_ERRSTATUS 0x3010 /* w1c */
#define POR_HNI_ERRADDR 0x3018 /* rw */
#define POR_HNI_ERRMISC 0x3020 /* rw */
#define POR_HNI_ERRFR_NS 0x3100 /* ro */
#define POR_HNI_ERRCTLR_NS 0x3108 /* rw */
#define POR_HNI_ERRSTATUS_NS 0x3110 /* w1c */
#define POR_HNI_ERRADDR_NS 0x3118 /* rw */
#define POR_HNI_ERRMISC_NS 0x3120 /* rw */
#define POR_HNI_PMU_EVENT_SEL 0x2000 /* rw */
/* XP registers */
#define POR_MXP_NODE_INFO 0x0000 /* ro */
#define POR_MXP_DEVICE_PORT_CONNECT_INFO_P0 0x0008 /* ro */
#define POR_MXP_DEVICE_PORT_CONNECT_INFO_P1 0x0010 /* ro */
#define POR_MXP_MESH_PORT_CONNECT_INFO_EAST 0x0018 /* ro */
#define POR_MXP_MESH_PORT_CONNECT_INFO_NORTH 0x0020 /* ro */
#define POR_MXP_CHILD_INFO 0x0080 /* ro */
#define POR_MXP_CHILD_POINTER_0 0x0100 /* ro */
#define POR_MXP_CHILD_POINTER_1 0x0108 /* ro */
#define POR_MXP_CHILD_POINTER_2 0x0110 /* ro */
#define POR_MXP_CHILD_POINTER_3 0x0118 /* ro */
#define POR_MXP_CHILD_POINTER_4 0x0120 /* ro */
#define POR_MXP_CHILD_POINTER_5 0x0128 /* ro */
#define POR_MXP_CHILD_POINTER_6 0x0130 /* ro */
#define POR_MXP_CHILD_POINTER_7 0x0138 /* ro */
#define POR_MXP_CHILD_POINTER_8 0x0140 /* ro */
#define POR_MXP_CHILD_POINTER_9 0x0148 /* ro */
#define POR_MXP_CHILD_POINTER_10 0x0150 /* ro */
#define POR_MXP_CHILD_POINTER_11 0x0158 /* ro */
#define POR_MXP_CHILD_POINTER_12 0x0160 /* ro */
#define POR_MXP_CHILD_POINTER_13 0x0168 /* ro */
#define POR_MXP_CHILD_POINTER_14 0x0170 /* ro */
#define POR_MXP_CHILD_POINTER_15 0x0178 /* ro */
#define POR_MXP_P0_INFO 0x0900 /* ro */
#define POR_MXP_P1_INFO 0x0908 /* ro */
#define POR_MXP_PX_INFO_DEV_TYPE_RN_I 0x01
#define POR_MXP_PX_INFO_DEV_TYPE_RN_D 0x02
#define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIB 0x04
#define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIB_ESAM 0x05
#define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIA 0x06
#define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIA_ESAM 0x07
#define POR_MXP_PX_INFO_DEV_TYPE_HN_T 0x08
#define POR_MXP_PX_INFO_DEV_TYPE_HN_I 0x09
#define POR_MXP_PX_INFO_DEV_TYPE_HN_D 0x0a
#define POR_MXP_PX_INFO_DEV_TYPE_SN_F 0x0c
#define POR_MXP_PX_INFO_DEV_TYPE_SBSX 0x0d
#define POR_MXP_PX_INFO_DEV_TYPE_HN_F 0x0e
#define POR_MXP_PX_INFO_DEV_TYPE_CXHA 0x11
#define POR_MXP_PX_INFO_DEV_TYPE_CXRA 0x12
#define POR_MXP_PX_INFO_DEV_TYPE_CXRH 0x13
#define POR_MXP_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_MXP_AUX_CTL 0x0a00 /* rw */
#define POR_MXP_P0_QOS_CONTROL 0x0a80 /* rw */
#define POR_MXP_P0_QOS_LAT_TGT 0x0a88 /* rw */
#define POR_MXP_P0_QOS_LAT_SCALE 0x0a90 /* rw */
#define POR_MXP_P0_QOS_LAT_RANGE 0x0a98 /* rw */
#define POR_MXP_P1_QOS_CONTROL 0x0aa0 /* rw */
#define POR_MXP_P1_QOS_LAT_TGT 0x0aa8 /* rw */
#define POR_MXP_P1_QOS_LAT_SCALE 0x0ab0 /* rw */
#define POR_MXP_P1_QOS_LAT_RANGE 0x0ab8 /* rw */
#define POR_MXP_PMU_EVENT_SEL 0x2000 /* rw */
#define POR_MXP_ERRFR 0x3000 /* ro */
#define POR_MXP_ERRCTLR 0x3008 /* rw */
#define POR_MXP_ERRSTATUS 0x3010 /* w1c */
#define POR_MXP_ERRMISC 0x3028 /* rw */
#define POR_MXP_P0_BYTE_PAR_ERR_INJ 0x3030 /* wo */
#define POR_MXP_P1_BYTE_PAR_ERR_INJ 0x3038 /* wo */
#define POR_MXP_ERRFR_NS 0x3100 /* ro */
#define POR_MXP_ERRCTLR_NS 0x3108 /* rw */
#define POR_MXP_ERRSTATUS_NS 0x3110 /* w1c */
#define POR_MXP_ERRMISC_NS 0x3128 /* rw */
#define POR_MXP_P0_SYSCOREQ_CTL 0x1000 /* rw */
#define POR_MXP_P1_SYSCOREQ_CTL 0x1008 /* rw */
#define POR_MXP_P0_SYSCOACK_STATUS 0x1010 /* ro */
#define POR_MXP_P1_SYSCOACK_STATUS 0x1018 /* ro */
#define POR_DTM_CONTROL 0x2100 /* rw */
#define POR_DTM_CONTROL_TRACE_NO_ATB (1 << 3)
#define POR_DTM_CONTROL_SAMPLE_PROFILE_ENABLE (1 << 2)
#define POR_DTM_CONTROL_TRACE_TAG_ENABLE (1 << 1)
#define POR_DTM_CONTROL_DTM_ENABLE (1 << 0)
#define POR_DTM_FIFO_ENTRY_READY 0x2118 /* w1c */
#define POR_DTM_FIFO_ENTRY0_0 0x2120 /* ro */
#define POR_DTM_FIFO_ENTRY0_1 0x2128 /* ro */
#define POR_DTM_FIFO_ENTRY0_2 0x2130 /* ro */
#define POR_DTM_FIFO_ENTRY1_0 0x2138 /* ro */
#define POR_DTM_FIFO_ENTRY1_1 0x2140 /* ro */
#define POR_DTM_FIFO_ENTRY1_2 0x2148 /* ro */
#define POR_DTM_FIFO_ENTRY2_0 0x2150 /* ro */
#define POR_DTM_FIFO_ENTRY2_1 0x2158 /* ro */
#define POR_DTM_FIFO_ENTRY2_2 0x2160 /* ro */
#define POR_DTM_FIFO_ENTRY3_0 0x2168 /* ro */
#define POR_DTM_FIFO_ENTRY3_1 0x2170 /* ro */
#define POR_DTM_FIFO_ENTRY3_2 0x2178 /* ro */
#define POR_DTM_WP0_CONFIG 0x21a0 /* rw */
#define POR_DTM_WP0_VAL 0x21a8 /* rw */
#define POR_DTM_WP0_MASK 0x21b0 /* rw */
#define POR_DTM_WP1_CONFIG 0x21b8 /* rw */
#define POR_DTM_WP1_VAL 0x21c0 /* rw */
#define POR_DTM_WP1_MASK 0x21c8 /* rw */
#define POR_DTM_WP2_CONFIG 0x21d0 /* rw */
#define POR_DTM_WP2_VAL 0x21d8 /* rw */
#define POR_DTM_WP2_MASK 0x21e0 /* rw */
#define POR_DTM_WP3_CONFIG 0x21e8 /* rw */
#define POR_DTM_WP3_VAL 0x21f0 /* rw */
#define POR_DTM_WP3_MASK 0x21f8 /* rw */
#define POR_DTM_PMSICR 0x2200 /* rw */
#define POR_DTM_PMSIRR 0x2208 /* rw */
#define POR_DTM_PMU_CONFIG 0x2210 /* rw */
#define POR_DTM_PMU_CONFIG_PMU_EN (1 << 0)
#define POR_DTM_PMU_CONFIG_VCNT_INPUT_SEL_SHIFT 32
#define POR_DTM_PMU_CONFIG_VCNT_INPUT_SEL_WIDTH 8
#define POR_DTM_PMEVCNT 0x2220 /* rw */
#define POR_DTM_PMEVCNT_CNTR_WIDTH 16
#define POR_DTM_PMEVCNTSR 0x2240 /* rw */
/* RN-D registers */
#define POR_RND_NODE_INFO 0x0000 /* ro */
#define POR_RND_CHILD_INFO 0x0080 /* ro */
#define POR_RND_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_RND_UNIT_INFO 0x0900 /* ro */
#define POR_RND_CFG_CTL 0x0a00 /* rw */
#define POR_RND_AUX_CTL 0x0a08 /* rw */
#define POR_RND_S0_PORT_CONTROL 0x0a10 /* rw */
#define POR_RND_S1_PORT_CONTROL 0x0a18 /* rw */
#define POR_RND_S2_PORT_CONTROL 0x0a20 /* rw */
#define POR_RND_S0_QOS_CONTROL 0x0a80 /* rw */
#define POR_RND_S0_QOS_LAT_TGT 0x0a88 /* rw */
#define POR_RND_S0_QOS_LAT_SCALE 0x0a90 /* rw */
#define POR_RND_S0_QOS_LAT_RANGE 0x0a98 /* rw */
#define POR_RND_S1_QOS_CONTROL 0x0aa0 /* rw */
#define POR_RND_S1_QOS_LAT_TGT 0x0aa8 /* rw */
#define POR_RND_S1_QOS_LAT_SCALE 0x0ab0 /* rw */
#define POR_RND_S1_QOS_LAT_RANGE 0x0ab8 /* rw */
#define POR_RND_S2_QOS_CONTROL 0x0ac0 /* rw */
#define POR_RND_S2_QOS_LAT_TGT 0x0ac8 /* rw */
#define POR_RND_S2_QOS_LAT_SCALE 0x0ad0 /* rw */
#define POR_RND_S2_QOS_LAT_RANGE 0x0ad8 /* rw */
#define POR_RND_PMU_EVENT_SEL 0x2000 /* rw */
#define POR_RND_SYSCOREQ_CTL 0x1000 /* rw */
#define POR_RND_SYSCOACK_STATUS 0x1008 /* ro */
/* RN-I registers */
#define POR_RNI_NODE_INFO 0x0000 /* ro */
#define POR_RNI_CHILD_INFO 0x0080 /* ro */
#define POR_RNI_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_RNI_UNIT_INFO 0x0900 /* ro */
#define POR_RNI_CFG_CTL 0x0a00 /* rw */
#define POR_RNI_AUX_CTL 0x0a08 /* rw */
#define POR_RNI_S0_PORT_CONTROL 0x0a10 /* rw */
#define POR_RNI_S1_PORT_CONTROL 0x0a18 /* rw */
#define POR_RNI_S2_PORT_CONTROL 0x0a20 /* rw */
#define POR_RNI_S0_QOS_CONTROL 0x0a80 /* rw */
#define POR_RNI_S0_QOS_LAT_TGT 0x0a88 /* rw */
#define POR_RNI_S0_QOS_LAT_SCALE 0x0a90 /* rw */
#define POR_RNI_S0_QOS_LAT_RANGE 0x0a98 /* rw */
#define POR_RNI_S1_QOS_CONTROL 0x0aa0 /* rw */
#define POR_RNI_S1_QOS_LAT_TGT 0x0aa8 /* rw */
#define POR_RNI_S1_QOS_LAT_SCALE 0x0ab0 /* rw */
#define POR_RNI_S1_QOS_LAT_RANGE 0x0ab8 /* rw */
#define POR_RNI_S2_QOS_CONTROL 0x0ac0 /* rw */
#define POR_RNI_S2_QOS_LAT_TGT 0x0ac8 /* rw */
#define POR_RNI_S2_QOS_LAT_SCALE 0x0ad0 /* rw */
#define POR_RNI_S2_QOS_LAT_RANGE 0x0ad8 /* rw */
#define POR_RNI_PMU_EVENT_SEL 0x2000 /* rw */
/* RN SAM registers */
#define POR_RNSAM_NODE_INFO 0x0000 /* ro */
#define POR_RNSAM_CHILD_INFO 0x0080 /* ro */
#define POR_RNSAM_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_RNSAM_UNIT_INFO 0x0900 /* ro */
#define RNSAM_STATUS 0x0c00 /* rw */
#define NON_HASH_MEM_REGION_REG0 0x0c08 /* rw */
#define NON_HASH_MEM_REGION_REG1 0x0c10 /* rw */
#define NON_HASH_MEM_REGION_REG2 0x0c18 /* rw */
#define NON_HASH_MEM_REGION_REG3 0x0c20 /* rw */
#define NON_HASH_TGT_NODEID0 0x0c30 /* rw */
#define NON_HASH_TGT_NODEID1 0x0c38 /* rw */
#define NON_HASH_TGT_NODEID2 0x0c40 /* rw */
#define SYS_CACHE_GRP_REGION0 0x0c48 /* rw */
#define SYS_CACHE_GRP_REGION1 0x0c50 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG0 0x0c58 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG1 0x0c60 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG2 0x0c68 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG3 0x0c70 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG4 0x0c78 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG5 0x0c80 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG6 0x0c88 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG7 0x0c90 /* rw */
#define SYS_CACHE_GRP_NONHASH_NODEID 0x0c98 /* rw */
#define SYS_CACHE_GROUP_HN_COUNT 0x0d00 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG0 0x0d08 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG1 0x0d10 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG2 0x0d18 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG3 0x0d20 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG4 0x0d28 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG5 0x0d30 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG6 0x0d38 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG7 0x0d40 /* rw */
#define SYS_CACHE_GRP_SN_SAM_CFG0 0x0d48 /* rw */
#define SYS_CACHE_GRP_SN_SAM_CFG1 0x0d50 /* rw */
#define GIC_MEM_REGION_REG 0x0d58 /* rw */
#define SYS_CACHE_GRP_SN_ATTR 0x0d60 /* rw */
#define SYS_CACHE_GRP_HN_CPA_EN_REG 0x0d68 /* rw */
#define SYS_CACHE_GRP_HN_CPA_GRP_REG 0x0d70 /* rw */
#define CML_PORT_AGGR_MODE_CTRL_REG 0x0e00 /* rw */
#define CML_PORT_AGGR_GRP0_ADD_MASK 0x0e08 /* rw */
#define CML_PORT_AGGR_GRP1_ADD_MASK 0x0e10 /* rw */
#define CML_PORT_AGGR_GRP0_REG 0x0e40 /* rw */
#define CML_PORT_AGGR_GRP1_REG 0x0e48 /* rw */
#define SYS_CACHE_GRP_SECONDARY_REG0 0x0f00 /* rw */
#define SYS_CACHE_GRP_SECONDARY_REG1 0x0f08 /* rw */
#define SYS_CACHE_GRP_CAL_MODE_REG 0x0f10 /* rw */
#define RNSAM_HASH_ADDR_MASK_REG 0x0f18 /* rw */
#define RNSAM_REGION_CMP_ADDR_MASK_REG 0x0f20 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG8 0x0f58 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG9 0x0f60 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG10 0x0f68 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG11 0x0f70 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG12 0x0f78 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG13 0x0f80 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG14 0x0f88 /* rw */
#define SYS_CACHE_GRP_HN_NODEID_REG15 0x0f90 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG8 0x1008 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG9 0x1010 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG10 0x1018 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG11 0x1020 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG12 0x1028 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG13 0x1030 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG14 0x1038 /* rw */
#define SYS_CACHE_GRP_SN_NODEID_REG15 0x1040 /* rw */
/* SBSX registers */
#define POR_SBSX_NODE_INFO 0x0000 /* ro */
#define POR_SBSX_CHILD_INFO 0x0080 /* ro */
#define POR_SBSX_UNIT_INFO 0x0900 /* ro */
#define POR_SBSX_AUX_CTL 0x0a08 /* rw */
#define POR_SBSX_ERRFR 0x3000 /* ro */
#define POR_SBSX_ERRCTLR 0x3008 /* rw */
#define POR_SBSX_ERRSTATUS 0x3010 /* w1c */
#define POR_SBSX_ERRADDR 0x3018 /* rw */
#define POR_SBSX_ERRMISC 0x3020 /* rw */
#define POR_SBSX_ERRFR_NS 0x3100 /* ro */
#define POR_SBSX_ERRCTLR_NS 0x3108 /* rw */
#define POR_SBSX_ERRSTATUS_NS 0x3110 /* w1c */
#define POR_SBSX_ERRADDR_NS 0x3118 /* rw */
#define POR_SBSX_ERRMISC_NS 0x3120 /* rw */
#define POR_SBSX_PMU_EVENT_SEL 0x2000 /* rw */
/* CXHA registers */
#define POR_CXG_HA_NODE_INFO 0x0000 /* ro */
#define POR_CXG_HA_ID 0x0008 /* rw */
#define POR_CXG_HA_CHILD_INFO 0x0080 /* ro */
#define POR_CXG_HA_AUX_CTL 0x0a08 /* rw */
#define POR_CXG_HA_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_CXG_HA_UNIT_INFO 0x0900 /* ro */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG0 0x0c00 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG1 0x0c08 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG2 0x0c10 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG3 0x0c18 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG4 0x0c20 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG5 0x0c28 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG6 0x0c30 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_REG7 0x0c38 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG0 0x0c40 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG1 0x0c48 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG2 0x0c50 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG3 0x0c58 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG4 0x0c60 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG5 0x0c68 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG6 0x0c70 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_REG7 0x0c78 /* rw */
#define POR_CXG_HA_AGENTID_TO_LINKID_VAL 0x0d00 /* rw */
#define POR_CXG_HA_RNF_RAID_TO_LDID_VAL 0x0d08 /* rw */
#define POR_CXG_HA_PMU_EVENT_SEL 0x2000 /* rw */
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID3_SHIFT 24
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID3_MASK (0x3f << 24)
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID2_SHIFT 16
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID2_MASK (0x3f << 16)
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID1_SHIFT 8
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID1_MASK (0x3f << 8)
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID0_SHIFT 0
#define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID0_MASK 0x3f
#define POR_CXG_HA_CXPRTCL_LINK0_CTL 0x1000 /* rw */
#define POR_CXG_HA_CXPRTCL_LINK0_STATUS 0x1008 /* ro */
#define POR_CXG_HA_CXPRTCL_LINK1_CTL 0x1010 /* rw */
#define POR_CXG_HA_CXPRTCL_LINK1_STATUS 0x1018 /* ro */
#define POR_CXG_HA_CXPRTCL_LINK2_CTL 0x1020 /* rw */
#define POR_CXG_HA_CXPRTCL_LINK2_STATUS 0x1028 /* ro */
#define POR_CXG_HA_ERRFR 0x3000 /* ro */
#define POR_CXG_HA_ERRCTLR 0x3008 /* rw */
#define POR_CXG_HA_ERRSTATUS 0x3010 /* w1c */
#define POR_CXG_HA_ERRADDR 0x3018 /* rw */
#define POR_CXG_HA_ERRMISC 0x3020 /* rw */
#define POR_CXG_HA_ERRFR_NS 0x3100 /* ro */
#define POR_CXG_HA_ERRCTLR_NS 0x3108 /* rw */
#define POR_CXG_HA_ERRSTATUS_NS 0x3110 /* w1c */
#define POR_CXG_HA_ERRADDR_NS 0x3118 /* rw */
#define POR_CXG_HA_ERRMISC_NS 0x3120 /* rw */
/* CXRA registers */
#define POR_CXG_RA_NODE_INFO 0x0000 /* ro */
#define POR_CXG_RA_CHILD_INFO 0x0080 /* ro */
#define POR_CXG_RA_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_CXG_RA_UNIT_INFO 0x0900 /* ro */
#define POR_CXG_RA_CFG_CTL 0x0a00 /* rw */
#define EN_CXLA_PMUCMD_PROP (1 << 8)
#define POR_CXG_RA_AUX_CTL 0x0a08 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG0 0x0da8 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG1 0x0db0 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG2 0x0db8 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG3 0x0dc0 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG4 0x0dc8 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG5 0x0dd0 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG6 0x0dd8 /* rw */
#define POR_CXG_RA_SAM_ADDR_REGION_REG7 0x0de0 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION0_LIMIT_REG 0x0e00 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION1_LIMIT_REG 0x0e08 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION2_LIMIT_REG 0x0e10 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION3_LIMIT_REG 0x0e18 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION4_LIMIT_REG 0x0e20 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION5_LIMIT_REG 0x0e28 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION6_LIMIT_REG 0x0e30 /* rw */
#define POR_CXG_RA_SAM_MEM_REGION7_LIMIT_REG 0x0e38 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG0 0x0e60 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG1 0x0e68 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG2 0x0e70 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG3 0x0e78 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG4 0x0e80 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG5 0x0e88 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG6 0x0e90 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_REG7 0x0e98 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG0 0x0ea0 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG1 0x0ea8 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG2 0x0eb0 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG3 0x0eb8 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG4 0x0ec0 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG5 0x0ec8 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG6 0x0ed0 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_REG7 0x0ed8 /* rw */
#define POR_CXG_RA_RNI_LDID_TO_RAID_REG0 0x0ee0 /* rw */
#define POR_CXG_RA_RNI_LDID_TO_RAID_REG1 0x0ee8 /* rw */
#define POR_CXG_RA_RNI_LDID_TO_RAID_REG2 0x0ef0 /* rw */
#define POR_CXG_RA_RNI_LDID_TO_RAID_REG3 0x0ef8 /* rw */
#define POR_CXG_RA_RND_LDID_TO_RAID_REG0 0x0f00 /* rw */
#define POR_CXG_RA_RND_LDID_TO_RAID_REG1 0x0f08 /* rw */
#define POR_CXG_RA_RND_LDID_TO_RAID_REG2 0x0f10 /* rw */
#define POR_CXG_RA_RND_LDID_TO_RAID_REG3 0x0f18 /* rw */
#define POR_CXG_RA_AGENTID_TO_LINKID_VAL 0x0f20 /* rw */
#define POR_CXG_RA_RNF_LDID_TO_RAID_VAL 0x0f28 /* rw */
#define POR_CXG_RA_RNI_LDID_TO_RAID_VAL 0x0f30 /* rw */
#define POR_CXG_RA_RND_LDID_TO_RAID_VAL 0x0f38 /* rw */
#define POR_CXG_RA_PMU_EVENT_SEL 0x2000 /* rw */
#define POR_CXG_RA_CXPRTCL_LINK0_CTL 0x1000 /* rw */
#define POR_CXG_RA_CXPRTCL_LINK0_STATUS 0x1008 /* ro */
#define POR_CXG_RA_CXPRTCL_LINK1_CTL 0x1010 /* rw */
#define POR_CXG_RA_CXPRTCL_LINK1_STATUS 0x1018 /* ro */
#define POR_CXG_RA_CXPRTCL_LINK2_CTL 0x1020 /* rw */
#define POR_CXG_RA_CXPRTCL_LINK2_STATUS 0x1028 /* ro */
/* CXLA registers */
#define POR_CXLA_NODE_INFO 0x0000 /* ro */
#define POR_CXLA_CHILD_INFO 0x0080 /* ro */
#define POR_CXLA_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */
#define POR_CXLA_UNIT_INFO 0x0900 /* ro */
#define POR_CXLA_AUX_CTL 0x0a08 /* rw */
#define POR_CXLA_CCIX_PROP_CAPABILITIES 0x0c00 /* ro */
#define POR_CXLA_CCIX_PROP_CONFIGURED 0x0c08 /* rw */
#define POR_CXLA_TX_CXS_ATTR_CAPABILITIES 0x0c10 /* ro */
#define POR_CXLA_RX_CXS_ATTR_CAPABILITIES 0x0c18 /* ro */
#define POR_CXLA_AGENTID_TO_LINKID_REG0 0x0c30 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG1 0x0c38 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG2 0x0c40 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG3 0x0c48 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG4 0x0c50 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG5 0x0c58 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG6 0x0c60 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_REG7 0x0c68 /* rw */
#define POR_CXLA_AGENTID_TO_LINKID_VAL 0x0c70 /* rw */
#define POR_CXLA_LINKID_TO_PCIE_BUS_NUM 0x0c78 /* rw */
#define POR_CXLA_PERMSG_PYLD_0_63 0x0d00 /* rw */
#define POR_CXLA_PERMSG_PYLD_64_127 0x0d08 /* rw */
#define POR_CXLA_PERMSG_PYLD_128_191 0x0d10 /* rw */
#define POR_CXLA_PERMSG_PYLD_192_255 0x0d18 /* rw */
#define POR_CXLA_PERMSG_CTL 0x0d20 /* rw */
#define POR_CXLA_ERR_AGENT_ID 0x0d28 /* rw */
#define POR_CXLA_PMU_EVENT_SEL 0x2000 /* rw */
#define POR_CXLA_PMU_CONFIG 0x2210 /* rw */
#define POR_CXLA_PMEVCNT 0x2220 /* rw */
#define POR_CXLA_PMEVCNTSR 0x2240 /* rw */
#endif /* _MACHINE_CMN600_REG_H_ */

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/*-
* Copyright (c) 2012 Konstantin Belousov <kib@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef __arm__
#include <arm/counter.h>
#else /* !__arm__ */
#ifndef _MACHINE_COUNTER_H_
#define _MACHINE_COUNTER_H_
#include <sys/pcpu.h>
#include <machine/atomic.h>
#define EARLY_COUNTER &pcpu0.pc_early_dummy_counter
#define counter_enter() do {} while (0)
#define counter_exit() do {} while (0)
#ifdef IN_SUBR_COUNTER_C
static inline uint64_t
counter_u64_read_one(uint64_t *p, int cpu)
{
return (*(uint64_t *)((char *)p + UMA_PCPU_ALLOC_SIZE * cpu));
}
static inline uint64_t
counter_u64_fetch_inline(uint64_t *p)
{
uint64_t r;
int i;
r = 0;
CPU_FOREACH(i)
r += counter_u64_read_one((uint64_t *)p, i);
return (r);
}
static void
counter_u64_zero_one_cpu(void *arg)
{
*((uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE *
PCPU_GET(cpuid))) = 0;
}
static inline void
counter_u64_zero_inline(counter_u64_t c)
{
smp_rendezvous(smp_no_rendezvous_barrier, counter_u64_zero_one_cpu,
smp_no_rendezvous_barrier, c);
}
#endif
#define counter_u64_add_protected(c, inc) counter_u64_add(c, inc)
static inline void
counter_u64_add(counter_u64_t c, int64_t inc)
{
atomic_add_64((uint64_t *)zpcpu_get(c), inc);
}
#endif /* ! _MACHINE_COUNTER_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 1990 The Regents of the University of California.
* Copyright (c) 2014-2016 The FreeBSD Foundation
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Portions of this software were developed by Andrew Turner
* under sponsorship from the FreeBSD Foundation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)cpu.h 5.4 (Berkeley) 5/9/91
* from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29
*/
#ifdef __arm__
#include <arm/cpu.h>
#else /* !__arm__ */
#ifndef _MACHINE_CPU_H_
#define _MACHINE_CPU_H_
#if !defined(__ASSEMBLER__)
#include <machine/atomic.h>
#include <machine/frame.h>
#endif
#include <machine/armreg.h>
#define TRAPF_PC(tfp) ((tfp)->tf_elr)
#define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t)
#define cpu_getstack(td) ((td)->td_frame->tf_sp)
#define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp))
#define cpu_spinwait() __asm __volatile("yield" ::: "memory")
#define cpu_lock_delay() DELAY(1)
/* Extract CPU affinity levels 0-3 */
#define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff)
#define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff)
#define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff)
#define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff)
#define CPU_AFF0_MASK 0xffUL
#define CPU_AFF1_MASK 0xff00UL
#define CPU_AFF2_MASK 0xff0000UL
#define CPU_AFF3_MASK 0xff00000000UL
#define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \
CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */
#ifdef _KERNEL
#define CPU_IMPL_ARM 0x41
#define CPU_IMPL_BROADCOM 0x42
#define CPU_IMPL_CAVIUM 0x43
#define CPU_IMPL_DEC 0x44
#define CPU_IMPL_FUJITSU 0x46
#define CPU_IMPL_INFINEON 0x49
#define CPU_IMPL_FREESCALE 0x4D
#define CPU_IMPL_NVIDIA 0x4E
#define CPU_IMPL_APM 0x50
#define CPU_IMPL_QUALCOMM 0x51
#define CPU_IMPL_MARVELL 0x56
#define CPU_IMPL_APPLE 0x61
#define CPU_IMPL_INTEL 0x69
#define CPU_IMPL_AMPERE 0xC0
/* ARM Part numbers */
#define CPU_PART_FOUNDATION 0xD00
#define CPU_PART_CORTEX_A34 0xD02
#define CPU_PART_CORTEX_A53 0xD03
#define CPU_PART_CORTEX_A35 0xD04
#define CPU_PART_CORTEX_A55 0xD05
#define CPU_PART_CORTEX_A65 0xD06
#define CPU_PART_CORTEX_A57 0xD07
#define CPU_PART_CORTEX_A72 0xD08
#define CPU_PART_CORTEX_A73 0xD09
#define CPU_PART_CORTEX_A75 0xD0A
#define CPU_PART_CORTEX_A76 0xD0B
#define CPU_PART_NEOVERSE_N1 0xD0C
#define CPU_PART_CORTEX_A77 0xD0D
#define CPU_PART_CORTEX_A76AE 0xD0E
#define CPU_PART_AEM_V8 0xD0F
#define CPU_PART_NEOVERSE_V1 0xD40
#define CPU_PART_CORTEX_A78 0xD41
#define CPU_PART_CORTEX_A65AE 0xD43
#define CPU_PART_CORTEX_X1 0xD44
#define CPU_PART_CORTEX_A510 0xD46
#define CPU_PART_CORTEX_A710 0xD47
#define CPU_PART_CORTEX_X2 0xD48
#define CPU_PART_NEOVERSE_N2 0xD49
#define CPU_PART_NEOVERSE_E1 0xD4A
#define CPU_PART_CORTEX_A78C 0xD4B
#define CPU_PART_CORTEX_X1C 0xD4C
#define CPU_PART_CORTEX_A715 0xD4D
#define CPU_PART_CORTEX_X3 0xD4E
#define CPU_PART_NEOVERSE_V2 0xD4F
/* Cavium Part numbers */
#define CPU_PART_THUNDERX 0x0A1
#define CPU_PART_THUNDERX_81XX 0x0A2
#define CPU_PART_THUNDERX_83XX 0x0A3
#define CPU_PART_THUNDERX2 0x0AF
#define CPU_REV_THUNDERX_1_0 0x00
#define CPU_REV_THUNDERX_1_1 0x01
#define CPU_REV_THUNDERX2_0 0x00
/* APM / Ampere Part Number */
#define CPU_PART_EMAG8180 0x000
/* Qualcomm */
#define CPU_PART_KRYO400_GOLD 0x804
#define CPU_PART_KRYO400_SILVER 0x805
/* Apple part numbers */
#define CPU_PART_M1_ICESTORM 0x022
#define CPU_PART_M1_FIRESTORM 0x023
#define CPU_PART_M1_ICESTORM_PRO 0x024
#define CPU_PART_M1_FIRESTORM_PRO 0x025
#define CPU_PART_M1_ICESTORM_MAX 0x028
#define CPU_PART_M1_FIRESTORM_MAX 0x029
#define CPU_PART_M2_BLIZZARD 0x032
#define CPU_PART_M2_AVALANCHE 0x033
#define CPU_PART_M2_BLIZZARD_PRO 0x034
#define CPU_PART_M2_AVALANCHE_PRO 0x035
#define CPU_PART_M2_BLIZZARD_MAX 0x038
#define CPU_PART_M2_AVALANCHE_MAX 0x039
#define CPU_IMPL(midr) (((midr) >> 24) & 0xff)
#define CPU_PART(midr) (((midr) >> 4) & 0xfff)
#define CPU_VAR(midr) (((midr) >> 20) & 0xf)
#define CPU_ARCH(midr) (((midr) >> 16) & 0xf)
#define CPU_REV(midr) (((midr) >> 0) & 0xf)
#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24)
#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4)
#define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20)
#define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16)
#define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0)
#define CPU_IMPL_MASK (0xff << 24)
#define CPU_PART_MASK (0xfff << 4)
#define CPU_VAR_MASK (0xf << 20)
#define CPU_ARCH_MASK (0xf << 16)
#define CPU_REV_MASK (0xf << 0)
#define CPU_ID_RAW(impl, part, var, rev) \
(CPU_IMPL_TO_MIDR((impl)) | \
CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \
CPU_REV_TO_MIDR((rev)))
#define CPU_MATCH(mask, impl, part, var, rev) \
(((mask) & PCPU_GET(midr)) == \
((mask) & CPU_ID_RAW((impl), (part), (var), (rev))))
#define CPU_MATCH_RAW(mask, devid) \
(((mask) & PCPU_GET(midr)) == ((mask) & (devid)))
/*
* Chip-specific errata. This defines are intended to be
* booleans used within if statements. When an appropriate
* kernel option is disabled, these defines must be defined
* as 0 to allow the compiler to remove a dead code thus
* produce better optimized kernel image.
*/
/*
* Vendor: Cavium
* Chip: ThunderX
* Revision(s): Pass 1.0, Pass 1.1
*/
#ifdef THUNDERX_PASS_1_1_ERRATA
#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \
(CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \
CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \
CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \
CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1))
#else
#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0
#endif
#if !defined(__ASSEMBLER__)
extern char btext[];
extern char etext[];
extern uint64_t __cpu_affinity[];
struct arm64_addr_mask;
extern struct arm64_addr_mask elf64_addr_mask;
void cpu_halt(void) __dead2;
void cpu_reset(void) __dead2;
void fork_trampoline(void);
void identify_cache(uint64_t);
void identify_cpu(u_int);
void install_cpu_errata(void);
/* Pointer Authentication Code (PAC) support */
void ptrauth_init(void);
void ptrauth_fork(struct thread *, struct thread *);
void ptrauth_exec(struct thread *);
void ptrauth_copy_thread(struct thread *, struct thread *);
void ptrauth_thread_alloc(struct thread *);
void ptrauth_thread0(struct thread *);
#ifdef SMP
void ptrauth_mp_start(uint64_t);
#endif
/* Functions to read the sanitised view of the special registers */
void update_special_regs(u_int);
bool extract_user_id_field(u_int, u_int, uint8_t *);
bool get_kernel_reg(u_int, uint64_t *);
bool get_kernel_reg_masked(u_int, uint64_t *, uint64_t);
void cpu_desc_init(void);
#define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)]
#define CPU_CURRENT_SOCKET \
(CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid))))
static __inline uint64_t
get_cyclecount(void)
{
uint64_t ret;
ret = READ_SPECIALREG(cntvct_el0);
return (ret);
}
#define ADDRESS_TRANSLATE_FUNC(stage) \
static inline uint64_t \
arm64_address_translate_ ##stage (uint64_t addr) \
{ \
uint64_t ret; \
\
__asm __volatile( \
"at " __STRING(stage) ", %1 \n" \
"isb \n" \
"mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \
\
return (ret); \
}
ADDRESS_TRANSLATE_FUNC(s1e0r)
ADDRESS_TRANSLATE_FUNC(s1e0w)
ADDRESS_TRANSLATE_FUNC(s1e1r)
ADDRESS_TRANSLATE_FUNC(s1e1w)
#endif /* !__ASSEMBLER__ */
#endif
#endif /* !_MACHINE_CPU_H_ */
#endif /* !__arm__ */

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/*-
* Copyright (c) 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef __arm__
#include <arm/cpufunc.h>
#else /* !__arm__ */
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
static __inline void
breakpoint(void)
{
__asm("brk #0");
}
#ifdef _KERNEL
#include <machine/armreg.h>
void pan_enable(void);
static __inline register_t
dbg_disable(void)
{
uint32_t ret;
__asm __volatile(
"mrs %x0, daif \n"
"msr daifset, #(" __XSTRING(DAIF_D) ") \n"
: "=&r" (ret));
return (ret);
}
static __inline void
dbg_enable(void)
{
__asm __volatile("msr daifclr, #(" __XSTRING(DAIF_D) ")");
}
static __inline register_t
intr_disable(void)
{
/* DAIF is a 32-bit register */
uint32_t ret;
__asm __volatile(
"mrs %x0, daif \n"
"msr daifset, #(" __XSTRING(DAIF_INTR) ") \n"
: "=&r" (ret));
return (ret);
}
static __inline void
intr_restore(register_t s)
{
WRITE_SPECIALREG(daif, s);
}
static __inline void
intr_enable(void)
{
__asm __volatile("msr daifclr, #(" __XSTRING(DAIF_INTR) ")");
}
static __inline void
serror_enable(void)
{
__asm __volatile("msr daifclr, #(" __XSTRING(DAIF_A) ")");
}
static __inline register_t
get_midr(void)
{
uint64_t midr;
midr = READ_SPECIALREG(midr_el1);
return (midr);
}
static __inline register_t
get_mpidr(void)
{
uint64_t mpidr;
mpidr = READ_SPECIALREG(mpidr_el1);
return (mpidr);
}
static __inline void
clrex(void)
{
/*
* Ensure compiler barrier, otherwise the monitor clear might
* occur too late for us ?
*/
__asm __volatile("clrex" : : : "memory");
}
static __inline void
set_ttbr0(uint64_t ttbr0)
{
__asm __volatile(
"msr ttbr0_el1, %0 \n"
"isb \n"
:
: "r" (ttbr0));
}
static __inline void
invalidate_icache(void)
{
__asm __volatile(
"ic ialluis \n"
"dsb ish \n"
"isb \n");
}
static __inline void
invalidate_local_icache(void)
{
__asm __volatile(
"ic iallu \n"
"dsb nsh \n"
"isb \n");
}
extern bool icache_aliasing;
extern bool icache_vmid;
extern int64_t dcache_line_size;
extern int64_t icache_line_size;
extern int64_t idcache_line_size;
extern int64_t dczva_line_size;
#define cpu_nullop() arm64_nullop()
#define cpufunc_nullop() arm64_nullop()
#define cpu_tlb_flushID() arm64_tlb_flushID()
#define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s))
#define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
#define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))
extern void (*arm64_icache_sync_range)(vm_offset_t, vm_size_t);
#define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
#define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s))
void arm64_nullop(void);
void arm64_tlb_flushID(void);
void arm64_dic_idc_icache_sync_range(vm_offset_t, vm_size_t);
void arm64_idc_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
void arm64_aliasing_icache_sync_range(vm_offset_t, vm_size_t);
int arm64_icache_sync_range_checked(vm_offset_t, vm_size_t);
void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
bool arm64_get_writable_addr(vm_offset_t, vm_offset_t *);
#endif /* _KERNEL */
#endif /* _MACHINE_CPUFUNC_H_ */
#endif /* !__arm__ */

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lib/libc/include/aarch64-freebsd-none/machine/cpuinfo.h vendored Normal file
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#ifdef __arm__
#include <arm/cpuinfo.h>
#else /* !__arm__ */
#error Do not include this header, used only for 32-bit compatibility
#endif /* !__arm__ */

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/* $NetBSD: csan.h,v 1.2 2019/11/06 06:57:22 maxv Exp $ */
/*
* Copyright (c) 2019 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Maxime Villard.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <machine/cpufunc.h>
#include <machine/stack.h>
#include <machine/vmparam.h>
static inline bool
kcsan_md_unsupported(vm_offset_t addr)
{
return false;
}
static inline bool
kcsan_md_is_avail(void)
{
return true;
}
static inline void
kcsan_md_disable_intrs(uint64_t *state)
{
*state = intr_disable();
}
static inline void
kcsan_md_enable_intrs(uint64_t *state)
{
intr_restore(*state);
}
static inline void
kcsan_md_delay(uint64_t us)
{
DELAY(us);
}
static void
kcsan_md_unwind(void)
{
#ifdef DDB
c_db_sym_t sym;
db_expr_t offset;
const char *symname;
#endif
struct unwind_state frame;
int nsym;
frame.fp = (uintptr_t)__builtin_frame_address(0);
frame.pc = (uintptr_t)kcsan_md_unwind;
nsym = 0;
while (1) {
if (!unwind_frame(curthread, &frame))
break;
if (!INKERNEL((vm_offset_t)frame.pc))
break;
#ifdef DDB
sym = db_search_symbol((vm_offset_t)frame.pc, DB_STGY_PROC,
&offset);
db_symbol_values(sym, &symname, NULL);
printf("#%d %p in %s+%#lx\n", nsym, (void *)frame.pc,
symname, offset);
#else
printf("#%d %p\n", nsym, (void *)frame.pc);
#endif
nsym++;
if (nsym >= 15) {
break;
}
}
}

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/*-
* Copyright (c) 2014 Andrew Turner
* Copyright (c) 2014-2015 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Semihalf under
* sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_DB_MACHDEP_H_
#define _MACHINE_DB_MACHDEP_H_
#include <machine/armreg.h>
#include <machine/frame.h>
#include <machine/trap.h>
#define T_BREAKPOINT (EXCP_BRK)
#define T_HW_BREAKPOINT (EXCP_BRKPT_EL1)
#define T_SINGLESTEP (EXCP_SOFTSTP_EL1)
#define T_WATCHPOINT (EXCP_WATCHPT_EL1)
typedef vm_offset_t db_addr_t;
typedef long db_expr_t;
#define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_x[PCB_LR])
#define BKPT_INST (0xd4200000)
#define BKPT_SIZE (4)
#define BKPT_SET(inst) (BKPT_INST)
#define BKPT_SKIP do { \
kdb_frame->tf_elr += BKPT_SIZE; \
kdb_thrctx->pcb_x[PCB_LR] += BKPT_SIZE; \
} while (0)
#define db_clear_single_step kdb_cpu_clear_singlestep
#define db_set_single_step kdb_cpu_set_singlestep
#define IS_BREAKPOINT_TRAP(type, code) \
(type == T_BREAKPOINT || type == T_HW_BREAKPOINT)
#define IS_SSTEP_TRAP(type, code) (type == T_SINGLESTEP)
#define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT)
#define inst_trap_return(ins) (0)
/* ret */
#define inst_return(ins) (((ins) & 0xfffffc1fu) == 0xd65f0000)
#define inst_call(ins) (((ins) & 0xfc000000u) == 0x94000000u || /* BL */ \
((ins) & 0xfffffc1fu) == 0xd63f0000u) /* BLR */
#define inst_load(ins) ({ \
uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
is_load_instr(tmp_instr); \
})
#define inst_store(ins) ({ \
uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
is_store_instr(tmp_instr); \
})
#define is_load_instr(ins) ((((ins) & 0x3b000000u) == 0x18000000u) || /* literal */ \
(((ins) & 0x3f400000u) == 0x08400000u) || /* exclusive */ \
(((ins) & 0x3bc00000u) == 0x28400000u) || /* no-allocate pair */ \
((((ins) & 0x3b200c00u) == 0x38000400u) && \
(((ins) & 0x3be00c00u) != 0x38000400u) && \
(((ins) & 0xffe00c00u) != 0x3c800400u)) || /* immediate post-indexed */ \
((((ins) & 0x3b200c00u) == 0x38000c00u) && \
(((ins) & 0x3be00c00u) != 0x38000c00u) && \
(((ins) & 0xffe00c00u) != 0x3c800c00u)) || /* immediate pre-indexed */ \
((((ins) & 0x3b200c00u) == 0x38200800u) && \
(((ins) & 0x3be00c00u) != 0x38200800u) && \
(((ins) & 0xffe00c00u) != 0x3ca00c80u)) || /* register offset */ \
((((ins) & 0x3b200c00u) == 0x38000800u) && \
(((ins) & 0x3be00c00u) != 0x38000800u)) || /* unprivileged */ \
((((ins) & 0x3b200c00u) == 0x38000000u) && \
(((ins) & 0x3be00c00u) != 0x38000000u) && \
(((ins) & 0xffe00c00u) != 0x3c800000u)) || /* unscaled immediate */ \
((((ins) & 0x3b000000u) == 0x39000000u) && \
(((ins) & 0x3bc00000u) != 0x39000000u) && \
(((ins) & 0xffc00000u) != 0x3d800000u)) || /* unsigned immediate */ \
(((ins) & 0x3bc00000u) == 0x28400000u) || /* pair (offset) */ \
(((ins) & 0x3bc00000u) == 0x28c00000u) || /* pair (post-indexed) */ \
(((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
#define is_store_instr(ins) ((((ins) & 0x3f400000u) == 0x08000000u) || /* exclusive */ \
(((ins) & 0x3bc00000u) == 0x28000000u) || /* no-allocate pair */ \
((((ins) & 0x3be00c00u) == 0x38000400u) || \
(((ins) & 0xffe00c00u) == 0x3c800400u)) || /* immediate post-indexed */ \
((((ins) & 0x3be00c00u) == 0x38000c00u) || \
(((ins) & 0xffe00c00u) == 0x3c800c00u)) || /* immediate pre-indexed */ \
((((ins) & 0x3be00c00u) == 0x38200800u) || \
(((ins) & 0xffe00c00u) == 0x3ca00800u)) || /* register offset */ \
(((ins) & 0x3be00c00u) == 0x38000800u) || /* unprivileged */ \
((((ins) & 0x3be00c00u) == 0x38000000u) || \
(((ins) & 0xffe00c00u) == 0x3c800000u)) || /* unscaled immediate */ \
((((ins) & 0x3bc00000u) == 0x39000000u) || \
(((ins) & 0xffc00000u) == 0x3d800000u)) || /* unsigned immediate */ \
(((ins) & 0x3bc00000u) == 0x28000000u) || /* pair (offset) */ \
(((ins) & 0x3bc00000u) == 0x28800000u) || /* pair (post-indexed) */ \
(((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4))
#define DB_ELFSIZE 64
#endif /* !_MACHINE_DB_MACHDEP_H_ */

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