From 7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2 Mon Sep 17 00:00:00 2001
From: joachimschmidt557 <joachim.schmidt557@outlook.com>
Date: Sat, 19 Mar 2022 19:48:27 +0100
Subject: [PATCH] stage2 RISCV64: implement move register to register

---
 src/arch/riscv64/CodeGen.zig | 14 ++++++++++++++
 src/arch/riscv64/Emit.zig    | 11 +++++++++++
 src/arch/riscv64/Mir.zig     |  8 ++++++++
 3 files changed, 33 insertions(+)

diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
index 65983a5661..36c1752e5d 100644
--- a/src/arch/riscv64/CodeGen.zig
+++ b/src/arch/riscv64/CodeGen.zig
@@ -2074,6 +2074,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
                 return self.fail("TODO genSetReg 33-64 bit immediates for riscv64", .{}); // glhf
             }
         },
+        .register => |src_reg| {
+            // If the registers are the same, nothing to do.
+            if (src_reg.id() == reg.id())
+                return;
+
+            // mov reg, src_reg
+            _ = try self.addInst(.{
+                .tag = .mv,
+                .data = .{ .rr = .{
+                    .rd = reg,
+                    .rs = src_reg,
+                } },
+            });
+        },
         .memory => |addr| {
             // The value is in memory at a hard-coded address.
             // If the type is a pointer, it means the pointer address is at this memory location.
diff --git a/src/arch/riscv64/Emit.zig b/src/arch/riscv64/Emit.zig
index 840247cf80..10eace940e 100644
--- a/src/arch/riscv64/Emit.zig
+++ b/src/arch/riscv64/Emit.zig
@@ -56,6 +56,8 @@ pub fn emitMir(
             .dbg_prologue_end => try emit.mirDebugPrologueEnd(),
             .dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
 
+            .mv => try emit.mirRR(inst),
+
             .nop => try emit.mirNop(inst),
             .ret => try emit.mirNop(inst),
 
@@ -186,6 +188,15 @@ fn mirDebugEpilogueBegin(self: *Emit) !void {
     }
 }
 
+fn mirRR(emit: *Emit, inst: Mir.Inst.Index) !void {
+    const tag = emit.mir.instructions.items(.tag)[inst];
+    const rr = emit.mir.instructions.items(.data)[inst].rr;
+
+    switch (tag) {
+        .mv => try emit.writeInstruction(Instruction.addi(rr.rd, rr.rs, 0)),
+        else => unreachable,
+    }
+}
 fn mirUType(emit: *Emit, inst: Mir.Inst.Index) !void {
     const tag = emit.mir.instructions.items(.tag)[inst];
     const u_type = emit.mir.instructions.items(.data)[inst].u_type;
diff --git a/src/arch/riscv64/Mir.zig b/src/arch/riscv64/Mir.zig
index 70546e0803..60e8af2117 100644
--- a/src/arch/riscv64/Mir.zig
+++ b/src/arch/riscv64/Mir.zig
@@ -36,6 +36,7 @@ pub const Inst = struct {
         jalr,
         ld,
         lui,
+        mv,
         nop,
         ret,
         sd,
@@ -68,6 +69,13 @@ pub const Inst = struct {
         ///
         /// Used by e.g. blr
         reg: Register,
+        /// Two registers
+        ///
+        /// Used by e.g. mv
+        rr: struct {
+            rd: Register,
+            rs: Register,
+        },
         /// I-Type
         ///
         /// Used by e.g. jalr