From 77abd3a96aa8c8c1277cdbb33d88149d4674d389 Mon Sep 17 00:00:00 2001 From: Jacob Young Date: Tue, 16 Apr 2024 15:04:41 -0400 Subject: [PATCH] x86_64: fix miscompilation regression in package fetching code --- src/arch/x86_64/CodeGen.zig | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index c165baf7e8..9e18dbb42e 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -15050,10 +15050,11 @@ fn genSetMem( .general_purpose, .segment, .x87 => @divExact(src_alias.bitSize(), 8), .mmx, .sse => abi_size, }); + const src_align = Alignment.fromNonzeroByteUnits(math.ceilPowerOfTwoAssert(u32, src_size)); if (src_size > mem_size) { const frame_index = try self.allocFrameIndex(FrameAlloc.init(.{ .size = src_size, - .alignment = Alignment.fromNonzeroByteUnits(src_size), + .alignment = src_align, })); const frame_mcv: MCValue = .{ .load_frame = .{ .index = frame_index } }; try (try self.moveStrategy(ty, src_alias.class(), true)).write( @@ -15066,14 +15067,15 @@ fn genSetMem( try self.genSetMem(base, disp, ty, frame_mcv, opts); try self.freeValue(frame_mcv); } else try (try self.moveStrategy(ty, src_alias.class(), switch (base) { - .none => ty.abiAlignment(mod).check(@as(u32, @bitCast(disp))), + .none => src_align.check(@as(u32, @bitCast(disp))), .reg => |reg| switch (reg) { - .es, .cs, .ss, .ds => ty.abiAlignment(mod).check(@as(u32, @bitCast(disp))), + .es, .cs, .ss, .ds => src_align.check(@as(u32, @bitCast(disp))), else => false, }, - .frame => |frame_index| self.getFrameAddrAlignment( - .{ .index = frame_index, .off = disp }, - ).compare(.gte, ty.abiAlignment(mod)), + .frame => |frame_index| self.getFrameAddrAlignment(.{ + .index = frame_index, + .off = disp, + }).compare(.gte, src_align), .reloc => false, })).write( self,