mirror of
https://github.com/ziglang/zig.git
synced 2026-02-04 13:43:46 +00:00
stage2: use correct register alias for mem operands
When loading/storing on the stack, use `registerAlias` to correctly workout the size of the register and thus correctly select target instruction.
This commit is contained in:
parent
00966b7258
commit
7747bf07c7
@ -1545,7 +1545,7 @@ fn genBinMathOpMir(
|
||||
_ = try self.addInst(.{
|
||||
.tag = mir_tag,
|
||||
.ops = (Mir.Ops{
|
||||
.reg1 = dst_reg,
|
||||
.reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
|
||||
.reg2 = .ebp,
|
||||
.flags = 0b01,
|
||||
}).encode(),
|
||||
@ -1576,7 +1576,7 @@ fn genBinMathOpMir(
|
||||
_ = try self.addInst(.{
|
||||
.tag = mir_tag,
|
||||
.ops = (Mir.Ops{
|
||||
.reg1 = src_reg,
|
||||
.reg1 = registerAlias(src_reg, @intCast(u32, abi_size)),
|
||||
.reg2 = .ebp,
|
||||
.flags = 0b10,
|
||||
}).encode(),
|
||||
@ -2749,7 +2749,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
|
||||
_ = try self.addInst(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{
|
||||
.reg1 = reg,
|
||||
.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
|
||||
.reg2 = .ebp,
|
||||
.flags = 0b10,
|
||||
}).encode(),
|
||||
@ -2970,7 +2970,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
|
||||
_ = try self.addInst(.{
|
||||
.tag = .mov,
|
||||
.ops = (Mir.Ops{
|
||||
.reg1 = reg,
|
||||
.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
|
||||
.reg2 = .ebp,
|
||||
.flags = 0b01,
|
||||
}).encode(),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user