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replace most aggregate interns in x86_64/CodeGen
This commit is contained in:
Justus Klausecker
parent
79e5c138c6
commit
76d2782149
@ -170058,12 +170058,9 @@ fn airTrunc(self: *CodeGen, inst: Air.Inst.Index) !void {
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});
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const splat_abi_size: u32 = @intCast(splat_ty.abiSize(zcu));
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const splat_val = try pt.intern(.{ .aggregate = .{
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.ty = splat_ty.ip_index,
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.storage = .{ .repeated_elem = mask_val.ip_index },
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} });
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const splat_val = try pt.aggregateSplatValue(splat_ty, mask_val);
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const splat_mcv = try self.lowerValue(.fromInterned(splat_val));
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const splat_mcv = try self.lowerValue(splat_val);
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const splat_addr_mcv: MCValue = switch (splat_mcv) {
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.memory, .indirect, .load_frame => splat_mcv.address(),
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else => .{ .register = try self.copyToTmpRegister(.usize, splat_mcv.address()) },
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@ -171693,12 +171690,12 @@ fn airShlShrBinOp(self: *CodeGen, inst: Air.Inst.Index) !void {
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defer self.register_manager.unlockReg(shift_lock);
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const mask_ty = try pt.vectorType(.{ .len = 16, .child = .u8_type });
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const mask_mcv = try self.lowerValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = mask_ty.toIntern(),
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.storage = .{ .elems = &([1]InternPool.Index{
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const mask_mcv = try self.lowerValue(try pt.aggregateValue(
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mask_ty,
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&([1]InternPool.Index{
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(try rhs_ty.childType(zcu).maxIntScalar(pt, .u8)).toIntern(),
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} ++ [1]InternPool.Index{.zero_u8} ** 15) },
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} })));
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} ++ [1]InternPool.Index{.zero_u8} ** 15),
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));
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const mask_addr_reg = try self.copyToTmpRegister(.usize, mask_mcv.address());
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const mask_addr_lock = self.register_manager.lockRegAssumeUnused(mask_addr_reg);
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defer self.register_manager.unlockReg(mask_addr_lock);
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@ -181139,10 +181136,7 @@ fn genSetReg(
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.child = .u8_type,
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});
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try self.genSetReg(dst_reg, full_ty, try self.lowerValue(
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.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = full_ty.toIntern(),
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.storage = .{ .repeated_elem = (try pt.intValue(.u8, 0xaa)).toIntern() },
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} })),
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try pt.aggregateSplatValue(full_ty, try pt.intValue(.u8, 0xaa)),
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), opts);
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},
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.x87 => try self.genSetReg(dst_reg, .f80, try self.lowerValue(
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@ -183565,10 +183559,7 @@ fn airSelect(self: *CodeGen, inst: Air.Inst.Index) !void {
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mask_elem_ty,
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@as(u8, 1) << @truncate(bit),
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)).toIntern();
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const mask_mcv = try self.lowerValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = mask_ty.toIntern(),
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.storage = .{ .elems = mask_elems },
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} })));
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const mask_mcv = try self.lowerValue(try pt.aggregateValue(mask_ty, mask_elems));
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const mask_mem: Memory = .{
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.base = .{ .reg = try self.copyToTmpRegister(.usize, mask_mcv.address()) },
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.mod = .{ .rm = .{ .size = self.memSize(ty) } },
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@ -184296,10 +184287,9 @@ fn airShuffle(self: *CodeGen, inst: Air.Inst.Index) !void {
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else
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try select_mask_elem_ty.minIntScalar(pt, select_mask_elem_ty)).toIntern();
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}
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const select_mask_mcv = try self.lowerValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = select_mask_ty.toIntern(),
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.storage = .{ .elems = select_mask_elems[0..mask_elems.len] },
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} })));
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const select_mask_mcv = try self.lowerValue(
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try pt.aggregateValue(select_mask_ty, select_mask_elems[0..mask_elems.len]),
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);
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if (self.hasFeature(.sse4_1)) {
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const mir_tag: Mir.Inst.FixedTag = .{
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@ -184441,10 +184431,9 @@ fn airShuffle(self: *CodeGen, inst: Air.Inst.Index) !void {
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})).toIntern();
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}
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const lhs_mask_ty = try pt.vectorType(.{ .len = max_abi_size, .child = .u8_type });
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const lhs_mask_mcv = try self.lowerValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = lhs_mask_ty.toIntern(),
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.storage = .{ .elems = lhs_mask_elems[0..max_abi_size] },
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} })));
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const lhs_mask_mcv = try self.lowerValue(
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try pt.aggregateValue(lhs_mask_ty, lhs_mask_elems[0..max_abi_size]),
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);
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const lhs_mask_mem: Memory = .{
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.base = .{ .reg = try self.copyToTmpRegister(.usize, lhs_mask_mcv.address()) },
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.mod = .{ .rm = .{ .size = .fromSize(@max(max_abi_size, 16)) } },
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@ -184472,10 +184461,9 @@ fn airShuffle(self: *CodeGen, inst: Air.Inst.Index) !void {
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})).toIntern();
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}
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const rhs_mask_ty = try pt.vectorType(.{ .len = max_abi_size, .child = .u8_type });
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const rhs_mask_mcv = try self.lowerValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = rhs_mask_ty.toIntern(),
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.storage = .{ .elems = rhs_mask_elems[0..max_abi_size] },
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} })));
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const rhs_mask_mcv = try self.lowerValue(
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try pt.aggregateValue(rhs_mask_ty, rhs_mask_elems[0..max_abi_size]),
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);
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const rhs_mask_mem: Memory = .{
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.base = .{ .reg = try self.copyToTmpRegister(.usize, rhs_mask_mcv.address()) },
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.mod = .{ .rm = .{ .size = .fromSize(@max(max_abi_size, 16)) } },
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@ -192924,36 +192912,30 @@ const Select = struct {
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break :res_scalar .{ res_scalar_ty, try pt.intValue_big(res_scalar_ty, res_big_int.toConst()) };
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},
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};
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const res_val: Value = if (res_vector_len) |len| .fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = (try pt.vectorType(.{
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.len = len,
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.child = res_scalar_ty.toIntern(),
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})).toIntern(),
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.storage = .{ .repeated_elem = res_scalar_val.toIntern() },
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} })) else res_scalar_val;
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const res_val = if (res_vector_len) |len| try pt.aggregateSplatValue(try pt.vectorType(.{
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.len = len,
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.child = res_scalar_ty.toIntern(),
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}), res_scalar_val) else res_scalar_val;
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return .{ try cg.tempMemFromValue(res_val), true };
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},
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.f64_0x1p52_0x1p84_mem => .{ try cg.tempMemFromValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = (try pt.vectorType(.{ .len = 2, .child = .f64_type })).toIntern(),
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.storage = .{ .elems = &.{
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.f64_0x1p52_0x1p84_mem => .{ try cg.tempMemFromValue(
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try pt.aggregateValue(try pt.vectorType(.{ .len = 2, .child = .f64_type }), &.{
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(try pt.floatValue(.f64, @as(f64, 0x1p52))).toIntern(),
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(try pt.floatValue(.f64, @as(f64, 0x1p84))).toIntern(),
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} },
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} }))), true },
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.u32_0x1p52_hi_0x1p84_hi_0_0_mem => .{ try cg.tempMemFromValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = (try pt.vectorType(.{ .len = 4, .child = .u32_type })).toIntern(),
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.storage = .{ .elems = &(.{
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}),
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), true },
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.u32_0x1p52_hi_0x1p84_hi_0_0_mem => .{ try cg.tempMemFromValue(
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try pt.aggregateValue(try pt.vectorType(.{ .len = 4, .child = .u32_type }), &(.{
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(try pt.intValue(.u32, @as(u64, @bitCast(@as(f64, 0x1p52))) >> 32)).toIntern(),
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(try pt.intValue(.u32, @as(u64, @bitCast(@as(f64, 0x1p84))) >> 32)).toIntern(),
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} ++ .{(try pt.intValue(.u32, 0)).toIntern()} ** 2) },
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} }))), true },
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.f32_0_0x1p64_mem => .{ try cg.tempMemFromValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = (try pt.vectorType(.{ .len = 2, .child = .f32_type })).toIntern(),
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.storage = .{ .elems = &.{
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} ++ .{(try pt.intValue(.u32, 0)).toIntern()} ** 2)),
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), true },
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.f32_0_0x1p64_mem => .{ try cg.tempMemFromValue(
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try pt.aggregateValue(try pt.vectorType(.{ .len = 2, .child = .f32_type }), &.{
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(try pt.floatValue(.f32, @as(f32, 0))).toIntern(),
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(try pt.floatValue(.f32, @as(f32, 0x1p64))).toIntern(),
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} },
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} }))), true },
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}),
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), true },
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.pshufb_splat_mem => |splat_spec| {
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const zcu = pt.zcu;
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assert(spec.type.isVector(zcu) and spec.type.childType(zcu).toIntern() == .u8_type);
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@ -193110,13 +193092,10 @@ const Select = struct {
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const mem_size = cg.unalignedSize(spec.type);
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return .{ try cg.tempMemFromAlignedValue(
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if (mem_size < 16) .fromByteUnits(mem_size) else .none,
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.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = if (mem_size < 16)
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(try pt.arrayType(.{ .len = elems.len, .child = elem_ty.toIntern() })).toIntern()
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else
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spec.type.toIntern(),
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.storage = .{ .elems = elems },
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} })),
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try pt.aggregateValue(if (mem_size < 16) try pt.arrayType(.{
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.len = elems.len,
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.child = elem_ty.toIntern(),
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}) else spec.type, elems),
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), true };
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},
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.splat_float_mem => |splat_spec| {
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@ -193133,10 +193112,7 @@ const Select = struct {
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.zero => 0.0,
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}))).toIntern());
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@memset(elems[inside_len..], (try pt.floatValue(elem_ty, splat_spec.outside)).toIntern());
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return .{ try cg.tempMemFromValue(.fromInterned(try pt.intern(.{ .aggregate = .{
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.ty = spec.type.toIntern(),
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.storage = .{ .elems = elems },
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} }))), true };
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return .{ try cg.tempMemFromValue(try pt.aggregateValue(spec.type, elems)), true };
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},
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.frame => |frame_index| .{ try cg.tempInit(spec.type, .{ .load_frame = .{
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.index = frame_index,
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