From 75d1b113aa6adf983497a78a0a0e61ecac7aaa54 Mon Sep 17 00:00:00 2001 From: Martin Wickham Date: Sat, 10 Jul 2021 21:47:07 -0500 Subject: [PATCH] Rename IrInstSrc to Stage1ZirInst and IrInstGen to Stage1AirInst --- src/stage1/all_types.hpp | 2188 +++++++++---------- src/stage1/analyze.cpp | 46 +- src/stage1/analyze.hpp | 2 +- src/stage1/astgen.cpp | 3138 +++++++++++++------------- src/stage1/astgen.hpp | 6 +- src/stage1/codegen.cpp | 602 ++--- src/stage1/ir.cpp | 4492 +++++++++++++++++++------------------- src/stage1/ir.hpp | 4 +- src/stage1/ir_print.cpp | 1910 ++++++++-------- src/stage1/ir_print.hpp | 10 +- 10 files changed, 6199 insertions(+), 6199 deletions(-) diff --git a/src/stage1/all_types.hpp b/src/stage1/all_types.hpp index 32550132e6..fa201f6bdf 100644 --- a/src/stage1/all_types.hpp +++ b/src/stage1/all_types.hpp @@ -31,14 +31,14 @@ struct BuiltinFnEntry; struct TypeStructField; struct CodeGen; struct ZigValue; -struct IrInstSrc; -struct IrInstGen; -struct IrInstGenCast; -struct IrInstGenAlloca; -struct IrInstGenCall; -struct IrInstGenAwait; +struct Stage1ZirInst; +struct Stage1AirInst; +struct Stage1AirInstCast; +struct Stage1AirInstAlloca; +struct Stage1AirInstCall; +struct Stage1AirInstAwait; struct Stage1ZirBasicBlock; -struct IrBasicBlockGen; +struct Stage1AirBasicBlock; struct ScopeDecls; struct ZigWindowsSDK; struct Tld; @@ -122,7 +122,7 @@ struct Stage1Zir { }; struct Stage1Air { - ZigList basic_block_list; + ZigList basic_block_list; Buf *name; ZigFn *name_fn; size_t mem_slot_count; @@ -311,7 +311,7 @@ struct ConstErrValue { struct ConstBoundFnValue { ZigFn *fn; - IrInstGen *first_arg; + Stage1AirInst *first_arg; AstNode *first_arg_src; }; @@ -400,14 +400,14 @@ struct LazyValueAlignOf { LazyValue base; IrAnalyze *ira; - IrInstGen *target_type; + Stage1AirInst *target_type; }; struct LazyValueSizeOf { LazyValue base; IrAnalyze *ira; - IrInstGen *target_type; + Stage1AirInst *target_type; bool bit_size; }; @@ -416,9 +416,9 @@ struct LazyValueSliceType { LazyValue base; IrAnalyze *ira; - IrInstGen *sentinel; // can be null - IrInstGen *elem_type; - IrInstGen *align_inst; // can be null + Stage1AirInst *sentinel; // can be null + Stage1AirInst *elem_type; + Stage1AirInst *align_inst; // can be null bool is_const; bool is_volatile; @@ -429,8 +429,8 @@ struct LazyValueArrayType { LazyValue base; IrAnalyze *ira; - IrInstGen *sentinel; // can be null - IrInstGen *elem_type; + Stage1AirInst *sentinel; // can be null + Stage1AirInst *elem_type; uint64_t length; }; @@ -438,9 +438,9 @@ struct LazyValuePtrType { LazyValue base; IrAnalyze *ira; - IrInstGen *sentinel; // can be null - IrInstGen *elem_type; - IrInstGen *align_inst; // can be null + Stage1AirInst *sentinel; // can be null + Stage1AirInst *elem_type; + Stage1AirInst *align_inst; // can be null PtrLen ptr_len; uint32_t bit_offset_in_host; @@ -455,14 +455,14 @@ struct LazyValuePtrTypeSimple { LazyValue base; IrAnalyze *ira; - IrInstGen *elem_type; + Stage1AirInst *elem_type; }; struct LazyValueOptType { LazyValue base; IrAnalyze *ira; - IrInstGen *payload_type; + Stage1AirInst *payload_type; }; struct LazyValueFnType { @@ -470,9 +470,9 @@ struct LazyValueFnType { IrAnalyze *ira; AstNode *proto_node; - IrInstGen **param_types; - IrInstGen *align_inst; // can be null - IrInstGen *return_type; + Stage1AirInst **param_types; + Stage1AirInst *align_inst; // can be null + Stage1AirInst *return_type; CallingConvention cc; bool is_generic; @@ -482,8 +482,8 @@ struct LazyValueErrUnionType { LazyValue base; IrAnalyze *ira; - IrInstGen *err_set_type; - IrInstGen *payload_type; + Stage1AirInst *err_set_type; + Stage1AirInst *payload_type; Buf *type_name; }; @@ -1651,13 +1651,13 @@ struct ZigFn { size_t branch_quota; AstNode **param_source_nodes; Buf **param_names; - IrInstGen *err_code_spill; + Stage1AirInst *err_code_spill; AstNode *assumed_non_async; AstNode *fn_no_inline_set_node; AstNode *fn_static_eval_set_node; - ZigList alloca_gen_list; + ZigList alloca_gen_list; ZigList variable_list; Buf *section_name; @@ -1669,8 +1669,8 @@ struct ZigFn { AstNode *non_async_node; ZigList export_list; - ZigList call_list; - ZigList await_list; + ZigList call_list; + ZigList await_list; LLVMValueRef valgrind_client_request_array; @@ -2096,9 +2096,9 @@ struct CodeGen { Buf *builtin_zig_path; Buf *zig_std_special_dir; // Cannot be overridden; derived from zig_lib_dir. - IrInstSrc *invalid_inst_src; - IrInstGen *invalid_inst_gen; - IrInstGen *unreach_instruction; + Stage1ZirInst *invalid_inst_src; + Stage1AirInst *invalid_inst_gen; + Stage1AirInst *unreach_instruction; ZigValue panic_msg_vals[PanicMsgIdCount]; @@ -2165,8 +2165,8 @@ struct ZigVar { ZigValue *const_value; ZigType *var_type; LLVMValueRef value_ref; - IrInstSrc *is_comptime; - IrInstGen *ptr_instruction; + Stage1ZirInst *is_comptime; + Stage1AirInst *ptr_instruction; // which node is the declaration of the variable AstNode *decl_node; ZigLLVMDILocalVariable *di_loc_var; @@ -2268,9 +2268,9 @@ struct ScopeBlock { Buf *name; Stage1ZirBasicBlock *end_block; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; ResultLocPeerParent *peer_parent; - ZigList *incoming_values; + ZigList *incoming_values; ZigList *incoming_blocks; AstNode *safety_set_node; @@ -2325,8 +2325,8 @@ struct ScopeLoop { Buf *name; Stage1ZirBasicBlock *break_block; Stage1ZirBasicBlock *continue_block; - IrInstSrc *is_comptime; - ZigList *incoming_values; + Stage1ZirInst *is_comptime; + ZigList *incoming_values; ZigList *incoming_blocks; ResultLocPeerParent *peer_parent; ScopeExpr *spill_scope; @@ -2340,7 +2340,7 @@ struct ScopeLoop { struct ScopeRuntime { Scope base; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; }; // This scope is created for a suspend block in order to have labeled @@ -2439,11 +2439,11 @@ enum AtomicRmwOp { // Phi instructions must be first in a basic block. // The last instruction in a basic block must be of type unreachable. struct Stage1ZirBasicBlock { - ZigList instruction_list; - IrBasicBlockGen *child; + ZigList instruction_list; + Stage1AirBasicBlock *child; Scope *scope; const char *name_hint; - IrInstSrc *suspend_instruction_ref; + Stage1ZirInst *suspend_instruction_ref; uint32_t ref_count; uint32_t index; // index into the basic block list @@ -2453,8 +2453,8 @@ struct Stage1ZirBasicBlock { bool in_resume_stack; }; -struct IrBasicBlockGen { - ZigList instruction_list; +struct Stage1AirBasicBlock { + ZigList instruction_list; Scope *scope; const char *name_hint; LLVMBasicBlockRef llvm_block; @@ -2462,7 +2462,7 @@ struct IrBasicBlockGen { // The instruction that referenced this basic block and caused us to // analyze the basic block. If the same instruction wants us to emit // the same basic block, then we re-generate it instead of saving it. - IrInstSrc *ref_instruction; + Stage1ZirInst *ref_instruction; // When this is non-null, a branch to this basic block is only allowed // if the branch is comptime. The instruction points to the reason // the basic block must be comptime. @@ -2475,246 +2475,246 @@ struct IrBasicBlockGen { // Src instructions are generated by ir_gen_* functions in ir.cpp from AST. // ir_analyze_* functions consume Src instructions and produce Gen instructions. // Src instructions do not have type information; Gen instructions do. -enum IrInstSrcId : uint8_t { - IrInstSrcIdInvalid, - IrInstSrcIdDeclVar, - IrInstSrcIdBr, - IrInstSrcIdCondBr, - IrInstSrcIdSwitchBr, - IrInstSrcIdSwitchVar, - IrInstSrcIdSwitchElseVar, - IrInstSrcIdSwitchTarget, - IrInstSrcIdPhi, - IrInstSrcIdUnOp, - IrInstSrcIdBinOp, - IrInstSrcIdMergeErrSets, - IrInstSrcIdLoadPtr, - IrInstSrcIdStorePtr, - IrInstSrcIdFieldPtr, - IrInstSrcIdElemPtr, - IrInstSrcIdVarPtr, - IrInstSrcIdCall, - IrInstSrcIdCallArgs, - IrInstSrcIdCallExtra, - IrInstSrcIdAsyncCallExtra, - IrInstSrcIdConst, - IrInstSrcIdReturn, - IrInstSrcIdContainerInitList, - IrInstSrcIdContainerInitFields, - IrInstSrcIdUnreachable, - IrInstSrcIdTypeOf, - IrInstSrcIdSetCold, - IrInstSrcIdSetRuntimeSafety, - IrInstSrcIdSetFloatMode, - IrInstSrcIdArrayType, - IrInstSrcIdAnyFrameType, - IrInstSrcIdSliceType, - IrInstSrcIdAsm, - IrInstSrcIdSizeOf, - IrInstSrcIdTestNonNull, - IrInstSrcIdOptionalUnwrapPtr, - IrInstSrcIdClz, - IrInstSrcIdCtz, - IrInstSrcIdPopCount, - IrInstSrcIdBswap, - IrInstSrcIdBitReverse, - IrInstSrcIdImport, - IrInstSrcIdCImport, - IrInstSrcIdCInclude, - IrInstSrcIdCDefine, - IrInstSrcIdCUndef, - IrInstSrcIdRef, - IrInstSrcIdCompileErr, - IrInstSrcIdCompileLog, - IrInstSrcIdErrName, - IrInstSrcIdEmbedFile, - IrInstSrcIdCmpxchg, - IrInstSrcIdFence, - IrInstSrcIdReduce, - IrInstSrcIdTruncate, - IrInstSrcIdIntCast, - IrInstSrcIdFloatCast, - IrInstSrcIdIntToFloat, - IrInstSrcIdFloatToInt, - IrInstSrcIdBoolToInt, - IrInstSrcIdVectorType, - IrInstSrcIdShuffleVector, - IrInstSrcIdSplat, - IrInstSrcIdBoolNot, - IrInstSrcIdMemset, - IrInstSrcIdMemcpy, - IrInstSrcIdSlice, - IrInstSrcIdBreakpoint, - IrInstSrcIdReturnAddress, - IrInstSrcIdFrameAddress, - IrInstSrcIdFrameHandle, - IrInstSrcIdFrameType, - IrInstSrcIdFrameSize, - IrInstSrcIdAlignOf, - IrInstSrcIdOverflowOp, - IrInstSrcIdTestErr, - IrInstSrcIdMulAdd, - IrInstSrcIdFloatOp, - IrInstSrcIdUnwrapErrCode, - IrInstSrcIdUnwrapErrPayload, - IrInstSrcIdFnProto, - IrInstSrcIdTestComptime, - IrInstSrcIdPtrCast, - IrInstSrcIdBitCast, - IrInstSrcIdIntToPtr, - IrInstSrcIdPtrToInt, - IrInstSrcIdIntToEnum, - IrInstSrcIdEnumToInt, - IrInstSrcIdIntToErr, - IrInstSrcIdErrToInt, - IrInstSrcIdCheckSwitchProngsUnderYes, - IrInstSrcIdCheckSwitchProngsUnderNo, - IrInstSrcIdCheckStatementIsVoid, - IrInstSrcIdTypeName, - IrInstSrcIdDeclRef, - IrInstSrcIdPanic, - IrInstSrcIdTagName, - IrInstSrcIdFieldParentPtr, - IrInstSrcIdOffsetOf, - IrInstSrcIdBitOffsetOf, - IrInstSrcIdTypeInfo, - IrInstSrcIdType, - IrInstSrcIdHasField, - IrInstSrcIdSetEvalBranchQuota, - IrInstSrcIdPtrType, - IrInstSrcIdPtrTypeSimple, - IrInstSrcIdPtrTypeSimpleConst, - IrInstSrcIdAlignCast, - IrInstSrcIdImplicitCast, - IrInstSrcIdResolveResult, - IrInstSrcIdResetResult, - IrInstSrcIdSetAlignStack, - IrInstSrcIdArgTypeAllowVarFalse, - IrInstSrcIdArgTypeAllowVarTrue, - IrInstSrcIdExport, - IrInstSrcIdExtern, - IrInstSrcIdErrorReturnTrace, - IrInstSrcIdErrorUnion, - IrInstSrcIdAtomicRmw, - IrInstSrcIdAtomicLoad, - IrInstSrcIdAtomicStore, - IrInstSrcIdSaveErrRetAddr, - IrInstSrcIdAddImplicitReturnType, - IrInstSrcIdErrSetCast, - IrInstSrcIdCheckRuntimeScope, - IrInstSrcIdHasDecl, - IrInstSrcIdUndeclaredIdent, - IrInstSrcIdAlloca, - IrInstSrcIdEndExpr, - IrInstSrcIdUnionInitNamedField, - IrInstSrcIdSuspendBegin, - IrInstSrcIdSuspendFinish, - IrInstSrcIdAwait, - IrInstSrcIdResume, - IrInstSrcIdSpillBegin, - IrInstSrcIdSpillEnd, - IrInstSrcIdWasmMemorySize, - IrInstSrcIdWasmMemoryGrow, - IrInstSrcIdSrc, +enum Stage1ZirInstId : uint8_t { + Stage1ZirInstIdInvalid, + Stage1ZirInstIdDeclVar, + Stage1ZirInstIdBr, + Stage1ZirInstIdCondBr, + Stage1ZirInstIdSwitchBr, + Stage1ZirInstIdSwitchVar, + Stage1ZirInstIdSwitchElseVar, + Stage1ZirInstIdSwitchTarget, + Stage1ZirInstIdPhi, + Stage1ZirInstIdUnOp, + Stage1ZirInstIdBinOp, + Stage1ZirInstIdMergeErrSets, + Stage1ZirInstIdLoadPtr, + Stage1ZirInstIdStorePtr, + Stage1ZirInstIdFieldPtr, + Stage1ZirInstIdElemPtr, + Stage1ZirInstIdVarPtr, + Stage1ZirInstIdCall, + Stage1ZirInstIdCallArgs, + Stage1ZirInstIdCallExtra, + Stage1ZirInstIdAsyncCallExtra, + Stage1ZirInstIdConst, + Stage1ZirInstIdReturn, + Stage1ZirInstIdContainerInitList, + Stage1ZirInstIdContainerInitFields, + Stage1ZirInstIdUnreachable, + Stage1ZirInstIdTypeOf, + Stage1ZirInstIdSetCold, + Stage1ZirInstIdSetRuntimeSafety, + Stage1ZirInstIdSetFloatMode, + Stage1ZirInstIdArrayType, + Stage1ZirInstIdAnyFrameType, + Stage1ZirInstIdSliceType, + Stage1ZirInstIdAsm, + Stage1ZirInstIdSizeOf, + Stage1ZirInstIdTestNonNull, + Stage1ZirInstIdOptionalUnwrapPtr, + Stage1ZirInstIdClz, + Stage1ZirInstIdCtz, + Stage1ZirInstIdPopCount, + Stage1ZirInstIdBswap, + Stage1ZirInstIdBitReverse, + Stage1ZirInstIdImport, + Stage1ZirInstIdCImport, + Stage1ZirInstIdCInclude, + Stage1ZirInstIdCDefine, + Stage1ZirInstIdCUndef, + Stage1ZirInstIdRef, + Stage1ZirInstIdCompileErr, + Stage1ZirInstIdCompileLog, + Stage1ZirInstIdErrName, + Stage1ZirInstIdEmbedFile, + Stage1ZirInstIdCmpxchg, + Stage1ZirInstIdFence, + Stage1ZirInstIdReduce, + Stage1ZirInstIdTruncate, + Stage1ZirInstIdIntCast, + Stage1ZirInstIdFloatCast, + Stage1ZirInstIdIntToFloat, + Stage1ZirInstIdFloatToInt, + Stage1ZirInstIdBoolToInt, + Stage1ZirInstIdVectorType, + Stage1ZirInstIdShuffleVector, + Stage1ZirInstIdSplat, + Stage1ZirInstIdBoolNot, + Stage1ZirInstIdMemset, + Stage1ZirInstIdMemcpy, + Stage1ZirInstIdSlice, + Stage1ZirInstIdBreakpoint, + Stage1ZirInstIdReturnAddress, + Stage1ZirInstIdFrameAddress, + Stage1ZirInstIdFrameHandle, + Stage1ZirInstIdFrameType, + Stage1ZirInstIdFrameSize, + Stage1ZirInstIdAlignOf, + Stage1ZirInstIdOverflowOp, + Stage1ZirInstIdTestErr, + Stage1ZirInstIdMulAdd, + Stage1ZirInstIdFloatOp, + Stage1ZirInstIdUnwrapErrCode, + Stage1ZirInstIdUnwrapErrPayload, + Stage1ZirInstIdFnProto, + Stage1ZirInstIdTestComptime, + Stage1ZirInstIdPtrCast, + Stage1ZirInstIdBitCast, + Stage1ZirInstIdIntToPtr, + Stage1ZirInstIdPtrToInt, + Stage1ZirInstIdIntToEnum, + Stage1ZirInstIdEnumToInt, + Stage1ZirInstIdIntToErr, + Stage1ZirInstIdErrToInt, + Stage1ZirInstIdCheckSwitchProngsUnderYes, + Stage1ZirInstIdCheckSwitchProngsUnderNo, + Stage1ZirInstIdCheckStatementIsVoid, + Stage1ZirInstIdTypeName, + Stage1ZirInstIdDeclRef, + Stage1ZirInstIdPanic, + Stage1ZirInstIdTagName, + Stage1ZirInstIdFieldParentPtr, + Stage1ZirInstIdOffsetOf, + Stage1ZirInstIdBitOffsetOf, + Stage1ZirInstIdTypeInfo, + Stage1ZirInstIdType, + Stage1ZirInstIdHasField, + Stage1ZirInstIdSetEvalBranchQuota, + Stage1ZirInstIdPtrType, + Stage1ZirInstIdPtrTypeSimple, + Stage1ZirInstIdPtrTypeSimpleConst, + Stage1ZirInstIdAlignCast, + Stage1ZirInstIdImplicitCast, + Stage1ZirInstIdResolveResult, + Stage1ZirInstIdResetResult, + Stage1ZirInstIdSetAlignStack, + Stage1ZirInstIdArgTypeAllowVarFalse, + Stage1ZirInstIdArgTypeAllowVarTrue, + Stage1ZirInstIdExport, + Stage1ZirInstIdExtern, + Stage1ZirInstIdErrorReturnTrace, + Stage1ZirInstIdErrorUnion, + Stage1ZirInstIdAtomicRmw, + Stage1ZirInstIdAtomicLoad, + Stage1ZirInstIdAtomicStore, + Stage1ZirInstIdSaveErrRetAddr, + Stage1ZirInstIdAddImplicitReturnType, + Stage1ZirInstIdErrSetCast, + Stage1ZirInstIdCheckRuntimeScope, + Stage1ZirInstIdHasDecl, + Stage1ZirInstIdUndeclaredIdent, + Stage1ZirInstIdAlloca, + Stage1ZirInstIdEndExpr, + Stage1ZirInstIdUnionInitNamedField, + Stage1ZirInstIdSuspendBegin, + Stage1ZirInstIdSuspendFinish, + Stage1ZirInstIdAwait, + Stage1ZirInstIdResume, + Stage1ZirInstIdSpillBegin, + Stage1ZirInstIdSpillEnd, + Stage1ZirInstIdWasmMemorySize, + Stage1ZirInstIdWasmMemoryGrow, + Stage1ZirInstIdSrc, }; // ir_render_* functions in codegen.cpp consume Gen instructions and produce LLVM IR. // Src instructions do not have type information; Gen instructions do. -enum IrInstGenId : uint8_t { - IrInstGenIdInvalid, - IrInstGenIdDeclVar, - IrInstGenIdBr, - IrInstGenIdCondBr, - IrInstGenIdSwitchBr, - IrInstGenIdPhi, - IrInstGenIdBinaryNot, - IrInstGenIdNegation, - IrInstGenIdBinOp, - IrInstGenIdLoadPtr, - IrInstGenIdStorePtr, - IrInstGenIdVectorStoreElem, - IrInstGenIdStructFieldPtr, - IrInstGenIdUnionFieldPtr, - IrInstGenIdElemPtr, - IrInstGenIdVarPtr, - IrInstGenIdReturnPtr, - IrInstGenIdCall, - IrInstGenIdReturn, - IrInstGenIdCast, - IrInstGenIdUnreachable, - IrInstGenIdAsm, - IrInstGenIdTestNonNull, - IrInstGenIdOptionalUnwrapPtr, - IrInstGenIdOptionalWrap, - IrInstGenIdUnionTag, - IrInstGenIdClz, - IrInstGenIdCtz, - IrInstGenIdPopCount, - IrInstGenIdBswap, - IrInstGenIdBitReverse, - IrInstGenIdRef, - IrInstGenIdErrName, - IrInstGenIdCmpxchg, - IrInstGenIdFence, - IrInstGenIdReduce, - IrInstGenIdTruncate, - IrInstGenIdShuffleVector, - IrInstGenIdSplat, - IrInstGenIdBoolNot, - IrInstGenIdMemset, - IrInstGenIdMemcpy, - IrInstGenIdSlice, - IrInstGenIdBreakpoint, - IrInstGenIdReturnAddress, - IrInstGenIdFrameAddress, - IrInstGenIdFrameHandle, - IrInstGenIdFrameSize, - IrInstGenIdOverflowOp, - IrInstGenIdTestErr, - IrInstGenIdMulAdd, - IrInstGenIdFloatOp, - IrInstGenIdUnwrapErrCode, - IrInstGenIdUnwrapErrPayload, - IrInstGenIdErrWrapCode, - IrInstGenIdErrWrapPayload, - IrInstGenIdPtrCast, - IrInstGenIdBitCast, - IrInstGenIdWidenOrShorten, - IrInstGenIdIntToPtr, - IrInstGenIdPtrToInt, - IrInstGenIdIntToEnum, - IrInstGenIdIntToErr, - IrInstGenIdErrToInt, - IrInstGenIdPanic, - IrInstGenIdTagName, - IrInstGenIdFieldParentPtr, - IrInstGenIdAlignCast, - IrInstGenIdErrorReturnTrace, - IrInstGenIdAtomicRmw, - IrInstGenIdAtomicLoad, - IrInstGenIdAtomicStore, - IrInstGenIdSaveErrRetAddr, - IrInstGenIdVectorToArray, - IrInstGenIdArrayToVector, - IrInstGenIdAssertZero, - IrInstGenIdAssertNonNull, - IrInstGenIdPtrOfArrayToSlice, - IrInstGenIdSuspendBegin, - IrInstGenIdSuspendFinish, - IrInstGenIdAwait, - IrInstGenIdResume, - IrInstGenIdSpillBegin, - IrInstGenIdSpillEnd, - IrInstGenIdVectorExtractElem, - IrInstGenIdAlloca, - IrInstGenIdConst, - IrInstGenIdWasmMemorySize, - IrInstGenIdWasmMemoryGrow, - IrInstGenIdExtern, +enum Stage1AirInstId : uint8_t { + Stage1AirInstIdInvalid, + Stage1AirInstIdDeclVar, + Stage1AirInstIdBr, + Stage1AirInstIdCondBr, + Stage1AirInstIdSwitchBr, + Stage1AirInstIdPhi, + Stage1AirInstIdBinaryNot, + Stage1AirInstIdNegation, + Stage1AirInstIdBinOp, + Stage1AirInstIdLoadPtr, + Stage1AirInstIdStorePtr, + Stage1AirInstIdVectorStoreElem, + Stage1AirInstIdStructFieldPtr, + Stage1AirInstIdUnionFieldPtr, + Stage1AirInstIdElemPtr, + Stage1AirInstIdVarPtr, + Stage1AirInstIdReturnPtr, + Stage1AirInstIdCall, + Stage1AirInstIdReturn, + Stage1AirInstIdCast, + Stage1AirInstIdUnreachable, + Stage1AirInstIdAsm, + Stage1AirInstIdTestNonNull, + Stage1AirInstIdOptionalUnwrapPtr, + Stage1AirInstIdOptionalWrap, + Stage1AirInstIdUnionTag, + Stage1AirInstIdClz, + Stage1AirInstIdCtz, + Stage1AirInstIdPopCount, + Stage1AirInstIdBswap, + Stage1AirInstIdBitReverse, + Stage1AirInstIdRef, + Stage1AirInstIdErrName, + Stage1AirInstIdCmpxchg, + Stage1AirInstIdFence, + Stage1AirInstIdReduce, + Stage1AirInstIdTruncate, + Stage1AirInstIdShuffleVector, + Stage1AirInstIdSplat, + Stage1AirInstIdBoolNot, + Stage1AirInstIdMemset, + Stage1AirInstIdMemcpy, + Stage1AirInstIdSlice, + Stage1AirInstIdBreakpoint, + Stage1AirInstIdReturnAddress, + Stage1AirInstIdFrameAddress, + Stage1AirInstIdFrameHandle, + Stage1AirInstIdFrameSize, + Stage1AirInstIdOverflowOp, + Stage1AirInstIdTestErr, + Stage1AirInstIdMulAdd, + Stage1AirInstIdFloatOp, + Stage1AirInstIdUnwrapErrCode, + Stage1AirInstIdUnwrapErrPayload, + Stage1AirInstIdErrWrapCode, + Stage1AirInstIdErrWrapPayload, + Stage1AirInstIdPtrCast, + Stage1AirInstIdBitCast, + Stage1AirInstIdWidenOrShorten, + Stage1AirInstIdIntToPtr, + Stage1AirInstIdPtrToInt, + Stage1AirInstIdIntToEnum, + Stage1AirInstIdIntToErr, + Stage1AirInstIdErrToInt, + Stage1AirInstIdPanic, + Stage1AirInstIdTagName, + Stage1AirInstIdFieldParentPtr, + Stage1AirInstIdAlignCast, + Stage1AirInstIdErrorReturnTrace, + Stage1AirInstIdAtomicRmw, + Stage1AirInstIdAtomicLoad, + Stage1AirInstIdAtomicStore, + Stage1AirInstIdSaveErrRetAddr, + Stage1AirInstIdVectorToArray, + Stage1AirInstIdArrayToVector, + Stage1AirInstIdAssertZero, + Stage1AirInstIdAssertNonNull, + Stage1AirInstIdPtrOfArrayToSlice, + Stage1AirInstIdSuspendBegin, + Stage1AirInstIdSuspendFinish, + Stage1AirInstIdAwait, + Stage1AirInstIdResume, + Stage1AirInstIdSpillBegin, + Stage1AirInstIdSpillEnd, + Stage1AirInstIdVectorExtractElem, + Stage1AirInstIdAlloca, + Stage1AirInstIdConst, + Stage1AirInstIdWasmMemorySize, + Stage1AirInstIdWasmMemoryGrow, + Stage1AirInstIdExtern, }; -struct IrInstSrc { - IrInstSrcId id; +struct Stage1ZirInst { + Stage1ZirInstId id; uint16_t ref_count; uint32_t debug_id; @@ -2724,7 +2724,7 @@ struct IrInstSrc { // When analyzing IR, instructions that point to this instruction in the "old ir" // can find the instruction that corresponds to this value in the "new ir" // with this child field. - IrInstGen *child; + Stage1AirInst *child; Stage1ZirBasicBlock *owner_bb; // for debugging purposes, these are useful to call to inspect the instruction @@ -2732,8 +2732,8 @@ struct IrInstSrc { void src(); }; -struct IrInstGen { - IrInstGenId id; +struct Stage1AirInst { + Stage1AirInstId id; // if ref_count is zero and the instruction has no side effects, // the instruction can be omitted in codegen uint16_t ref_count; @@ -2744,130 +2744,130 @@ struct IrInstGen { LLVMValueRef llvm_value; ZigValue *value; - IrBasicBlockGen *owner_bb; + Stage1AirBasicBlock *owner_bb; // Nearly any instruction can have to be stored as a local variable before suspending // and then loaded after resuming, in case there is an expression with a suspend point // in it, such as: x + await y - IrInstGen *spill; + Stage1AirInst *spill; // for debugging purposes, these are useful to call to inspect the instruction void dump(); void src(); }; -struct IrInstSrcDeclVar { - IrInstSrc base; +struct Stage1ZirInstDeclVar { + Stage1ZirInst base; ZigVar *var; - IrInstSrc *var_type; - IrInstSrc *align_value; - IrInstSrc *ptr; + Stage1ZirInst *var_type; + Stage1ZirInst *align_value; + Stage1ZirInst *ptr; }; -struct IrInstGenDeclVar { - IrInstGen base; +struct Stage1AirInstDeclVar { + Stage1AirInst base; ZigVar *var; - IrInstGen *var_ptr; + Stage1AirInst *var_ptr; }; -struct IrInstSrcCondBr { - IrInstSrc base; +struct Stage1ZirInstCondBr { + Stage1ZirInst base; - IrInstSrc *condition; + Stage1ZirInst *condition; Stage1ZirBasicBlock *then_block; Stage1ZirBasicBlock *else_block; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; ResultLoc *result_loc; }; -struct IrInstGenCondBr { - IrInstGen base; +struct Stage1AirInstCondBr { + Stage1AirInst base; - IrInstGen *condition; - IrBasicBlockGen *then_block; - IrBasicBlockGen *else_block; + Stage1AirInst *condition; + Stage1AirBasicBlock *then_block; + Stage1AirBasicBlock *else_block; }; -struct IrInstSrcBr { - IrInstSrc base; +struct Stage1ZirInstBr { + Stage1ZirInst base; Stage1ZirBasicBlock *dest_block; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; }; -struct IrInstGenBr { - IrInstGen base; +struct Stage1AirInstBr { + Stage1AirInst base; - IrBasicBlockGen *dest_block; + Stage1AirBasicBlock *dest_block; }; -struct IrInstSrcSwitchBrCase { - IrInstSrc *value; +struct Stage1ZirInstSwitchBrCase { + Stage1ZirInst *value; Stage1ZirBasicBlock *block; }; -struct IrInstSrcSwitchBr { - IrInstSrc base; +struct Stage1ZirInstSwitchBr { + Stage1ZirInst base; - IrInstSrc *target_value; + Stage1ZirInst *target_value; Stage1ZirBasicBlock *else_block; size_t case_count; - IrInstSrcSwitchBrCase *cases; - IrInstSrc *is_comptime; - IrInstSrc *switch_prongs_void; + Stage1ZirInstSwitchBrCase *cases; + Stage1ZirInst *is_comptime; + Stage1ZirInst *switch_prongs_void; }; -struct IrInstGenSwitchBrCase { - IrInstGen *value; - IrBasicBlockGen *block; +struct Stage1AirInstSwitchBrCase { + Stage1AirInst *value; + Stage1AirBasicBlock *block; }; -struct IrInstGenSwitchBr { - IrInstGen base; +struct Stage1AirInstSwitchBr { + Stage1AirInst base; - IrInstGen *target_value; - IrBasicBlockGen *else_block; + Stage1AirInst *target_value; + Stage1AirBasicBlock *else_block; size_t case_count; - IrInstGenSwitchBrCase *cases; + Stage1AirInstSwitchBrCase *cases; }; -struct IrInstSrcSwitchVar { - IrInstSrc base; +struct Stage1ZirInstSwitchVar { + Stage1ZirInst base; - IrInstSrc *target_value_ptr; - IrInstSrc **prongs_ptr; + Stage1ZirInst *target_value_ptr; + Stage1ZirInst **prongs_ptr; size_t prongs_len; }; -struct IrInstSrcSwitchElseVar { - IrInstSrc base; +struct Stage1ZirInstSwitchElseVar { + Stage1ZirInst base; - IrInstSrc *target_value_ptr; - IrInstSrcSwitchBr *switch_br; + Stage1ZirInst *target_value_ptr; + Stage1ZirInstSwitchBr *switch_br; }; -struct IrInstSrcSwitchTarget { - IrInstSrc base; +struct Stage1ZirInstSwitchTarget { + Stage1ZirInst base; - IrInstSrc *target_value_ptr; + Stage1ZirInst *target_value_ptr; }; -struct IrInstSrcPhi { - IrInstSrc base; +struct Stage1ZirInstPhi { + Stage1ZirInst base; size_t incoming_count; Stage1ZirBasicBlock **incoming_blocks; - IrInstSrc **incoming_values; + Stage1ZirInst **incoming_values; ResultLocPeerParent *peer_parent; }; -struct IrInstGenPhi { - IrInstGen base; +struct Stage1AirInstPhi { + Stage1AirInst base; size_t incoming_count; - IrBasicBlockGen **incoming_blocks; - IrInstGen **incoming_values; + Stage1AirBasicBlock **incoming_blocks; + Stage1AirInst **incoming_values; }; enum IrUnOp { @@ -2879,23 +2879,23 @@ enum IrUnOp { IrUnOpOptional, }; -struct IrInstSrcUnOp { - IrInstSrc base; +struct Stage1ZirInstUnOp { + Stage1ZirInst base; IrUnOp op_id; LVal lval; - IrInstSrc *value; + Stage1ZirInst *value; ResultLoc *result_loc; }; -struct IrInstGenBinaryNot { - IrInstGen base; - IrInstGen *operand; +struct Stage1AirInstBinaryNot { + Stage1AirInst base; + Stage1AirInst *operand; }; -struct IrInstGenNegation { - IrInstGen base; - IrInstGen *operand; +struct Stage1AirInstNegation { + Stage1AirInst base; + Stage1AirInst *operand; bool wrapping; }; @@ -2933,122 +2933,122 @@ enum IrBinOp { IrBinOpArrayMult, }; -struct IrInstSrcBinOp { - IrInstSrc base; +struct Stage1ZirInstBinOp { + Stage1ZirInst base; - IrInstSrc *op1; - IrInstSrc *op2; + Stage1ZirInst *op1; + Stage1ZirInst *op2; IrBinOp op_id; bool safety_check_on; }; -struct IrInstGenBinOp { - IrInstGen base; +struct Stage1AirInstBinOp { + Stage1AirInst base; - IrInstGen *op1; - IrInstGen *op2; + Stage1AirInst *op1; + Stage1AirInst *op2; IrBinOp op_id; bool safety_check_on; }; -struct IrInstSrcMergeErrSets { - IrInstSrc base; +struct Stage1ZirInstMergeErrSets { + Stage1ZirInst base; - IrInstSrc *op1; - IrInstSrc *op2; + Stage1ZirInst *op1; + Stage1ZirInst *op2; Buf *type_name; }; -struct IrInstSrcLoadPtr { - IrInstSrc base; +struct Stage1ZirInstLoadPtr { + Stage1ZirInst base; - IrInstSrc *ptr; + Stage1ZirInst *ptr; }; -struct IrInstGenLoadPtr { - IrInstGen base; +struct Stage1AirInstLoadPtr { + Stage1AirInst base; - IrInstGen *ptr; - IrInstGen *result_loc; + Stage1AirInst *ptr; + Stage1AirInst *result_loc; }; -struct IrInstSrcStorePtr { - IrInstSrc base; +struct Stage1ZirInstStorePtr { + Stage1ZirInst base; - IrInstSrc *ptr; - IrInstSrc *value; + Stage1ZirInst *ptr; + Stage1ZirInst *value; bool allow_write_through_const; }; -struct IrInstGenStorePtr { - IrInstGen base; +struct Stage1AirInstStorePtr { + Stage1AirInst base; - IrInstGen *ptr; - IrInstGen *value; + Stage1AirInst *ptr; + Stage1AirInst *value; }; -struct IrInstGenVectorStoreElem { - IrInstGen base; +struct Stage1AirInstVectorStoreElem { + Stage1AirInst base; - IrInstGen *vector_ptr; - IrInstGen *index; - IrInstGen *value; + Stage1AirInst *vector_ptr; + Stage1AirInst *index; + Stage1AirInst *value; }; -struct IrInstSrcFieldPtr { - IrInstSrc base; +struct Stage1ZirInstFieldPtr { + Stage1ZirInst base; - IrInstSrc *container_ptr; + Stage1ZirInst *container_ptr; Buf *field_name_buffer; - IrInstSrc *field_name_expr; + Stage1ZirInst *field_name_expr; bool initializing; }; -struct IrInstGenStructFieldPtr { - IrInstGen base; +struct Stage1AirInstStructFieldPtr { + Stage1AirInst base; - IrInstGen *struct_ptr; + Stage1AirInst *struct_ptr; TypeStructField *field; bool is_const; }; -struct IrInstGenUnionFieldPtr { - IrInstGen base; +struct Stage1AirInstUnionFieldPtr { + Stage1AirInst base; - IrInstGen *union_ptr; + Stage1AirInst *union_ptr; TypeUnionField *field; bool safety_check_on; bool initializing; }; -struct IrInstSrcElemPtr { - IrInstSrc base; +struct Stage1ZirInstElemPtr { + Stage1ZirInst base; - IrInstSrc *array_ptr; - IrInstSrc *elem_index; + Stage1ZirInst *array_ptr; + Stage1ZirInst *elem_index; AstNode *init_array_type_source_node; PtrLen ptr_len; bool safety_check_on; }; -struct IrInstGenElemPtr { - IrInstGen base; +struct Stage1AirInstElemPtr { + Stage1AirInst base; - IrInstGen *array_ptr; - IrInstGen *elem_index; + Stage1AirInst *array_ptr; + Stage1AirInst *elem_index; bool safety_check_on; }; -struct IrInstSrcVarPtr { - IrInstSrc base; +struct Stage1ZirInstVarPtr { + Stage1ZirInst base; ZigVar *var; ScopeFnDef *crossed_fndef_scope; }; -struct IrInstGenVarPtr { - IrInstGen base; +struct Stage1AirInstVarPtr { + Stage1AirInst base; ZigVar *var; }; @@ -3056,21 +3056,21 @@ struct IrInstGenVarPtr { // For functions that have a return type for which handle_is_ptr is true, a // result location pointer is the secret first parameter ("sret"). This // instruction returns that pointer. -struct IrInstGenReturnPtr { - IrInstGen base; +struct Stage1AirInstReturnPtr { + Stage1AirInst base; }; -struct IrInstSrcCall { - IrInstSrc base; +struct Stage1ZirInstCall { + Stage1ZirInst base; - IrInstSrc *fn_ref; + Stage1ZirInst *fn_ref; ZigFn *fn_entry; size_t arg_count; - IrInstSrc **args; - IrInstSrc *ret_ptr; + Stage1ZirInst **args; + Stage1ZirInst *ret_ptr; ResultLoc *result_loc; - IrInstSrc *new_stack; + Stage1ZirInst *new_stack; CallModifier modifier; bool is_async_call_builtin; @@ -3078,12 +3078,12 @@ struct IrInstSrcCall { // This is a pass1 instruction, used by @call when the args node is // a tuple or struct literal. -struct IrInstSrcCallArgs { - IrInstSrc base; +struct Stage1ZirInstCallArgs { + Stage1ZirInst base; - IrInstSrc *options; - IrInstSrc *fn_ref; - IrInstSrc **args_ptr; + Stage1ZirInst *options; + Stage1ZirInst *fn_ref; + Stage1ZirInst **args_ptr; size_t args_len; ResultLoc *result_loc; }; @@ -3091,68 +3091,68 @@ struct IrInstSrcCallArgs { // This is a pass1 instruction, used by @call, when the args node // is not a literal. // `args` is expected to be either a struct or a tuple. -struct IrInstSrcCallExtra { - IrInstSrc base; +struct Stage1ZirInstCallExtra { + Stage1ZirInst base; - IrInstSrc *options; - IrInstSrc *fn_ref; - IrInstSrc *args; + Stage1ZirInst *options; + Stage1ZirInst *fn_ref; + Stage1ZirInst *args; ResultLoc *result_loc; }; // This is a pass1 instruction, used by @asyncCall, when the args node // is not a literal. // `args` is expected to be either a struct or a tuple. -struct IrInstSrcAsyncCallExtra { - IrInstSrc base; +struct Stage1ZirInstAsyncCallExtra { + Stage1ZirInst base; CallModifier modifier; - IrInstSrc *fn_ref; - IrInstSrc *ret_ptr; - IrInstSrc *new_stack; - IrInstSrc *args; + Stage1ZirInst *fn_ref; + Stage1ZirInst *ret_ptr; + Stage1ZirInst *new_stack; + Stage1ZirInst *args; ResultLoc *result_loc; }; -struct IrInstGenCall { - IrInstGen base; +struct Stage1AirInstCall { + Stage1AirInst base; - IrInstGen *fn_ref; + Stage1AirInst *fn_ref; ZigFn *fn_entry; size_t arg_count; - IrInstGen **args; - IrInstGen *result_loc; - IrInstGen *frame_result_loc; - IrInstGen *new_stack; + Stage1AirInst **args; + Stage1AirInst *result_loc; + Stage1AirInst *frame_result_loc; + Stage1AirInst *new_stack; CallModifier modifier; bool is_async_call_builtin; }; -struct IrInstSrcConst { - IrInstSrc base; +struct Stage1ZirInstConst { + Stage1ZirInst base; ZigValue *value; }; -struct IrInstGenConst { - IrInstGen base; +struct Stage1AirInstConst { + Stage1AirInst base; }; -struct IrInstSrcReturn { - IrInstSrc base; +struct Stage1ZirInstReturn { + Stage1ZirInst base; - IrInstSrc *operand; + Stage1ZirInst *operand; }; // When an IrExecutable is not in a function, a return instruction means that // the expression returns with that value, even though a return statement from // an AST perspective is invalid. -struct IrInstGenReturn { - IrInstGen base; +struct Stage1AirInstReturn { + Stage1AirInst base; - IrInstGen *operand; + Stage1AirInst *operand; }; enum CastOp { @@ -3167,94 +3167,94 @@ enum CastOp { }; // TODO get rid of this instruction, replace with instructions for each op code -struct IrInstGenCast { - IrInstGen base; +struct Stage1AirInstCast { + Stage1AirInst base; - IrInstGen *value; + Stage1AirInst *value; CastOp cast_op; }; -struct IrInstSrcContainerInitList { - IrInstSrc base; +struct Stage1ZirInstContainerInitList { + Stage1ZirInst base; - IrInstSrc *elem_type; + Stage1ZirInst *elem_type; size_t item_count; - IrInstSrc **elem_result_loc_list; - IrInstSrc *result_loc; + Stage1ZirInst **elem_result_loc_list; + Stage1ZirInst *result_loc; AstNode *init_array_type_source_node; }; -struct IrInstSrcContainerInitFieldsField { +struct Stage1ZirInstContainerInitFieldsField { Buf *name; AstNode *source_node; - IrInstSrc *result_loc; + Stage1ZirInst *result_loc; }; -struct IrInstSrcContainerInitFields { - IrInstSrc base; +struct Stage1ZirInstContainerInitFields { + Stage1ZirInst base; size_t field_count; - IrInstSrcContainerInitFieldsField *fields; - IrInstSrc *result_loc; + Stage1ZirInstContainerInitFieldsField *fields; + Stage1ZirInst *result_loc; }; -struct IrInstSrcUnreachable { - IrInstSrc base; +struct Stage1ZirInstUnreachable { + Stage1ZirInst base; }; -struct IrInstGenUnreachable { - IrInstGen base; +struct Stage1AirInstUnreachable { + Stage1AirInst base; }; -struct IrInstSrcTypeOf { - IrInstSrc base; +struct Stage1ZirInstTypeOf { + Stage1ZirInst base; union { - IrInstSrc *scalar; // value_count == 1 - IrInstSrc **list; // value_count > 1 + Stage1ZirInst *scalar; // value_count == 1 + Stage1ZirInst **list; // value_count > 1 } value; size_t value_count; }; -struct IrInstSrcSetCold { - IrInstSrc base; +struct Stage1ZirInstSetCold { + Stage1ZirInst base; - IrInstSrc *is_cold; + Stage1ZirInst *is_cold; }; -struct IrInstSrcSetRuntimeSafety { - IrInstSrc base; +struct Stage1ZirInstSetRuntimeSafety { + Stage1ZirInst base; - IrInstSrc *safety_on; + Stage1ZirInst *safety_on; }; -struct IrInstSrcSetFloatMode { - IrInstSrc base; +struct Stage1ZirInstSetFloatMode { + Stage1ZirInst base; - IrInstSrc *scope_value; - IrInstSrc *mode_value; + Stage1ZirInst *scope_value; + Stage1ZirInst *mode_value; }; -struct IrInstSrcArrayType { - IrInstSrc base; +struct Stage1ZirInstArrayType { + Stage1ZirInst base; - IrInstSrc *size; - IrInstSrc *sentinel; - IrInstSrc *child_type; + Stage1ZirInst *size; + Stage1ZirInst *sentinel; + Stage1ZirInst *child_type; }; -struct IrInstSrcPtrTypeSimple { - IrInstSrc base; +struct Stage1ZirInstPtrTypeSimple { + Stage1ZirInst base; - IrInstSrc *child_type; + Stage1ZirInst *child_type; }; -struct IrInstSrcPtrType { - IrInstSrc base; +struct Stage1ZirInstPtrType { + Stage1ZirInst base; - IrInstSrc *sentinel; - IrInstSrc *align_value; - IrInstSrc *child_type; + Stage1ZirInst *sentinel; + Stage1ZirInst *align_value; + Stage1ZirInst *child_type; uint32_t bit_offset_start; uint32_t host_int_bytes; PtrLen ptr_len; @@ -3263,459 +3263,459 @@ struct IrInstSrcPtrType { bool is_allow_zero; }; -struct IrInstSrcAnyFrameType { - IrInstSrc base; +struct Stage1ZirInstAnyFrameType { + Stage1ZirInst base; - IrInstSrc *payload_type; + Stage1ZirInst *payload_type; }; -struct IrInstSrcSliceType { - IrInstSrc base; +struct Stage1ZirInstSliceType { + Stage1ZirInst base; - IrInstSrc *sentinel; - IrInstSrc *align_value; - IrInstSrc *child_type; + Stage1ZirInst *sentinel; + Stage1ZirInst *align_value; + Stage1ZirInst *child_type; bool is_const; bool is_volatile; bool is_allow_zero; }; -struct IrInstSrcAsm { - IrInstSrc base; +struct Stage1ZirInstAsm { + Stage1ZirInst base; - IrInstSrc *asm_template; - IrInstSrc **input_list; - IrInstSrc **output_types; + Stage1ZirInst *asm_template; + Stage1ZirInst **input_list; + Stage1ZirInst **output_types; ZigVar **output_vars; size_t return_count; bool has_side_effects; bool is_global; }; -struct IrInstGenAsm { - IrInstGen base; +struct Stage1AirInstAsm { + Stage1AirInst base; Buf *asm_template; AsmToken *token_list; size_t token_list_len; - IrInstGen **input_list; - IrInstGen **output_types; + Stage1AirInst **input_list; + Stage1AirInst **output_types; ZigVar **output_vars; size_t return_count; bool has_side_effects; }; -struct IrInstSrcSizeOf { - IrInstSrc base; +struct Stage1ZirInstSizeOf { + Stage1ZirInst base; - IrInstSrc *type_value; + Stage1ZirInst *type_value; bool bit_size; }; // returns true if nonnull, returns false if null -struct IrInstSrcTestNonNull { - IrInstSrc base; +struct Stage1ZirInstTestNonNull { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; }; -struct IrInstGenTestNonNull { - IrInstGen base; +struct Stage1AirInstTestNonNull { + Stage1AirInst base; - IrInstGen *value; + Stage1AirInst *value; }; // Takes a pointer to an optional value, returns a pointer // to the payload. -struct IrInstSrcOptionalUnwrapPtr { - IrInstSrc base; +struct Stage1ZirInstOptionalUnwrapPtr { + Stage1ZirInst base; - IrInstSrc *base_ptr; + Stage1ZirInst *base_ptr; bool safety_check_on; }; -struct IrInstGenOptionalUnwrapPtr { - IrInstGen base; +struct Stage1AirInstOptionalUnwrapPtr { + Stage1AirInst base; - IrInstGen *base_ptr; + Stage1AirInst *base_ptr; bool safety_check_on; bool initializing; }; -struct IrInstSrcCtz { - IrInstSrc base; +struct Stage1ZirInstCtz { + Stage1ZirInst base; - IrInstSrc *type; - IrInstSrc *op; + Stage1ZirInst *type; + Stage1ZirInst *op; }; -struct IrInstGenCtz { - IrInstGen base; +struct Stage1AirInstCtz { + Stage1AirInst base; - IrInstGen *op; + Stage1AirInst *op; }; -struct IrInstSrcClz { - IrInstSrc base; +struct Stage1ZirInstClz { + Stage1ZirInst base; - IrInstSrc *type; - IrInstSrc *op; + Stage1ZirInst *type; + Stage1ZirInst *op; }; -struct IrInstGenClz { - IrInstGen base; +struct Stage1AirInstClz { + Stage1AirInst base; - IrInstGen *op; + Stage1AirInst *op; }; -struct IrInstSrcPopCount { - IrInstSrc base; +struct Stage1ZirInstPopCount { + Stage1ZirInst base; - IrInstSrc *type; - IrInstSrc *op; + Stage1ZirInst *type; + Stage1ZirInst *op; }; -struct IrInstGenPopCount { - IrInstGen base; +struct Stage1AirInstPopCount { + Stage1AirInst base; - IrInstGen *op; + Stage1AirInst *op; }; -struct IrInstGenUnionTag { - IrInstGen base; +struct Stage1AirInstUnionTag { + Stage1AirInst base; - IrInstGen *value; + Stage1AirInst *value; }; -struct IrInstSrcImport { - IrInstSrc base; +struct Stage1ZirInstImport { + Stage1ZirInst base; - IrInstSrc *name; + Stage1ZirInst *name; }; -struct IrInstSrcRef { - IrInstSrc base; +struct Stage1ZirInstRef { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; }; -struct IrInstGenRef { - IrInstGen base; +struct Stage1AirInstRef { + Stage1AirInst base; - IrInstGen *operand; - IrInstGen *result_loc; + Stage1AirInst *operand; + Stage1AirInst *result_loc; }; -struct IrInstSrcCompileErr { - IrInstSrc base; +struct Stage1ZirInstCompileErr { + Stage1ZirInst base; - IrInstSrc *msg; + Stage1ZirInst *msg; }; -struct IrInstSrcCompileLog { - IrInstSrc base; +struct Stage1ZirInstCompileLog { + Stage1ZirInst base; size_t msg_count; - IrInstSrc **msg_list; + Stage1ZirInst **msg_list; }; -struct IrInstSrcErrName { - IrInstSrc base; +struct Stage1ZirInstErrName { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; }; -struct IrInstGenErrName { - IrInstGen base; +struct Stage1AirInstErrName { + Stage1AirInst base; - IrInstGen *value; + Stage1AirInst *value; }; -struct IrInstSrcCImport { - IrInstSrc base; +struct Stage1ZirInstCImport { + Stage1ZirInst base; }; -struct IrInstSrcCInclude { - IrInstSrc base; +struct Stage1ZirInstCInclude { + Stage1ZirInst base; - IrInstSrc *name; + Stage1ZirInst *name; }; -struct IrInstSrcCDefine { - IrInstSrc base; +struct Stage1ZirInstCDefine { + Stage1ZirInst base; - IrInstSrc *name; - IrInstSrc *value; + Stage1ZirInst *name; + Stage1ZirInst *value; }; -struct IrInstSrcCUndef { - IrInstSrc base; +struct Stage1ZirInstCUndef { + Stage1ZirInst base; - IrInstSrc *name; + Stage1ZirInst *name; }; -struct IrInstSrcEmbedFile { - IrInstSrc base; +struct Stage1ZirInstEmbedFile { + Stage1ZirInst base; - IrInstSrc *name; + Stage1ZirInst *name; }; -struct IrInstSrcCmpxchg { - IrInstSrc base; +struct Stage1ZirInstCmpxchg { + Stage1ZirInst base; bool is_weak; - IrInstSrc *type_value; - IrInstSrc *ptr; - IrInstSrc *cmp_value; - IrInstSrc *new_value; - IrInstSrc *success_order_value; - IrInstSrc *failure_order_value; + Stage1ZirInst *type_value; + Stage1ZirInst *ptr; + Stage1ZirInst *cmp_value; + Stage1ZirInst *new_value; + Stage1ZirInst *success_order_value; + Stage1ZirInst *failure_order_value; ResultLoc *result_loc; }; -struct IrInstGenCmpxchg { - IrInstGen base; +struct Stage1AirInstCmpxchg { + Stage1AirInst base; AtomicOrder success_order; AtomicOrder failure_order; - IrInstGen *ptr; - IrInstGen *cmp_value; - IrInstGen *new_value; - IrInstGen *result_loc; + Stage1AirInst *ptr; + Stage1AirInst *cmp_value; + Stage1AirInst *new_value; + Stage1AirInst *result_loc; bool is_weak; }; -struct IrInstSrcFence { - IrInstSrc base; +struct Stage1ZirInstFence { + Stage1ZirInst base; - IrInstSrc *order; + Stage1ZirInst *order; }; -struct IrInstGenFence { - IrInstGen base; +struct Stage1AirInstFence { + Stage1AirInst base; AtomicOrder order; }; -struct IrInstSrcReduce { - IrInstSrc base; +struct Stage1ZirInstReduce { + Stage1ZirInst base; - IrInstSrc *op; - IrInstSrc *value; + Stage1ZirInst *op; + Stage1ZirInst *value; }; -struct IrInstGenReduce { - IrInstGen base; +struct Stage1AirInstReduce { + Stage1AirInst base; ReduceOp op; - IrInstGen *value; + Stage1AirInst *value; }; -struct IrInstSrcTruncate { - IrInstSrc base; +struct Stage1ZirInstTruncate { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstGenTruncate { - IrInstGen base; +struct Stage1AirInstTruncate { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcIntCast { - IrInstSrc base; +struct Stage1ZirInstIntCast { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstSrcFloatCast { - IrInstSrc base; +struct Stage1ZirInstFloatCast { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstSrcErrSetCast { - IrInstSrc base; +struct Stage1ZirInstErrSetCast { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstSrcIntToFloat { - IrInstSrc base; +struct Stage1ZirInstIntToFloat { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstSrcFloatToInt { - IrInstSrc base; +struct Stage1ZirInstFloatToInt { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstSrcBoolToInt { - IrInstSrc base; +struct Stage1ZirInstBoolToInt { + Stage1ZirInst base; - IrInstSrc *target; + Stage1ZirInst *target; }; -struct IrInstSrcVectorType { - IrInstSrc base; +struct Stage1ZirInstVectorType { + Stage1ZirInst base; - IrInstSrc *len; - IrInstSrc *elem_type; + Stage1ZirInst *len; + Stage1ZirInst *elem_type; }; -struct IrInstSrcBoolNot { - IrInstSrc base; +struct Stage1ZirInstBoolNot { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; }; -struct IrInstGenBoolNot { - IrInstGen base; +struct Stage1AirInstBoolNot { + Stage1AirInst base; - IrInstGen *value; + Stage1AirInst *value; }; -struct IrInstSrcMemset { - IrInstSrc base; +struct Stage1ZirInstMemset { + Stage1ZirInst base; - IrInstSrc *dest_ptr; - IrInstSrc *byte; - IrInstSrc *count; + Stage1ZirInst *dest_ptr; + Stage1ZirInst *byte; + Stage1ZirInst *count; }; -struct IrInstGenMemset { - IrInstGen base; +struct Stage1AirInstMemset { + Stage1AirInst base; - IrInstGen *dest_ptr; - IrInstGen *byte; - IrInstGen *count; + Stage1AirInst *dest_ptr; + Stage1AirInst *byte; + Stage1AirInst *count; }; -struct IrInstSrcMemcpy { - IrInstSrc base; +struct Stage1ZirInstMemcpy { + Stage1ZirInst base; - IrInstSrc *dest_ptr; - IrInstSrc *src_ptr; - IrInstSrc *count; + Stage1ZirInst *dest_ptr; + Stage1ZirInst *src_ptr; + Stage1ZirInst *count; }; -struct IrInstGenMemcpy { - IrInstGen base; +struct Stage1AirInstMemcpy { + Stage1AirInst base; - IrInstGen *dest_ptr; - IrInstGen *src_ptr; - IrInstGen *count; + Stage1AirInst *dest_ptr; + Stage1AirInst *src_ptr; + Stage1AirInst *count; }; -struct IrInstSrcWasmMemorySize { - IrInstSrc base; +struct Stage1ZirInstWasmMemorySize { + Stage1ZirInst base; - IrInstSrc *index; + Stage1ZirInst *index; }; -struct IrInstGenWasmMemorySize { - IrInstGen base; +struct Stage1AirInstWasmMemorySize { + Stage1AirInst base; - IrInstGen *index; + Stage1AirInst *index; }; -struct IrInstSrcWasmMemoryGrow { - IrInstSrc base; +struct Stage1ZirInstWasmMemoryGrow { + Stage1ZirInst base; - IrInstSrc *index; - IrInstSrc *delta; + Stage1ZirInst *index; + Stage1ZirInst *delta; }; -struct IrInstGenWasmMemoryGrow { - IrInstGen base; +struct Stage1AirInstWasmMemoryGrow { + Stage1AirInst base; - IrInstGen *index; - IrInstGen *delta; + Stage1AirInst *index; + Stage1AirInst *delta; }; -struct IrInstSrcSrc { - IrInstSrc base; +struct Stage1ZirInstSrc { + Stage1ZirInst base; }; -struct IrInstSrcSlice { - IrInstSrc base; +struct Stage1ZirInstSlice { + Stage1ZirInst base; - IrInstSrc *ptr; - IrInstSrc *start; - IrInstSrc *end; - IrInstSrc *sentinel; + Stage1ZirInst *ptr; + Stage1ZirInst *start; + Stage1ZirInst *end; + Stage1ZirInst *sentinel; ResultLoc *result_loc; bool safety_check_on; }; -struct IrInstGenSlice { - IrInstGen base; +struct Stage1AirInstSlice { + Stage1AirInst base; - IrInstGen *ptr; - IrInstGen *start; - IrInstGen *end; - IrInstGen *result_loc; + Stage1AirInst *ptr; + Stage1AirInst *start; + Stage1AirInst *end; + Stage1AirInst *result_loc; ZigValue *sentinel; bool safety_check_on; }; -struct IrInstSrcBreakpoint { - IrInstSrc base; +struct Stage1ZirInstBreakpoint { + Stage1ZirInst base; }; -struct IrInstGenBreakpoint { - IrInstGen base; +struct Stage1AirInstBreakpoint { + Stage1AirInst base; }; -struct IrInstSrcReturnAddress { - IrInstSrc base; +struct Stage1ZirInstReturnAddress { + Stage1ZirInst base; }; -struct IrInstGenReturnAddress { - IrInstGen base; +struct Stage1AirInstReturnAddress { + Stage1AirInst base; }; -struct IrInstSrcFrameAddress { - IrInstSrc base; +struct Stage1ZirInstFrameAddress { + Stage1ZirInst base; }; -struct IrInstGenFrameAddress { - IrInstGen base; +struct Stage1AirInstFrameAddress { + Stage1AirInst base; }; -struct IrInstSrcFrameHandle { - IrInstSrc base; +struct Stage1ZirInstFrameHandle { + Stage1ZirInst base; }; -struct IrInstGenFrameHandle { - IrInstGen base; +struct Stage1AirInstFrameHandle { + Stage1AirInst base; }; -struct IrInstSrcFrameType { - IrInstSrc base; +struct Stage1ZirInstFrameType { + Stage1ZirInst base; - IrInstSrc *fn; + Stage1ZirInst *fn; }; -struct IrInstSrcFrameSize { - IrInstSrc base; +struct Stage1ZirInstFrameSize { + Stage1ZirInst base; - IrInstSrc *fn; + Stage1ZirInst *fn; }; -struct IrInstGenFrameSize { - IrInstGen base; +struct Stage1AirInstFrameSize { + Stage1AirInst base; - IrInstGen *fn; + Stage1AirInst *fn; }; enum IrOverflowOp { @@ -3725,397 +3725,397 @@ enum IrOverflowOp { IrOverflowOpShl, }; -struct IrInstSrcOverflowOp { - IrInstSrc base; +struct Stage1ZirInstOverflowOp { + Stage1ZirInst base; IrOverflowOp op; - IrInstSrc *type_value; - IrInstSrc *op1; - IrInstSrc *op2; - IrInstSrc *result_ptr; + Stage1ZirInst *type_value; + Stage1ZirInst *op1; + Stage1ZirInst *op2; + Stage1ZirInst *result_ptr; }; -struct IrInstGenOverflowOp { - IrInstGen base; +struct Stage1AirInstOverflowOp { + Stage1AirInst base; IrOverflowOp op; - IrInstGen *op1; - IrInstGen *op2; - IrInstGen *result_ptr; + Stage1AirInst *op1; + Stage1AirInst *op2; + Stage1AirInst *result_ptr; // TODO can this field be removed? ZigType *result_ptr_type; }; -struct IrInstSrcMulAdd { - IrInstSrc base; +struct Stage1ZirInstMulAdd { + Stage1ZirInst base; - IrInstSrc *type_value; - IrInstSrc *op1; - IrInstSrc *op2; - IrInstSrc *op3; + Stage1ZirInst *type_value; + Stage1ZirInst *op1; + Stage1ZirInst *op2; + Stage1ZirInst *op3; }; -struct IrInstGenMulAdd { - IrInstGen base; +struct Stage1AirInstMulAdd { + Stage1AirInst base; - IrInstGen *op1; - IrInstGen *op2; - IrInstGen *op3; + Stage1AirInst *op1; + Stage1AirInst *op2; + Stage1AirInst *op3; }; -struct IrInstSrcAlignOf { - IrInstSrc base; +struct Stage1ZirInstAlignOf { + Stage1ZirInst base; - IrInstSrc *type_value; + Stage1ZirInst *type_value; }; // returns true if error, returns false if not error -struct IrInstSrcTestErr { - IrInstSrc base; +struct Stage1ZirInstTestErr { + Stage1ZirInst base; - IrInstSrc *base_ptr; + Stage1ZirInst *base_ptr; bool resolve_err_set; bool base_ptr_is_payload; }; -struct IrInstGenTestErr { - IrInstGen base; +struct Stage1AirInstTestErr { + Stage1AirInst base; - IrInstGen *err_union; + Stage1AirInst *err_union; }; // Takes an error union pointer, returns a pointer to the error code. -struct IrInstSrcUnwrapErrCode { - IrInstSrc base; +struct Stage1ZirInstUnwrapErrCode { + Stage1ZirInst base; - IrInstSrc *err_union_ptr; + Stage1ZirInst *err_union_ptr; bool initializing; }; -struct IrInstGenUnwrapErrCode { - IrInstGen base; +struct Stage1AirInstUnwrapErrCode { + Stage1AirInst base; - IrInstGen *err_union_ptr; + Stage1AirInst *err_union_ptr; bool initializing; }; -struct IrInstSrcUnwrapErrPayload { - IrInstSrc base; +struct Stage1ZirInstUnwrapErrPayload { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; bool safety_check_on; bool initializing; }; -struct IrInstGenUnwrapErrPayload { - IrInstGen base; +struct Stage1AirInstUnwrapErrPayload { + Stage1AirInst base; - IrInstGen *value; + Stage1AirInst *value; bool safety_check_on; bool initializing; }; -struct IrInstGenOptionalWrap { - IrInstGen base; +struct Stage1AirInstOptionalWrap { + Stage1AirInst base; - IrInstGen *operand; - IrInstGen *result_loc; + Stage1AirInst *operand; + Stage1AirInst *result_loc; }; -struct IrInstGenErrWrapPayload { - IrInstGen base; +struct Stage1AirInstErrWrapPayload { + Stage1AirInst base; - IrInstGen *operand; - IrInstGen *result_loc; + Stage1AirInst *operand; + Stage1AirInst *result_loc; }; -struct IrInstGenErrWrapCode { - IrInstGen base; +struct Stage1AirInstErrWrapCode { + Stage1AirInst base; - IrInstGen *operand; - IrInstGen *result_loc; + Stage1AirInst *operand; + Stage1AirInst *result_loc; }; -struct IrInstSrcFnProto { - IrInstSrc base; +struct Stage1ZirInstFnProto { + Stage1ZirInst base; - IrInstSrc **param_types; - IrInstSrc *align_value; - IrInstSrc *callconv_value; - IrInstSrc *return_type; + Stage1ZirInst **param_types; + Stage1ZirInst *align_value; + Stage1ZirInst *callconv_value; + Stage1ZirInst *return_type; bool is_var_args; }; // true if the target value is compile time known, false otherwise -struct IrInstSrcTestComptime { - IrInstSrc base; +struct Stage1ZirInstTestComptime { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; }; -struct IrInstSrcPtrCast { - IrInstSrc base; +struct Stage1ZirInstPtrCast { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *ptr; + Stage1ZirInst *dest_type; + Stage1ZirInst *ptr; bool safety_check_on; }; -struct IrInstGenPtrCast { - IrInstGen base; +struct Stage1AirInstPtrCast { + Stage1AirInst base; - IrInstGen *ptr; + Stage1AirInst *ptr; bool safety_check_on; }; -struct IrInstSrcImplicitCast { - IrInstSrc base; +struct Stage1ZirInstImplicitCast { + Stage1ZirInst base; - IrInstSrc *operand; + Stage1ZirInst *operand; ResultLocCast *result_loc_cast; }; -struct IrInstSrcBitCast { - IrInstSrc base; +struct Stage1ZirInstBitCast { + Stage1ZirInst base; - IrInstSrc *operand; + Stage1ZirInst *operand; ResultLocBitCast *result_loc_bit_cast; }; -struct IrInstGenBitCast { - IrInstGen base; +struct Stage1AirInstBitCast { + Stage1AirInst base; - IrInstGen *operand; + Stage1AirInst *operand; }; -struct IrInstGenWidenOrShorten { - IrInstGen base; +struct Stage1AirInstWidenOrShorten { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcPtrToInt { - IrInstSrc base; +struct Stage1ZirInstPtrToInt { + Stage1ZirInst base; - IrInstSrc *target; + Stage1ZirInst *target; }; -struct IrInstGenPtrToInt { - IrInstGen base; +struct Stage1AirInstPtrToInt { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcIntToPtr { - IrInstSrc base; +struct Stage1ZirInstIntToPtr { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstGenIntToPtr { - IrInstGen base; +struct Stage1AirInstIntToPtr { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcIntToEnum { - IrInstSrc base; +struct Stage1ZirInstIntToEnum { + Stage1ZirInst base; - IrInstSrc *dest_type; - IrInstSrc *target; + Stage1ZirInst *dest_type; + Stage1ZirInst *target; }; -struct IrInstGenIntToEnum { - IrInstGen base; +struct Stage1AirInstIntToEnum { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcEnumToInt { - IrInstSrc base; +struct Stage1ZirInstEnumToInt { + Stage1ZirInst base; - IrInstSrc *target; + Stage1ZirInst *target; }; -struct IrInstSrcIntToErr { - IrInstSrc base; +struct Stage1ZirInstIntToErr { + Stage1ZirInst base; - IrInstSrc *target; + Stage1ZirInst *target; }; -struct IrInstGenIntToErr { - IrInstGen base; +struct Stage1AirInstIntToErr { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcErrToInt { - IrInstSrc base; +struct Stage1ZirInstErrToInt { + Stage1ZirInst base; - IrInstSrc *target; + Stage1ZirInst *target; }; -struct IrInstGenErrToInt { - IrInstGen base; +struct Stage1AirInstErrToInt { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcCheckSwitchProngsRange { - IrInstSrc *start; - IrInstSrc *end; +struct Stage1ZirInstCheckSwitchProngsRange { + Stage1ZirInst *start; + Stage1ZirInst *end; }; -struct IrInstSrcCheckSwitchProngs { - IrInstSrc base; +struct Stage1ZirInstCheckSwitchProngs { + Stage1ZirInst base; - IrInstSrc *target_value; - IrInstSrcCheckSwitchProngsRange *ranges; + Stage1ZirInst *target_value; + Stage1ZirInstCheckSwitchProngsRange *ranges; size_t range_count; AstNode* else_prong; }; -struct IrInstSrcCheckStatementIsVoid { - IrInstSrc base; +struct Stage1ZirInstCheckStatementIsVoid { + Stage1ZirInst base; - IrInstSrc *statement_value; + Stage1ZirInst *statement_value; }; -struct IrInstSrcTypeName { - IrInstSrc base; +struct Stage1ZirInstTypeName { + Stage1ZirInst base; - IrInstSrc *type_value; + Stage1ZirInst *type_value; }; -struct IrInstSrcDeclRef { - IrInstSrc base; +struct Stage1ZirInstDeclRef { + Stage1ZirInst base; LVal lval; Tld *tld; }; -struct IrInstSrcPanic { - IrInstSrc base; +struct Stage1ZirInstPanic { + Stage1ZirInst base; - IrInstSrc *msg; + Stage1ZirInst *msg; }; -struct IrInstGenPanic { - IrInstGen base; +struct Stage1AirInstPanic { + Stage1AirInst base; - IrInstGen *msg; + Stage1AirInst *msg; }; -struct IrInstSrcTagName { - IrInstSrc base; +struct Stage1ZirInstTagName { + Stage1ZirInst base; - IrInstSrc *target; + Stage1ZirInst *target; }; -struct IrInstGenTagName { - IrInstGen base; +struct Stage1AirInstTagName { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcFieldParentPtr { - IrInstSrc base; +struct Stage1ZirInstFieldParentPtr { + Stage1ZirInst base; - IrInstSrc *type_value; - IrInstSrc *field_name; - IrInstSrc *field_ptr; + Stage1ZirInst *type_value; + Stage1ZirInst *field_name; + Stage1ZirInst *field_ptr; }; -struct IrInstGenFieldParentPtr { - IrInstGen base; +struct Stage1AirInstFieldParentPtr { + Stage1AirInst base; - IrInstGen *field_ptr; + Stage1AirInst *field_ptr; TypeStructField *field; }; -struct IrInstSrcOffsetOf { - IrInstSrc base; +struct Stage1ZirInstOffsetOf { + Stage1ZirInst base; - IrInstSrc *type_value; - IrInstSrc *field_name; + Stage1ZirInst *type_value; + Stage1ZirInst *field_name; }; -struct IrInstSrcBitOffsetOf { - IrInstSrc base; +struct Stage1ZirInstBitOffsetOf { + Stage1ZirInst base; - IrInstSrc *type_value; - IrInstSrc *field_name; + Stage1ZirInst *type_value; + Stage1ZirInst *field_name; }; -struct IrInstSrcTypeInfo { - IrInstSrc base; +struct Stage1ZirInstTypeInfo { + Stage1ZirInst base; - IrInstSrc *type_value; + Stage1ZirInst *type_value; }; -struct IrInstSrcType { - IrInstSrc base; +struct Stage1ZirInstType { + Stage1ZirInst base; - IrInstSrc *type_info; + Stage1ZirInst *type_info; }; -struct IrInstSrcHasField { - IrInstSrc base; +struct Stage1ZirInstHasField { + Stage1ZirInst base; - IrInstSrc *container_type; - IrInstSrc *field_name; + Stage1ZirInst *container_type; + Stage1ZirInst *field_name; }; -struct IrInstSrcSetEvalBranchQuota { - IrInstSrc base; +struct Stage1ZirInstSetEvalBranchQuota { + Stage1ZirInst base; - IrInstSrc *new_quota; + Stage1ZirInst *new_quota; }; -struct IrInstSrcAlignCast { - IrInstSrc base; +struct Stage1ZirInstAlignCast { + Stage1ZirInst base; - IrInstSrc *align_bytes; - IrInstSrc *target; + Stage1ZirInst *align_bytes; + Stage1ZirInst *target; }; -struct IrInstGenAlignCast { - IrInstGen base; +struct Stage1AirInstAlignCast { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcSetAlignStack { - IrInstSrc base; +struct Stage1ZirInstSetAlignStack { + Stage1ZirInst base; - IrInstSrc *align_bytes; + Stage1ZirInst *align_bytes; }; -struct IrInstSrcArgType { - IrInstSrc base; +struct Stage1ZirInstArgType { + Stage1ZirInst base; - IrInstSrc *fn_type; - IrInstSrc *arg_index; + Stage1ZirInst *fn_type; + Stage1ZirInst *arg_index; }; -struct IrInstSrcExport { - IrInstSrc base; +struct Stage1ZirInstExport { + Stage1ZirInst base; - IrInstSrc *target; - IrInstSrc *options; + Stage1ZirInst *target; + Stage1ZirInst *options; }; -struct IrInstSrcExtern { - IrInstSrc base; +struct Stage1ZirInstExtern { + Stage1ZirInst base; - IrInstSrc *type; - IrInstSrc *options; + Stage1ZirInst *type; + Stage1ZirInst *options; }; -struct IrInstGenExtern { - IrInstGen base; +struct Stage1AirInstExtern { + Stage1AirInst base; Buf *name; GlobalLinkageId linkage; @@ -4127,310 +4127,310 @@ enum IrInstErrorReturnTraceOptional { IrInstErrorReturnTraceNonNull, }; -struct IrInstSrcErrorReturnTrace { - IrInstSrc base; +struct Stage1ZirInstErrorReturnTrace { + Stage1ZirInst base; IrInstErrorReturnTraceOptional optional; }; -struct IrInstGenErrorReturnTrace { - IrInstGen base; +struct Stage1AirInstErrorReturnTrace { + Stage1AirInst base; IrInstErrorReturnTraceOptional optional; }; -struct IrInstSrcErrorUnion { - IrInstSrc base; +struct Stage1ZirInstErrorUnion { + Stage1ZirInst base; - IrInstSrc *err_set; - IrInstSrc *payload; + Stage1ZirInst *err_set; + Stage1ZirInst *payload; Buf *type_name; }; -struct IrInstSrcAtomicRmw { - IrInstSrc base; +struct Stage1ZirInstAtomicRmw { + Stage1ZirInst base; - IrInstSrc *operand_type; - IrInstSrc *ptr; - IrInstSrc *op; - IrInstSrc *operand; - IrInstSrc *ordering; + Stage1ZirInst *operand_type; + Stage1ZirInst *ptr; + Stage1ZirInst *op; + Stage1ZirInst *operand; + Stage1ZirInst *ordering; }; -struct IrInstGenAtomicRmw { - IrInstGen base; +struct Stage1AirInstAtomicRmw { + Stage1AirInst base; - IrInstGen *ptr; - IrInstGen *operand; + Stage1AirInst *ptr; + Stage1AirInst *operand; AtomicRmwOp op; AtomicOrder ordering; }; -struct IrInstSrcAtomicLoad { - IrInstSrc base; +struct Stage1ZirInstAtomicLoad { + Stage1ZirInst base; - IrInstSrc *operand_type; - IrInstSrc *ptr; - IrInstSrc *ordering; + Stage1ZirInst *operand_type; + Stage1ZirInst *ptr; + Stage1ZirInst *ordering; }; -struct IrInstGenAtomicLoad { - IrInstGen base; +struct Stage1AirInstAtomicLoad { + Stage1AirInst base; - IrInstGen *ptr; + Stage1AirInst *ptr; AtomicOrder ordering; }; -struct IrInstSrcAtomicStore { - IrInstSrc base; +struct Stage1ZirInstAtomicStore { + Stage1ZirInst base; - IrInstSrc *operand_type; - IrInstSrc *ptr; - IrInstSrc *value; - IrInstSrc *ordering; + Stage1ZirInst *operand_type; + Stage1ZirInst *ptr; + Stage1ZirInst *value; + Stage1ZirInst *ordering; }; -struct IrInstGenAtomicStore { - IrInstGen base; +struct Stage1AirInstAtomicStore { + Stage1AirInst base; - IrInstGen *ptr; - IrInstGen *value; + Stage1AirInst *ptr; + Stage1AirInst *value; AtomicOrder ordering; }; -struct IrInstSrcSaveErrRetAddr { - IrInstSrc base; +struct Stage1ZirInstSaveErrRetAddr { + Stage1ZirInst base; }; -struct IrInstGenSaveErrRetAddr { - IrInstGen base; +struct Stage1AirInstSaveErrRetAddr { + Stage1AirInst base; }; -struct IrInstSrcAddImplicitReturnType { - IrInstSrc base; +struct Stage1ZirInstAddImplicitReturnType { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; ResultLocReturn *result_loc_ret; }; // For float ops that take a single argument -struct IrInstSrcFloatOp { - IrInstSrc base; +struct Stage1ZirInstFloatOp { + Stage1ZirInst base; - IrInstSrc *operand; + Stage1ZirInst *operand; BuiltinFnId fn_id; }; -struct IrInstGenFloatOp { - IrInstGen base; +struct Stage1AirInstFloatOp { + Stage1AirInst base; - IrInstGen *operand; + Stage1AirInst *operand; BuiltinFnId fn_id; }; -struct IrInstSrcCheckRuntimeScope { - IrInstSrc base; +struct Stage1ZirInstCheckRuntimeScope { + Stage1ZirInst base; - IrInstSrc *scope_is_comptime; - IrInstSrc *is_comptime; + Stage1ZirInst *scope_is_comptime; + Stage1ZirInst *is_comptime; }; -struct IrInstSrcBswap { - IrInstSrc base; +struct Stage1ZirInstBswap { + Stage1ZirInst base; - IrInstSrc *type; - IrInstSrc *op; + Stage1ZirInst *type; + Stage1ZirInst *op; }; -struct IrInstGenBswap { - IrInstGen base; +struct Stage1AirInstBswap { + Stage1AirInst base; - IrInstGen *op; + Stage1AirInst *op; }; -struct IrInstSrcBitReverse { - IrInstSrc base; +struct Stage1ZirInstBitReverse { + Stage1ZirInst base; - IrInstSrc *type; - IrInstSrc *op; + Stage1ZirInst *type; + Stage1ZirInst *op; }; -struct IrInstGenBitReverse { - IrInstGen base; +struct Stage1AirInstBitReverse { + Stage1AirInst base; - IrInstGen *op; + Stage1AirInst *op; }; -struct IrInstGenArrayToVector { - IrInstGen base; +struct Stage1AirInstArrayToVector { + Stage1AirInst base; - IrInstGen *array; + Stage1AirInst *array; }; -struct IrInstGenVectorToArray { - IrInstGen base; +struct Stage1AirInstVectorToArray { + Stage1AirInst base; - IrInstGen *vector; - IrInstGen *result_loc; + Stage1AirInst *vector; + Stage1AirInst *result_loc; }; -struct IrInstSrcShuffleVector { - IrInstSrc base; +struct Stage1ZirInstShuffleVector { + Stage1ZirInst base; - IrInstSrc *scalar_type; - IrInstSrc *a; - IrInstSrc *b; - IrInstSrc *mask; // This is in zig-format, not llvm format + Stage1ZirInst *scalar_type; + Stage1ZirInst *a; + Stage1ZirInst *b; + Stage1ZirInst *mask; // This is in zig-format, not llvm format }; -struct IrInstGenShuffleVector { - IrInstGen base; +struct Stage1AirInstShuffleVector { + Stage1AirInst base; - IrInstGen *a; - IrInstGen *b; - IrInstGen *mask; // This is in zig-format, not llvm format + Stage1AirInst *a; + Stage1AirInst *b; + Stage1AirInst *mask; // This is in zig-format, not llvm format }; -struct IrInstSrcSplat { - IrInstSrc base; +struct Stage1ZirInstSplat { + Stage1ZirInst base; - IrInstSrc *len; - IrInstSrc *scalar; + Stage1ZirInst *len; + Stage1ZirInst *scalar; }; -struct IrInstGenSplat { - IrInstGen base; +struct Stage1AirInstSplat { + Stage1AirInst base; - IrInstGen *scalar; + Stage1AirInst *scalar; }; -struct IrInstGenAssertZero { - IrInstGen base; +struct Stage1AirInstAssertZero { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstGenAssertNonNull { - IrInstGen base; +struct Stage1AirInstAssertNonNull { + Stage1AirInst base; - IrInstGen *target; + Stage1AirInst *target; }; -struct IrInstSrcUnionInitNamedField { - IrInstSrc base; +struct Stage1ZirInstUnionInitNamedField { + Stage1ZirInst base; - IrInstSrc *union_type; - IrInstSrc *field_name; - IrInstSrc *field_result_loc; - IrInstSrc *result_loc; + Stage1ZirInst *union_type; + Stage1ZirInst *field_name; + Stage1ZirInst *field_result_loc; + Stage1ZirInst *result_loc; }; -struct IrInstSrcHasDecl { - IrInstSrc base; +struct Stage1ZirInstHasDecl { + Stage1ZirInst base; - IrInstSrc *container; - IrInstSrc *name; + Stage1ZirInst *container; + Stage1ZirInst *name; }; -struct IrInstSrcUndeclaredIdent { - IrInstSrc base; +struct Stage1ZirInstUndeclaredIdent { + Stage1ZirInst base; Buf *name; }; -struct IrInstSrcAlloca { - IrInstSrc base; +struct Stage1ZirInstAlloca { + Stage1ZirInst base; - IrInstSrc *align; - IrInstSrc *is_comptime; + Stage1ZirInst *align; + Stage1ZirInst *is_comptime; const char *name_hint; }; -struct IrInstGenAlloca { - IrInstGen base; +struct Stage1AirInstAlloca { + Stage1AirInst base; uint32_t align; const char *name_hint; size_t field_index; }; -struct IrInstSrcEndExpr { - IrInstSrc base; +struct Stage1ZirInstEndExpr { + Stage1ZirInst base; - IrInstSrc *value; + Stage1ZirInst *value; ResultLoc *result_loc; }; // This one is for writing through the result pointer. -struct IrInstSrcResolveResult { - IrInstSrc base; +struct Stage1ZirInstResolveResult { + Stage1ZirInst base; ResultLoc *result_loc; - IrInstSrc *ty; + Stage1ZirInst *ty; }; -struct IrInstSrcResetResult { - IrInstSrc base; +struct Stage1ZirInstResetResult { + Stage1ZirInst base; ResultLoc *result_loc; }; -struct IrInstGenPtrOfArrayToSlice { - IrInstGen base; +struct Stage1AirInstPtrOfArrayToSlice { + Stage1AirInst base; - IrInstGen *operand; - IrInstGen *result_loc; + Stage1AirInst *operand; + Stage1AirInst *result_loc; }; -struct IrInstSrcSuspendBegin { - IrInstSrc base; +struct Stage1ZirInstSuspendBegin { + Stage1ZirInst base; }; -struct IrInstGenSuspendBegin { - IrInstGen base; +struct Stage1AirInstSuspendBegin { + Stage1AirInst base; LLVMBasicBlockRef resume_bb; }; -struct IrInstSrcSuspendFinish { - IrInstSrc base; +struct Stage1ZirInstSuspendFinish { + Stage1ZirInst base; - IrInstSrcSuspendBegin *begin; + Stage1ZirInstSuspendBegin *begin; }; -struct IrInstGenSuspendFinish { - IrInstGen base; +struct Stage1AirInstSuspendFinish { + Stage1AirInst base; - IrInstGenSuspendBegin *begin; + Stage1AirInstSuspendBegin *begin; }; -struct IrInstSrcAwait { - IrInstSrc base; +struct Stage1ZirInstAwait { + Stage1ZirInst base; - IrInstSrc *frame; + Stage1ZirInst *frame; ResultLoc *result_loc; bool is_nosuspend; }; -struct IrInstGenAwait { - IrInstGen base; +struct Stage1AirInstAwait { + Stage1AirInst base; - IrInstGen *frame; - IrInstGen *result_loc; + Stage1AirInst *frame; + Stage1AirInst *result_loc; ZigFn *target_fn; bool is_nosuspend; }; -struct IrInstSrcResume { - IrInstSrc base; +struct Stage1ZirInstResume { + Stage1ZirInst base; - IrInstSrc *frame; + Stage1ZirInst *frame; }; -struct IrInstGenResume { - IrInstGen base; +struct Stage1AirInstResume { + Stage1AirInst base; - IrInstGen *frame; + Stage1AirInst *frame; }; enum SpillId { @@ -4438,37 +4438,37 @@ enum SpillId { SpillIdRetErrCode, }; -struct IrInstSrcSpillBegin { - IrInstSrc base; +struct Stage1ZirInstSpillBegin { + Stage1ZirInst base; - IrInstSrc *operand; + Stage1ZirInst *operand; SpillId spill_id; }; -struct IrInstGenSpillBegin { - IrInstGen base; +struct Stage1AirInstSpillBegin { + Stage1AirInst base; SpillId spill_id; - IrInstGen *operand; + Stage1AirInst *operand; }; -struct IrInstSrcSpillEnd { - IrInstSrc base; +struct Stage1ZirInstSpillEnd { + Stage1ZirInst base; - IrInstSrcSpillBegin *begin; + Stage1ZirInstSpillBegin *begin; }; -struct IrInstGenSpillEnd { - IrInstGen base; +struct Stage1AirInstSpillEnd { + Stage1AirInst base; - IrInstGenSpillBegin *begin; + Stage1AirInstSpillBegin *begin; }; -struct IrInstGenVectorExtractElem { - IrInstGen base; +struct Stage1AirInstVectorExtractElem { + Stage1AirInst base; - IrInstGen *vector; - IrInstGen *index; + Stage1AirInst *vector; + Stage1AirInst *index; }; enum ResultLocId { @@ -4489,9 +4489,9 @@ struct ResultLoc { ResultLocId id; bool written; bool allow_write_through_const; - IrInstGen *resolved_loc; // result ptr - IrInstSrc *source_instruction; - IrInstGen *gen_instruction; // value to store to the result loc + Stage1AirInst *resolved_loc; // result ptr + Stage1ZirInst *source_instruction; + Stage1AirInst *gen_instruction; // value to store to the result loc ZigType *implicit_elem_type; }; @@ -4525,7 +4525,7 @@ struct ResultLocPeerParent { ResultLoc *parent; ZigList peers; ZigType *resolved_type; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; }; struct ResultLocPeer { @@ -4603,7 +4603,7 @@ struct FnWalkAttrs { struct FnWalkCall { ZigList *gen_param_values; ZigList *gen_param_types; - IrInstGenCall *inst; + Stage1AirInstCall *inst; bool is_var_args; }; diff --git a/src/stage1/analyze.cpp b/src/stage1/analyze.cpp index 06bd1e1ed6..37c3d58ae3 100644 --- a/src/stage1/analyze.cpp +++ b/src/stage1/analyze.cpp @@ -206,7 +206,7 @@ ScopeLoop *create_loop_scope(CodeGen *g, AstNode *node, Scope *parent) { return scope; } -Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, IrInstSrc *is_comptime) { +Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, Stage1ZirInst *is_comptime) { ScopeRuntime *scope = heap::c_allocator.create(); scope->is_comptime = is_comptime; init_scope(g, &scope->base, ScopeIdRuntime, node, parent); @@ -5071,7 +5071,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) { } for (size_t i = 0; i < fn->call_list.length; i += 1) { - IrInstGenCall *call = fn->call_list.at(i); + Stage1AirInstCall *call = fn->call_list.at(i); if (call->fn_entry == nullptr) { // TODO function pointer call here, could be anything continue; @@ -5094,7 +5094,7 @@ static void analyze_fn_async(CodeGen *g, ZigFn *fn, bool resolve_frame) { } } for (size_t i = 0; i < fn->await_list.length; i += 1) { - IrInstGenAwait *await = fn->await_list.at(i); + Stage1AirInstAwait *await = fn->await_list.at(i); if (await->is_nosuspend) continue; switch (analyze_callee_async(g, fn, await->target_fn, await->base.source_node, must_not_be_async, CallModifierNone)) @@ -6755,8 +6755,8 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) { ZigType *fn_type = get_async_fn_type(g, fn->type_entry); if (fn->analyzed_executable.need_err_code_spill) { - IrInstGenAlloca *alloca_gen = heap::c_allocator.create(); - alloca_gen->base.id = IrInstGenIdAlloca; + Stage1AirInstAlloca *alloca_gen = heap::c_allocator.create(); + alloca_gen->base.id = Stage1AirInstIdAlloca; alloca_gen->base.source_node = fn->proto_node; alloca_gen->base.scope = fn->child_scope; alloca_gen->base.value = g->pass1_arena->create(); @@ -6769,11 +6769,11 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) { ZigType *largest_call_frame_type = nullptr; // Later we'll change this to be largest_call_frame_type instead of void. - IrInstGen *all_calls_alloca = ir_create_alloca(g, &fn->fndef_scope->base, fn->body_node, + Stage1AirInst *all_calls_alloca = ir_create_alloca(g, &fn->fndef_scope->base, fn->body_node, fn, g->builtin_types.entry_void, "@async_call_frame"); for (size_t i = 0; i < fn->call_list.length; i += 1) { - IrInstGenCall *call = fn->call_list.at(i); + Stage1AirInstCall *call = fn->call_list.at(i); if (call->new_stack != nullptr) { // don't need to allocate a frame for this continue; @@ -6838,7 +6838,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) { // For example: foo() + await z // The funtion call result of foo() must be spilled. for (size_t i = 0; i < fn->await_list.length; i += 1) { - IrInstGenAwait *await = fn->await_list.at(i); + Stage1AirInstAwait *await = fn->await_list.at(i); if (await->is_nosuspend) { continue; } @@ -6875,10 +6875,10 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) { await->base.value->type, ""); } for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) { - IrBasicBlockGen *block = fn->analyzed_executable.basic_block_list.at(block_i); + Stage1AirBasicBlock *block = fn->analyzed_executable.basic_block_list.at(block_i); for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) { - IrInstGen *instruction = block->instruction_list.at(instr_i); - if (instruction->id == IrInstGenIdSuspendFinish) { + Stage1AirInst *instruction = block->instruction_list.at(instr_i); + if (instruction->id == Stage1AirInstIdSuspendFinish) { mark_suspension_point(instruction->scope); } } @@ -6886,20 +6886,20 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) { // Now that we've marked all the expr scopes that have to spill, we go over the instructions // and spill the relevant ones. for (size_t block_i = 0; block_i < fn->analyzed_executable.basic_block_list.length; block_i += 1) { - IrBasicBlockGen *block = fn->analyzed_executable.basic_block_list.at(block_i); + Stage1AirBasicBlock *block = fn->analyzed_executable.basic_block_list.at(block_i); for (size_t instr_i = 0; instr_i < block->instruction_list.length; instr_i += 1) { - IrInstGen *instruction = block->instruction_list.at(instr_i); - if (instruction->id == IrInstGenIdAwait || - instruction->id == IrInstGenIdVarPtr || - instruction->id == IrInstGenIdAlloca || - instruction->id == IrInstGenIdSpillBegin || - instruction->id == IrInstGenIdSpillEnd) + Stage1AirInst *instruction = block->instruction_list.at(instr_i); + if (instruction->id == Stage1AirInstIdAwait || + instruction->id == Stage1AirInstIdVarPtr || + instruction->id == Stage1AirInstIdAlloca || + instruction->id == Stage1AirInstIdSpillBegin || + instruction->id == Stage1AirInstIdSpillEnd) { // This instruction does its own spilling specially, or otherwise doesn't need it. continue; } - if (instruction->id == IrInstGenIdCast && - reinterpret_cast(instruction)->cast_op == CastOpNoop) + if (instruction->id == Stage1AirInstIdCast && + reinterpret_cast(instruction)->cast_op == CastOpNoop) { // The IR instruction exists only to change the type according to Zig. No spill needed. continue; @@ -6964,7 +6964,7 @@ static Error resolve_async_frame(CodeGen *g, ZigType *frame_type) { } for (size_t alloca_i = 0; alloca_i < fn->alloca_gen_list.length; alloca_i += 1) { - IrInstGenAlloca *instruction = fn->alloca_gen_list.at(alloca_i); + Stage1AirInstAlloca *instruction = fn->alloca_gen_list.at(alloca_i); instruction->field_index = SIZE_MAX; ZigType *ptr_type = instruction->base.value->type; assert(ptr_type->id == ZigTypeIdPointer); @@ -7146,8 +7146,8 @@ bool ir_get_var_is_comptime(ZigVar *var) { // As an optimization, is_comptime values which are constant are allowed // to be omitted from analysis. In this case, there is no child instruction // and we simply look at the unanalyzed const parent instruction. - assert(var->is_comptime->id == IrInstSrcIdConst); - IrInstSrcConst *const_inst = reinterpret_cast(var->is_comptime); + assert(var->is_comptime->id == Stage1ZirInstIdConst); + Stage1ZirInstConst *const_inst = reinterpret_cast(var->is_comptime); assert(const_inst->value->type->id == ZigTypeIdBool); var->is_comptime_memoized_value = const_inst->value->data.x_bool; var->is_comptime = nullptr; diff --git a/src/stage1/analyze.hpp b/src/stage1/analyze.hpp index 5c232bf4b6..22951db0f0 100644 --- a/src/stage1/analyze.hpp +++ b/src/stage1/analyze.hpp @@ -138,7 +138,7 @@ ScopeSuspend *create_suspend_scope(CodeGen *g, AstNode *node, Scope *parent); ScopeFnDef *create_fndef_scope(CodeGen *g, AstNode *node, Scope *parent, ZigFn *fn_entry); Scope *create_comptime_scope(CodeGen *g, AstNode *node, Scope *parent); Scope *create_nosuspend_scope(CodeGen *g, AstNode *node, Scope *parent); -Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, IrInstSrc *is_comptime); +Scope *create_runtime_scope(CodeGen *g, AstNode *node, Scope *parent, Stage1ZirInst *is_comptime); Scope *create_typeof_scope(CodeGen *g, AstNode *node, Scope *parent); ScopeExpr *create_expr_scope(CodeGen *g, AstNode *node, Scope *parent); diff --git a/src/stage1/astgen.cpp b/src/stage1/astgen.cpp index e3eebab0bc..88587c5805 100644 --- a/src/stage1/astgen.cpp +++ b/src/stage1/astgen.cpp @@ -21,25 +21,25 @@ struct Stage1AstGen { bool in_c_import_scope; }; -static IrInstSrc *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope); -static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval, +static Stage1ZirInst *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope); +static Stage1ZirInst *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval, ResultLoc *result_loc); -static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, LVal lval, +static Stage1ZirInst *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *value, LVal lval, ResultLoc *result_loc); -static IrInstSrc *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *inst, +static Stage1ZirInst *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *inst, ResultLoc *result_loc); -static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *union_type, IrInstSrc *field_name, AstNode *expr_node, +static Stage1ZirInst *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *union_type, Stage1ZirInst *field_name, AstNode *expr_node, LVal lval, ResultLoc *parent_result_loc); -static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest_type, +static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, Stage1ZirInst *dest_type, ResultLoc *parent_result_loc); static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name, - bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime); + bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime); static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - ZigVar *var, IrInstSrc *init, const char *name_hint, IrInstSrc *is_comptime); + ZigVar *var, Stage1ZirInst *init, const char *name_hint, Stage1ZirInst *is_comptime); -static void ir_assert_impl(bool ok, IrInstSrc *source_instruction, char const *file, unsigned int line) { +static void ir_assert_impl(bool ok, Stage1ZirInst *source_instruction, char const *file, unsigned int line) { if (ok) return; src_assert_impl(ok, source_instruction->source_node, file, line); } @@ -54,299 +54,299 @@ static ErrorMsg *exec_add_error_node(CodeGen *codegen, Stage1Zir *exec, AstNode #define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__) -static bool instr_is_unreachable(IrInstSrc *instruction) { +static bool instr_is_unreachable(Stage1ZirInst *instruction) { switch (instruction->id) { - case IrInstSrcIdCondBr: - case IrInstSrcIdReturn: - case IrInstSrcIdBr: - case IrInstSrcIdUnreachable: - case IrInstSrcIdSwitchBr: - case IrInstSrcIdPanic: + case Stage1ZirInstIdCondBr: + case Stage1ZirInstIdReturn: + case Stage1ZirInstIdBr: + case Stage1ZirInstIdUnreachable: + case Stage1ZirInstIdSwitchBr: + case Stage1ZirInstIdPanic: return true; default: return false; } } -void destroy_instruction_src(IrInstSrc *inst) { +void destroy_instruction_src(Stage1ZirInst *inst) { switch (inst->id) { - case IrInstSrcIdInvalid: + case Stage1ZirInstIdInvalid: zig_unreachable(); - case IrInstSrcIdReturn: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdConst: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBinOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdMergeErrSets: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdDeclVar: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCall: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCallExtra: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAsyncCallExtra: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdUnOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCondBr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPhi: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdContainerInitList: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdContainerInitFields: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdUnreachable: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdElemPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdVarPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdLoadPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdStorePtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTypeOf: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFieldPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSetCold: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSetRuntimeSafety: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSetFloatMode: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdArrayType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSliceType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAnyFrameType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAsm: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSizeOf: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTestNonNull: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdOptionalUnwrapPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPopCount: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdClz: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCtz: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBswap: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBitReverse: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSwitchBr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSwitchVar: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSwitchElseVar: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSwitchTarget: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdImport: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdRef: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCompileErr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCompileLog: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdErrName: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCImport: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCInclude: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCDefine: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCUndef: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdEmbedFile: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCmpxchg: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFence: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdReduce: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTruncate: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdIntCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFloatCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdErrSetCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdIntToFloat: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFloatToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBoolToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdVectorType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdShuffleVector: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSplat: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBoolNot: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdMemset: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdMemcpy: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSlice: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBreakpoint: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdReturnAddress: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFrameAddress: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFrameHandle: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFrameType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFrameSize: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAlignOf: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdOverflowOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTestErr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdUnwrapErrCode: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdUnwrapErrPayload: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFnProto: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTestComptime: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPtrCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBitCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPtrToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdIntToPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdIntToEnum: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdIntToErr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdErrToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCheckSwitchProngsUnderNo: - case IrInstSrcIdCheckSwitchProngsUnderYes: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCheckStatementIsVoid: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTypeName: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTagName: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPtrType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPtrTypeSimple: - case IrInstSrcIdPtrTypeSimpleConst: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdDeclRef: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdPanic: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFieldParentPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdOffsetOf: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdBitOffsetOf: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdTypeInfo: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdHasField: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSetEvalBranchQuota: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAlignCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdImplicitCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdResolveResult: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdResetResult: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSetAlignStack: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdArgTypeAllowVarFalse: - case IrInstSrcIdArgTypeAllowVarTrue: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdExport: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdExtern: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdErrorReturnTrace: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdErrorUnion: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAtomicRmw: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSaveErrRetAddr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAddImplicitReturnType: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdFloatOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdMulAdd: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAtomicLoad: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAtomicStore: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdEnumToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCheckRuntimeScope: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdHasDecl: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdUndeclaredIdent: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAlloca: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdEndExpr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdUnionInitNamedField: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSuspendBegin: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSuspendFinish: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdResume: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdAwait: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSpillBegin: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSpillEnd: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdCallArgs: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdWasmMemorySize: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdWasmMemoryGrow: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstSrcIdSrc: - return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdReturn: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdConst: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBinOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdMergeErrSets: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdDeclVar: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCall: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCallExtra: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAsyncCallExtra: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdUnOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCondBr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPhi: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdContainerInitList: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdContainerInitFields: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdUnreachable: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdElemPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdVarPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdLoadPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdStorePtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTypeOf: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFieldPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSetCold: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSetRuntimeSafety: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSetFloatMode: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdArrayType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSliceType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAnyFrameType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAsm: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSizeOf: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTestNonNull: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdOptionalUnwrapPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPopCount: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdClz: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCtz: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBswap: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBitReverse: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSwitchBr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSwitchVar: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSwitchElseVar: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSwitchTarget: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdImport: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdRef: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCompileErr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCompileLog: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdErrName: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCImport: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCInclude: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCDefine: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCUndef: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdEmbedFile: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCmpxchg: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFence: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdReduce: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTruncate: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdIntCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFloatCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdErrSetCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdIntToFloat: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFloatToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBoolToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdVectorType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdShuffleVector: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSplat: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBoolNot: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdMemset: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdMemcpy: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSlice: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBreakpoint: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdReturnAddress: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFrameAddress: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFrameHandle: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFrameType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFrameSize: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAlignOf: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdOverflowOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTestErr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdUnwrapErrCode: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdUnwrapErrPayload: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFnProto: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTestComptime: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPtrCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBitCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPtrToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdIntToPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdIntToEnum: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdIntToErr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdErrToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCheckSwitchProngsUnderNo: + case Stage1ZirInstIdCheckSwitchProngsUnderYes: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCheckStatementIsVoid: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTypeName: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTagName: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPtrType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPtrTypeSimple: + case Stage1ZirInstIdPtrTypeSimpleConst: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdDeclRef: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdPanic: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFieldParentPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdOffsetOf: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdBitOffsetOf: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdTypeInfo: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdHasField: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSetEvalBranchQuota: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAlignCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdImplicitCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdResolveResult: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdResetResult: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSetAlignStack: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdArgTypeAllowVarFalse: + case Stage1ZirInstIdArgTypeAllowVarTrue: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdExport: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdExtern: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdErrorReturnTrace: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdErrorUnion: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAtomicRmw: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSaveErrRetAddr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAddImplicitReturnType: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdFloatOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdMulAdd: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAtomicLoad: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAtomicStore: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdEnumToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCheckRuntimeScope: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdHasDecl: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdUndeclaredIdent: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAlloca: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdEndExpr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdUnionInitNamedField: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSuspendBegin: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSuspendFinish: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdResume: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdAwait: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSpillBegin: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSpillEnd: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdCallArgs: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdWasmMemorySize: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdWasmMemoryGrow: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1ZirInstIdSrc: + return heap::c_allocator.destroy(reinterpret_cast(inst)); } zig_unreachable(); } @@ -368,7 +368,7 @@ bool ir_should_inline(Stage1Zir *exec, Scope *scope) { return false; } -static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, IrInstSrc *instruction) { +static void ir_instruction_append(Stage1ZirBasicBlock *basic_block, Stage1ZirInst *instruction) { assert(basic_block); assert(instruction); basic_block->instruction_list.append(instruction); @@ -384,11 +384,11 @@ static void ir_ref_bb(Stage1ZirBasicBlock *bb) { bb->ref_count += 1; } -static void ir_ref_instruction(IrInstSrc *instruction, Stage1ZirBasicBlock *cur_bb) { - assert(instruction->id != IrInstSrcIdInvalid); +static void ir_ref_instruction(Stage1ZirInst *instruction, Stage1ZirBasicBlock *cur_bb) { + assert(instruction->id != Stage1ZirInstIdInvalid); instruction->ref_count += 1; if (instruction->owner_bb != cur_bb && !instr_is_unreachable(instruction) - && instruction->id != IrInstSrcIdConst) + && instruction->id != Stage1ZirInstIdConst) { ir_ref_bb(instruction->owner_bb); } @@ -403,536 +403,536 @@ static Stage1ZirBasicBlock *ir_create_basic_block(Stage1AstGen *ag, Scope *scope return result; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcDeclVar *) { - return IrInstSrcIdDeclVar; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstDeclVar *) { + return Stage1ZirInstIdDeclVar; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBr *) { - return IrInstSrcIdBr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBr *) { + return Stage1ZirInstIdBr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCondBr *) { - return IrInstSrcIdCondBr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCondBr *) { + return Stage1ZirInstIdCondBr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchBr *) { - return IrInstSrcIdSwitchBr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchBr *) { + return Stage1ZirInstIdSwitchBr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchVar *) { - return IrInstSrcIdSwitchVar; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchVar *) { + return Stage1ZirInstIdSwitchVar; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchElseVar *) { - return IrInstSrcIdSwitchElseVar; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchElseVar *) { + return Stage1ZirInstIdSwitchElseVar; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSwitchTarget *) { - return IrInstSrcIdSwitchTarget; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSwitchTarget *) { + return Stage1ZirInstIdSwitchTarget; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcPhi *) { - return IrInstSrcIdPhi; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPhi *) { + return Stage1ZirInstIdPhi; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnOp *) { - return IrInstSrcIdUnOp; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnOp *) { + return Stage1ZirInstIdUnOp; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBinOp *) { - return IrInstSrcIdBinOp; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBinOp *) { + return Stage1ZirInstIdBinOp; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcMergeErrSets *) { - return IrInstSrcIdMergeErrSets; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMergeErrSets *) { + return Stage1ZirInstIdMergeErrSets; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcLoadPtr *) { - return IrInstSrcIdLoadPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstLoadPtr *) { + return Stage1ZirInstIdLoadPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcStorePtr *) { - return IrInstSrcIdStorePtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstStorePtr *) { + return Stage1ZirInstIdStorePtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFieldPtr *) { - return IrInstSrcIdFieldPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFieldPtr *) { + return Stage1ZirInstIdFieldPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcElemPtr *) { - return IrInstSrcIdElemPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstElemPtr *) { + return Stage1ZirInstIdElemPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcVarPtr *) { - return IrInstSrcIdVarPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstVarPtr *) { + return Stage1ZirInstIdVarPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCall *) { - return IrInstSrcIdCall; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCall *) { + return Stage1ZirInstIdCall; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCallArgs *) { - return IrInstSrcIdCallArgs; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCallArgs *) { + return Stage1ZirInstIdCallArgs; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCallExtra *) { - return IrInstSrcIdCallExtra; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCallExtra *) { + return Stage1ZirInstIdCallExtra; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAsyncCallExtra *) { - return IrInstSrcIdAsyncCallExtra; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAsyncCallExtra *) { + return Stage1ZirInstIdAsyncCallExtra; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcConst *) { - return IrInstSrcIdConst; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstConst *) { + return Stage1ZirInstIdConst; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcReturn *) { - return IrInstSrcIdReturn; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReturn *) { + return Stage1ZirInstIdReturn; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcContainerInitList *) { - return IrInstSrcIdContainerInitList; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstContainerInitList *) { + return Stage1ZirInstIdContainerInitList; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcContainerInitFields *) { - return IrInstSrcIdContainerInitFields; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstContainerInitFields *) { + return Stage1ZirInstIdContainerInitFields; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnreachable *) { - return IrInstSrcIdUnreachable; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnreachable *) { + return Stage1ZirInstIdUnreachable; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeOf *) { - return IrInstSrcIdTypeOf; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeOf *) { + return Stage1ZirInstIdTypeOf; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetCold *) { - return IrInstSrcIdSetCold; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetCold *) { + return Stage1ZirInstIdSetCold; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetRuntimeSafety *) { - return IrInstSrcIdSetRuntimeSafety; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetRuntimeSafety *) { + return Stage1ZirInstIdSetRuntimeSafety; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetFloatMode *) { - return IrInstSrcIdSetFloatMode; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetFloatMode *) { + return Stage1ZirInstIdSetFloatMode; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcArrayType *) { - return IrInstSrcIdArrayType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstArrayType *) { + return Stage1ZirInstIdArrayType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAnyFrameType *) { - return IrInstSrcIdAnyFrameType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAnyFrameType *) { + return Stage1ZirInstIdAnyFrameType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSliceType *) { - return IrInstSrcIdSliceType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSliceType *) { + return Stage1ZirInstIdSliceType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAsm *) { - return IrInstSrcIdAsm; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAsm *) { + return Stage1ZirInstIdAsm; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSizeOf *) { - return IrInstSrcIdSizeOf; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSizeOf *) { + return Stage1ZirInstIdSizeOf; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestNonNull *) { - return IrInstSrcIdTestNonNull; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestNonNull *) { + return Stage1ZirInstIdTestNonNull; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcOptionalUnwrapPtr *) { - return IrInstSrcIdOptionalUnwrapPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOptionalUnwrapPtr *) { + return Stage1ZirInstIdOptionalUnwrapPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcClz *) { - return IrInstSrcIdClz; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstClz *) { + return Stage1ZirInstIdClz; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCtz *) { - return IrInstSrcIdCtz; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCtz *) { + return Stage1ZirInstIdCtz; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcPopCount *) { - return IrInstSrcIdPopCount; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPopCount *) { + return Stage1ZirInstIdPopCount; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBswap *) { - return IrInstSrcIdBswap; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBswap *) { + return Stage1ZirInstIdBswap; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitReverse *) { - return IrInstSrcIdBitReverse; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitReverse *) { + return Stage1ZirInstIdBitReverse; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcImport *) { - return IrInstSrcIdImport; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstImport *) { + return Stage1ZirInstIdImport; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCImport *) { - return IrInstSrcIdCImport; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCImport *) { + return Stage1ZirInstIdCImport; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCInclude *) { - return IrInstSrcIdCInclude; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCInclude *) { + return Stage1ZirInstIdCInclude; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCDefine *) { - return IrInstSrcIdCDefine; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCDefine *) { + return Stage1ZirInstIdCDefine; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCUndef *) { - return IrInstSrcIdCUndef; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCUndef *) { + return Stage1ZirInstIdCUndef; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcRef *) { - return IrInstSrcIdRef; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstRef *) { + return Stage1ZirInstIdRef; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCompileErr *) { - return IrInstSrcIdCompileErr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCompileErr *) { + return Stage1ZirInstIdCompileErr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCompileLog *) { - return IrInstSrcIdCompileLog; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCompileLog *) { + return Stage1ZirInstIdCompileLog; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrName *) { - return IrInstSrcIdErrName; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrName *) { + return Stage1ZirInstIdErrName; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcEmbedFile *) { - return IrInstSrcIdEmbedFile; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEmbedFile *) { + return Stage1ZirInstIdEmbedFile; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCmpxchg *) { - return IrInstSrcIdCmpxchg; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCmpxchg *) { + return Stage1ZirInstIdCmpxchg; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFence *) { - return IrInstSrcIdFence; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFence *) { + return Stage1ZirInstIdFence; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcReduce *) { - return IrInstSrcIdReduce; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReduce *) { + return Stage1ZirInstIdReduce; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTruncate *) { - return IrInstSrcIdTruncate; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTruncate *) { + return Stage1ZirInstIdTruncate; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntCast *) { - return IrInstSrcIdIntCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntCast *) { + return Stage1ZirInstIdIntCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatCast *) { - return IrInstSrcIdFloatCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatCast *) { + return Stage1ZirInstIdFloatCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToFloat *) { - return IrInstSrcIdIntToFloat; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToFloat *) { + return Stage1ZirInstIdIntToFloat; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatToInt *) { - return IrInstSrcIdFloatToInt; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatToInt *) { + return Stage1ZirInstIdFloatToInt; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolToInt *) { - return IrInstSrcIdBoolToInt; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBoolToInt *) { + return Stage1ZirInstIdBoolToInt; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcVectorType *) { - return IrInstSrcIdVectorType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstVectorType *) { + return Stage1ZirInstIdVectorType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcShuffleVector *) { - return IrInstSrcIdShuffleVector; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstShuffleVector *) { + return Stage1ZirInstIdShuffleVector; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSplat *) { - return IrInstSrcIdSplat; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSplat *) { + return Stage1ZirInstIdSplat; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBoolNot *) { - return IrInstSrcIdBoolNot; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBoolNot *) { + return Stage1ZirInstIdBoolNot; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemset *) { - return IrInstSrcIdMemset; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMemset *) { + return Stage1ZirInstIdMemset; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcMemcpy *) { - return IrInstSrcIdMemcpy; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMemcpy *) { + return Stage1ZirInstIdMemcpy; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSlice *) { - return IrInstSrcIdSlice; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSlice *) { + return Stage1ZirInstIdSlice; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBreakpoint *) { - return IrInstSrcIdBreakpoint; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBreakpoint *) { + return Stage1ZirInstIdBreakpoint; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcReturnAddress *) { - return IrInstSrcIdReturnAddress; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstReturnAddress *) { + return Stage1ZirInstIdReturnAddress; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameAddress *) { - return IrInstSrcIdFrameAddress; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameAddress *) { + return Stage1ZirInstIdFrameAddress; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameHandle *) { - return IrInstSrcIdFrameHandle; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameHandle *) { + return Stage1ZirInstIdFrameHandle; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameType *) { - return IrInstSrcIdFrameType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameType *) { + return Stage1ZirInstIdFrameType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFrameSize *) { - return IrInstSrcIdFrameSize; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFrameSize *) { + return Stage1ZirInstIdFrameSize; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlignOf *) { - return IrInstSrcIdAlignOf; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlignOf *) { + return Stage1ZirInstIdAlignOf; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcOverflowOp *) { - return IrInstSrcIdOverflowOp; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOverflowOp *) { + return Stage1ZirInstIdOverflowOp; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestErr *) { - return IrInstSrcIdTestErr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestErr *) { + return Stage1ZirInstIdTestErr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcMulAdd *) { - return IrInstSrcIdMulAdd; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMulAdd *) { + return Stage1ZirInstIdMulAdd; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFloatOp *) { - return IrInstSrcIdFloatOp; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFloatOp *) { + return Stage1ZirInstIdFloatOp; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnwrapErrCode *) { - return IrInstSrcIdUnwrapErrCode; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnwrapErrCode *) { + return Stage1ZirInstIdUnwrapErrCode; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnwrapErrPayload *) { - return IrInstSrcIdUnwrapErrPayload; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnwrapErrPayload *) { + return Stage1ZirInstIdUnwrapErrPayload; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFnProto *) { - return IrInstSrcIdFnProto; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFnProto *) { + return Stage1ZirInstIdFnProto; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTestComptime *) { - return IrInstSrcIdTestComptime; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTestComptime *) { + return Stage1ZirInstIdTestComptime; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrCast *) { - return IrInstSrcIdPtrCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrCast *) { + return Stage1ZirInstIdPtrCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitCast *) { - return IrInstSrcIdBitCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitCast *) { + return Stage1ZirInstIdBitCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToPtr *) { - return IrInstSrcIdIntToPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToPtr *) { + return Stage1ZirInstIdIntToPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrToInt *) { - return IrInstSrcIdPtrToInt; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrToInt *) { + return Stage1ZirInstIdPtrToInt; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToEnum *) { - return IrInstSrcIdIntToEnum; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToEnum *) { + return Stage1ZirInstIdIntToEnum; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcEnumToInt *) { - return IrInstSrcIdEnumToInt; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEnumToInt *) { + return Stage1ZirInstIdEnumToInt; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcIntToErr *) { - return IrInstSrcIdIntToErr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstIntToErr *) { + return Stage1ZirInstIdIntToErr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrToInt *) { - return IrInstSrcIdErrToInt; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrToInt *) { + return Stage1ZirInstIdErrToInt; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCheckStatementIsVoid *) { - return IrInstSrcIdCheckStatementIsVoid; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCheckStatementIsVoid *) { + return Stage1ZirInstIdCheckStatementIsVoid; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeName *) { - return IrInstSrcIdTypeName; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeName *) { + return Stage1ZirInstIdTypeName; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcDeclRef *) { - return IrInstSrcIdDeclRef; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstDeclRef *) { + return Stage1ZirInstIdDeclRef; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcPanic *) { - return IrInstSrcIdPanic; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPanic *) { + return Stage1ZirInstIdPanic; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTagName *) { - return IrInstSrcIdTagName; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTagName *) { + return Stage1ZirInstIdTagName; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcFieldParentPtr *) { - return IrInstSrcIdFieldParentPtr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstFieldParentPtr *) { + return Stage1ZirInstIdFieldParentPtr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcOffsetOf *) { - return IrInstSrcIdOffsetOf; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstOffsetOf *) { + return Stage1ZirInstIdOffsetOf; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcBitOffsetOf *) { - return IrInstSrcIdBitOffsetOf; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstBitOffsetOf *) { + return Stage1ZirInstIdBitOffsetOf; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcTypeInfo *) { - return IrInstSrcIdTypeInfo; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstTypeInfo *) { + return Stage1ZirInstIdTypeInfo; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcType *) { - return IrInstSrcIdType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstType *) { + return Stage1ZirInstIdType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcHasField *) { - return IrInstSrcIdHasField; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstHasField *) { + return Stage1ZirInstIdHasField; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetEvalBranchQuota *) { - return IrInstSrcIdSetEvalBranchQuota; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetEvalBranchQuota *) { + return Stage1ZirInstIdSetEvalBranchQuota; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcPtrType *) { - return IrInstSrcIdPtrType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstPtrType *) { + return Stage1ZirInstIdPtrType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlignCast *) { - return IrInstSrcIdAlignCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlignCast *) { + return Stage1ZirInstIdAlignCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcImplicitCast *) { - return IrInstSrcIdImplicitCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstImplicitCast *) { + return Stage1ZirInstIdImplicitCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcResolveResult *) { - return IrInstSrcIdResolveResult; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResolveResult *) { + return Stage1ZirInstIdResolveResult; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcResetResult *) { - return IrInstSrcIdResetResult; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResetResult *) { + return Stage1ZirInstIdResetResult; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSetAlignStack *) { - return IrInstSrcIdSetAlignStack; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSetAlignStack *) { + return Stage1ZirInstIdSetAlignStack; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcExport *) { - return IrInstSrcIdExport; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstExport *) { + return Stage1ZirInstIdExport; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcExtern *) { - return IrInstSrcIdExtern; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstExtern *) { + return Stage1ZirInstIdExtern; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrorReturnTrace *) { - return IrInstSrcIdErrorReturnTrace; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrorReturnTrace *) { + return Stage1ZirInstIdErrorReturnTrace; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrorUnion *) { - return IrInstSrcIdErrorUnion; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrorUnion *) { + return Stage1ZirInstIdErrorUnion; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicRmw *) { - return IrInstSrcIdAtomicRmw; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicRmw *) { + return Stage1ZirInstIdAtomicRmw; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicLoad *) { - return IrInstSrcIdAtomicLoad; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicLoad *) { + return Stage1ZirInstIdAtomicLoad; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAtomicStore *) { - return IrInstSrcIdAtomicStore; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAtomicStore *) { + return Stage1ZirInstIdAtomicStore; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSaveErrRetAddr *) { - return IrInstSrcIdSaveErrRetAddr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSaveErrRetAddr *) { + return Stage1ZirInstIdSaveErrRetAddr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAddImplicitReturnType *) { - return IrInstSrcIdAddImplicitReturnType; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAddImplicitReturnType *) { + return Stage1ZirInstIdAddImplicitReturnType; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcErrSetCast *) { - return IrInstSrcIdErrSetCast; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstErrSetCast *) { + return Stage1ZirInstIdErrSetCast; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcCheckRuntimeScope *) { - return IrInstSrcIdCheckRuntimeScope; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstCheckRuntimeScope *) { + return Stage1ZirInstIdCheckRuntimeScope; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcHasDecl *) { - return IrInstSrcIdHasDecl; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstHasDecl *) { + return Stage1ZirInstIdHasDecl; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcUndeclaredIdent *) { - return IrInstSrcIdUndeclaredIdent; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUndeclaredIdent *) { + return Stage1ZirInstIdUndeclaredIdent; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAlloca *) { - return IrInstSrcIdAlloca; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAlloca *) { + return Stage1ZirInstIdAlloca; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcEndExpr *) { - return IrInstSrcIdEndExpr; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstEndExpr *) { + return Stage1ZirInstIdEndExpr; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcUnionInitNamedField *) { - return IrInstSrcIdUnionInitNamedField; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstUnionInitNamedField *) { + return Stage1ZirInstIdUnionInitNamedField; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSuspendBegin *) { - return IrInstSrcIdSuspendBegin; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSuspendBegin *) { + return Stage1ZirInstIdSuspendBegin; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSuspendFinish *) { - return IrInstSrcIdSuspendFinish; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSuspendFinish *) { + return Stage1ZirInstIdSuspendFinish; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcAwait *) { - return IrInstSrcIdAwait; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstAwait *) { + return Stage1ZirInstIdAwait; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcResume *) { - return IrInstSrcIdResume; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstResume *) { + return Stage1ZirInstIdResume; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillBegin *) { - return IrInstSrcIdSpillBegin; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSpillBegin *) { + return Stage1ZirInstIdSpillBegin; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSpillEnd *) { - return IrInstSrcIdSpillEnd; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSpillEnd *) { + return Stage1ZirInstIdSpillEnd; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemorySize *) { - return IrInstSrcIdWasmMemorySize; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstWasmMemorySize *) { + return Stage1ZirInstIdWasmMemorySize; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcWasmMemoryGrow *) { - return IrInstSrcIdWasmMemoryGrow; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstWasmMemoryGrow *) { + return Stage1ZirInstIdWasmMemoryGrow; } -static constexpr IrInstSrcId ir_inst_id(IrInstSrcSrc *) { - return IrInstSrcIdSrc; +static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSrc *) { + return Stage1ZirInstIdSrc; } template @@ -953,10 +953,10 @@ static T *ir_build_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_n return special_instruction; } -static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *condition, - Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, IrInstSrc *is_comptime) +static Stage1ZirInst *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *condition, + Stage1ZirBasicBlock *then_block, Stage1ZirBasicBlock *else_block, Stage1ZirInst *is_comptime) { - IrInstSrcCondBr *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCondBr *inst = ir_build_instruction(ag, scope, source_node); inst->condition = condition; inst->then_block = then_block; inst->else_block = else_block; @@ -970,8 +970,8 @@ static IrInstSrc *ir_build_cond_br(Stage1AstGen *ag, Scope *scope, AstNode *sour return &inst->base; } -static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand) { - IrInstSrcReturn *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *operand) { + Stage1ZirInstReturn *inst = ir_build_instruction(ag, scope, source_node); inst->operand = operand; if (operand != nullptr) ir_ref_instruction(operand, ag->current_basic_block); @@ -979,23 +979,23 @@ static IrInstSrc *ir_build_return_src(Stage1AstGen *ag, Scope *scope, AstNode *s return &inst->base; } -static IrInstSrc *ir_build_const_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcConst *const_instruction = ir_create_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstConst *const_instruction = ir_create_instruction(ag, scope, source_node); ir_instruction_append(ag->current_basic_block, &const_instruction->base); const_instruction->value = ag->codegen->intern.for_void(); return &const_instruction->base; } -static IrInstSrc *ir_build_const_undefined(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcConst *const_instruction = ir_create_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_undefined(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstConst *const_instruction = ir_create_instruction(ag, scope, source_node); ir_instruction_append(ag->current_basic_block, &const_instruction->base); const_instruction->value = ag->codegen->intern.for_undefined(); const_instruction->value->special = ConstValSpecialUndef; return &const_instruction->base; } -static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) { + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int; const_instruction->value->special = ConstValSpecialStatic; @@ -1003,10 +1003,10 @@ static IrInstSrc *ir_build_const_uint(Stage1AstGen *ag, Scope *scope, AstNode *s return &const_instruction->base; } -static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode *source_node, BigInt bigint) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_int; const_instruction->value->special = ConstValSpecialStatic; @@ -1014,10 +1014,10 @@ static IrInstSrc *ir_build_const_bigint(Stage1AstGen *ag, Scope *scope, AstNode return &const_instruction->base; } -static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNode *source_node, BigFloat bigfloat) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_num_lit_float; const_instruction->value->special = ConstValSpecialStatic; @@ -1025,15 +1025,15 @@ static IrInstSrc *ir_build_const_bigfloat(Stage1AstGen *ag, Scope *scope, AstNod return &const_instruction->base; } -static IrInstSrc *ir_build_const_null(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcConst *const_instruction = ir_create_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_null(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstConst *const_instruction = ir_create_instruction(ag, scope, source_node); ir_instruction_append(ag->current_basic_block, &const_instruction->base); const_instruction->value = ag->codegen->intern.for_null(); return &const_instruction->base; } -static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode *source_node, uint64_t value) { + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_usize; const_instruction->value->special = ConstValSpecialStatic; @@ -1041,10 +1041,10 @@ static IrInstSrc *ir_build_const_usize(Stage1AstGen *ag, Scope *scope, AstNode * return &const_instruction->base; } -static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *type_entry) { - IrInstSrcConst *const_instruction = ir_create_instruction(ag, scope, source_node); + Stage1ZirInstConst *const_instruction = ir_create_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_type; const_instruction->value->special = ConstValSpecialStatic; @@ -1052,16 +1052,16 @@ static IrInstSrc *ir_create_const_type(Stage1AstGen *ag, Scope *scope, AstNode * return &const_instruction->base; } -static IrInstSrc *ir_build_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *ir_build_const_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *type_entry) { - IrInstSrc *instruction = ir_create_const_type(ag, scope, source_node, type_entry); + Stage1ZirInst *instruction = ir_create_const_type(ag, scope, source_node, type_entry); ir_instruction_append(ag->current_basic_block, instruction); return instruction; } -static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *import) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigType *import) { + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_type; const_instruction->value->special = ConstValSpecialStatic; @@ -1069,8 +1069,8 @@ static IrInstSrc *ir_build_const_import(Stage1AstGen *ag, Scope *scope, AstNode return &const_instruction->base; } -static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *source_node, bool value) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *source_node, bool value) { + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_bool; const_instruction->value->special = ConstValSpecialStatic; @@ -1078,8 +1078,8 @@ static IrInstSrc *ir_build_const_bool(Stage1AstGen *ag, Scope *scope, AstNode *s return &const_instruction->base; } -static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) { + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = ag->codegen->builtin_types.entry_enum_literal; const_instruction->value->special = ConstValSpecialStatic; @@ -1088,8 +1088,8 @@ static IrInstSrc *ir_build_const_enum_literal(Stage1AstGen *ag, Scope *scope, As } // Consumes `str`. -static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) { - IrInstSrcConst *const_instruction = ir_create_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) { + Stage1ZirInstConst *const_instruction = ir_create_instruction(ag, scope, source_node); const_instruction->value = ag->codegen->pass1_arena->create(); init_const_str_lit(ag->codegen, const_instruction->value, str, true); @@ -1097,16 +1097,16 @@ static IrInstSrc *ir_create_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNod } // Consumes `str`. -static IrInstSrc *ir_build_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) { - IrInstSrc *instruction = ir_create_const_str_lit(ag, scope, source_node, str); +static Stage1ZirInst *ir_build_const_str_lit(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *str) { + Stage1ZirInst *instruction = ir_create_const_str_lit(ag, scope, source_node, str); ir_instruction_append(ag->current_basic_block, instruction); return instruction; } -static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrBinOp op_id, - IrInstSrc *op1, IrInstSrc *op2, bool safety_check_on) +static Stage1ZirInst *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrBinOp op_id, + Stage1ZirInst *op1, Stage1ZirInst *op2, bool safety_check_on) { - IrInstSrcBinOp *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstBinOp *inst = ir_build_instruction(ag, scope, source_node); inst->op_id = op_id; inst->op1 = op1; inst->op2 = op2; @@ -1118,10 +1118,10 @@ static IrInstSrc *ir_build_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *sourc return &inst->base; } -static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *op1, IrInstSrc *op2, Buf *type_name) +static Stage1ZirInst *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *op1, Stage1ZirInst *op2, Buf *type_name) { - IrInstSrcMergeErrSets *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstMergeErrSets *inst = ir_build_instruction(ag, scope, source_node); inst->op1 = op1; inst->op2 = op2; inst->type_name = type_name; @@ -1132,10 +1132,10 @@ static IrInstSrc *ir_build_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNod return &inst->base; } -static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var, +static Stage1ZirInst *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var, ScopeFnDef *crossed_fndef_scope) { - IrInstSrcVarPtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstVarPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->var = var; instruction->crossed_fndef_scope = crossed_fndef_scope; @@ -1144,15 +1144,15 @@ static IrInstSrc *ir_build_var_ptr_x(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_var_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var) { +static Stage1ZirInst *ir_build_var_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var) { return ir_build_var_ptr_x(ag, scope, source_node, var, nullptr); } -static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *array_ptr, IrInstSrc *elem_index, bool safety_check_on, PtrLen ptr_len, +static Stage1ZirInst *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *array_ptr, Stage1ZirInst *elem_index, bool safety_check_on, PtrLen ptr_len, AstNode *init_array_type_source_node) { - IrInstSrcElemPtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstElemPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->array_ptr = array_ptr; instruction->elem_index = elem_index; instruction->safety_check_on = safety_check_on; @@ -1165,10 +1165,10 @@ static IrInstSrc *ir_build_elem_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *container_ptr, IrInstSrc *field_name_expr, bool initializing) +static Stage1ZirInst *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *container_ptr, Stage1ZirInst *field_name_expr, bool initializing) { - IrInstSrcFieldPtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstFieldPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->container_ptr = container_ptr; instruction->field_name_buffer = nullptr; instruction->field_name_expr = field_name_expr; @@ -1180,10 +1180,10 @@ static IrInstSrc *ir_build_field_ptr_instruction(Stage1AstGen *ag, Scope *scope, return &instruction->base; } -static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *container_ptr, Buf *field_name, bool initializing) +static Stage1ZirInst *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *container_ptr, Buf *field_name, bool initializing) { - IrInstSrcFieldPtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstFieldPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->container_ptr = container_ptr; instruction->field_name_buffer = field_name; instruction->field_name_expr = nullptr; @@ -1194,10 +1194,10 @@ static IrInstSrc *ir_build_field_ptr(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *container_type, IrInstSrc *field_name) +static Stage1ZirInst *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *container_type, Stage1ZirInst *field_name) { - IrInstSrcHasField *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstHasField *instruction = ir_build_instruction(ag, scope, source_node); instruction->container_type = container_type; instruction->field_name = field_name; @@ -1207,10 +1207,10 @@ static IrInstSrc *ir_build_has_field(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *options, IrInstSrc *fn_ref, IrInstSrc *args, ResultLoc *result_loc) +static Stage1ZirInst *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *options, Stage1ZirInst *fn_ref, Stage1ZirInst *args, ResultLoc *result_loc) { - IrInstSrcCallExtra *call_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCallExtra *call_instruction = ir_build_instruction(ag, scope, source_node); call_instruction->options = options; call_instruction->fn_ref = fn_ref; call_instruction->args = args; @@ -1223,10 +1223,10 @@ static IrInstSrc *ir_build_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *s return &call_instruction->base; } -static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - CallModifier modifier, IrInstSrc *fn_ref, IrInstSrc *ret_ptr, IrInstSrc *new_stack, IrInstSrc *args, ResultLoc *result_loc) +static Stage1ZirInst *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + CallModifier modifier, Stage1ZirInst *fn_ref, Stage1ZirInst *ret_ptr, Stage1ZirInst *new_stack, Stage1ZirInst *args, ResultLoc *result_loc) { - IrInstSrcAsyncCallExtra *call_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAsyncCallExtra *call_instruction = ir_build_instruction(ag, scope, source_node); call_instruction->modifier = modifier; call_instruction->fn_ref = fn_ref; call_instruction->ret_ptr = ret_ptr; @@ -1242,11 +1242,11 @@ static IrInstSrc *ir_build_async_call_extra(Stage1AstGen *ag, Scope *scope, AstN return &call_instruction->base; } -static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *options, IrInstSrc *fn_ref, IrInstSrc **args_ptr, size_t args_len, +static Stage1ZirInst *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *options, Stage1ZirInst *fn_ref, Stage1ZirInst **args_ptr, size_t args_len, ResultLoc *result_loc) { - IrInstSrcCallArgs *call_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCallArgs *call_instruction = ir_build_instruction(ag, scope, source_node); call_instruction->options = options; call_instruction->fn_ref = fn_ref; call_instruction->args_ptr = args_ptr; @@ -1261,12 +1261,12 @@ static IrInstSrc *ir_build_call_args(Stage1AstGen *ag, Scope *scope, AstNode *so return &call_instruction->base; } -static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - ZigFn *fn_entry, IrInstSrc *fn_ref, size_t arg_count, IrInstSrc **args, - IrInstSrc *ret_ptr, CallModifier modifier, bool is_async_call_builtin, - IrInstSrc *new_stack, ResultLoc *result_loc) +static Stage1ZirInst *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + ZigFn *fn_entry, Stage1ZirInst *fn_ref, size_t arg_count, Stage1ZirInst **args, + Stage1ZirInst *ret_ptr, CallModifier modifier, bool is_async_call_builtin, + Stage1ZirInst *new_stack, ResultLoc *result_loc) { - IrInstSrcCall *call_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCall *call_instruction = ir_build_instruction(ag, scope, source_node); call_instruction->fn_entry = fn_entry; call_instruction->fn_ref = fn_ref; call_instruction->args = args; @@ -1286,14 +1286,14 @@ static IrInstSrc *ir_build_call_src(Stage1AstGen *ag, Scope *scope, AstNode *sou return &call_instruction->base; } -static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, IrInstSrc **incoming_values, +static Stage1ZirInst *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + size_t incoming_count, Stage1ZirBasicBlock **incoming_blocks, Stage1ZirInst **incoming_values, ResultLocPeerParent *peer_parent) { assert(incoming_count != 0); assert(incoming_count != SIZE_MAX); - IrInstSrcPhi *phi_instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstPhi *phi_instruction = ir_build_instruction(ag, scope, source_node); phi_instruction->incoming_count = incoming_count; phi_instruction->incoming_blocks = incoming_blocks; phi_instruction->incoming_values = incoming_values; @@ -1307,10 +1307,10 @@ static IrInstSrc *ir_build_phi(Stage1AstGen *ag, Scope *scope, AstNode *source_n return &phi_instruction->base; } -static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - Stage1ZirBasicBlock *dest_block, IrInstSrc *is_comptime) +static Stage1ZirInst *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirBasicBlock *dest_block, Stage1ZirInst *is_comptime) { - IrInstSrcBr *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstBr *inst = ir_build_instruction(ag, scope, source_node); inst->dest_block = dest_block; inst->is_comptime = is_comptime; @@ -1320,11 +1320,11 @@ static IrInstSrc *ir_build_br(Stage1AstGen *ag, Scope *scope, AstNode *source_no return &inst->base; } -static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *child_type, bool is_const) +static Stage1ZirInst *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *child_type, bool is_const) { - IrInstSrcPtrTypeSimple *inst = heap::c_allocator.create(); - inst->base.id = is_const ? IrInstSrcIdPtrTypeSimpleConst : IrInstSrcIdPtrTypeSimple; + Stage1ZirInstPtrTypeSimple *inst = heap::c_allocator.create(); + inst->base.id = is_const ? Stage1ZirInstIdPtrTypeSimpleConst : Stage1ZirInstIdPtrTypeSimple; inst->base.scope = scope; inst->base.source_node = source_node; inst->base.debug_id = irb_next_debug_id(ag); @@ -1338,9 +1338,9 @@ static IrInstSrc *ir_build_ptr_type_simple(Stage1AstGen *ag, Scope *scope, AstNo return &inst->base; } -static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *child_type, bool is_const, bool is_volatile, PtrLen ptr_len, - IrInstSrc *sentinel, IrInstSrc *align_value, +static Stage1ZirInst *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *child_type, bool is_const, bool is_volatile, PtrLen ptr_len, + Stage1ZirInst *sentinel, Stage1ZirInst *align_value, uint32_t bit_offset_start, uint32_t host_int_bytes, bool is_allow_zero) { if (!is_volatile && ptr_len == PtrLenSingle && sentinel == nullptr && align_value == nullptr && @@ -1349,7 +1349,7 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou return ir_build_ptr_type_simple(ag, scope, source_node, child_type, is_const); } - IrInstSrcPtrType *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstPtrType *inst = ir_build_instruction(ag, scope, source_node); inst->sentinel = sentinel; inst->align_value = align_value; inst->child_type = child_type; @@ -1367,10 +1367,10 @@ static IrInstSrc *ir_build_ptr_type(Stage1AstGen *ag, Scope *scope, AstNode *sou return &inst->base; } -static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id, - IrInstSrc *value, LVal lval, ResultLoc *result_loc) +static Stage1ZirInst *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id, + Stage1ZirInst *value, LVal lval, ResultLoc *result_loc) { - IrInstSrcUnOp *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstUnOp *instruction = ir_build_instruction(ag, scope, source_node); instruction->op_id = op_id; instruction->value = value; instruction->lval = lval; @@ -1381,18 +1381,18 @@ static IrInstSrc *ir_build_un_op_lval(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_un_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id, - IrInstSrc *value) +static Stage1ZirInst *ir_build_un_op(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrUnOp op_id, + Stage1ZirInst *value) { return ir_build_un_op_lval(ag, scope, source_node, op_id, value, LValNone, nullptr); } -static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - size_t item_count, IrInstSrc **elem_result_loc_list, IrInstSrc *result_loc, +static Stage1ZirInst *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + size_t item_count, Stage1ZirInst **elem_result_loc_list, Stage1ZirInst *result_loc, AstNode *init_array_type_source_node) { - IrInstSrcContainerInitList *container_init_list_instruction = - ir_build_instruction(ag, scope, source_node); + Stage1ZirInstContainerInitList *container_init_list_instruction = + ir_build_instruction(ag, scope, source_node); container_init_list_instruction->item_count = item_count; container_init_list_instruction->elem_result_loc_list = elem_result_loc_list; container_init_list_instruction->result_loc = result_loc; @@ -1406,11 +1406,11 @@ static IrInstSrc *ir_build_container_init_list(Stage1AstGen *ag, Scope *scope, A return &container_init_list_instruction->base; } -static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - size_t field_count, IrInstSrcContainerInitFieldsField *fields, IrInstSrc *result_loc) +static Stage1ZirInst *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + size_t field_count, Stage1ZirInstContainerInitFieldsField *fields, Stage1ZirInst *result_loc) { - IrInstSrcContainerInitFields *container_init_fields_instruction = - ir_build_instruction(ag, scope, source_node); + Stage1ZirInstContainerInitFields *container_init_fields_instruction = + ir_build_instruction(ag, scope, source_node); container_init_fields_instruction->field_count = field_count; container_init_fields_instruction->fields = fields; container_init_fields_instruction->result_loc = result_loc; @@ -1423,15 +1423,15 @@ static IrInstSrc *ir_build_container_init_fields(Stage1AstGen *ag, Scope *scope, return &container_init_fields_instruction->base; } -static IrInstSrc *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcUnreachable *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstUnreachable *inst = ir_build_instruction(ag, scope, source_node); return &inst->base; } -static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *ptr, IrInstSrc *value) +static Stage1ZirInstStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *ptr, Stage1ZirInst *value) { - IrInstSrcStorePtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstStorePtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->ptr = ptr; instruction->value = value; @@ -1441,10 +1441,10 @@ static IrInstSrcStorePtr *ir_build_store_ptr(Stage1AstGen *ag, Scope *scope, Ast return instruction; } -static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - ZigVar *var, IrInstSrc *align_value, IrInstSrc *ptr) +static Stage1ZirInst *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + ZigVar *var, Stage1ZirInst *align_value, Stage1ZirInst *ptr) { - IrInstSrcDeclVar *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstDeclVar *inst = ir_build_instruction(ag, scope, source_node); inst->var = var; inst->align_value = align_value; inst->ptr = ptr; @@ -1455,10 +1455,10 @@ static IrInstSrc *ir_build_var_decl_src(Stage1AstGen *ag, Scope *scope, AstNode return &inst->base; } -static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target, IrInstSrc *options) +static Stage1ZirInst *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target, Stage1ZirInst *options) { - IrInstSrcExport *export_instruction = ir_build_instruction( + Stage1ZirInstExport *export_instruction = ir_build_instruction( ag, scope, source_node); export_instruction->target = target; export_instruction->options = options; @@ -1469,10 +1469,10 @@ static IrInstSrc *ir_build_export(Stage1AstGen *ag, Scope *scope, AstNode *sourc return &export_instruction->base; } -static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type, IrInstSrc *options) +static Stage1ZirInst *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type, Stage1ZirInst *options) { - IrInstSrcExtern *extern_instruction = ir_build_instruction( + Stage1ZirInstExtern *extern_instruction = ir_build_instruction( ag, scope, source_node); extern_instruction->type = type; extern_instruction->options = options; @@ -1483,8 +1483,8 @@ static IrInstSrc *ir_build_extern(Stage1AstGen *ag, Scope *scope, AstNode *sourc return &extern_instruction->base; } -static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *ptr) { - IrInstSrcLoadPtr *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *ptr) { + Stage1ZirInstLoadPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->ptr = ptr; ir_ref_instruction(ptr, ag->current_basic_block); @@ -1492,12 +1492,12 @@ static IrInstSrc *ir_build_load_ptr(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc **values, size_t value_count) +static Stage1ZirInst *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst **values, size_t value_count) { assert(value_count >= 2); - IrInstSrcTypeOf *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstTypeOf *instruction = ir_build_instruction(ag, scope, source_node); instruction->value.list = values; instruction->value_count = value_count; @@ -1507,8 +1507,8 @@ static IrInstSrc *ir_build_typeof_n(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) { - IrInstSrcTypeOf *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) { + Stage1ZirInstTypeOf *instruction = ir_build_instruction(ag, scope, source_node); instruction->value.scalar = value; ir_ref_instruction(value, ag->current_basic_block); @@ -1516,8 +1516,8 @@ static IrInstSrc *ir_build_typeof_1(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *is_cold) { - IrInstSrcSetCold *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *is_cold) { + Stage1ZirInstSetCold *instruction = ir_build_instruction(ag, scope, source_node); instruction->is_cold = is_cold; ir_ref_instruction(is_cold, ag->current_basic_block); @@ -1525,10 +1525,10 @@ static IrInstSrc *ir_build_set_cold(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *safety_on) +static Stage1ZirInst *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *safety_on) { - IrInstSrcSetRuntimeSafety *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSetRuntimeSafety *inst = ir_build_instruction(ag, scope, source_node); inst->safety_on = safety_on; ir_ref_instruction(safety_on, ag->current_basic_block); @@ -1536,10 +1536,10 @@ static IrInstSrc *ir_build_set_runtime_safety(Stage1AstGen *ag, Scope *scope, As return &inst->base; } -static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *mode_value) +static Stage1ZirInst *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *mode_value) { - IrInstSrcSetFloatMode *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSetFloatMode *instruction = ir_build_instruction(ag, scope, source_node); instruction->mode_value = mode_value; ir_ref_instruction(mode_value, ag->current_basic_block); @@ -1547,10 +1547,10 @@ static IrInstSrc *ir_build_set_float_mode(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *size, - IrInstSrc *sentinel, IrInstSrc *child_type) +static Stage1ZirInst *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *size, + Stage1ZirInst *sentinel, Stage1ZirInst *child_type) { - IrInstSrcArrayType *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstArrayType *instruction = ir_build_instruction(ag, scope, source_node); instruction->size = size; instruction->sentinel = sentinel; instruction->child_type = child_type; @@ -1562,10 +1562,10 @@ static IrInstSrc *ir_build_array_type(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *payload_type) +static Stage1ZirInst *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *payload_type) { - IrInstSrcAnyFrameType *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAnyFrameType *instruction = ir_build_instruction(ag, scope, source_node); instruction->payload_type = payload_type; if (payload_type != nullptr) ir_ref_instruction(payload_type, ag->current_basic_block); @@ -1573,11 +1573,11 @@ static IrInstSrc *ir_build_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *child_type, bool is_const, bool is_volatile, - IrInstSrc *sentinel, IrInstSrc *align_value, bool is_allow_zero) +static Stage1ZirInst *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *child_type, bool is_const, bool is_volatile, + Stage1ZirInst *sentinel, Stage1ZirInst *align_value, bool is_allow_zero) { - IrInstSrcSliceType *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSliceType *instruction = ir_build_instruction(ag, scope, source_node); instruction->is_const = is_const; instruction->is_volatile = is_volatile; instruction->child_type = child_type; @@ -1592,11 +1592,11 @@ static IrInstSrc *ir_build_slice_type(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *asm_template, IrInstSrc **input_list, IrInstSrc **output_types, +static Stage1ZirInst *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *asm_template, Stage1ZirInst **input_list, Stage1ZirInst **output_types, ZigVar **output_vars, size_t return_count, bool has_side_effects, bool is_global) { - IrInstSrcAsm *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAsm *instruction = ir_build_instruction(ag, scope, source_node); instruction->asm_template = asm_template; instruction->input_list = input_list; instruction->output_types = output_types; @@ -1607,22 +1607,22 @@ static IrInstSrc *ir_build_asm_src(Stage1AstGen *ag, Scope *scope, AstNode *sour assert(source_node->type == NodeTypeAsmExpr); for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) { - IrInstSrc *output_type = output_types[i]; + Stage1ZirInst *output_type = output_types[i]; if (output_type) ir_ref_instruction(output_type, ag->current_basic_block); } for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) { - IrInstSrc *input_value = input_list[i]; + Stage1ZirInst *input_value = input_list[i]; ir_ref_instruction(input_value, ag->current_basic_block); } return &instruction->base; } -static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value, +static Stage1ZirInst *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value, bool bit_size) { - IrInstSrcSizeOf *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSizeOf *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; instruction->bit_size = bit_size; @@ -1631,10 +1631,10 @@ static IrInstSrc *ir_build_size_of(Stage1AstGen *ag, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *value) +static Stage1ZirInst *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *value) { - IrInstSrcTestNonNull *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstTestNonNull *instruction = ir_build_instruction(ag, scope, source_node); instruction->value = value; ir_ref_instruction(value, ag->current_basic_block); @@ -1642,10 +1642,10 @@ static IrInstSrc *ir_build_test_non_null_src(Stage1AstGen *ag, Scope *scope, Ast return &instruction->base; } -static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *base_ptr, bool safety_check_on) +static Stage1ZirInst *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *base_ptr, bool safety_check_on) { - IrInstSrcOptionalUnwrapPtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstOptionalUnwrapPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->base_ptr = base_ptr; instruction->safety_check_on = safety_check_on; @@ -1654,10 +1654,10 @@ static IrInstSrc *ir_build_optional_unwrap_ptr(Stage1AstGen *ag, Scope *scope, A return &instruction->base; } -static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type, - IrInstSrc *op) +static Stage1ZirInst *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type, + Stage1ZirInst *op) { - IrInstSrcClz *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstClz *instruction = ir_build_instruction(ag, scope, source_node); instruction->type = type; instruction->op = op; @@ -1667,10 +1667,10 @@ static IrInstSrc *ir_build_clz(Stage1AstGen *ag, Scope *scope, AstNode *source_n return &instruction->base; } -static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type, - IrInstSrc *op) +static Stage1ZirInst *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type, + Stage1ZirInst *op) { - IrInstSrcCtz *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCtz *instruction = ir_build_instruction(ag, scope, source_node); instruction->type = type; instruction->op = op; @@ -1680,10 +1680,10 @@ static IrInstSrc *ir_build_ctz(Stage1AstGen *ag, Scope *scope, AstNode *source_n return &instruction->base; } -static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type, - IrInstSrc *op) +static Stage1ZirInst *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type, + Stage1ZirInst *op) { - IrInstSrcPopCount *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstPopCount *instruction = ir_build_instruction(ag, scope, source_node); instruction->type = type; instruction->op = op; @@ -1693,10 +1693,10 @@ static IrInstSrc *ir_build_pop_count(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type, - IrInstSrc *op) +static Stage1ZirInst *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type, + Stage1ZirInst *op) { - IrInstSrcBswap *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstBswap *instruction = ir_build_instruction(ag, scope, source_node); instruction->type = type; instruction->op = op; @@ -1706,10 +1706,10 @@ static IrInstSrc *ir_build_bswap(Stage1AstGen *ag, Scope *scope, AstNode *source return &instruction->base; } -static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type, - IrInstSrc *op) +static Stage1ZirInst *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type, + Stage1ZirInst *op) { - IrInstSrcBitReverse *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstBitReverse *instruction = ir_build_instruction(ag, scope, source_node); instruction->type = type; instruction->op = op; @@ -1719,11 +1719,11 @@ static IrInstSrc *ir_build_bit_reverse(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, IrInstSrcSwitchBrCase *cases, - IrInstSrc *is_comptime, IrInstSrc *switch_prongs_void) +static Stage1ZirInstSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target_value, Stage1ZirBasicBlock *else_block, size_t case_count, Stage1ZirInstSwitchBrCase *cases, + Stage1ZirInst *is_comptime, Stage1ZirInst *switch_prongs_void) { - IrInstSrcSwitchBr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSwitchBr *instruction = ir_build_instruction(ag, scope, source_node); instruction->target_value = target_value; instruction->else_block = else_block; instruction->case_count = case_count; @@ -1744,10 +1744,10 @@ static IrInstSrcSwitchBr *ir_build_switch_br_src(Stage1AstGen *ag, Scope *scope, return instruction; } -static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target_value_ptr) +static Stage1ZirInst *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target_value_ptr) { - IrInstSrcSwitchTarget *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSwitchTarget *instruction = ir_build_instruction(ag, scope, source_node); instruction->target_value_ptr = target_value_ptr; ir_ref_instruction(target_value_ptr, ag->current_basic_block); @@ -1755,10 +1755,10 @@ static IrInstSrc *ir_build_switch_target(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target_value_ptr, IrInstSrc **prongs_ptr, size_t prongs_len) +static Stage1ZirInst *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target_value_ptr, Stage1ZirInst **prongs_ptr, size_t prongs_len) { - IrInstSrcSwitchVar *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSwitchVar *instruction = ir_build_instruction(ag, scope, source_node); instruction->target_value_ptr = target_value_ptr; instruction->prongs_ptr = prongs_ptr; instruction->prongs_len = prongs_len; @@ -1772,10 +1772,10 @@ static IrInstSrc *ir_build_switch_var(Stage1AstGen *ag, Scope *scope, AstNode *s } // For this instruction the switch_br must be set later. -static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target_value_ptr) +static Stage1ZirInstSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target_value_ptr) { - IrInstSrcSwitchElseVar *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSwitchElseVar *instruction = ir_build_instruction(ag, scope, source_node); instruction->target_value_ptr = target_value_ptr; ir_ref_instruction(target_value_ptr, ag->current_basic_block); @@ -1783,8 +1783,8 @@ static IrInstSrcSwitchElseVar *ir_build_switch_else_var(Stage1AstGen *ag, Scope return instruction; } -static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) { - IrInstSrcImport *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) { + Stage1ZirInstImport *instruction = ir_build_instruction(ag, scope, source_node); instruction->name = name; ir_ref_instruction(name, ag->current_basic_block); @@ -1792,8 +1792,8 @@ static IrInstSrc *ir_build_import(Stage1AstGen *ag, Scope *scope, AstNode *sourc return &instruction->base; } -static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) { - IrInstSrcRef *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) { + Stage1ZirInstRef *instruction = ir_build_instruction(ag, scope, source_node); instruction->value = value; ir_ref_instruction(value, ag->current_basic_block); @@ -1801,8 +1801,8 @@ static IrInstSrc *ir_build_ref_src(Stage1AstGen *ag, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) { - IrInstSrcCompileErr *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *msg) { + Stage1ZirInstCompileErr *instruction = ir_build_instruction(ag, scope, source_node); instruction->msg = msg; ir_ref_instruction(msg, ag->current_basic_block); @@ -1810,10 +1810,10 @@ static IrInstSrc *ir_build_compile_err(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - size_t msg_count, IrInstSrc **msg_list) +static Stage1ZirInst *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + size_t msg_count, Stage1ZirInst **msg_list) { - IrInstSrcCompileLog *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCompileLog *instruction = ir_build_instruction(ag, scope, source_node); instruction->msg_count = msg_count; instruction->msg_list = msg_list; @@ -1824,8 +1824,8 @@ static IrInstSrc *ir_build_compile_log(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) { - IrInstSrcErrName *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) { + Stage1ZirInstErrName *instruction = ir_build_instruction(ag, scope, source_node); instruction->value = value; ir_ref_instruction(value, ag->current_basic_block); @@ -1833,13 +1833,13 @@ static IrInstSrc *ir_build_err_name(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_c_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcCImport *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_c_import(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstCImport *instruction = ir_build_instruction(ag, scope, source_node); return &instruction->base; } -static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) { - IrInstSrcCInclude *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) { + Stage1ZirInstCInclude *instruction = ir_build_instruction(ag, scope, source_node); instruction->name = name; ir_ref_instruction(name, ag->current_basic_block); @@ -1847,8 +1847,8 @@ static IrInstSrc *ir_build_c_include(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name, IrInstSrc *value) { - IrInstSrcCDefine *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name, Stage1ZirInst *value) { + Stage1ZirInstCDefine *instruction = ir_build_instruction(ag, scope, source_node); instruction->name = name; instruction->value = value; @@ -1858,8 +1858,8 @@ static IrInstSrc *ir_build_c_define(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) { - IrInstSrcCUndef *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) { + Stage1ZirInstCUndef *instruction = ir_build_instruction(ag, scope, source_node); instruction->name = name; ir_ref_instruction(name, ag->current_basic_block); @@ -1867,8 +1867,8 @@ static IrInstSrc *ir_build_c_undef(Stage1AstGen *ag, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *name) { - IrInstSrcEmbedFile *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *name) { + Stage1ZirInstEmbedFile *instruction = ir_build_instruction(ag, scope, source_node); instruction->name = name; ir_ref_instruction(name, ag->current_basic_block); @@ -1876,11 +1876,11 @@ static IrInstSrc *ir_build_embed_file(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type_value, IrInstSrc *ptr, IrInstSrc *cmp_value, IrInstSrc *new_value, - IrInstSrc *success_order_value, IrInstSrc *failure_order_value, bool is_weak, ResultLoc *result_loc) +static Stage1ZirInst *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type_value, Stage1ZirInst *ptr, Stage1ZirInst *cmp_value, Stage1ZirInst *new_value, + Stage1ZirInst *success_order_value, Stage1ZirInst *failure_order_value, bool is_weak, ResultLoc *result_loc) { - IrInstSrcCmpxchg *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstCmpxchg *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; instruction->ptr = ptr; instruction->cmp_value = cmp_value; @@ -1900,8 +1900,8 @@ static IrInstSrc *ir_build_cmpxchg_src(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *order) { - IrInstSrcFence *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *order) { + Stage1ZirInstFence *instruction = ir_build_instruction(ag, scope, source_node); instruction->order = order; ir_ref_instruction(order, ag->current_basic_block); @@ -1909,8 +1909,8 @@ static IrInstSrc *ir_build_fence(Stage1AstGen *ag, Scope *scope, AstNode *source return &instruction->base; } -static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *op, IrInstSrc *value) { - IrInstSrcReduce *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *op, Stage1ZirInst *value) { + Stage1ZirInstReduce *instruction = ir_build_instruction(ag, scope, source_node); instruction->op = op; instruction->value = value; @@ -1920,10 +1920,10 @@ static IrInstSrc *ir_build_reduce(Stage1AstGen *ag, Scope *scope, AstNode *sourc return &instruction->base; } -static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *target) +static Stage1ZirInst *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *target) { - IrInstSrcTruncate *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstTruncate *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -1933,10 +1933,10 @@ static IrInstSrc *ir_build_truncate(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *dest_type, - IrInstSrc *target) +static Stage1ZirInst *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *dest_type, + Stage1ZirInst *target) { - IrInstSrcIntCast *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstIntCast *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -1946,10 +1946,10 @@ static IrInstSrc *ir_build_int_cast(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *dest_type, - IrInstSrc *target) +static Stage1ZirInst *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *dest_type, + Stage1ZirInst *target) { - IrInstSrcFloatCast *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstFloatCast *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -1959,10 +1959,10 @@ static IrInstSrc *ir_build_float_cast(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *target) +static Stage1ZirInst *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *target) { - IrInstSrcErrSetCast *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstErrSetCast *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -1972,10 +1972,10 @@ static IrInstSrc *ir_build_err_set_cast(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *target) +static Stage1ZirInst *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *target) { - IrInstSrcIntToFloat *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstIntToFloat *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -1985,10 +1985,10 @@ static IrInstSrc *ir_build_int_to_float(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *target) +static Stage1ZirInst *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *target) { - IrInstSrcFloatToInt *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstFloatToInt *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -1998,8 +1998,8 @@ static IrInstSrc *ir_build_float_to_int(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *target) { - IrInstSrcBoolToInt *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *target) { + Stage1ZirInstBoolToInt *instruction = ir_build_instruction(ag, scope, source_node); instruction->target = target; ir_ref_instruction(target, ag->current_basic_block); @@ -2007,10 +2007,10 @@ static IrInstSrc *ir_build_bool_to_int(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *len, - IrInstSrc *elem_type) +static Stage1ZirInst *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *len, + Stage1ZirInst *elem_type) { - IrInstSrcVectorType *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstVectorType *instruction = ir_build_instruction(ag, scope, source_node); instruction->len = len; instruction->elem_type = elem_type; @@ -2020,10 +2020,10 @@ static IrInstSrc *ir_build_vector_type(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *scalar_type, IrInstSrc *a, IrInstSrc *b, IrInstSrc *mask) +static Stage1ZirInst *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *scalar_type, Stage1ZirInst *a, Stage1ZirInst *b, Stage1ZirInst *mask) { - IrInstSrcShuffleVector *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstShuffleVector *instruction = ir_build_instruction(ag, scope, source_node); instruction->scalar_type = scalar_type; instruction->a = a; instruction->b = b; @@ -2037,10 +2037,10 @@ static IrInstSrc *ir_build_shuffle_vector(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *len, IrInstSrc *scalar) +static Stage1ZirInst *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *len, Stage1ZirInst *scalar) { - IrInstSrcSplat *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSplat *instruction = ir_build_instruction(ag, scope, source_node); instruction->len = len; instruction->scalar = scalar; @@ -2050,8 +2050,8 @@ static IrInstSrc *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) { - IrInstSrcBoolNot *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) { + Stage1ZirInstBoolNot *instruction = ir_build_instruction(ag, scope, source_node); instruction->value = value; ir_ref_instruction(value, ag->current_basic_block); @@ -2059,10 +2059,10 @@ static IrInstSrc *ir_build_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_ptr, IrInstSrc *byte, IrInstSrc *count) +static Stage1ZirInst *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_ptr, Stage1ZirInst *byte, Stage1ZirInst *count) { - IrInstSrcMemset *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstMemset *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_ptr = dest_ptr; instruction->byte = byte; instruction->count = count; @@ -2074,10 +2074,10 @@ static IrInstSrc *ir_build_memset_src(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_ptr, IrInstSrc *src_ptr, IrInstSrc *count) +static Stage1ZirInst *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_ptr, Stage1ZirInst *src_ptr, Stage1ZirInst *count) { - IrInstSrcMemcpy *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstMemcpy *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_ptr = dest_ptr; instruction->src_ptr = src_ptr; instruction->count = count; @@ -2089,11 +2089,11 @@ static IrInstSrc *ir_build_memcpy_src(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *ptr, IrInstSrc *start, IrInstSrc *end, IrInstSrc *sentinel, +static Stage1ZirInst *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *ptr, Stage1ZirInst *start, Stage1ZirInst *end, Stage1ZirInst *sentinel, bool safety_check_on, ResultLoc *result_loc) { - IrInstSrcSlice *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSlice *instruction = ir_build_instruction(ag, scope, source_node); instruction->ptr = ptr; instruction->start = start; instruction->end = end; @@ -2109,28 +2109,28 @@ static IrInstSrc *ir_build_slice_src(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_breakpoint(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcBreakpoint *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_breakpoint(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstBreakpoint *instruction = ir_build_instruction(ag, scope, source_node); return &instruction->base; } -static IrInstSrc *ir_build_return_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcReturnAddress *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_return_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstReturnAddress *instruction = ir_build_instruction(ag, scope, source_node); return &instruction->base; } -static IrInstSrc *ir_build_frame_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcFrameAddress *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_frame_address_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstFrameAddress *inst = ir_build_instruction(ag, scope, source_node); return &inst->base; } -static IrInstSrc *ir_build_handle_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcFrameHandle *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_handle_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstFrameHandle *inst = ir_build_instruction(ag, scope, source_node); return &inst->base; } -static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *fn) { - IrInstSrcFrameType *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *fn) { + Stage1ZirInstFrameType *inst = ir_build_instruction(ag, scope, source_node); inst->fn = fn; ir_ref_instruction(fn, ag->current_basic_block); @@ -2138,8 +2138,8 @@ static IrInstSrc *ir_build_frame_type(Stage1AstGen *ag, Scope *scope, AstNode *s return &inst->base; } -static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *fn) { - IrInstSrcFrameSize *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *fn) { + Stage1ZirInstFrameSize *inst = ir_build_instruction(ag, scope, source_node); inst->fn = fn; ir_ref_instruction(fn, ag->current_basic_block); @@ -2147,10 +2147,10 @@ static IrInstSrc *ir_build_frame_size_src(Stage1AstGen *ag, Scope *scope, AstNod return &inst->base; } -static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrOverflowOp op, IrInstSrc *type_value, IrInstSrc *op1, IrInstSrc *op2, IrInstSrc *result_ptr) +static Stage1ZirInst *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + IrOverflowOp op, Stage1ZirInst *type_value, Stage1ZirInst *op1, Stage1ZirInst *op2, Stage1ZirInst *result_ptr) { - IrInstSrcOverflowOp *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstOverflowOp *instruction = ir_build_instruction(ag, scope, source_node); instruction->op = op; instruction->type_value = type_value; instruction->op1 = op1; @@ -2165,10 +2165,10 @@ static IrInstSrc *ir_build_overflow_op_src(Stage1AstGen *ag, Scope *scope, AstNo return &instruction->base; } -static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *operand, +static Stage1ZirInst *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *operand, BuiltinFnId fn_id) { - IrInstSrcFloatOp *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstFloatOp *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand = operand; instruction->fn_id = fn_id; @@ -2177,10 +2177,10 @@ static IrInstSrc *ir_build_float_op_src(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type_value, IrInstSrc *op1, IrInstSrc *op2, IrInstSrc *op3) +static Stage1ZirInst *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type_value, Stage1ZirInst *op1, Stage1ZirInst *op2, Stage1ZirInst *op3) { - IrInstSrcMulAdd *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstMulAdd *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; instruction->op1 = op1; instruction->op2 = op2; @@ -2194,8 +2194,8 @@ static IrInstSrc *ir_build_mul_add_src(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value) { - IrInstSrcAlignOf *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value) { + Stage1ZirInstAlignOf *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; ir_ref_instruction(type_value, ag->current_basic_block); @@ -2203,10 +2203,10 @@ static IrInstSrc *ir_build_align_of(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *base_ptr, bool resolve_err_set, bool base_ptr_is_payload) +static Stage1ZirInst *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *base_ptr, bool resolve_err_set, bool base_ptr_is_payload) { - IrInstSrcTestErr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstTestErr *instruction = ir_build_instruction(ag, scope, source_node); instruction->base_ptr = base_ptr; instruction->resolve_err_set = resolve_err_set; instruction->base_ptr_is_payload = base_ptr_is_payload; @@ -2216,10 +2216,10 @@ static IrInstSrc *ir_build_test_err_src(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *err_union_ptr) +static Stage1ZirInst *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *err_union_ptr) { - IrInstSrcUnwrapErrCode *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstUnwrapErrCode *inst = ir_build_instruction(ag, scope, source_node); inst->err_union_ptr = err_union_ptr; ir_ref_instruction(err_union_ptr, ag->current_basic_block); @@ -2227,10 +2227,10 @@ static IrInstSrc *ir_build_unwrap_err_code_src(Stage1AstGen *ag, Scope *scope, A return &inst->base; } -static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *value, bool safety_check_on, bool initializing) +static Stage1ZirInst *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *value, bool safety_check_on, bool initializing) { - IrInstSrcUnwrapErrPayload *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstUnwrapErrPayload *inst = ir_build_instruction(ag, scope, source_node); inst->value = value; inst->safety_check_on = safety_check_on; inst->initializing = initializing; @@ -2240,11 +2240,11 @@ static IrInstSrc *ir_build_unwrap_err_payload_src(Stage1AstGen *ag, Scope *scope return &inst->base; } -static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc **param_types, IrInstSrc *align_value, IrInstSrc *callconv_value, - IrInstSrc *return_type, bool is_var_args) +static Stage1ZirInst *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst **param_types, Stage1ZirInst *align_value, Stage1ZirInst *callconv_value, + Stage1ZirInst *return_type, bool is_var_args) { - IrInstSrcFnProto *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstFnProto *instruction = ir_build_instruction(ag, scope, source_node); instruction->param_types = param_types; instruction->align_value = align_value; instruction->callconv_value = callconv_value; @@ -2264,8 +2264,8 @@ static IrInstSrc *ir_build_fn_proto(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *value) { - IrInstSrcTestComptime *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *value) { + Stage1ZirInstTestComptime *instruction = ir_build_instruction(ag, scope, source_node); instruction->value = value; ir_ref_instruction(value, ag->current_basic_block); @@ -2273,10 +2273,10 @@ static IrInstSrc *ir_build_test_comptime(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *ptr, bool safety_check_on) +static Stage1ZirInst *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *ptr, bool safety_check_on) { - IrInstSrcPtrCast *instruction = ir_build_instruction( + Stage1ZirInstPtrCast *instruction = ir_build_instruction( ag, scope, source_node); instruction->dest_type = dest_type; instruction->ptr = ptr; @@ -2288,10 +2288,10 @@ static IrInstSrc *ir_build_ptr_cast_src(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *operand, ResultLocCast *result_loc_cast) +static Stage1ZirInst *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *operand, ResultLocCast *result_loc_cast) { - IrInstSrcImplicitCast *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstImplicitCast *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand = operand; instruction->result_loc_cast = result_loc_cast; @@ -2300,10 +2300,10 @@ static IrInstSrc *ir_build_implicit_cast(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *operand, ResultLocBitCast *result_loc_bit_cast) +static Stage1ZirInst *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *operand, ResultLocBitCast *result_loc_bit_cast) { - IrInstSrcBitCast *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstBitCast *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand = operand; instruction->result_loc_bit_cast = result_loc_bit_cast; @@ -2312,10 +2312,10 @@ static IrInstSrc *ir_build_bit_cast_src(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *target) +static Stage1ZirInst *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *target) { - IrInstSrcIntToPtr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstIntToPtr *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -2325,10 +2325,10 @@ static IrInstSrc *ir_build_int_to_ptr_src(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target) +static Stage1ZirInst *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target) { - IrInstSrcPtrToInt *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstPtrToInt *inst = ir_build_instruction(ag, scope, source_node); inst->target = target; ir_ref_instruction(target, ag->current_basic_block); @@ -2336,10 +2336,10 @@ static IrInstSrc *ir_build_ptr_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod return &inst->base; } -static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *dest_type, IrInstSrc *target) +static Stage1ZirInst *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *dest_type, Stage1ZirInst *target) { - IrInstSrcIntToEnum *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstIntToEnum *instruction = ir_build_instruction(ag, scope, source_node); instruction->dest_type = dest_type; instruction->target = target; @@ -2349,10 +2349,10 @@ static IrInstSrc *ir_build_int_to_enum_src(Stage1AstGen *ag, Scope *scope, AstNo return &instruction->base; } -static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target) +static Stage1ZirInst *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target) { - IrInstSrcEnumToInt *instruction = ir_build_instruction( + Stage1ZirInstEnumToInt *instruction = ir_build_instruction( ag, scope, source_node); instruction->target = target; @@ -2361,10 +2361,10 @@ static IrInstSrc *ir_build_enum_to_int(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target) +static Stage1ZirInst *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target) { - IrInstSrcIntToErr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstIntToErr *instruction = ir_build_instruction(ag, scope, source_node); instruction->target = target; ir_ref_instruction(target, ag->current_basic_block); @@ -2372,10 +2372,10 @@ static IrInstSrc *ir_build_int_to_err_src(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target) +static Stage1ZirInst *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target) { - IrInstSrcErrToInt *instruction = ir_build_instruction( + Stage1ZirInstErrToInt *instruction = ir_build_instruction( ag, scope, source_node); instruction->target = target; @@ -2384,13 +2384,13 @@ static IrInstSrc *ir_build_err_to_int_src(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *target_value, IrInstSrcCheckSwitchProngsRange *ranges, size_t range_count, +static Stage1ZirInst *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *target_value, Stage1ZirInstCheckSwitchProngsRange *ranges, size_t range_count, AstNode* else_prong, bool have_underscore_prong) { - IrInstSrcCheckSwitchProngs *instruction = heap::c_allocator.create(); + Stage1ZirInstCheckSwitchProngs *instruction = heap::c_allocator.create(); instruction->base.id = have_underscore_prong ? - IrInstSrcIdCheckSwitchProngsUnderYes : IrInstSrcIdCheckSwitchProngsUnderNo; + Stage1ZirInstIdCheckSwitchProngsUnderYes : Stage1ZirInstIdCheckSwitchProngsUnderNo; instruction->base.scope = scope; instruction->base.source_node = source_node; instruction->base.debug_id = irb_next_debug_id(ag); @@ -2411,10 +2411,10 @@ static IrInstSrc *ir_build_check_switch_prongs(Stage1AstGen *ag, Scope *scope, A return &instruction->base; } -static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc* statement_value) +static Stage1ZirInst *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst* statement_value) { - IrInstSrcCheckStatementIsVoid *instruction = ir_build_instruction( + Stage1ZirInstCheckStatementIsVoid *instruction = ir_build_instruction( ag, scope, source_node); instruction->statement_value = statement_value; @@ -2423,10 +2423,10 @@ static IrInstSrc *ir_build_check_statement_is_void(Stage1AstGen *ag, Scope *scop return &instruction->base; } -static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type_value) +static Stage1ZirInst *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type_value) { - IrInstSrcTypeName *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstTypeName *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; ir_ref_instruction(type_value, ag->current_basic_block); @@ -2434,16 +2434,16 @@ static IrInstSrc *ir_build_type_name(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Tld *tld, LVal lval) { - IrInstSrcDeclRef *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_decl_ref(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Tld *tld, LVal lval) { + Stage1ZirInstDeclRef *instruction = ir_build_instruction(ag, scope, source_node); instruction->tld = tld; instruction->lval = lval; return &instruction->base; } -static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *msg) { - IrInstSrcPanic *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *msg) { + Stage1ZirInstPanic *instruction = ir_build_instruction(ag, scope, source_node); instruction->msg = msg; ir_ref_instruction(msg, ag->current_basic_block); @@ -2451,8 +2451,8 @@ static IrInstSrc *ir_build_panic_src(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *target) { - IrInstSrcTagName *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *target) { + Stage1ZirInstTagName *instruction = ir_build_instruction(ag, scope, source_node); instruction->target = target; ir_ref_instruction(target, ag->current_basic_block); @@ -2460,10 +2460,10 @@ static IrInstSrc *ir_build_tag_name_src(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type_value, IrInstSrc *field_name, IrInstSrc *field_ptr) +static Stage1ZirInst *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type_value, Stage1ZirInst *field_name, Stage1ZirInst *field_ptr) { - IrInstSrcFieldParentPtr *inst = ir_build_instruction( + Stage1ZirInstFieldParentPtr *inst = ir_build_instruction( ag, scope, source_node); inst->type_value = type_value; inst->field_name = field_name; @@ -2476,10 +2476,10 @@ static IrInstSrc *ir_build_field_parent_ptr_src(Stage1AstGen *ag, Scope *scope, return &inst->base; } -static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type_value, IrInstSrc *field_name) +static Stage1ZirInst *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type_value, Stage1ZirInst *field_name) { - IrInstSrcOffsetOf *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstOffsetOf *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; instruction->field_name = field_name; @@ -2489,10 +2489,10 @@ static IrInstSrc *ir_build_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *type_value, IrInstSrc *field_name) +static Stage1ZirInst *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *type_value, Stage1ZirInst *field_name) { - IrInstSrcBitOffsetOf *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstBitOffsetOf *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; instruction->field_name = field_name; @@ -2502,8 +2502,8 @@ static IrInstSrc *ir_build_bit_offset_of(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_value) { - IrInstSrcTypeInfo *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_value) { + Stage1ZirInstTypeInfo *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_value = type_value; ir_ref_instruction(type_value, ag->current_basic_block); @@ -2511,8 +2511,8 @@ static IrInstSrc *ir_build_type_info(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *type_info) { - IrInstSrcType *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *type_info) { + Stage1ZirInstType *instruction = ir_build_instruction(ag, scope, source_node); instruction->type_info = type_info; ir_ref_instruction(type_info, ag->current_basic_block); @@ -2520,10 +2520,10 @@ static IrInstSrc *ir_build_type(Stage1AstGen *ag, Scope *scope, AstNode *source_ return &instruction->base; } -static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *new_quota) +static Stage1ZirInst *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *new_quota) { - IrInstSrcSetEvalBranchQuota *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSetEvalBranchQuota *instruction = ir_build_instruction(ag, scope, source_node); instruction->new_quota = new_quota; ir_ref_instruction(new_quota, ag->current_basic_block); @@ -2531,10 +2531,10 @@ static IrInstSrc *ir_build_set_eval_branch_quota(Stage1AstGen *ag, Scope *scope, return &instruction->base; } -static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *align_bytes, IrInstSrc *target) +static Stage1ZirInst *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *align_bytes, Stage1ZirInst *target) { - IrInstSrcAlignCast *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAlignCast *instruction = ir_build_instruction(ag, scope, source_node); instruction->align_bytes = align_bytes; instruction->target = target; @@ -2544,10 +2544,10 @@ static IrInstSrc *ir_build_align_cast_src(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - ResultLoc *result_loc, IrInstSrc *ty) +static Stage1ZirInst *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + ResultLoc *result_loc, Stage1ZirInst *ty) { - IrInstSrcResolveResult *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstResolveResult *instruction = ir_build_instruction(ag, scope, source_node); instruction->result_loc = result_loc; instruction->ty = ty; @@ -2556,19 +2556,19 @@ static IrInstSrc *ir_build_resolve_result(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_reset_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *ir_build_reset_result(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ResultLoc *result_loc) { - IrInstSrcResetResult *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstResetResult *instruction = ir_build_instruction(ag, scope, source_node); instruction->result_loc = result_loc; return &instruction->base; } -static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *align_bytes) +static Stage1ZirInst *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *align_bytes) { - IrInstSrcSetAlignStack *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSetAlignStack *instruction = ir_build_instruction(ag, scope, source_node); instruction->align_bytes = align_bytes; ir_ref_instruction(align_bytes, ag->current_basic_block); @@ -2576,12 +2576,12 @@ static IrInstSrc *ir_build_set_align_stack(Stage1AstGen *ag, Scope *scope, AstNo return &instruction->base; } -static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *fn_type, IrInstSrc *arg_index, bool allow_var) +static Stage1ZirInst *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *fn_type, Stage1ZirInst *arg_index, bool allow_var) { - IrInstSrcArgType *instruction = heap::c_allocator.create(); + Stage1ZirInstArgType *instruction = heap::c_allocator.create(); instruction->base.id = allow_var ? - IrInstSrcIdArgTypeAllowVarTrue : IrInstSrcIdArgTypeAllowVarFalse; + Stage1ZirInstIdArgTypeAllowVarTrue : Stage1ZirInstIdArgTypeAllowVarFalse; instruction->base.scope = scope; instruction->base.source_node = source_node; instruction->base.debug_id = irb_next_debug_id(ag); @@ -2597,19 +2597,19 @@ static IrInstSrc *ir_build_arg_type(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_error_return_trace_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *ir_build_error_return_trace_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstErrorReturnTraceOptional optional) { - IrInstSrcErrorReturnTrace *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstErrorReturnTrace *inst = ir_build_instruction(ag, scope, source_node); inst->optional = optional; return &inst->base; } -static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *err_set, IrInstSrc *payload) +static Stage1ZirInst *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *err_set, Stage1ZirInst *payload) { - IrInstSrcErrorUnion *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstErrorUnion *instruction = ir_build_instruction(ag, scope, source_node); instruction->err_set = err_set; instruction->payload = payload; @@ -2619,11 +2619,11 @@ static IrInstSrc *ir_build_error_union(Stage1AstGen *ag, Scope *scope, AstNode * return &instruction->base; } -static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *op, IrInstSrc *operand, - IrInstSrc *ordering) +static Stage1ZirInst *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *op, Stage1ZirInst *operand, + Stage1ZirInst *ordering) { - IrInstSrcAtomicRmw *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAtomicRmw *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand_type = operand_type; instruction->ptr = ptr; instruction->op = op; @@ -2639,10 +2639,10 @@ static IrInstSrc *ir_build_atomic_rmw_src(Stage1AstGen *ag, Scope *scope, AstNod return &instruction->base; } -static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *ordering) +static Stage1ZirInst *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *ordering) { - IrInstSrcAtomicLoad *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAtomicLoad *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand_type = operand_type; instruction->ptr = ptr; instruction->ordering = ordering; @@ -2654,10 +2654,10 @@ static IrInstSrc *ir_build_atomic_load_src(Stage1AstGen *ag, Scope *scope, AstNo return &instruction->base; } -static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *operand_type, IrInstSrc *ptr, IrInstSrc *value, IrInstSrc *ordering) +static Stage1ZirInst *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *operand_type, Stage1ZirInst *ptr, Stage1ZirInst *value, Stage1ZirInst *ordering) { - IrInstSrcAtomicStore *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAtomicStore *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand_type = operand_type; instruction->ptr = ptr; instruction->value = value; @@ -2671,15 +2671,15 @@ static IrInstSrc *ir_build_atomic_store_src(Stage1AstGen *ag, Scope *scope, AstN return &instruction->base; } -static IrInstSrc *ir_build_save_err_ret_addr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcSaveErrRetAddr *inst = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_save_err_ret_addr_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstSaveErrRetAddr *inst = ir_build_instruction(ag, scope, source_node); return &inst->base; } -static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *value, ResultLocReturn *result_loc_ret) +static Stage1ZirInst *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *value, ResultLocReturn *result_loc_ret) { - IrInstSrcAddImplicitReturnType *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAddImplicitReturnType *inst = ir_build_instruction(ag, scope, source_node); inst->value = value; inst->result_loc_ret = result_loc_ret; @@ -2688,10 +2688,10 @@ static IrInstSrc *ir_build_add_implicit_return_type(Stage1AstGen *ag, Scope *sco return &inst->base; } -static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *container, IrInstSrc *name) +static Stage1ZirInst *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *container, Stage1ZirInst *name) { - IrInstSrcHasDecl *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstHasDecl *instruction = ir_build_instruction(ag, scope, source_node); instruction->container = container; instruction->name = name; @@ -2701,15 +2701,15 @@ static IrInstSrc *ir_build_has_decl(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrc *ir_build_undeclared_identifier(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) { - IrInstSrcUndeclaredIdent *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_undeclared_identifier(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Buf *name) { + Stage1ZirInstUndeclaredIdent *instruction = ir_build_instruction(ag, scope, source_node); instruction->name = name; return &instruction->base; } -static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *scope_is_comptime, IrInstSrc *is_comptime) { - IrInstSrcCheckRuntimeScope *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *scope_is_comptime, Stage1ZirInst *is_comptime) { + Stage1ZirInstCheckRuntimeScope *instruction = ir_build_instruction(ag, scope, source_node); instruction->scope_is_comptime = scope_is_comptime; instruction->is_comptime = is_comptime; @@ -2719,10 +2719,10 @@ static IrInstSrc *ir_build_check_runtime_scope(Stage1AstGen *ag, Scope *scope, A return &instruction->base; } -static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *union_type, IrInstSrc *field_name, IrInstSrc *field_result_loc, IrInstSrc *result_loc) +static Stage1ZirInst *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *union_type, Stage1ZirInst *field_name, Stage1ZirInst *field_result_loc, Stage1ZirInst *result_loc) { - IrInstSrcUnionInitNamedField *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstUnionInitNamedField *instruction = ir_build_instruction(ag, scope, source_node); instruction->union_type = union_type; instruction->field_name = field_name; instruction->field_result_loc = field_result_loc; @@ -2736,10 +2736,10 @@ static IrInstSrc *ir_build_union_init_named_field(Stage1AstGen *ag, Scope *scope return &instruction->base; } -static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *align, const char *name_hint, IrInstSrc *is_comptime) +static Stage1ZirInst *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *align, const char *name_hint, Stage1ZirInst *is_comptime) { - IrInstSrcAlloca *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAlloca *instruction = ir_build_instruction(ag, scope, source_node); instruction->align = align; instruction->name_hint = name_hint; instruction->is_comptime = is_comptime; @@ -2750,10 +2750,10 @@ static IrInstSrc *ir_build_alloca_src(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *value, ResultLoc *result_loc) +static Stage1ZirInst *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *value, ResultLoc *result_loc) { - IrInstSrcEndExpr *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstEndExpr *instruction = ir_build_instruction(ag, scope, source_node); instruction->value = value; instruction->result_loc = result_loc; @@ -2762,14 +2762,14 @@ static IrInstSrc *ir_build_end_expr(Stage1AstGen *ag, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstSrcSuspendBegin *ir_build_suspend_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - return ir_build_instruction(ag, scope, source_node); +static Stage1ZirInstSuspendBegin *ir_build_suspend_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + return ir_build_instruction(ag, scope, source_node); } -static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrcSuspendBegin *begin) +static Stage1ZirInst *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInstSuspendBegin *begin) { - IrInstSrcSuspendFinish *inst = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSuspendFinish *inst = ir_build_instruction(ag, scope, source_node); inst->begin = begin; ir_ref_instruction(&begin->base, ag->current_basic_block); @@ -2777,10 +2777,10 @@ static IrInstSrc *ir_build_suspend_finish_src(Stage1AstGen *ag, Scope *scope, As return &inst->base; } -static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *frame, ResultLoc *result_loc, bool is_nosuspend) +static Stage1ZirInst *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *frame, ResultLoc *result_loc, bool is_nosuspend) { - IrInstSrcAwait *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstAwait *instruction = ir_build_instruction(ag, scope, source_node); instruction->frame = frame; instruction->result_loc = result_loc; instruction->is_nosuspend = is_nosuspend; @@ -2790,8 +2790,8 @@ static IrInstSrc *ir_build_await_src(Stage1AstGen *ag, Scope *scope, AstNode *so return &instruction->base; } -static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *frame) { - IrInstSrcResume *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *frame) { + Stage1ZirInstResume *instruction = ir_build_instruction(ag, scope, source_node); instruction->frame = frame; ir_ref_instruction(frame, ag->current_basic_block); @@ -2799,10 +2799,10 @@ static IrInstSrc *ir_build_resume_src(Stage1AstGen *ag, Scope *scope, AstNode *s return &instruction->base; } -static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *operand, SpillId spill_id) +static Stage1ZirInstSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *operand, SpillId spill_id) { - IrInstSrcSpillBegin *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSpillBegin *instruction = ir_build_instruction(ag, scope, source_node); instruction->operand = operand; instruction->spill_id = spill_id; @@ -2811,10 +2811,10 @@ static IrInstSrcSpillBegin *ir_build_spill_begin_src(Stage1AstGen *ag, Scope *sc return instruction; } -static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrcSpillBegin *begin) +static Stage1ZirInst *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInstSpillBegin *begin) { - IrInstSrcSpillEnd *instruction = ir_build_instruction(ag, scope, source_node); + Stage1ZirInstSpillEnd *instruction = ir_build_instruction(ag, scope, source_node); instruction->begin = begin; ir_ref_instruction(&begin->base, ag->current_basic_block); @@ -2822,8 +2822,8 @@ static IrInstSrc *ir_build_spill_end_src(Stage1AstGen *ag, Scope *scope, AstNode return &instruction->base; } -static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *index) { - IrInstSrcWasmMemorySize *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *index) { + Stage1ZirInstWasmMemorySize *instruction = ir_build_instruction(ag, scope, source_node); instruction->index = index; ir_ref_instruction(index, ag->current_basic_block); @@ -2831,8 +2831,8 @@ static IrInstSrc *ir_build_wasm_memory_size_src(Stage1AstGen *ag, Scope *scope, return &instruction->base; } -static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, IrInstSrc *index, IrInstSrc *delta) { - IrInstSrcWasmMemoryGrow *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node, Stage1ZirInst *index, Stage1ZirInst *delta) { + Stage1ZirInstWasmMemoryGrow *instruction = ir_build_instruction(ag, scope, source_node); instruction->index = index; instruction->delta = delta; @@ -2842,8 +2842,8 @@ static IrInstSrc *ir_build_wasm_memory_grow_src(Stage1AstGen *ag, Scope *scope, return &instruction->base; } -static IrInstSrc *ir_build_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { - IrInstSrcSrc *instruction = ir_build_instruction(ag, scope, source_node); +static Stage1ZirInst *ir_build_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node) { + Stage1ZirInstSrc *instruction = ir_build_instruction(ag, scope, source_node); return &instruction->base; } @@ -2886,7 +2886,7 @@ static void ir_count_defers(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_s } } -static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_scope, bool *is_noreturn, IrInstSrc *err_value) { +static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope *outer_scope, bool *is_noreturn, Stage1ZirInst *err_value) { Scope *scope = inner_scope; if (is_noreturn != nullptr) *is_noreturn = false; while (scope != outer_scope) { @@ -2920,7 +2920,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope return false; } - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, defer_expr_scope)) { is_comptime = ir_build_const_bool(ag, defer_expr_scope, defer_expr_node, true); @@ -2937,7 +2937,7 @@ static bool astgen_defers_for_block(Stage1AstGen *ag, Scope *inner_scope, Scope defer_expr_scope = err_var->child_scope; } - IrInstSrc *defer_expr_value = astgen_node(ag, defer_expr_node, defer_expr_scope); + Stage1ZirInst *defer_expr_value = astgen_node(ag, defer_expr_node, defer_expr_scope); if (defer_expr_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -3007,7 +3007,7 @@ static ScopeDeferExpr *get_scope_defer_expr(Scope *scope) { return nullptr; } -static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { +static Stage1ZirInst *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeReturnExpr); ScopeDeferExpr *scope_defer_expr = get_scope_defer_expr(scope); @@ -3029,7 +3029,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L result_loc_ret->base.id = ResultLocIdReturn; ir_build_reset_result(ag, scope, node, &result_loc_ret->base); - IrInstSrc *return_value; + Stage1ZirInst *return_value; if (expr_node) { // Temporarily set this so that if we return a type it gets the name of the function ZigFn *prev_name_fn = ag->exec->name_fn; @@ -3052,7 +3052,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L // only generate unconditional defers if (!astgen_defers_for_block(ag, scope, outer_scope, nullptr, nullptr)) return ag->codegen->invalid_inst_src; - IrInstSrc *result = ir_build_return_src(ag, scope, node, nullptr); + Stage1ZirInst *result = ir_build_return_src(ag, scope, node, nullptr); result_loc_ret->base.source_instruction = result; return result; } @@ -3061,9 +3061,9 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, scope, "ErrRetErr"); Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "ErrRetOk"); - IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true); + Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node, return_value, false, true); - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (should_inline) { is_comptime = ir_build_const_bool(ag, scope, node, should_inline); } else { @@ -3087,21 +3087,21 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L ir_build_br(ag, scope, node, ret_stmt_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, ret_stmt_block); - IrInstSrc *result = ir_build_return_src(ag, scope, node, nullptr); + Stage1ZirInst *result = ir_build_return_src(ag, scope, node, nullptr); result_loc_ret->base.source_instruction = result; return result; } case ReturnKindError: { assert(expr_node); - IrInstSrc *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); + Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); if (err_union_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false); + Stage1ZirInst *is_err_val = ir_build_test_err_src(ag, scope, node, err_union_ptr, true, false); Stage1ZirBasicBlock *return_block = ir_create_basic_block(ag, scope, "ErrRetReturn"); Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, scope, "ErrRetContinue"); - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; bool should_inline = ir_should_inline(ag->exec, scope); if (should_inline) { is_comptime = ir_build_const_bool(ag, scope, node, true); @@ -3111,10 +3111,10 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L ir_build_cond_br(ag, scope, node, is_err_val, return_block, continue_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, return_block); - IrInstSrc *err_val_ptr = ir_build_unwrap_err_code_src(ag, scope, node, err_union_ptr); - IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr); + Stage1ZirInst *err_val_ptr = ir_build_unwrap_err_code_src(ag, scope, node, err_union_ptr); + Stage1ZirInst *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr); ir_build_add_implicit_return_type(ag, scope, node, err_val, nullptr); - IrInstSrcSpillBegin *spill_begin = ir_build_spill_begin_src(ag, scope, node, err_val, + Stage1ZirInstSpillBegin *spill_begin = ir_build_spill_begin_src(ag, scope, node, err_val, SpillIdRetErrCode); ResultLocReturn *result_loc_ret = heap::c_allocator.create(); result_loc_ret->base.id = ResultLocIdReturn; @@ -3130,12 +3130,12 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L ir_build_save_err_ret_addr_src(ag, scope, node); } err_val = ir_build_spill_end_src(ag, scope, node, spill_begin); - IrInstSrc *ret_inst = ir_build_return_src(ag, scope, node, err_val); + Stage1ZirInst *ret_inst = ir_build_return_src(ag, scope, node, err_val); result_loc_ret->base.source_instruction = ret_inst; } ir_set_cursor_at_end_and_append_block(ag, continue_block); - IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, scope, node, err_union_ptr, false, false); + Stage1ZirInst *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, scope, node, err_union_ptr, false, false); if (lval == LValPtr) return unwrapped_ptr; else @@ -3146,7 +3146,7 @@ static IrInstSrc *astgen_return(Stage1AstGen *ag, Scope *scope, AstNode *node, L } ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope, - Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime, + Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime, bool skip_name_check) { ZigVar *variable_entry = heap::c_allocator.create(); @@ -3218,7 +3218,7 @@ ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope, // Set name to nullptr to make the variable anonymous (not visible to programmer). // After you call this function var->child_scope has the variable in scope static ZigVar *ir_create_var(Stage1AstGen *ag, AstNode *node, Scope *scope, Buf *name, - bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime) + bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime) { bool is_underscored = name ? buf_eql_str(name, "_") : false; ZigVar *var = create_local_var(ag->codegen, node, scope, @@ -3256,12 +3256,12 @@ static bool is_duplicate_label(CodeGen *g, Scope *scope, AstNode *node, Buf *nam return false; } -static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *block_node, LVal lval, +static Stage1ZirInst *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *block_node, LVal lval, ResultLoc *result_loc) { assert(block_node->type == NodeTypeBlock); - ZigList incoming_values = {0}; + ZigList incoming_values = {0}; ZigList incoming_blocks = {0}; if (is_duplicate_label(ag->codegen, parent_scope, block_node, block_node->data.block.name)) @@ -3305,11 +3305,11 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b bool is_continuation_unreachable = false; bool found_invalid_inst = false; - IrInstSrc *noreturn_return_value = nullptr; + Stage1ZirInst *noreturn_return_value = nullptr; for (size_t i = 0; i < block_node->data.block.statements.length; i += 1) { AstNode *statement_node = block_node->data.block.statements.at(i); - IrInstSrc *statement_value = astgen_node(ag, statement_node, child_scope); + Stage1ZirInst *statement_value = astgen_node(ag, statement_node, child_scope); if (statement_value == ag->codegen->invalid_inst_src) { // keep generating all the elements of the block in case of error, // we want to collect other compile errors @@ -3328,9 +3328,9 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b // defer starts a new scope child_scope = statement_node->data.defer.child_scope; assert(child_scope); - } else if (statement_value->id == IrInstSrcIdDeclVar) { + } else if (statement_value->id == Stage1ZirInstIdDeclVar) { // variable declarations start a new scope - IrInstSrcDeclVar *decl_var_instruction = (IrInstSrcDeclVar *)statement_value; + Stage1ZirInstDeclVar *decl_var_instruction = (Stage1ZirInstDeclVar *)statement_value; child_scope = decl_var_instruction->var->child_scope; } else if (!is_continuation_unreachable) { // this statement's value must be void @@ -3355,12 +3355,12 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b scope_block->peer_parent->peers.last()->next_bb = scope_block->end_block; } ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block); - IrInstSrc *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length, + Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length, incoming_blocks.items, incoming_values.items, scope_block->peer_parent); return ir_expr_wrap(ag, parent_scope, phi, result_loc); } else { incoming_blocks.append(ag->current_basic_block); - IrInstSrc *else_expr_result = ir_build_const_void(ag, parent_scope, block_node); + Stage1ZirInst *else_expr_result = ir_build_const_void(ag, parent_scope, block_node); if (scope_block->peer_parent != nullptr) { ResultLocPeer *peer_result = create_peer_result(scope_block->peer_parent); @@ -3381,15 +3381,15 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b return ag->codegen->invalid_inst_src; } - IrInstSrc *result; + Stage1ZirInst *result; if (block_node->data.block.name != nullptr) { ir_build_br(ag, parent_scope, block_node, scope_block->end_block, scope_block->is_comptime); ir_set_cursor_at_end_and_append_block(ag, scope_block->end_block); - IrInstSrc *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length, + Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, block_node, incoming_blocks.length, incoming_blocks.items, incoming_values.items, scope_block->peer_parent); result = ir_expr_wrap(ag, parent_scope, phi, result_loc); } else { - IrInstSrc *void_inst = ir_build_const_void(ag, child_scope, block_node); + Stage1ZirInst *void_inst = ir_build_const_void(ag, child_scope, block_node); result = ir_lval_wrap(ag, parent_scope, void_inst, lval, result_loc); } if (!is_return_from_fn) @@ -3408,14 +3408,14 @@ static IrInstSrc *astgen_block(Stage1AstGen *ag, Scope *parent_scope, AstNode *b return ir_build_return_src(ag, child_scope, result->source_node, result); } -static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) { +static Stage1ZirInst *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) { Scope *inner_scope = scope; if (op_id == IrBinOpArrayCat || op_id == IrBinOpArrayMult) { inner_scope = create_comptime_scope(ag->codegen, node, scope); } - IrInstSrc *op1 = astgen_node(ag, node->data.bin_op_expr.op1, inner_scope); - IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, inner_scope); + Stage1ZirInst *op1 = astgen_node(ag, node->data.bin_op_expr.op1, inner_scope); + Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, inner_scope); if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -3423,9 +3423,9 @@ static IrInstSrc *astgen_bin_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node return ir_build_bin_op(ag, scope, node, op_id, op1, op2, true); } -static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *node) { - IrInstSrc *op1 = astgen_node(ag, node->data.bin_op_expr.op1, scope); - IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); +static Stage1ZirInst *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode *node) { + Stage1ZirInst *op1 = astgen_node(ag, node->data.bin_op_expr.op1, scope); + Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); if (op1 == ag->codegen->invalid_inst_src || op2 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -3437,8 +3437,8 @@ static IrInstSrc *astgen_merge_err_sets(Stage1AstGen *ag, Scope *scope, AstNode return ir_build_merge_err_sets(ag, scope, node, op1, op2, type_name); } -static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) { - IrInstSrc *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr); +static Stage1ZirInst *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) { + Stage1ZirInst *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr); if (lvalue == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -3448,7 +3448,7 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) { ir_ref_instruction(lvalue, ag->current_basic_block); ir_build_reset_result(ag, scope, node, &result_loc_inst->base); - IrInstSrc *rvalue = astgen_node_extra(ag, node->data.bin_op_expr.op2, scope, LValNone, + Stage1ZirInst *rvalue = astgen_node_extra(ag, node->data.bin_op_expr.op2, scope, LValNone, &result_loc_inst->base); if (rvalue == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -3456,28 +3456,28 @@ static IrInstSrc *astgen_assign(Stage1AstGen *ag, Scope *scope, AstNode *node) { return ir_build_const_void(ag, scope, node); } -static IrInstSrc *astgen_assign_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) { - IrInstSrc *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr); +static Stage1ZirInst *astgen_assign_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrBinOp op_id) { + Stage1ZirInst *lvalue = astgen_node_extra(ag, node->data.bin_op_expr.op1, scope, LValAssign, nullptr); if (lvalue == ag->codegen->invalid_inst_src) return lvalue; - IrInstSrc *op1 = ir_build_load_ptr(ag, scope, node->data.bin_op_expr.op1, lvalue); - IrInstSrc *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); + Stage1ZirInst *op1 = ir_build_load_ptr(ag, scope, node->data.bin_op_expr.op1, lvalue); + Stage1ZirInst *op2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); if (op2 == ag->codegen->invalid_inst_src) return op2; - IrInstSrc *result = ir_build_bin_op(ag, scope, node, op_id, op1, op2, true); + Stage1ZirInst *result = ir_build_bin_op(ag, scope, node, op_id, op1, op2, true); ir_build_store_ptr(ag, scope, node, lvalue, result); return ir_build_const_void(ag, scope, node); } -static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeBinOpExpr); - IrInstSrc *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope); + Stage1ZirInst *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope); if (val1 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, scope)) { is_comptime = ir_build_const_bool(ag, scope, node, true); } else { @@ -3492,7 +3492,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, false_block); - IrInstSrc *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); + Stage1ZirInst *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); if (val2 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block; @@ -3501,7 +3501,7 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) ir_set_cursor_at_end_and_append_block(ag, true_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = val1; incoming_values[1] = val2; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); @@ -3511,15 +3511,15 @@ static IrInstSrc *astgen_bool_or(Stage1AstGen *ag, Scope *scope, AstNode *node) return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr); } -static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeBinOpExpr); - IrInstSrc *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope); + Stage1ZirInst *val1 = astgen_node(ag, node->data.bin_op_expr.op1, scope); if (val1 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; Stage1ZirBasicBlock *post_val1_block = ag->current_basic_block; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, scope)) { is_comptime = ir_build_const_bool(ag, scope, node, true); } else { @@ -3534,7 +3534,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) ir_build_cond_br(ag, scope, node, val1, true_block, false_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, true_block); - IrInstSrc *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); + Stage1ZirInst *val2 = astgen_node(ag, node->data.bin_op_expr.op2, scope); if (val2 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; Stage1ZirBasicBlock *post_val2_block = ag->current_basic_block; @@ -3543,7 +3543,7 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) ir_set_cursor_at_end_and_append_block(ag, false_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = val1; incoming_values[1] = val2; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); @@ -3553,8 +3553,8 @@ static IrInstSrc *astgen_bool_and(Stage1AstGen *ag, Scope *scope, AstNode *node) return ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, nullptr); } -static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst, - Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime) +static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, Stage1ZirInst *cond_br_inst, + Stage1ZirBasicBlock *end_block, ResultLoc *parent, Stage1ZirInst *is_comptime) { ResultLocPeerParent *peer_parent = heap::c_allocator.create(); peer_parent->base.id = ResultLocIdPeerParent; @@ -3564,7 +3564,7 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c peer_parent->is_comptime = is_comptime; peer_parent->parent = parent; - IrInstSrc *popped_inst = ag->current_basic_block->instruction_list.pop(); + Stage1ZirInst *popped_inst = ag->current_basic_block->instruction_list.pop(); ir_assert(popped_inst == cond_br_inst, cond_br_inst); ir_build_reset_result(ag, cond_br_inst->scope, cond_br_inst->source_node, &peer_parent->base); @@ -3573,8 +3573,8 @@ static ResultLocPeerParent *ir_build_result_peers(Stage1AstGen *ag, IrInstSrc *c return peer_parent; } -static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrInstSrc *cond_br_inst, - Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, IrInstSrc *is_comptime) +static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, Stage1ZirInst *cond_br_inst, + Stage1ZirBasicBlock *else_block, Stage1ZirBasicBlock *end_block, ResultLoc *parent, Stage1ZirInst *is_comptime) { ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, parent, is_comptime); @@ -3587,7 +3587,7 @@ static ResultLocPeerParent *ir_build_binary_result_peers(Stage1AstGen *ag, IrIns return peer_parent; } -static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeBinOpExpr); @@ -3595,14 +3595,14 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode * AstNode *op1_node = node->data.bin_op_expr.op1; AstNode *op2_node = node->data.bin_op_expr.op2; - IrInstSrc *maybe_ptr = astgen_node_extra(ag, op1_node, parent_scope, LValPtr, nullptr); + Stage1ZirInst *maybe_ptr = astgen_node_extra(ag, op1_node, parent_scope, LValPtr, nullptr); if (maybe_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *maybe_val = ir_build_load_ptr(ag, parent_scope, node, maybe_ptr); - IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, parent_scope, node, maybe_val); + Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, parent_scope, node, maybe_ptr); + Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, parent_scope, node, maybe_val); - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, parent_scope)) { is_comptime = ir_build_const_bool(ag, parent_scope, node, true); } else { @@ -3612,13 +3612,13 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode * Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "OptionalNonNull"); Stage1ZirBasicBlock *null_block = ir_create_basic_block(ag, parent_scope, "OptionalNull"); Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "OptionalEnd"); - IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime); + Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_non_null, ok_block, null_block, is_comptime); ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc, is_comptime); ir_set_cursor_at_end_and_append_block(ag, null_block); - IrInstSrc *null_result = astgen_node_extra(ag, op2_node, parent_scope, LValNone, + Stage1ZirInst *null_result = astgen_node_extra(ag, op2_node, parent_scope, LValNone, &peer_parent->peers.at(0)->base); if (null_result == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -3627,41 +3627,41 @@ static IrInstSrc *astgen_orelse(Stage1AstGen *ag, Scope *parent_scope, AstNode * ir_build_br(ag, parent_scope, node, end_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, ok_block); - IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false); - IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr); + Stage1ZirInst *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, parent_scope, node, maybe_ptr, false); + Stage1ZirInst *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr); ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base); Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block; ir_build_br(ag, parent_scope, node, end_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, end_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = null_result; incoming_values[1] = unwrapped_payload; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); incoming_blocks[0] = after_null_block; incoming_blocks[1] = after_ok_block; - IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent); + Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent); return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc); } -static IrInstSrc *astgen_error_union(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { +static Stage1ZirInst *astgen_error_union(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { assert(node->type == NodeTypeBinOpExpr); AstNode *op1_node = node->data.bin_op_expr.op1; AstNode *op2_node = node->data.bin_op_expr.op2; - IrInstSrc *err_set = astgen_node(ag, op1_node, parent_scope); + Stage1ZirInst *err_set = astgen_node(ag, op1_node, parent_scope); if (err_set == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *payload = astgen_node(ag, op2_node, parent_scope); + Stage1ZirInst *payload = astgen_node(ag, op2_node, parent_scope); if (payload == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; return ir_build_error_union(ag, parent_scope, node, err_set, payload); } -static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { +static Stage1ZirInst *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeBinOpExpr); BinOpType bin_op_type = node->data.bin_op_expr.bin_op; @@ -3752,7 +3752,7 @@ static IrInstSrc *astgen_bin_op(Stage1AstGen *ag, Scope *scope, AstNode *node, L zig_unreachable(); } -static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeIntLiteral); RootStruct *root_struct = node->owner->data.structure.root_struct; @@ -3761,7 +3761,7 @@ static IrInstSrc *astgen_int_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) return ir_build_const_bigint(ag, scope, node, bigint); } -static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) { Error err; assert(node->type == NodeTypeFloatLiteral); @@ -3778,7 +3778,7 @@ static IrInstSrc *astgen_float_lit(Stage1AstGen *ag, Scope *scope, AstNode *node return ir_build_const_bigfloat(ag, scope, node, bigfloat); } -static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) { Error err; assert(node->type == NodeTypeCharLiteral); @@ -3798,13 +3798,13 @@ static IrInstSrc *astgen_char_lit(Stage1AstGen *ag, Scope *scope, AstNode *node) return ir_build_const_uint(ag, scope, node, codepoint); } -static IrInstSrc *astgen_null_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_null_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeNullLiteral); return ir_build_const_null(ag, scope, node); } -static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { Error err; @@ -3814,7 +3814,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod if (buf_eql_str(variable_name, "_")) { if (lval == LValAssign) { - IrInstSrcConst *const_instruction = ir_build_instruction(ag, scope, node); + Stage1ZirInstConst *const_instruction = ir_build_instruction(ag, scope, node); const_instruction->value = ag->codegen->pass1_arena->create(); const_instruction->value->type = get_pointer_to_type(ag->codegen, ag->codegen->builtin_types.entry_void, false); @@ -3837,7 +3837,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod } assert(err == ErrorPrimitiveTypeNotFound); } else { - IrInstSrc *value = ir_build_const_type(ag, scope, node, primitive_type); + Stage1ZirInst *value = ir_build_const_type(ag, scope, node, primitive_type); if (lval == LValPtr || lval == LValAssign) { return ir_build_ref_src(ag, scope, node, value); } else { @@ -3848,7 +3848,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod ScopeFnDef *crossed_fndef_scope; ZigVar *var = find_variable(ag->codegen, scope, variable_name, &crossed_fndef_scope); if (var) { - IrInstSrc *var_ptr = ir_build_var_ptr_x(ag, scope, node, var, crossed_fndef_scope); + Stage1ZirInst *var_ptr = ir_build_var_ptr_x(ag, scope, node, var, crossed_fndef_scope); if (lval == LValPtr || lval == LValAssign) { return var_ptr; } else { @@ -3858,7 +3858,7 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod Tld *tld = find_decl(ag->codegen, scope, variable_name); if (tld) { - IrInstSrc *decl_ref = ir_build_decl_ref(ag, scope, node, tld, lval); + Stage1ZirInst *decl_ref = ir_build_decl_ref(ag, scope, node, tld, lval); if (lval == LValPtr || lval == LValAssign) { return decl_ref; } else { @@ -3875,52 +3875,52 @@ static IrInstSrc *astgen_identifier(Stage1AstGen *ag, Scope *scope, AstNode *nod return ir_build_undeclared_identifier(ag, scope, node, variable_name); } -static IrInstSrc *astgen_array_access(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_array_access(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeArrayAccessExpr); AstNode *array_ref_node = node->data.array_access_expr.array_ref_expr; - IrInstSrc *array_ref_instruction = astgen_node_extra(ag, array_ref_node, scope, LValPtr, nullptr); + Stage1ZirInst *array_ref_instruction = astgen_node_extra(ag, array_ref_node, scope, LValPtr, nullptr); if (array_ref_instruction == ag->codegen->invalid_inst_src) return array_ref_instruction; // Create an usize-typed result location to hold the subscript value, this // makes it possible for the compiler to infer the subscript expression type // if needed - IrInstSrc *usize_type_inst = ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_usize); + Stage1ZirInst *usize_type_inst = ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_usize); ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, usize_type_inst, no_result_loc()); AstNode *subscript_node = node->data.array_access_expr.subscript; - IrInstSrc *subscript_value = astgen_node_extra(ag, subscript_node, scope, LValNone, &result_loc_cast->base); + Stage1ZirInst *subscript_value = astgen_node_extra(ag, subscript_node, scope, LValNone, &result_loc_cast->base); if (subscript_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *subscript_instruction = ir_build_implicit_cast(ag, scope, subscript_node, subscript_value, result_loc_cast); + Stage1ZirInst *subscript_instruction = ir_build_implicit_cast(ag, scope, subscript_node, subscript_value, result_loc_cast); - IrInstSrc *ptr_instruction = ir_build_elem_ptr(ag, scope, node, array_ref_instruction, + Stage1ZirInst *ptr_instruction = ir_build_elem_ptr(ag, scope, node, array_ref_instruction, subscript_instruction, true, PtrLenSingle, nullptr); if (lval == LValPtr || lval == LValAssign) return ptr_instruction; - IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction); + Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction); return ir_expr_wrap(ag, scope, load_ptr, result_loc); } -static IrInstSrc *astgen_field_access(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_field_access(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeFieldAccessExpr); AstNode *container_ref_node = node->data.field_access_expr.struct_expr; Buf *field_name = node->data.field_access_expr.field_name; - IrInstSrc *container_ref_instruction = astgen_node_extra(ag, container_ref_node, scope, LValPtr, nullptr); + Stage1ZirInst *container_ref_instruction = astgen_node_extra(ag, container_ref_node, scope, LValPtr, nullptr); if (container_ref_instruction == ag->codegen->invalid_inst_src) return container_ref_instruction; return ir_build_field_ptr(ag, scope, node, container_ref_instruction, field_name, false); } -static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrOverflowOp op) { +static Stage1ZirInst *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *node, IrOverflowOp op) { assert(node->type == NodeTypeFnCallExpr); AstNode *type_node = node->data.fn_call_expr.params.at(0); @@ -3929,26 +3929,26 @@ static IrInstSrc *astgen_overflow_op(Stage1AstGen *ag, Scope *scope, AstNode *no AstNode *result_ptr_node = node->data.fn_call_expr.params.at(3); - IrInstSrc *type_value = astgen_node(ag, type_node, scope); + Stage1ZirInst *type_value = astgen_node(ag, type_node, scope); if (type_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *op1 = astgen_node(ag, op1_node, scope); + Stage1ZirInst *op1 = astgen_node(ag, op1_node, scope); if (op1 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *op2 = astgen_node(ag, op2_node, scope); + Stage1ZirInst *op2 = astgen_node(ag, op2_node, scope); if (op2 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *result_ptr = astgen_node(ag, result_ptr_node, scope); + Stage1ZirInst *result_ptr = astgen_node(ag, result_ptr_node, scope); if (result_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; return ir_build_overflow_op_src(ag, scope, node, op, type_value, op1, op2, result_ptr); } -static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeFnCallExpr); AstNode *type_node = node->data.fn_call_expr.params.at(0); @@ -3956,26 +3956,26 @@ static IrInstSrc *astgen_mul_add(Stage1AstGen *ag, Scope *scope, AstNode *node) AstNode *op2_node = node->data.fn_call_expr.params.at(2); AstNode *op3_node = node->data.fn_call_expr.params.at(3); - IrInstSrc *type_value = astgen_node(ag, type_node, scope); + Stage1ZirInst *type_value = astgen_node(ag, type_node, scope); if (type_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *op1 = astgen_node(ag, op1_node, scope); + Stage1ZirInst *op1 = astgen_node(ag, op1_node, scope); if (op1 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *op2 = astgen_node(ag, op2_node, scope); + Stage1ZirInst *op2 = astgen_node(ag, op2_node, scope); if (op2 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *op3 = astgen_node(ag, op3_node, scope); + Stage1ZirInst *op3 = astgen_node(ag, op3_node, scope); if (op3 == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; return ir_build_mul_add_src(ag, scope, node, type_value, op1, op2, op3); } -static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node) { +static Stage1ZirInst *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node) { for (Scope *it_scope = orig_scope; it_scope != nullptr; it_scope = it_scope->parent) { if (it_scope->id == ScopeIdDecls) { ScopeDecls *decls_scope = (ScopeDecls *)it_scope; @@ -3990,7 +3990,7 @@ static IrInstSrc *astgen_this(Stage1AstGen *ag, Scope *orig_scope, AstNode *node zig_unreachable(); } -static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *await_node, AstNode *call_node, +static Stage1ZirInst *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *await_node, AstNode *call_node, LVal lval, ResultLoc *result_loc) { if (call_node->data.fn_call_expr.params.length != 4) { @@ -4001,17 +4001,17 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa } AstNode *bytes_node = call_node->data.fn_call_expr.params.at(0); - IrInstSrc *bytes = astgen_node(ag, bytes_node, scope); + Stage1ZirInst *bytes = astgen_node(ag, bytes_node, scope); if (bytes == ag->codegen->invalid_inst_src) return bytes; AstNode *ret_ptr_node = call_node->data.fn_call_expr.params.at(1); - IrInstSrc *ret_ptr = astgen_node(ag, ret_ptr_node, scope); + Stage1ZirInst *ret_ptr = astgen_node(ag, ret_ptr_node, scope); if (ret_ptr == ag->codegen->invalid_inst_src) return ret_ptr; AstNode *fn_ref_node = call_node->data.fn_call_expr.params.at(2); - IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope); + Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope); if (fn_ref == ag->codegen->invalid_inst_src) return fn_ref; @@ -4023,16 +4023,16 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa args_node->data.container_init_expr.entries.length == 0) { size_t arg_count = args_node->data.container_init_expr.entries.length; - IrInstSrc **args = heap::c_allocator.allocate(arg_count); + Stage1ZirInst **args = heap::c_allocator.allocate(arg_count); for (size_t i = 0; i < arg_count; i += 1) { AstNode *arg_node = args_node->data.container_init_expr.entries.at(i); - IrInstSrc *arg = astgen_node(ag, arg_node, scope); + Stage1ZirInst *arg = astgen_node(ag, arg_node, scope); if (arg == ag->codegen->invalid_inst_src) return arg; args[i] = arg; } - IrInstSrc *call = ir_build_call_src(ag, scope, call_node, nullptr, fn_ref, arg_count, args, + Stage1ZirInst *call = ir_build_call_src(ag, scope, call_node, nullptr, fn_ref, arg_count, args, ret_ptr, modifier, is_async_call_builtin, bytes, result_loc); return ir_lval_wrap(ag, scope, call, lval, result_loc); } else { @@ -4041,42 +4041,42 @@ static IrInstSrc *astgen_async_call(Stage1AstGen *ag, Scope *scope, AstNode *awa return ag->codegen->invalid_inst_src; } } - IrInstSrc *args = astgen_node(ag, args_node, scope); + Stage1ZirInst *args = astgen_node(ag, args_node, scope); if (args == ag->codegen->invalid_inst_src) return args; - IrInstSrc *call = ir_build_async_call_extra(ag, scope, call_node, modifier, fn_ref, ret_ptr, bytes, args, result_loc); + Stage1ZirInst *call = ir_build_async_call_extra(ag, scope, call_node, modifier, fn_ref, ret_ptr, bytes, args, result_loc); return ir_lval_wrap(ag, scope, call, lval, result_loc); } -static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - AstNode *fn_ref_node, CallModifier modifier, IrInstSrc *options, +static Stage1ZirInst *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + AstNode *fn_ref_node, CallModifier modifier, Stage1ZirInst *options, AstNode **args_ptr, size_t args_len, LVal lval, ResultLoc *result_loc) { - IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope); + Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope); if (fn_ref == ag->codegen->invalid_inst_src) return fn_ref; - IrInstSrc *fn_type = ir_build_typeof_1(ag, scope, source_node, fn_ref); + Stage1ZirInst *fn_type = ir_build_typeof_1(ag, scope, source_node, fn_ref); - IrInstSrc **args = heap::c_allocator.allocate(args_len); + Stage1ZirInst **args = heap::c_allocator.allocate(args_len); for (size_t i = 0; i < args_len; i += 1) { AstNode *arg_node = args_ptr[i]; - IrInstSrc *arg_index = ir_build_const_usize(ag, scope, arg_node, i); - IrInstSrc *arg_type = ir_build_arg_type(ag, scope, source_node, fn_type, arg_index, true); + Stage1ZirInst *arg_index = ir_build_const_usize(ag, scope, arg_node, i); + Stage1ZirInst *arg_type = ir_build_arg_type(ag, scope, source_node, fn_type, arg_index, true); ResultLoc *no_result = no_result_loc(); ir_build_reset_result(ag, scope, source_node, no_result); ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, arg_type, no_result); - IrInstSrc *arg = astgen_node_extra(ag, arg_node, scope, LValNone, &result_loc_cast->base); + Stage1ZirInst *arg = astgen_node_extra(ag, arg_node, scope, LValNone, &result_loc_cast->base); if (arg == ag->codegen->invalid_inst_src) return arg; args[i] = ir_build_implicit_cast(ag, scope, arg_node, arg, result_loc_cast); } - IrInstSrc *fn_call; + Stage1ZirInst *fn_call; if (options != nullptr) { fn_call = ir_build_call_args(ag, scope, source_node, options, fn_ref, args, args_len, result_loc); } else { @@ -4086,7 +4086,7 @@ static IrInstSrc *astgen_fn_call_with_args(Stage1AstGen *ag, Scope *scope, AstNo return ir_lval_wrap(ag, scope, fn_call, lval, result_loc); } -static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeFnCallExpr); @@ -4120,7 +4120,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode size_t arg_count = node->data.fn_call_expr.params.length; - IrInstSrc *type_of; + Stage1ZirInst *type_of; if (arg_count == 0) { add_node_error(ag->codegen, node, @@ -4128,16 +4128,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ag->codegen->invalid_inst_src; } else if (arg_count == 1) { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, sub_scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, sub_scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; type_of = ir_build_typeof_1(ag, scope, node, arg0_value); } else { - IrInstSrc **args = heap::c_allocator.allocate(arg_count); + Stage1ZirInst **args = heap::c_allocator.allocate(arg_count); for (size_t i = 0; i < arg_count; i += 1) { AstNode *arg_node = node->data.fn_call_expr.params.at(i); - IrInstSrc *arg = astgen_node(ag, arg_node, sub_scope); + Stage1ZirInst *arg = astgen_node(ag, arg_node, sub_scope); if (arg == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; args[i] = arg; @@ -4150,63 +4150,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdSetCold: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *set_cold = ir_build_set_cold(ag, scope, node, arg0_value); + Stage1ZirInst *set_cold = ir_build_set_cold(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, set_cold, lval, result_loc); } case BuiltinFnIdSetRuntimeSafety: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *set_safety = ir_build_set_runtime_safety(ag, scope, node, arg0_value); + Stage1ZirInst *set_safety = ir_build_set_runtime_safety(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, set_safety, lval, result_loc); } case BuiltinFnIdSetFloatMode: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *set_float_mode = ir_build_set_float_mode(ag, scope, node, arg0_value); + Stage1ZirInst *set_float_mode = ir_build_set_float_mode(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, set_float_mode, lval, result_loc); } case BuiltinFnIdSizeof: case BuiltinFnIdBitSizeof: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *size_of = ir_build_size_of(ag, scope, node, arg0_value, builtin_fn->id == BuiltinFnIdBitSizeof); + Stage1ZirInst *size_of = ir_build_size_of(ag, scope, node, arg0_value, builtin_fn->id == BuiltinFnIdBitSizeof); return ir_lval_wrap(ag, scope, size_of, lval, result_loc); } case BuiltinFnIdImport: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *import = ir_build_import(ag, scope, node, arg0_value); + Stage1ZirInst *import = ir_build_import(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, import, lval, result_loc); } case BuiltinFnIdCImport: { - IrInstSrc *c_import = ir_build_c_import(ag, scope, node); + Stage1ZirInst *c_import = ir_build_c_import(ag, scope, node); return ir_lval_wrap(ag, scope, c_import, lval, result_loc); } case BuiltinFnIdCInclude: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; @@ -4215,18 +4215,18 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ag->codegen->invalid_inst_src; } - IrInstSrc *c_include = ir_build_c_include(ag, scope, node, arg0_value); + Stage1ZirInst *c_include = ir_build_c_include(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, c_include, lval, result_loc); } case BuiltinFnIdCDefine: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; @@ -4235,13 +4235,13 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ag->codegen->invalid_inst_src; } - IrInstSrc *c_define = ir_build_c_define(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *c_define = ir_build_c_define(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, c_define, lval, result_loc); } case BuiltinFnIdCUndef: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; @@ -4250,22 +4250,22 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ag->codegen->invalid_inst_src; } - IrInstSrc *c_undef = ir_build_c_undef(ag, scope, node, arg0_value); + Stage1ZirInst *c_undef = ir_build_c_undef(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, c_undef, lval, result_loc); } case BuiltinFnIdCompileErr: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *compile_err = ir_build_compile_err(ag, scope, node, arg0_value); + Stage1ZirInst *compile_err = ir_build_compile_err(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, compile_err, lval, result_loc); } case BuiltinFnIdCompileLog: { - IrInstSrc **args = heap::c_allocator.allocate(actual_param_count); + Stage1ZirInst **args = heap::c_allocator.allocate(actual_param_count); for (size_t i = 0; i < actual_param_count; i += 1) { AstNode *arg_node = node->data.fn_call_expr.params.at(i); @@ -4274,63 +4274,63 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ag->codegen->invalid_inst_src; } - IrInstSrc *compile_log = ir_build_compile_log(ag, scope, node, actual_param_count, args); + Stage1ZirInst *compile_log = ir_build_compile_log(ag, scope, node, actual_param_count, args); return ir_lval_wrap(ag, scope, compile_log, lval, result_loc); } case BuiltinFnIdErrName: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *err_name = ir_build_err_name(ag, scope, node, arg0_value); + Stage1ZirInst *err_name = ir_build_err_name(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, err_name, lval, result_loc); } case BuiltinFnIdEmbedFile: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *embed_file = ir_build_embed_file(ag, scope, node, arg0_value); + Stage1ZirInst *embed_file = ir_build_embed_file(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, embed_file, lval, result_loc); } case BuiltinFnIdCmpxchgWeak: case BuiltinFnIdCmpxchgStrong: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; AstNode *arg3_node = node->data.fn_call_expr.params.at(3); - IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope); + Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope); if (arg3_value == ag->codegen->invalid_inst_src) return arg3_value; AstNode *arg4_node = node->data.fn_call_expr.params.at(4); - IrInstSrc *arg4_value = astgen_node(ag, arg4_node, scope); + Stage1ZirInst *arg4_value = astgen_node(ag, arg4_node, scope); if (arg4_value == ag->codegen->invalid_inst_src) return arg4_value; AstNode *arg5_node = node->data.fn_call_expr.params.at(5); - IrInstSrc *arg5_value = astgen_node(ag, arg5_node, scope); + Stage1ZirInst *arg5_value = astgen_node(ag, arg5_node, scope); if (arg5_value == ag->codegen->invalid_inst_src) return arg5_value; - IrInstSrc *cmpxchg = ir_build_cmpxchg_src(ag, scope, node, arg0_value, arg1_value, + Stage1ZirInst *cmpxchg = ir_build_cmpxchg_src(ag, scope, node, arg0_value, arg1_value, arg2_value, arg3_value, arg4_value, arg5_value, (builtin_fn->id == BuiltinFnIdCmpxchgWeak), result_loc); return ir_lval_wrap(ag, scope, cmpxchg, lval, result_loc); @@ -4338,101 +4338,101 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdFence: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *fence = ir_build_fence(ag, scope, node, arg0_value); + Stage1ZirInst *fence = ir_build_fence(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, fence, lval, result_loc); } case BuiltinFnIdReduce: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *reduce = ir_build_reduce(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *reduce = ir_build_reduce(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, reduce, lval, result_loc); } case BuiltinFnIdDivExact: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivExact, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivExact, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdDivTrunc: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivTrunc, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivTrunc, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdDivFloor: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivFloor, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpDivFloor, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdRem: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemRem, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemRem, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdMod: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemMod, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpRemMod, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdSqrt: @@ -4451,146 +4451,146 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdRound: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *inst = ir_build_float_op_src(ag, scope, node, arg0_value, builtin_fn->id); + Stage1ZirInst *inst = ir_build_float_op_src(ag, scope, node, arg0_value, builtin_fn->id); return ir_lval_wrap(ag, scope, inst, lval, result_loc); } case BuiltinFnIdTruncate: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *truncate = ir_build_truncate(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *truncate = ir_build_truncate(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, truncate, lval, result_loc); } case BuiltinFnIdIntCast: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_int_cast(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *result = ir_build_int_cast(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdFloatCast: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_float_cast(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *result = ir_build_float_cast(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdErrSetCast: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_err_set_cast(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *result = ir_build_err_set_cast(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdIntToFloat: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_int_to_float(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *result = ir_build_int_to_float(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdFloatToInt: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_float_to_int(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *result = ir_build_float_to_int(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdErrToInt: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *result = ir_build_err_to_int_src(ag, scope, node, arg0_value); + Stage1ZirInst *result = ir_build_err_to_int_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdIntToErr: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *result = ir_build_int_to_err_src(ag, scope, node, arg0_value); + Stage1ZirInst *result = ir_build_int_to_err_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdBoolToInt: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *result = ir_build_bool_to_int(ag, scope, node, arg0_value); + Stage1ZirInst *result = ir_build_bool_to_int(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdVectorType: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *vector_type = ir_build_vector_type(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *vector_type = ir_build_vector_type(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, vector_type, lval, result_loc); } case BuiltinFnIdShuffle: @@ -4599,164 +4599,164 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope); AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, comptime_scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, comptime_scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; AstNode *arg3_node = node->data.fn_call_expr.params.at(3); - IrInstSrc *arg3_value = astgen_node(ag, arg3_node, comptime_scope); + Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, comptime_scope); if (arg3_value == ag->codegen->invalid_inst_src) return arg3_value; - IrInstSrc *shuffle_vector = ir_build_shuffle_vector(ag, scope, node, + Stage1ZirInst *shuffle_vector = ir_build_shuffle_vector(ag, scope, node, arg0_value, arg1_value, arg2_value, arg3_value); return ir_lval_wrap(ag, scope, shuffle_vector, lval, result_loc); } case BuiltinFnIdSplat: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *splat = ir_build_splat_src(ag, scope, node, + Stage1ZirInst *splat = ir_build_splat_src(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, splat, lval, result_loc); } case BuiltinFnIdMemcpy: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; - IrInstSrc *ir_memcpy = ir_build_memcpy_src(ag, scope, node, arg0_value, arg1_value, arg2_value); + Stage1ZirInst *ir_memcpy = ir_build_memcpy_src(ag, scope, node, arg0_value, arg1_value, arg2_value); return ir_lval_wrap(ag, scope, ir_memcpy, lval, result_loc); } case BuiltinFnIdMemset: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; - IrInstSrc *ir_memset = ir_build_memset_src(ag, scope, node, arg0_value, arg1_value, arg2_value); + Stage1ZirInst *ir_memset = ir_build_memset_src(ag, scope, node, arg0_value, arg1_value, arg2_value); return ir_lval_wrap(ag, scope, ir_memset, lval, result_loc); } case BuiltinFnIdWasmMemorySize: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *ir_wasm_memory_size = ir_build_wasm_memory_size_src(ag, scope, node, arg0_value); + Stage1ZirInst *ir_wasm_memory_size = ir_build_wasm_memory_size_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, ir_wasm_memory_size, lval, result_loc); } case BuiltinFnIdWasmMemoryGrow: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *ir_wasm_memory_grow = ir_build_wasm_memory_grow_src(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, ir_wasm_memory_grow, lval, result_loc); } case BuiltinFnIdField: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node_extra(ag, arg0_node, scope, LValPtr, nullptr); + Stage1ZirInst *arg0_value = astgen_node_extra(ag, arg0_node, scope, LValPtr, nullptr); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *ptr_instruction = ir_build_field_ptr_instruction(ag, scope, node, + Stage1ZirInst *ptr_instruction = ir_build_field_ptr_instruction(ag, scope, node, arg0_value, arg1_value, false); if (lval == LValPtr || lval == LValAssign) return ptr_instruction; - IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction); + Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction); return ir_expr_wrap(ag, scope, load_ptr, result_loc); } case BuiltinFnIdHasField: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *type_info = ir_build_has_field(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *type_info = ir_build_has_field(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, type_info, lval, result_loc); } case BuiltinFnIdTypeInfo: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *type_info = ir_build_type_info(ag, scope, node, arg0_value); + Stage1ZirInst *type_info = ir_build_type_info(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, type_info, lval, result_loc); } case BuiltinFnIdType: { AstNode *arg_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg = astgen_node(ag, arg_node, scope); + Stage1ZirInst *arg = astgen_node(ag, arg_node, scope); if (arg == ag->codegen->invalid_inst_src) return arg; - IrInstSrc *type = ir_build_type(ag, scope, node, arg); + Stage1ZirInst *type = ir_build_type(ag, scope, node, arg); return ir_lval_wrap(ag, scope, type, lval, result_loc); } case BuiltinFnIdBreakpoint: @@ -4774,30 +4774,30 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ir_lval_wrap(ag, scope, ir_build_handle_src(ag, scope, node), lval, result_loc); case BuiltinFnIdFrameType: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *frame_type = ir_build_frame_type(ag, scope, node, arg0_value); + Stage1ZirInst *frame_type = ir_build_frame_type(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, frame_type, lval, result_loc); } case BuiltinFnIdFrameSize: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *frame_size = ir_build_frame_size_src(ag, scope, node, arg0_value); + Stage1ZirInst *frame_size = ir_build_frame_size_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, frame_size, lval, result_loc); } case BuiltinFnIdAlignOf: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *align_of = ir_build_align_of(ag, scope, node, arg0_value); + Stage1ZirInst *align_of = ir_build_align_of(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, align_of, lval, result_loc); } case BuiltinFnIdAddWithOverflow: @@ -4813,42 +4813,42 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdTypeName: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *type_name = ir_build_type_name(ag, scope, node, arg0_value); + Stage1ZirInst *type_name = ir_build_type_name(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, type_name, lval, result_loc); } case BuiltinFnIdPanic: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *panic = ir_build_panic_src(ag, scope, node, arg0_value); + Stage1ZirInst *panic = ir_build_panic_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, panic, lval, result_loc); } case BuiltinFnIdPtrCast: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *ptr_cast = ir_build_ptr_cast_src(ag, scope, node, arg0_value, arg1_value, true); + Stage1ZirInst *ptr_cast = ir_build_ptr_cast_src(ag, scope, node, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, ptr_cast, lval, result_loc); } case BuiltinFnIdBitCast: { AstNode *dest_type_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *dest_type = astgen_node(ag, dest_type_node, scope); + Stage1ZirInst *dest_type = astgen_node(ag, dest_type_node, scope); if (dest_type == ag->codegen->invalid_inst_src) return dest_type; @@ -4862,130 +4862,130 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode ir_build_reset_result(ag, scope, node, &result_loc_bit_cast->base); AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone, + Stage1ZirInst *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone, &result_loc_bit_cast->base); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bitcast = ir_build_bit_cast_src(ag, scope, arg1_node, arg1_value, result_loc_bit_cast); + Stage1ZirInst *bitcast = ir_build_bit_cast_src(ag, scope, arg1_node, arg1_value, result_loc_bit_cast); return ir_lval_wrap(ag, scope, bitcast, lval, result_loc); } case BuiltinFnIdAs: { AstNode *dest_type_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *dest_type = astgen_node(ag, dest_type_node, scope); + Stage1ZirInst *dest_type = astgen_node(ag, dest_type_node, scope); if (dest_type == ag->codegen->invalid_inst_src) return dest_type; ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, dest_type, result_loc); AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone, + Stage1ZirInst *arg1_value = astgen_node_extra(ag, arg1_node, scope, LValNone, &result_loc_cast->base); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_implicit_cast(ag, scope, node, arg1_value, result_loc_cast); + Stage1ZirInst *result = ir_build_implicit_cast(ag, scope, node, arg1_value, result_loc_cast); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdIntToPtr: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *int_to_ptr = ir_build_int_to_ptr_src(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *int_to_ptr = ir_build_int_to_ptr_src(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, int_to_ptr, lval, result_loc); } case BuiltinFnIdPtrToInt: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *ptr_to_int = ir_build_ptr_to_int_src(ag, scope, node, arg0_value); + Stage1ZirInst *ptr_to_int = ir_build_ptr_to_int_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, ptr_to_int, lval, result_loc); } case BuiltinFnIdTagName: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *tag_name = ir_build_tag_name_src(ag, scope, node, arg0_value); + Stage1ZirInst *tag_name = ir_build_tag_name_src(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, tag_name, lval, result_loc); } case BuiltinFnIdFieldParentPtr: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; - IrInstSrc *field_parent_ptr = ir_build_field_parent_ptr_src(ag, scope, node, + Stage1ZirInst *field_parent_ptr = ir_build_field_parent_ptr_src(ag, scope, node, arg0_value, arg1_value, arg2_value); return ir_lval_wrap(ag, scope, field_parent_ptr, lval, result_loc); } case BuiltinFnIdOffsetOf: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *offset_of = ir_build_offset_of(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *offset_of = ir_build_offset_of(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, offset_of, lval, result_loc); } case BuiltinFnIdBitOffsetOf: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *offset_of = ir_build_bit_offset_of(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *offset_of = ir_build_bit_offset_of(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, offset_of, lval, result_loc); } case BuiltinFnIdCall: { // Cast the options parameter to the options type ZigType *options_type = get_builtin_type(ag->codegen, "CallOptions"); - IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type); + Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type); ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc()); AstNode *options_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *options_inner = astgen_node_extra(ag, options_node, scope, + Stage1ZirInst *options_inner = astgen_node_extra(ag, options_node, scope, LValNone, &result_loc_cast->base); if (options_inner == ag->codegen->invalid_inst_src) return options_inner; - IrInstSrc *options = ir_build_implicit_cast(ag, scope, options_node, options_inner, result_loc_cast); + Stage1ZirInst *options = ir_build_implicit_cast(ag, scope, options_node, options_inner, result_loc_cast); AstNode *fn_ref_node = node->data.fn_call_expr.params.at(1); AstNode *args_node = node->data.fn_call_expr.params.at(2); @@ -5004,15 +5004,15 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode return ag->codegen->invalid_inst_src; } } else { - IrInstSrc *fn_ref = astgen_node(ag, fn_ref_node, scope); + Stage1ZirInst *fn_ref = astgen_node(ag, fn_ref_node, scope); if (fn_ref == ag->codegen->invalid_inst_src) return fn_ref; - IrInstSrc *args = astgen_node(ag, args_node, scope); + Stage1ZirInst *args = astgen_node(ag, args_node, scope); if (args == ag->codegen->invalid_inst_src) return args; - IrInstSrc *call = ir_build_call_extra(ag, scope, node, options, fn_ref, args, result_loc); + Stage1ZirInst *call = ir_build_call_extra(ag, scope, node, options, fn_ref, args, result_loc); return ir_lval_wrap(ag, scope, call, lval, result_loc); } } @@ -5021,227 +5021,227 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdShlExact: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftLeftExact, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftLeftExact, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdShrExact: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftRightExact, arg0_value, arg1_value, true); + Stage1ZirInst *bin_op = ir_build_bin_op(ag, scope, node, IrBinOpBitShiftRightExact, arg0_value, arg1_value, true); return ir_lval_wrap(ag, scope, bin_op, lval, result_loc); } case BuiltinFnIdSetEvalBranchQuota: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *set_eval_branch_quota = ir_build_set_eval_branch_quota(ag, scope, node, arg0_value); + Stage1ZirInst *set_eval_branch_quota = ir_build_set_eval_branch_quota(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, set_eval_branch_quota, lval, result_loc); } case BuiltinFnIdAlignCast: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *align_cast = ir_build_align_cast_src(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *align_cast = ir_build_align_cast_src(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, align_cast, lval, result_loc); } case BuiltinFnIdThis: { - IrInstSrc *this_inst = astgen_this(ag, scope, node); + Stage1ZirInst *this_inst = astgen_this(ag, scope, node); return ir_lval_wrap(ag, scope, this_inst, lval, result_loc); } case BuiltinFnIdSetAlignStack: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *set_align_stack = ir_build_set_align_stack(ag, scope, node, arg0_value); + Stage1ZirInst *set_align_stack = ir_build_set_align_stack(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, set_align_stack, lval, result_loc); } case BuiltinFnIdExport: { // Cast the options parameter to the options type ZigType *options_type = get_builtin_type(ag->codegen, "ExportOptions"); - IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type); + Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type); ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc()); AstNode *target_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *target_value = astgen_node(ag, target_node, scope); + Stage1ZirInst *target_value = astgen_node(ag, target_node, scope); if (target_value == ag->codegen->invalid_inst_src) return target_value; AstNode *options_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *options_value = astgen_node_extra(ag, options_node, + Stage1ZirInst *options_value = astgen_node_extra(ag, options_node, scope, LValNone, &result_loc_cast->base); if (options_value == ag->codegen->invalid_inst_src) return options_value; - IrInstSrc *casted_options_value = ir_build_implicit_cast( + Stage1ZirInst *casted_options_value = ir_build_implicit_cast( ag, scope, options_node, options_value, result_loc_cast); - IrInstSrc *ir_export = ir_build_export(ag, scope, node, target_value, casted_options_value); + Stage1ZirInst *ir_export = ir_build_export(ag, scope, node, target_value, casted_options_value); return ir_lval_wrap(ag, scope, ir_export, lval, result_loc); } case BuiltinFnIdExtern: { // Cast the options parameter to the options type ZigType *options_type = get_builtin_type(ag->codegen, "ExternOptions"); - IrInstSrc *options_type_inst = ir_build_const_type(ag, scope, node, options_type); + Stage1ZirInst *options_type_inst = ir_build_const_type(ag, scope, node, options_type); ResultLocCast *result_loc_cast = ir_build_cast_result_loc(ag, options_type_inst, no_result_loc()); AstNode *type_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *type_value = astgen_node(ag, type_node, scope); + Stage1ZirInst *type_value = astgen_node(ag, type_node, scope); if (type_value == ag->codegen->invalid_inst_src) return type_value; AstNode *options_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *options_value = astgen_node_extra(ag, options_node, + Stage1ZirInst *options_value = astgen_node_extra(ag, options_node, scope, LValNone, &result_loc_cast->base); if (options_value == ag->codegen->invalid_inst_src) return options_value; - IrInstSrc *casted_options_value = ir_build_implicit_cast( + Stage1ZirInst *casted_options_value = ir_build_implicit_cast( ag, scope, options_node, options_value, result_loc_cast); - IrInstSrc *ir_extern = ir_build_extern(ag, scope, node, type_value, casted_options_value); + Stage1ZirInst *ir_extern = ir_build_extern(ag, scope, node, type_value, casted_options_value); return ir_lval_wrap(ag, scope, ir_extern, lval, result_loc); } case BuiltinFnIdErrorReturnTrace: { - IrInstSrc *error_return_trace = ir_build_error_return_trace_src(ag, scope, node, + Stage1ZirInst *error_return_trace = ir_build_error_return_trace_src(ag, scope, node, IrInstErrorReturnTraceNull); return ir_lval_wrap(ag, scope, error_return_trace, lval, result_loc); } case BuiltinFnIdAtomicRmw: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; AstNode *arg3_node = node->data.fn_call_expr.params.at(3); - IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope); + Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope); if (arg3_value == ag->codegen->invalid_inst_src) return arg3_value; AstNode *arg4_node = node->data.fn_call_expr.params.at(4); - IrInstSrc *arg4_value = astgen_node(ag, arg4_node, scope); + Stage1ZirInst *arg4_value = astgen_node(ag, arg4_node, scope); if (arg4_value == ag->codegen->invalid_inst_src) return arg4_value; - IrInstSrc *inst = ir_build_atomic_rmw_src(ag, scope, node, + Stage1ZirInst *inst = ir_build_atomic_rmw_src(ag, scope, node, arg0_value, arg1_value, arg2_value, arg3_value, arg4_value); return ir_lval_wrap(ag, scope, inst, lval, result_loc); } case BuiltinFnIdAtomicLoad: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; - IrInstSrc *inst = ir_build_atomic_load_src(ag, scope, node, arg0_value, arg1_value, arg2_value); + Stage1ZirInst *inst = ir_build_atomic_load_src(ag, scope, node, arg0_value, arg1_value, arg2_value); return ir_lval_wrap(ag, scope, inst, lval, result_loc); } case BuiltinFnIdAtomicStore: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; AstNode *arg2_node = node->data.fn_call_expr.params.at(2); - IrInstSrc *arg2_value = astgen_node(ag, arg2_node, scope); + Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope); if (arg2_value == ag->codegen->invalid_inst_src) return arg2_value; AstNode *arg3_node = node->data.fn_call_expr.params.at(3); - IrInstSrc *arg3_value = astgen_node(ag, arg3_node, scope); + Stage1ZirInst *arg3_value = astgen_node(ag, arg3_node, scope); if (arg3_value == ag->codegen->invalid_inst_src) return arg3_value; - IrInstSrc *inst = ir_build_atomic_store_src(ag, scope, node, arg0_value, arg1_value, + Stage1ZirInst *inst = ir_build_atomic_store_src(ag, scope, node, arg0_value, arg1_value, arg2_value, arg3_value); return ir_lval_wrap(ag, scope, inst, lval, result_loc); } case BuiltinFnIdIntToEnum: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result = ir_build_int_to_enum_src(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *result = ir_build_int_to_enum_src(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdEnumToInt: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; - IrInstSrc *result = ir_build_enum_to_int(ag, scope, node, arg0_value); + Stage1ZirInst *result = ir_build_enum_to_int(ag, scope, node, arg0_value); return ir_lval_wrap(ag, scope, result, lval, result_loc); } case BuiltinFnIdCtz: @@ -5251,16 +5251,16 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdBitReverse: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *result; + Stage1ZirInst *result; switch (builtin_fn->id) { case BuiltinFnIdCtz: result = ir_build_ctz(ag, scope, node, arg0_value, arg1_value); @@ -5285,27 +5285,27 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode case BuiltinFnIdHasDecl: { AstNode *arg0_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *arg0_value = astgen_node(ag, arg0_node, scope); + Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, scope); if (arg0_value == ag->codegen->invalid_inst_src) return arg0_value; AstNode *arg1_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *arg1_value = astgen_node(ag, arg1_node, scope); + Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope); if (arg1_value == ag->codegen->invalid_inst_src) return arg1_value; - IrInstSrc *has_decl = ir_build_has_decl(ag, scope, node, arg0_value, arg1_value); + Stage1ZirInst *has_decl = ir_build_has_decl(ag, scope, node, arg0_value, arg1_value); return ir_lval_wrap(ag, scope, has_decl, lval, result_loc); } case BuiltinFnIdUnionInit: { AstNode *union_type_node = node->data.fn_call_expr.params.at(0); - IrInstSrc *union_type_inst = astgen_node(ag, union_type_node, scope); + Stage1ZirInst *union_type_inst = astgen_node(ag, union_type_node, scope); if (union_type_inst == ag->codegen->invalid_inst_src) return union_type_inst; AstNode *name_node = node->data.fn_call_expr.params.at(1); - IrInstSrc *name_inst = astgen_node(ag, name_node, scope); + Stage1ZirInst *name_inst = astgen_node(ag, name_node, scope); if (name_inst == ag->codegen->invalid_inst_src) return name_inst; @@ -5316,7 +5316,7 @@ static IrInstSrc *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, AstNode } case BuiltinFnIdSrc: { - IrInstSrc *src_inst = ir_build_src(ag, scope, node); + Stage1ZirInst *src_inst = ir_build_src(ag, scope, node); return ir_lval_wrap(ag, scope, src_inst, lval, result_loc); } } @@ -5335,7 +5335,7 @@ static ScopeNoSuspend *get_scope_nosuspend(Scope *scope) { return nullptr; } -static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeFnCallExpr); @@ -5354,16 +5354,16 @@ static IrInstSrc *astgen_fn_call(Stage1AstGen *ag, Scope *scope, AstNode *node, nullptr, node->data.fn_call_expr.params.items, node->data.fn_call_expr.params.length, lval, result_loc); } -static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeIfBoolExpr); - IrInstSrc *condition = astgen_node(ag, node->data.if_bool_expr.condition, scope); + Stage1ZirInst *condition = astgen_node(ag, node->data.if_bool_expr.condition, scope); if (condition == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, scope)) { is_comptime = ir_build_const_bool(ag, scope, node, true); } else { @@ -5377,7 +5377,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "Else"); Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "EndIf"); - IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, condition, + Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, condition, then_block, else_block, is_comptime); ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block, result_loc, is_comptime); @@ -5385,7 +5385,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n ir_set_cursor_at_end_and_append_block(ag, then_block); Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime); - IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, subexpr_scope, lval, + Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, subexpr_scope, lval, &peer_parent->peers.at(0)->base); if (then_expr_result == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -5394,7 +5394,7 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n ir_build_br(ag, scope, node, endif_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, else_block); - IrInstSrc *else_expr_result; + Stage1ZirInst *else_expr_result; if (else_node) { else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base); if (else_expr_result == ag->codegen->invalid_inst_src) @@ -5408,39 +5408,39 @@ static IrInstSrc *astgen_if_bool_expr(Stage1AstGen *ag, Scope *scope, AstNode *n ir_build_br(ag, scope, node, endif_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, endif_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = then_expr_result; incoming_values[1] = else_expr_result; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); incoming_blocks[0] = after_then_block; incoming_blocks[1] = after_else_block; - IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent); + Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent); return ir_expr_wrap(ag, scope, phi, result_loc); } -static IrInstSrc *astgen_prefix_op_id_lval(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id, LVal lval) { +static Stage1ZirInst *astgen_prefix_op_id_lval(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id, LVal lval) { assert(node->type == NodeTypePrefixOpExpr); AstNode *expr_node = node->data.prefix_op_expr.primary_expr; - IrInstSrc *value = astgen_node_extra(ag, expr_node, scope, lval, nullptr); + Stage1ZirInst *value = astgen_node_extra(ag, expr_node, scope, lval, nullptr); if (value == ag->codegen->invalid_inst_src) return value; return ir_build_un_op(ag, scope, node, op_id, value); } -static IrInstSrc *astgen_prefix_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id) { +static Stage1ZirInst *astgen_prefix_op_id(Stage1AstGen *ag, Scope *scope, AstNode *node, IrUnOp op_id) { return astgen_prefix_op_id_lval(ag, scope, node, op_id, LValNone); } -static IrInstSrc *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *inst, ResultLoc *result_loc) { +static Stage1ZirInst *ir_expr_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *inst, ResultLoc *result_loc) { if (inst == ag->codegen->invalid_inst_src) return inst; ir_build_end_expr(ag, scope, inst->source_node, inst, result_loc); return inst; } -static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, LVal lval, +static Stage1ZirInst *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, Stage1ZirInst *value, LVal lval, ResultLoc *result_loc) { // This logic must be kept in sync with @@ -5448,7 +5448,7 @@ static IrInstSrc *ir_lval_wrap(Stage1AstGen *ag, Scope *scope, IrInstSrc *value, if (value == ag->codegen->invalid_inst_src || instr_is_unreachable(value) || value->source_node->type == NodeTypeDefer || - value->id == IrInstSrcIdDeclVar) + value->id == Stage1ZirInstIdDeclVar) { return value; } @@ -5500,7 +5500,7 @@ static Error token_number_literal_u32(Stage1AstGen *ag, AstNode *source_node, } -static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { Error err; assert(node->type == NodeTypePointerType); @@ -5515,7 +5515,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n AstNode *expr_node = node->data.pointer_type.op_expr; AstNode *align_expr = node->data.pointer_type.align_expr; - IrInstSrc *sentinel; + Stage1ZirInst *sentinel; if (sentinel_expr != nullptr) { sentinel = astgen_node(ag, sentinel_expr, scope); if (sentinel == ag->codegen->invalid_inst_src) @@ -5524,7 +5524,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n sentinel = nullptr; } - IrInstSrc *align_value; + Stage1ZirInst *align_value; if (align_expr != nullptr) { align_value = astgen_node(ag, align_expr, scope); if (align_value == ag->codegen->invalid_inst_src) @@ -5533,7 +5533,7 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n align_value = nullptr; } - IrInstSrc *child_type = astgen_node(ag, expr_node, scope); + Stage1ZirInst *child_type = astgen_node(ag, expr_node, scope); if (child_type == ag->codegen->invalid_inst_src) return child_type; @@ -5565,36 +5565,36 @@ static IrInstSrc *astgen_pointer_type(Stage1AstGen *ag, Scope *scope, AstNode *n ptr_len, sentinel, align_value, bit_offset_start, host_int_bytes, is_allow_zero); } -static IrInstSrc *astgen_catch_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node, +static Stage1ZirInst *astgen_catch_unreachable(Stage1AstGen *ag, Scope *scope, AstNode *source_node, AstNode *expr_node, LVal lval, ResultLoc *result_loc) { - IrInstSrc *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); + Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); if (err_union_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, scope, source_node, err_union_ptr, true, false); + Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, scope, source_node, err_union_ptr, true, false); if (payload_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; if (lval == LValPtr) return payload_ptr; - IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, source_node, payload_ptr); + Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, source_node, payload_ptr); return ir_expr_wrap(ag, scope, load_ptr, result_loc); } -static IrInstSrc *astgen_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_bool_not(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypePrefixOpExpr); AstNode *expr_node = node->data.prefix_op_expr.primary_expr; - IrInstSrc *value = astgen_node(ag, expr_node, scope); + Stage1ZirInst *value = astgen_node(ag, expr_node, scope); if (value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; return ir_build_bool_not(ag, scope, node, value); } -static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypePrefixOpExpr); @@ -5622,12 +5622,12 @@ static IrInstSrc *astgen_prefix_op_expr(Stage1AstGen *ag, Scope *scope, AstNode zig_unreachable(); } -static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, - IrInstSrc *union_type, IrInstSrc *field_name, AstNode *expr_node, +static Stage1ZirInst *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *source_node, + Stage1ZirInst *union_type, Stage1ZirInst *field_name, AstNode *expr_node, LVal lval, ResultLoc *parent_result_loc) { - IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, source_node, parent_result_loc, union_type); - IrInstSrc *field_ptr = ir_build_field_ptr_instruction(ag, scope, source_node, container_ptr, + Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, source_node, parent_result_loc, union_type); + Stage1ZirInst *field_ptr = ir_build_field_ptr_instruction(ag, scope, source_node, container_ptr, field_name, true); ResultLocInstruction *result_loc_inst = heap::c_allocator.create(); @@ -5636,18 +5636,18 @@ static IrInstSrc *astgen_union_init_expr(Stage1AstGen *ag, Scope *scope, AstNode ir_ref_instruction(field_ptr, ag->current_basic_block); ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base); - IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone, + Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone, &result_loc_inst->base); if (expr_value == ag->codegen->invalid_inst_src) return expr_value; - IrInstSrc *init_union = ir_build_union_init_named_field(ag, scope, source_node, union_type, + Stage1ZirInst *init_union = ir_build_union_init_named_field(ag, scope, source_node, union_type, field_name, field_ptr, container_ptr); return ir_lval_wrap(ag, scope, init_union, lval, parent_result_loc); } -static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *parent_result_loc) { assert(node->type == NodeTypeContainerInitExpr); @@ -5659,14 +5659,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast ResultLoc *child_result_loc; AstNode *init_array_type_source_node; if (container_init_expr->type != nullptr) { - IrInstSrc *container_type; + Stage1ZirInst *container_type; if (container_init_expr->type->type == NodeTypeInferredArrayType) { if (kind == ContainerInitKindStruct) { add_node_error(ag->codegen, container_init_expr->type, buf_sprintf("initializing array with struct syntax")); return ag->codegen->invalid_inst_src; } - IrInstSrc *sentinel; + Stage1ZirInst *sentinel; if (container_init_expr->type->data.inferred_array_type.sentinel != nullptr) { sentinel = astgen_node(ag, container_init_expr->type->data.inferred_array_type.sentinel, scope); if (sentinel == ag->codegen->invalid_inst_src) @@ -5675,12 +5675,12 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast sentinel = nullptr; } - IrInstSrc *elem_type = astgen_node(ag, + Stage1ZirInst *elem_type = astgen_node(ag, container_init_expr->type->data.inferred_array_type.child_type, scope); if (elem_type == ag->codegen->invalid_inst_src) return elem_type; size_t item_count = container_init_expr->entries.length; - IrInstSrc *item_count_inst = ir_build_const_usize(ag, scope, node, item_count); + Stage1ZirInst *item_count_inst = ir_build_const_usize(ag, scope, node, item_count); container_type = ir_build_array_type(ag, scope, node, item_count_inst, sentinel, elem_type); } else { container_type = astgen_node(ag, container_init_expr->type, scope); @@ -5702,11 +5702,11 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast switch (kind) { case ContainerInitKindStruct: { - IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc, + Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc, nullptr); size_t field_count = container_init_expr->entries.length; - IrInstSrcContainerInitFieldsField *fields = heap::c_allocator.allocate(field_count); + Stage1ZirInstContainerInitFieldsField *fields = heap::c_allocator.allocate(field_count); for (size_t i = 0; i < field_count; i += 1) { AstNode *entry_node = container_init_expr->entries.at(i); assert(entry_node->type == NodeTypeStructValueField); @@ -5714,7 +5714,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast Buf *name = entry_node->data.struct_val_field.name; AstNode *expr_node = entry_node->data.struct_val_field.expr; - IrInstSrc *field_ptr = ir_build_field_ptr(ag, scope, entry_node, container_ptr, name, true); + Stage1ZirInst *field_ptr = ir_build_field_ptr(ag, scope, entry_node, container_ptr, name, true); ResultLocInstruction *result_loc_inst = heap::c_allocator.create(); result_loc_inst->base.id = ResultLocIdInstruction; result_loc_inst->base.source_instruction = field_ptr; @@ -5722,7 +5722,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast ir_ref_instruction(field_ptr, ag->current_basic_block); ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base); - IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone, + Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone, &result_loc_inst->base); if (expr_value == ag->codegen->invalid_inst_src) return expr_value; @@ -5731,7 +5731,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast fields[i].source_node = entry_node; fields[i].result_loc = field_ptr; } - IrInstSrc *result = ir_build_container_init_fields(ag, scope, node, field_count, + Stage1ZirInst *result = ir_build_container_init_fields(ag, scope, node, field_count, fields, container_ptr); if (result_loc_cast != nullptr) { @@ -5742,15 +5742,15 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast case ContainerInitKindArray: { size_t item_count = container_init_expr->entries.length; - IrInstSrc *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc, + Stage1ZirInst *container_ptr = ir_build_resolve_result(ag, scope, node, child_result_loc, nullptr); - IrInstSrc **result_locs = heap::c_allocator.allocate(item_count); + Stage1ZirInst **result_locs = heap::c_allocator.allocate(item_count); for (size_t i = 0; i < item_count; i += 1) { AstNode *expr_node = container_init_expr->entries.at(i); - IrInstSrc *elem_index = ir_build_const_usize(ag, scope, expr_node, i); - IrInstSrc *elem_ptr = ir_build_elem_ptr(ag, scope, expr_node, container_ptr, + Stage1ZirInst *elem_index = ir_build_const_usize(ag, scope, expr_node, i); + Stage1ZirInst *elem_ptr = ir_build_elem_ptr(ag, scope, expr_node, container_ptr, elem_index, false, PtrLenSingle, init_array_type_source_node); ResultLocInstruction *result_loc_inst = heap::c_allocator.create(); result_loc_inst->base.id = ResultLocIdInstruction; @@ -5759,14 +5759,14 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast ir_ref_instruction(elem_ptr, ag->current_basic_block); ir_build_reset_result(ag, scope, expr_node, &result_loc_inst->base); - IrInstSrc *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone, + Stage1ZirInst *expr_value = astgen_node_extra(ag, expr_node, scope, LValNone, &result_loc_inst->base); if (expr_value == ag->codegen->invalid_inst_src) return expr_value; result_locs[i] = elem_ptr; } - IrInstSrc *result = ir_build_container_init_list(ag, scope, node, item_count, + Stage1ZirInst *result = ir_build_container_init_list(ag, scope, node, item_count, result_locs, container_ptr, init_array_type_source_node); if (result_loc_cast != nullptr) { result = ir_build_implicit_cast(ag, scope, node, result, result_loc_cast); @@ -5777,7 +5777,7 @@ static IrInstSrc *astgen_container_init_expr(Stage1AstGen *ag, Scope *scope, Ast zig_unreachable(); } -static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca, ZigVar *var) { +static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, Stage1ZirInst *alloca, ZigVar *var) { ResultLocVar *result_loc_var = heap::c_allocator.create(); result_loc_var->base.id = ResultLocIdVar; result_loc_var->base.source_instruction = alloca; @@ -5789,7 +5789,7 @@ static ResultLocVar *ir_build_var_result_loc(Stage1AstGen *ag, IrInstSrc *alloca return result_loc_var; } -static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest_type, +static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, Stage1ZirInst *dest_type, ResultLoc *parent_result_loc) { ResultLocCast *result_loc_cast = heap::c_allocator.create(); @@ -5805,15 +5805,15 @@ static ResultLocCast *ir_build_cast_result_loc(Stage1AstGen *ag, IrInstSrc *dest } static void build_decl_var_and_init(Stage1AstGen *ag, Scope *scope, AstNode *source_node, ZigVar *var, - IrInstSrc *init, const char *name_hint, IrInstSrc *is_comptime) + Stage1ZirInst *init, const char *name_hint, Stage1ZirInst *is_comptime) { - IrInstSrc *alloca = ir_build_alloca_src(ag, scope, source_node, nullptr, name_hint, is_comptime); + Stage1ZirInst *alloca = ir_build_alloca_src(ag, scope, source_node, nullptr, name_hint, is_comptime); ResultLocVar *var_result_loc = ir_build_var_result_loc(ag, alloca, var); ir_build_end_expr(ag, scope, source_node, init, &var_result_loc->base); ir_build_var_decl_src(ag, scope, source_node, var, nullptr, alloca); } -static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeVariableDeclaration); AstNodeVariableDeclaration *variable_declaration = &node->data.variable_declaration; @@ -5826,7 +5826,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) // Used for the type expr and the align expr Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope); - IrInstSrc *type_instruction; + Stage1ZirInst *type_instruction; if (variable_declaration->type != nullptr) { type_instruction = astgen_node(ag, variable_declaration->type, comptime_scope); if (type_instruction == ag->codegen->invalid_inst_src) @@ -5840,10 +5840,10 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) bool is_extern = variable_declaration->is_extern; bool is_comptime_scalar = ir_should_inline(ag->exec, scope) || variable_declaration->is_comptime; - IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node, is_comptime_scalar); + Stage1ZirInst *is_comptime = ir_build_const_bool(ag, scope, node, is_comptime_scalar); ZigVar *var = ir_create_var(ag, node, scope, variable_declaration->symbol, is_const, is_const, is_shadowable, is_comptime); - // we detect IrInstSrcDeclVar in gen_block to make sure the next node + // we detect Stage1ZirInstDeclVar in gen_block to make sure the next node // is inside var->child_scope if (!is_extern && !variable_declaration->expr) { @@ -5852,7 +5852,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) return ag->codegen->invalid_inst_src; } - IrInstSrc *align_value = nullptr; + Stage1ZirInst *align_value = nullptr; if (variable_declaration->align_expr != nullptr) { align_value = astgen_node(ag, variable_declaration->align_expr, comptime_scope); if (align_value == ag->codegen->invalid_inst_src) @@ -5867,7 +5867,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) // Parser should ensure that this never happens assert(variable_declaration->threadlocal_tok == 0); - IrInstSrc *alloca = ir_build_alloca_src(ag, scope, node, align_value, + Stage1ZirInst *alloca = ir_build_alloca_src(ag, scope, node, align_value, buf_ptr(variable_declaration->symbol), is_comptime); // Create a result location for the initialization expression. @@ -5889,7 +5889,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) // so that the struct or enum from the init expression inherits the name. Buf *old_exec_name = ag->exec->name; ag->exec->name = variable_declaration->symbol; - IrInstSrc *init_value = astgen_node_extra(ag, variable_declaration->expr, init_scope, + Stage1ZirInst *init_value = astgen_node_extra(ag, variable_declaration->expr, init_scope, LValNone, init_result_loc); ag->exec->name = old_exec_name; @@ -5897,7 +5897,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) return ag->codegen->invalid_inst_src; if (result_loc_cast != nullptr) { - IrInstSrc *implicit_cast = ir_build_implicit_cast(ag, scope, init_value->source_node, + Stage1ZirInst *implicit_cast = ir_build_implicit_cast(ag, scope, init_value->source_node, init_value, result_loc_cast); ir_build_end_expr(ag, scope, node, implicit_cast, &result_loc_var->base); } @@ -5905,7 +5905,7 @@ static IrInstSrc *astgen_var_decl(Stage1AstGen *ag, Scope *scope, AstNode *node) return ir_build_var_decl_src(ag, scope, node, var, align_value, alloca); } -static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeWhileExpr); @@ -5921,7 +5921,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod Stage1ZirBasicBlock *else_block = else_node ? ir_create_basic_block(ag, scope, "WhileElse") : end_block; - IrInstSrc *is_comptime = ir_build_const_bool(ag, scope, node, + Stage1ZirInst *is_comptime = ir_build_const_bool(ag, scope, node, ir_should_inline(ag->exec, scope) || node->data.while_expr.is_inline); ir_build_br(ag, scope, node, cond_block, is_comptime); @@ -5943,15 +5943,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod payload_scope = subexpr_scope; } ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, payload_scope); - IrInstSrc *err_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope, + Stage1ZirInst *err_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope, LValPtr, nullptr); if (err_val_ptr == ag->codegen->invalid_inst_src) return err_val_ptr; - IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr, + Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node->data.while_expr.condition, err_val_ptr, true, false); Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block; - IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node); - IrInstSrc *cond_br_inst; + Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node); + Stage1ZirInst *cond_br_inst; if (!instr_is_unreachable(is_err)) { cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_err, else_block, body_block, is_comptime); @@ -5965,14 +5965,14 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod ir_set_cursor_at_end_and_append_block(ag, body_block); if (var_symbol) { - IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, &spill_scope->base, symbol_node, + Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, &spill_scope->base, symbol_node, err_val_ptr, false, false); - IrInstSrc *var_value = node->data.while_expr.var_is_ptr ? + Stage1ZirInst *var_value = node->data.while_expr.var_is_ptr ? payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr); build_decl_var_and_init(ag, payload_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime); } - ZigList incoming_values = {0}; + ZigList incoming_values = {0}; ZigList incoming_blocks = {0}; if (is_duplicate_label(ag->codegen, payload_scope, node, node->data.while_expr.name)) @@ -5991,7 +5991,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod // Note the body block of the loop is not the place that lval and result_loc are used - // it's actually in break statements, handled similarly to return statements. // That is why we set those values in loop_scope above and not in this astgen_node call. - IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base); + Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base); if (body_result == ag->codegen->invalid_inst_src) return body_result; @@ -6006,7 +6006,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod if (continue_expr_node) { ir_set_cursor_at_end_and_append_block(ag, continue_block); - IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, payload_scope); + Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, payload_scope); if (expr_result == ag->codegen->invalid_inst_src) return expr_result; if (!instr_is_unreachable(expr_result)) { @@ -6023,8 +6023,8 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod ZigVar *err_var = ir_create_var(ag, err_symbol_node, scope, err_symbol, true, false, false, is_comptime); Scope *err_scope = err_var->child_scope; - IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, err_symbol_node, err_val_ptr); - IrInstSrc *err_value = ir_build_load_ptr(ag, err_scope, err_symbol_node, err_ptr); + Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, err_symbol_node, err_val_ptr); + Stage1ZirInst *err_value = ir_build_load_ptr(ag, err_scope, err_symbol_node, err_ptr); build_decl_var_and_init(ag, err_scope, err_symbol_node, err_var, err_value, buf_ptr(err_symbol), is_comptime); if (peer_parent->peers.length != 0) { @@ -6032,7 +6032,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod } ResultLocPeer *peer_result = create_peer_result(peer_parent); peer_parent->peers.append(peer_result); - IrInstSrc *else_result = astgen_node_extra(ag, else_node, err_scope, lval, &peer_result->base); + Stage1ZirInst *else_result = astgen_node_extra(ag, else_node, err_scope, lval, &peer_result->base); if (else_result == ag->codegen->invalid_inst_src) return else_result; if (!instr_is_unreachable(else_result)) @@ -6050,7 +6050,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod peer_parent->peers.last()->next_bb = end_block; } - IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length, + Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length, incoming_blocks.items, incoming_values.items, peer_parent); return ir_expr_wrap(ag, scope, phi, result_loc); } else if (var_symbol != nullptr) { @@ -6063,15 +6063,15 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod true, false, false, is_comptime); Scope *child_scope = payload_var->child_scope; ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, child_scope); - IrInstSrc *maybe_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope, + Stage1ZirInst *maybe_val_ptr = astgen_node_extra(ag, node->data.while_expr.condition, subexpr_scope, LValPtr, nullptr); if (maybe_val_ptr == ag->codegen->invalid_inst_src) return maybe_val_ptr; - IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr); - IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val); + Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, scope, node->data.while_expr.condition, maybe_val_ptr); + Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, scope, node->data.while_expr.condition, maybe_val); Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block; - IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node); - IrInstSrc *cond_br_inst; + Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node); + Stage1ZirInst *cond_br_inst; if (!instr_is_unreachable(is_non_null)) { cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, is_non_null, body_block, else_block, is_comptime); @@ -6084,12 +6084,12 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod is_comptime); ir_set_cursor_at_end_and_append_block(ag, body_block); - IrInstSrc *payload_ptr = ir_build_optional_unwrap_ptr(ag, &spill_scope->base, symbol_node, maybe_val_ptr, false); - IrInstSrc *var_value = node->data.while_expr.var_is_ptr ? + Stage1ZirInst *payload_ptr = ir_build_optional_unwrap_ptr(ag, &spill_scope->base, symbol_node, maybe_val_ptr, false); + Stage1ZirInst *var_value = node->data.while_expr.var_is_ptr ? payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, symbol_node, payload_ptr); build_decl_var_and_init(ag, child_scope, symbol_node, payload_var, var_value, buf_ptr(var_symbol), is_comptime); - ZigList incoming_values = {0}; + ZigList incoming_values = {0}; ZigList incoming_blocks = {0}; if (is_duplicate_label(ag->codegen, child_scope, node, node->data.while_expr.name)) @@ -6108,7 +6108,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod // Note the body block of the loop is not the place that lval and result_loc are used - // it's actually in break statements, handled similarly to return statements. // That is why we set those values in loop_scope above and not in this astgen_node call. - IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base); + Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base); if (body_result == ag->codegen->invalid_inst_src) return body_result; @@ -6123,7 +6123,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod if (continue_expr_node) { ir_set_cursor_at_end_and_append_block(ag, continue_block); - IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, child_scope); + Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, child_scope); if (expr_result == ag->codegen->invalid_inst_src) return expr_result; if (!instr_is_unreachable(expr_result)) { @@ -6132,7 +6132,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod } } - IrInstSrc *else_result = nullptr; + Stage1ZirInst *else_result = nullptr; if (else_node) { ir_set_cursor_at_end_and_append_block(ag, else_block); @@ -6160,17 +6160,17 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod peer_parent->peers.last()->next_bb = end_block; } - IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length, + Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length, incoming_blocks.items, incoming_values.items, peer_parent); return ir_expr_wrap(ag, scope, phi, result_loc); } else { ir_set_cursor_at_end_and_append_block(ag, cond_block); - IrInstSrc *cond_val = astgen_node(ag, node->data.while_expr.condition, scope); + Stage1ZirInst *cond_val = astgen_node(ag, node->data.while_expr.condition, scope); if (cond_val == ag->codegen->invalid_inst_src) return cond_val; Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block; - IrInstSrc *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node); - IrInstSrc *cond_br_inst; + Stage1ZirInst *void_else_result = else_node ? nullptr : ir_build_const_void(ag, scope, node); + Stage1ZirInst *cond_br_inst; if (!instr_is_unreachable(cond_val)) { cond_br_inst = ir_build_cond_br(ag, scope, node->data.while_expr.condition, cond_val, body_block, else_block, is_comptime); @@ -6183,7 +6183,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod is_comptime); ir_set_cursor_at_end_and_append_block(ag, body_block); - ZigList incoming_values = {0}; + ZigList incoming_values = {0}; ZigList incoming_blocks = {0}; Scope *subexpr_scope = create_runtime_scope(ag->codegen, node, scope, is_comptime); @@ -6203,7 +6203,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod // Note the body block of the loop is not the place that lval and result_loc are used - // it's actually in break statements, handled similarly to return statements. // That is why we set those values in loop_scope above and not in this astgen_node call. - IrInstSrc *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base); + Stage1ZirInst *body_result = astgen_node(ag, node->data.while_expr.body, &loop_scope->base); if (body_result == ag->codegen->invalid_inst_src) return body_result; @@ -6218,7 +6218,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod if (continue_expr_node) { ir_set_cursor_at_end_and_append_block(ag, continue_block); - IrInstSrc *expr_result = astgen_node(ag, continue_expr_node, subexpr_scope); + Stage1ZirInst *expr_result = astgen_node(ag, continue_expr_node, subexpr_scope); if (expr_result == ag->codegen->invalid_inst_src) return expr_result; if (!instr_is_unreachable(expr_result)) { @@ -6227,7 +6227,7 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod } } - IrInstSrc *else_result = nullptr; + Stage1ZirInst *else_result = nullptr; if (else_node) { ir_set_cursor_at_end_and_append_block(ag, else_block); @@ -6256,13 +6256,13 @@ static IrInstSrc *astgen_while_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod peer_parent->peers.last()->next_bb = end_block; } - IrInstSrc *phi = ir_build_phi(ag, scope, node, incoming_blocks.length, + Stage1ZirInst *phi = ir_build_phi(ag, scope, node, incoming_blocks.length, incoming_blocks.items, incoming_values.items, peer_parent); return ir_expr_wrap(ag, scope, phi, result_loc); } } -static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeForExpr); @@ -6281,11 +6281,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode ScopeExpr *spill_scope = create_expr_scope(ag->codegen, node, parent_scope); - IrInstSrc *array_val_ptr = astgen_node_extra(ag, array_node, &spill_scope->base, LValPtr, nullptr); + Stage1ZirInst *array_val_ptr = astgen_node_extra(ag, array_node, &spill_scope->base, LValPtr, nullptr); if (array_val_ptr == ag->codegen->invalid_inst_src) return array_val_ptr; - IrInstSrc *is_comptime = ir_build_const_bool(ag, parent_scope, node, + Stage1ZirInst *is_comptime = ir_build_const_bool(ag, parent_scope, node, ir_should_inline(ag->exec, parent_scope) || node->data.for_expr.is_inline); AstNode *index_var_source_node; @@ -6302,12 +6302,12 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode index_var_name = "i"; } - IrInstSrc *zero = ir_build_const_usize(ag, parent_scope, node, 0); + Stage1ZirInst *zero = ir_build_const_usize(ag, parent_scope, node, 0); build_decl_var_and_init(ag, parent_scope, index_var_source_node, index_var, zero, index_var_name, is_comptime); parent_scope = index_var->child_scope; - IrInstSrc *one = ir_build_const_usize(ag, parent_scope, node, 1); - IrInstSrc *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var); + Stage1ZirInst *one = ir_build_const_usize(ag, parent_scope, node, 1); + Stage1ZirInst *index_ptr = ir_build_var_ptr(ag, parent_scope, node, index_var); Stage1ZirBasicBlock *cond_block = ir_create_basic_block(ag, parent_scope, "ForCond"); @@ -6317,36 +6317,36 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode Stage1ZirBasicBlock *continue_block = ir_create_basic_block(ag, parent_scope, "ForContinue"); Buf *len_field_name = buf_create_from_str("len"); - IrInstSrc *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false); - IrInstSrc *len_val = ir_build_load_ptr(ag, &spill_scope->base, node, len_ref); + Stage1ZirInst *len_ref = ir_build_field_ptr(ag, parent_scope, node, array_val_ptr, len_field_name, false); + Stage1ZirInst *len_val = ir_build_load_ptr(ag, &spill_scope->base, node, len_ref); ir_build_br(ag, parent_scope, node, cond_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, cond_block); - IrInstSrc *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr); - IrInstSrc *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false); + Stage1ZirInst *index_val = ir_build_load_ptr(ag, &spill_scope->base, node, index_ptr); + Stage1ZirInst *cond = ir_build_bin_op(ag, parent_scope, node, IrBinOpCmpLessThan, index_val, len_val, false); Stage1ZirBasicBlock *after_cond_block = ag->current_basic_block; - IrInstSrc *void_else_value = else_node ? nullptr : ir_build_const_void(ag, parent_scope, node); - IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, cond, + Stage1ZirInst *void_else_value = else_node ? nullptr : ir_build_const_void(ag, parent_scope, node); + Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, cond, body_block, else_block, is_comptime); ResultLocPeerParent *peer_parent = ir_build_result_peers(ag, cond_br_inst, end_block, result_loc, is_comptime); ir_set_cursor_at_end_and_append_block(ag, body_block); - IrInstSrc *elem_ptr = ir_build_elem_ptr(ag, &spill_scope->base, node, array_val_ptr, index_val, + Stage1ZirInst *elem_ptr = ir_build_elem_ptr(ag, &spill_scope->base, node, array_val_ptr, index_val, false, PtrLenSingle, nullptr); // TODO make it an error to write to element variable or i variable. Buf *elem_var_name = node_identifier_buf(elem_node); ZigVar *elem_var = ir_create_var(ag, elem_node, parent_scope, elem_var_name, true, false, false, is_comptime); Scope *child_scope = elem_var->child_scope; - IrInstSrc *elem_value = node->data.for_expr.elem_is_ptr ? + Stage1ZirInst *elem_value = node->data.for_expr.elem_is_ptr ? elem_ptr : ir_build_load_ptr(ag, &spill_scope->base, elem_node, elem_ptr); build_decl_var_and_init(ag, parent_scope, elem_node, elem_var, elem_value, buf_ptr(elem_var_name), is_comptime); if (is_duplicate_label(ag->codegen, child_scope, node, node->data.for_expr.name)) return ag->codegen->invalid_inst_src; - ZigList incoming_values = {0}; + ZigList incoming_values = {0}; ZigList incoming_blocks = {0}; ScopeLoop *loop_scope = create_loop_scope(ag->codegen, node, child_scope); loop_scope->break_block = end_block; @@ -6361,7 +6361,7 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode // Note the body block of the loop is not the place that lval and result_loc are used - // it's actually in break statements, handled similarly to return statements. // That is why we set those values in loop_scope above and not in this astgen_node call. - IrInstSrc *body_result = astgen_node(ag, body_node, &loop_scope->base); + Stage1ZirInst *body_result = astgen_node(ag, body_node, &loop_scope->base); if (body_result == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -6375,11 +6375,11 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode } ir_set_cursor_at_end_and_append_block(ag, continue_block); - IrInstSrc *new_index_val = ir_build_bin_op(ag, child_scope, node, IrBinOpAdd, index_val, one, false); + Stage1ZirInst *new_index_val = ir_build_bin_op(ag, child_scope, node, IrBinOpAdd, index_val, one, false); ir_build_store_ptr(ag, child_scope, node, index_ptr, new_index_val)->allow_write_through_const = true; ir_build_br(ag, child_scope, node, cond_block, is_comptime); - IrInstSrc *else_result = nullptr; + Stage1ZirInst *else_result = nullptr; if (else_node) { ir_set_cursor_at_end_and_append_block(ag, else_block); @@ -6408,17 +6408,17 @@ static IrInstSrc *astgen_for_expr(Stage1AstGen *ag, Scope *parent_scope, AstNode peer_parent->peers.last()->next_bb = end_block; } - IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, incoming_blocks.length, + Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, incoming_blocks.length, incoming_blocks.items, incoming_values.items, peer_parent); return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc); } -static IrInstSrc *astgen_bool_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_bool_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeBoolLiteral); return ir_build_const_bool(ag, scope, node, node->data.bool_literal.value); } -static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeEnumLiteral); // Currently, stage1 runs astgen for every comptime function call, // resulting the allocation here wasting memory. As a workaround until @@ -6431,7 +6431,7 @@ static IrInstSrc *astgen_enum_literal(Stage1AstGen *ag, Scope *scope, AstNode *n return ir_build_const_enum_literal(ag, scope, node, node->data.enum_literal.name); } -static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { Error err; assert(node->type == NodeTypeStringLiteral); @@ -6473,7 +6473,7 @@ static IrInstSrc *astgen_string_literal(Stage1AstGen *ag, Scope *scope, AstNode return ir_build_const_str_lit(ag, scope, node, str); } -static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeArrayType); AstNode *size_node = node->data.array_type.size; @@ -6486,7 +6486,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope); - IrInstSrc *sentinel; + Stage1ZirInst *sentinel; if (sentinel_expr != nullptr) { sentinel = astgen_node(ag, sentinel_expr, comptime_scope); if (sentinel == ag->codegen->invalid_inst_src) @@ -6513,17 +6513,17 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod return ag->codegen->invalid_inst_src; } - IrInstSrc *size_value = astgen_node(ag, size_node, comptime_scope); + Stage1ZirInst *size_value = astgen_node(ag, size_node, comptime_scope); if (size_value == ag->codegen->invalid_inst_src) return size_value; - IrInstSrc *child_type = astgen_node(ag, child_type_node, comptime_scope); + Stage1ZirInst *child_type = astgen_node(ag, child_type_node, comptime_scope); if (child_type == ag->codegen->invalid_inst_src) return child_type; return ir_build_array_type(ag, scope, node, size_value, sentinel, child_type); } else { - IrInstSrc *align_value; + Stage1ZirInst *align_value; if (align_expr != nullptr) { align_value = astgen_node(ag, align_expr, comptime_scope); if (align_value == ag->codegen->invalid_inst_src) @@ -6532,7 +6532,7 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod align_value = nullptr; } - IrInstSrc *child_type = astgen_node(ag, child_type_node, comptime_scope); + Stage1ZirInst *child_type = astgen_node(ag, child_type_node, comptime_scope); if (child_type == ag->codegen->invalid_inst_src) return child_type; @@ -6541,11 +6541,11 @@ static IrInstSrc *astgen_array_type(Stage1AstGen *ag, Scope *scope, AstNode *nod } } -static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeAnyFrameType); AstNode *payload_type_node = node->data.anyframe_type.payload_type; - IrInstSrc *payload_type_value = nullptr; + Stage1ZirInst *payload_type_value = nullptr; if (payload_type_node != nullptr) { payload_type_value = astgen_node(ag, payload_type_node, scope); @@ -6557,16 +6557,16 @@ static IrInstSrc *astgen_anyframe_type(Stage1AstGen *ag, Scope *scope, AstNode * return ir_build_anyframe_type(ag, scope, node, payload_type_value); } -static IrInstSrc *astgen_undefined_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_undefined_literal(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeUndefinedLiteral); return ir_build_const_undefined(ag, scope, node); } -static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeAsmExpr); AstNodeAsmExpr *asm_expr = &node->data.asm_expr; - IrInstSrc *asm_template = astgen_node(ag, asm_expr->asm_template, scope); + Stage1ZirInst *asm_template = astgen_node(ag, asm_expr->asm_template, scope); if (asm_template == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -6592,8 +6592,8 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) nullptr, 0, is_volatile, true); } - IrInstSrc **input_list = heap::c_allocator.allocate(asm_expr->input_list.length); - IrInstSrc **output_types = heap::c_allocator.allocate(asm_expr->output_list.length); + Stage1ZirInst **input_list = heap::c_allocator.allocate(asm_expr->input_list.length); + Stage1ZirInst **output_types = heap::c_allocator.allocate(asm_expr->output_list.length); ZigVar **output_vars = heap::c_allocator.allocate(asm_expr->output_list.length); size_t return_count = 0; if (!is_volatile && asm_expr->output_list.length == 0) { @@ -6606,7 +6606,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) if (asm_output->return_type) { return_count += 1; - IrInstSrc *return_type = astgen_node(ag, asm_output->return_type, scope); + Stage1ZirInst *return_type = astgen_node(ag, asm_output->return_type, scope); if (return_type == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; if (return_count > 1) { @@ -6640,7 +6640,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) } for (size_t i = 0; i < asm_expr->input_list.length; i += 1) { AsmInput *asm_input = asm_expr->input_list.at(i); - IrInstSrc *input_value = astgen_node(ag, asm_input->expr, scope); + Stage1ZirInst *input_value = astgen_node(ag, asm_input->expr, scope); if (input_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; @@ -6651,7 +6651,7 @@ static IrInstSrc *astgen_asm_expr(Stage1AstGen *ag, Scope *scope, AstNode *node) output_vars, return_count, is_volatile, false); } -static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeIfOptional); @@ -6665,24 +6665,24 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod ScopeExpr *spill_scope = create_expr_scope(ag->codegen, expr_node, scope); spill_scope->spill_harder = true; - IrInstSrc *maybe_val_ptr = astgen_node_extra(ag, expr_node, &spill_scope->base, LValPtr, nullptr); + Stage1ZirInst *maybe_val_ptr = astgen_node_extra(ag, expr_node, &spill_scope->base, LValPtr, nullptr); if (maybe_val_ptr == ag->codegen->invalid_inst_src) return maybe_val_ptr; - IrInstSrc *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr); - IrInstSrc *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val); + Stage1ZirInst *maybe_val = ir_build_load_ptr(ag, scope, node, maybe_val_ptr); + Stage1ZirInst *is_non_null = ir_build_test_non_null_src(ag, scope, node, maybe_val); Stage1ZirBasicBlock *then_block = ir_create_basic_block(ag, scope, "OptionalThen"); Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "OptionalElse"); Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "OptionalEndIf"); - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, scope)) { is_comptime = ir_build_const_bool(ag, scope, node, true); } else { is_comptime = ir_build_test_comptime(ag, scope, node, is_non_null); } - IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, is_non_null, + Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, is_non_null, then_block, else_block, is_comptime); ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block, @@ -6698,15 +6698,15 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod ZigVar *var = ir_create_var(ag, node, subexpr_scope, var_symbol, is_const, is_const, is_shadowable, is_comptime); - IrInstSrc *payload_ptr = ir_build_optional_unwrap_ptr(ag, subexpr_scope, node, maybe_val_ptr, false); - IrInstSrc *var_value = var_is_ptr ? + Stage1ZirInst *payload_ptr = ir_build_optional_unwrap_ptr(ag, subexpr_scope, node, maybe_val_ptr, false); + Stage1ZirInst *var_value = var_is_ptr ? payload_ptr : ir_build_load_ptr(ag, &spill_scope->base, node, payload_ptr); build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), is_comptime); var_scope = var->child_scope; } else { var_scope = subexpr_scope; } - IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval, + Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval, &peer_parent->peers.at(0)->base); if (then_expr_result == ag->codegen->invalid_inst_src) return then_expr_result; @@ -6715,7 +6715,7 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod ir_build_br(ag, scope, node, endif_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, else_block); - IrInstSrc *else_expr_result; + Stage1ZirInst *else_expr_result; if (else_node) { else_expr_result = astgen_node_extra(ag, else_node, subexpr_scope, lval, &peer_parent->peers.at(1)->base); if (else_expr_result == ag->codegen->invalid_inst_src) @@ -6729,18 +6729,18 @@ static IrInstSrc *astgen_if_optional_expr(Stage1AstGen *ag, Scope *scope, AstNod ir_build_br(ag, scope, node, endif_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, endif_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = then_expr_result; incoming_values[1] = else_expr_result; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); incoming_blocks[0] = after_then_block; incoming_blocks[1] = after_else_block; - IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent); + Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent); return ir_expr_wrap(ag, scope, phi, result_loc); } -static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeIfErrorExpr); @@ -6753,20 +6753,20 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no Buf *var_symbol = node->data.if_err_expr.var_symbol; Buf *err_symbol = node->data.if_err_expr.err_symbol; - IrInstSrc *err_val_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr); + Stage1ZirInst *err_val_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr); if (err_val_ptr == ag->codegen->invalid_inst_src) return err_val_ptr; - IrInstSrc *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr); - IrInstSrc *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false); + Stage1ZirInst *err_val = ir_build_load_ptr(ag, scope, node, err_val_ptr); + Stage1ZirInst *is_err = ir_build_test_err_src(ag, scope, node, err_val_ptr, true, false); Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, scope, "TryOk"); Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "TryElse"); Stage1ZirBasicBlock *endif_block = ir_create_basic_block(ag, scope, "TryEnd"); bool force_comptime = ir_should_inline(ag->exec, scope); - IrInstSrc *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err); - IrInstSrc *cond_br_inst = ir_build_cond_br(ag, scope, node, is_err, else_block, ok_block, is_comptime); + Stage1ZirInst *is_comptime = force_comptime ? ir_build_const_bool(ag, scope, node, true) : ir_build_test_comptime(ag, scope, node, is_err); + Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, scope, node, is_err, else_block, ok_block, is_comptime); ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, else_block, endif_block, result_loc, is_comptime); @@ -6777,19 +6777,19 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no Scope *var_scope; if (var_symbol) { bool is_shadowable = false; - IrInstSrc *var_is_comptime = force_comptime ? ir_build_const_bool(ag, subexpr_scope, node, true) : ir_build_test_comptime(ag, subexpr_scope, node, err_val); + Stage1ZirInst *var_is_comptime = force_comptime ? ir_build_const_bool(ag, subexpr_scope, node, true) : ir_build_test_comptime(ag, subexpr_scope, node, err_val); ZigVar *var = ir_create_var(ag, node, subexpr_scope, var_symbol, var_is_const, var_is_const, is_shadowable, var_is_comptime); - IrInstSrc *payload_ptr = ir_build_unwrap_err_payload_src(ag, subexpr_scope, node, err_val_ptr, false, false); - IrInstSrc *var_value = var_is_ptr ? + Stage1ZirInst *payload_ptr = ir_build_unwrap_err_payload_src(ag, subexpr_scope, node, err_val_ptr, false, false); + Stage1ZirInst *var_value = var_is_ptr ? payload_ptr : ir_build_load_ptr(ag, subexpr_scope, node, payload_ptr); build_decl_var_and_init(ag, subexpr_scope, node, var, var_value, buf_ptr(var_symbol), var_is_comptime); var_scope = var->child_scope; } else { var_scope = subexpr_scope; } - IrInstSrc *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval, + Stage1ZirInst *then_expr_result = astgen_node_extra(ag, then_node, var_scope, lval, &peer_parent->peers.at(0)->base); if (then_expr_result == ag->codegen->invalid_inst_src) return then_expr_result; @@ -6799,7 +6799,7 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no ir_set_cursor_at_end_and_append_block(ag, else_block); - IrInstSrc *else_expr_result; + Stage1ZirInst *else_expr_result; if (else_node) { Scope *err_var_scope; if (err_symbol) { @@ -6808,8 +6808,8 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no ZigVar *var = ir_create_var(ag, node, subexpr_scope, err_symbol, is_const, is_const, is_shadowable, is_comptime); - IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, subexpr_scope, node, err_val_ptr); - IrInstSrc *err_value = ir_build_load_ptr(ag, subexpr_scope, node, err_ptr); + Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, subexpr_scope, node, err_val_ptr); + Stage1ZirInst *err_value = ir_build_load_ptr(ag, subexpr_scope, node, err_ptr); build_decl_var_and_init(ag, subexpr_scope, node, var, err_value, buf_ptr(err_symbol), is_comptime); err_var_scope = var->child_scope; } else { @@ -6827,22 +6827,22 @@ static IrInstSrc *astgen_if_err_expr(Stage1AstGen *ag, Scope *scope, AstNode *no ir_build_br(ag, scope, node, endif_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, endif_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = then_expr_result; incoming_values[1] = else_expr_result; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); incoming_blocks[0] = after_then_block; incoming_blocks[1] = after_else_block; - IrInstSrc *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent); + Stage1ZirInst *phi = ir_build_phi(ag, scope, node, 2, incoming_blocks, incoming_values, peer_parent); return ir_expr_wrap(ag, scope, phi, result_loc); } static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *switch_node, AstNode *prong_node, - Stage1ZirBasicBlock *end_block, IrInstSrc *is_comptime, IrInstSrc *var_is_comptime, - IrInstSrc *target_value_ptr, IrInstSrc **prong_values, size_t prong_values_len, - ZigList *incoming_blocks, ZigList *incoming_values, - IrInstSrcSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc) + Stage1ZirBasicBlock *end_block, Stage1ZirInst *is_comptime, Stage1ZirInst *var_is_comptime, + Stage1ZirInst *target_value_ptr, Stage1ZirInst **prong_values, size_t prong_values_len, + ZigList *incoming_blocks, ZigList *incoming_values, + Stage1ZirInstSwitchElseVar **out_switch_else_var, LVal lval, ResultLoc *result_loc) { assert(switch_node->type == NodeTypeSwitchExpr); assert(prong_node->type == NodeTypeSwitchProng); @@ -6860,16 +6860,16 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw ZigVar *var = ir_create_var(ag, var_symbol_node, scope, var_name, is_const, is_const, is_shadowable, var_is_comptime); child_scope = var->child_scope; - IrInstSrc *var_value; + Stage1ZirInst *var_value; if (out_switch_else_var != nullptr) { - IrInstSrcSwitchElseVar *switch_else_var = ir_build_switch_else_var(ag, scope, var_symbol_node, + Stage1ZirInstSwitchElseVar *switch_else_var = ir_build_switch_else_var(ag, scope, var_symbol_node, target_value_ptr); *out_switch_else_var = switch_else_var; - IrInstSrc *payload_ptr = &switch_else_var->base; + Stage1ZirInst *payload_ptr = &switch_else_var->base; var_value = var_is_ptr ? payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr); } else if (prong_values != nullptr) { - IrInstSrc *payload_ptr = ir_build_switch_var(ag, scope, var_symbol_node, target_value_ptr, + Stage1ZirInst *payload_ptr = ir_build_switch_var(ag, scope, var_symbol_node, target_value_ptr, prong_values, prong_values_len); var_value = var_is_ptr ? payload_ptr : ir_build_load_ptr(ag, scope, var_symbol_node, payload_ptr); @@ -6882,7 +6882,7 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw child_scope = scope; } - IrInstSrc *expr_result = astgen_node_extra(ag, expr_node, child_scope, lval, result_loc); + Stage1ZirInst *expr_result = astgen_node_extra(ag, expr_node, child_scope, lval, result_loc); if (expr_result == ag->codegen->invalid_inst_src) return false; if (!instr_is_unreachable(expr_result)) @@ -6892,25 +6892,25 @@ static bool astgen_switch_prong_expr(Stage1AstGen *ag, Scope *scope, AstNode *sw return true; } -static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeSwitchExpr); AstNode *target_node = node->data.switch_expr.expr; - IrInstSrc *target_value_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr); + Stage1ZirInst *target_value_ptr = astgen_node_extra(ag, target_node, scope, LValPtr, nullptr); if (target_value_ptr == ag->codegen->invalid_inst_src) return target_value_ptr; - IrInstSrc *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr); + Stage1ZirInst *target_value = ir_build_switch_target(ag, scope, node, target_value_ptr); Stage1ZirBasicBlock *else_block = ir_create_basic_block(ag, scope, "SwitchElse"); Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, scope, "SwitchEnd"); size_t prong_count = node->data.switch_expr.prongs.length; - ZigList cases = {0}; + ZigList cases = {0}; - IrInstSrc *is_comptime; - IrInstSrc *var_is_comptime; + Stage1ZirInst *is_comptime; + Stage1ZirInst *var_is_comptime; if (ir_should_inline(ag->exec, scope)) { is_comptime = ir_build_const_bool(ag, scope, node, true); var_is_comptime = is_comptime; @@ -6919,11 +6919,11 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no var_is_comptime = ir_build_test_comptime(ag, scope, node, target_value_ptr); } - ZigList incoming_values = {0}; + ZigList incoming_values = {0}; ZigList incoming_blocks = {0}; - ZigList check_ranges = {0}; + ZigList check_ranges = {0}; - IrInstSrcSwitchElseVar *switch_else_var = nullptr; + Stage1ZirInstSwitchElseVar *switch_else_var = nullptr; ResultLocPeerParent *peer_parent = heap::c_allocator.create(); peer_parent->base.id = ResultLocIdPeerParent; @@ -6945,7 +6945,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no if (prong_node->data.switch_prong.any_items_are_range) { ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent); - IrInstSrc *ok_bit = nullptr; + Stage1ZirInst *ok_bit = nullptr; AstNode *last_item_node = nullptr; for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) { AstNode *item_node = prong_node->data.switch_prong.items.at(item_i); @@ -6954,23 +6954,23 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no AstNode *start_node = item_node->data.switch_range.start; AstNode *end_node = item_node->data.switch_range.end; - IrInstSrc *start_value = astgen_node(ag, start_node, comptime_scope); + Stage1ZirInst *start_value = astgen_node(ag, start_node, comptime_scope); if (start_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *end_value = astgen_node(ag, end_node, comptime_scope); + Stage1ZirInst *end_value = astgen_node(ag, end_node, comptime_scope); if (end_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one(); + Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one(); check_range->start = start_value; check_range->end = end_value; - IrInstSrc *lower_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpGreaterOrEq, + Stage1ZirInst *lower_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpGreaterOrEq, target_value, start_value, false); - IrInstSrc *upper_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpLessOrEq, + Stage1ZirInst *upper_range_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpLessOrEq, target_value, end_value, false); - IrInstSrc *both_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolAnd, + Stage1ZirInst *both_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolAnd, lower_range_ok, upper_range_ok, false); if (ok_bit) { ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, both_ok, ok_bit, false); @@ -6978,15 +6978,15 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no ok_bit = both_ok; } } else { - IrInstSrc *item_value = astgen_node(ag, item_node, comptime_scope); + Stage1ZirInst *item_value = astgen_node(ag, item_node, comptime_scope); if (item_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one(); + Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one(); check_range->start = item_value; check_range->end = item_value; - IrInstSrc *cmp_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpEq, + Stage1ZirInst *cmp_ok = ir_build_bin_op(ag, scope, item_node, IrBinOpCmpEq, item_value, target_value, false); if (ok_bit) { ok_bit = ir_build_bin_op(ag, scope, item_node, IrBinOpBoolOr, cmp_ok, ok_bit, false); @@ -7001,7 +7001,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no assert(ok_bit); assert(last_item_node); - IrInstSrc *br_inst = ir_build_cond_br(ag, scope, last_item_node, ok_bit, + Stage1ZirInst *br_inst = ir_build_cond_br(ag, scope, last_item_node, ok_bit, range_block_yes, range_block_no, is_comptime); if (peer_parent->base.source_instruction == nullptr) { peer_parent->base.source_instruction = br_inst; @@ -7087,21 +7087,21 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no ResultLocPeer *this_peer_result_loc = create_peer_result(peer_parent); Stage1ZirBasicBlock *prong_block = ir_create_basic_block(ag, scope, "SwitchProng"); - IrInstSrc **items = heap::c_allocator.allocate(prong_item_count); + Stage1ZirInst **items = heap::c_allocator.allocate(prong_item_count); for (size_t item_i = 0; item_i < prong_item_count; item_i += 1) { AstNode *item_node = prong_node->data.switch_prong.items.at(item_i); assert(item_node->type != NodeTypeSwitchRange); - IrInstSrc *item_value = astgen_node(ag, item_node, comptime_scope); + Stage1ZirInst *item_value = astgen_node(ag, item_node, comptime_scope); if (item_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrcCheckSwitchProngsRange *check_range = check_ranges.add_one(); + Stage1ZirInstCheckSwitchProngsRange *check_range = check_ranges.add_one(); check_range->start = item_value; check_range->end = item_value; - IrInstSrcSwitchBrCase *this_case = cases.add_one(); + Stage1ZirInstSwitchBrCase *this_case = cases.add_one(); this_case->value = item_value; this_case->block = prong_block; @@ -7125,14 +7125,14 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no } - IrInstSrc *switch_prongs_void = ir_build_check_switch_prongs(ag, scope, node, target_value, + Stage1ZirInst *switch_prongs_void = ir_build_check_switch_prongs(ag, scope, node, target_value, check_ranges.items, check_ranges.length, else_prong, underscore_prong != nullptr); - IrInstSrc *br_instruction; + Stage1ZirInst *br_instruction; if (cases.length == 0) { br_instruction = ir_build_br(ag, scope, node, else_block, is_comptime); } else { - IrInstSrcSwitchBr *switch_br = ir_build_switch_br_src(ag, scope, node, target_value, else_block, + Stage1ZirInstSwitchBr *switch_br = ir_build_switch_br_src(ag, scope, node, target_value, else_block, cases.length, cases.items, is_comptime, switch_prongs_void); if (switch_else_var != nullptr) { switch_else_var->switch_br = switch_br; @@ -7160,7 +7160,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no ir_set_cursor_at_end_and_append_block(ag, end_block); assert(incoming_blocks.length == incoming_values.length); - IrInstSrc *result_instruction; + Stage1ZirInst *result_instruction; if (incoming_blocks.length == 0) { result_instruction = ir_build_const_void(ag, scope, node); } else { @@ -7170,7 +7170,7 @@ static IrInstSrc *astgen_switch_expr(Stage1AstGen *ag, Scope *scope, AstNode *no return ir_lval_wrap(ag, scope, result_instruction, lval, result_loc); } -static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) { +static Stage1ZirInst *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) { assert(node->type == NodeTypeCompTime); Scope *child_scope = create_comptime_scope(ag->codegen, node, parent_scope); @@ -7178,7 +7178,7 @@ static IrInstSrc *astgen_comptime(Stage1AstGen *ag, Scope *parent_scope, AstNode return astgen_node_extra(ag, node->data.comptime_expr.expr, child_scope, lval, nullptr); } -static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) { +static Stage1ZirInst *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval) { assert(node->type == NodeTypeNoSuspend); Scope *child_scope = create_nosuspend_scope(ag->codegen, node, parent_scope); @@ -7186,15 +7186,15 @@ static IrInstSrc *astgen_nosuspend(Stage1AstGen *ag, Scope *parent_scope, AstNod return astgen_node_extra(ag, node->data.nosuspend_expr.expr, child_scope, lval, nullptr); } -static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, AstNode *node, ScopeBlock *block_scope) { - IrInstSrc *is_comptime; +static Stage1ZirInst *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, AstNode *node, ScopeBlock *block_scope) { + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, break_scope)) { is_comptime = ir_build_const_bool(ag, break_scope, node, true); } else { is_comptime = block_scope->is_comptime; } - IrInstSrc *result_value; + Stage1ZirInst *result_value; if (node->data.break_expr.expr) { ResultLocPeer *peer_result = create_peer_result(block_scope->peer_parent); block_scope->peer_parent->peers.append(peer_result); @@ -7216,7 +7216,7 @@ static IrInstSrc *astgen_return_from_block(Stage1AstGen *ag, Scope *break_scope, return ir_build_br(ag, break_scope, node, dest_block, is_comptime); } -static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *node) { +static Stage1ZirInst *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *node) { assert(node->type == NodeTypeBreak); // Search up the scope. We'll find one of these things first: @@ -7264,14 +7264,14 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no search_scope = search_scope->parent; } - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, break_scope)) { is_comptime = ir_build_const_bool(ag, break_scope, node, true); } else { is_comptime = loop_scope->is_comptime; } - IrInstSrc *result_value; + Stage1ZirInst *result_value; if (node->data.break_expr.expr) { ResultLocPeer *peer_result = create_peer_result(loop_scope->peer_parent); loop_scope->peer_parent->peers.append(peer_result); @@ -7293,7 +7293,7 @@ static IrInstSrc *astgen_break(Stage1AstGen *ag, Scope *break_scope, AstNode *no return ir_build_br(ag, break_scope, node, dest_block, is_comptime); } -static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNode *node) { +static Stage1ZirInst *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNode *node) { assert(node->type == NodeTypeContinue); // Search up the scope. We'll find one of these things first: @@ -7333,7 +7333,7 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo search_scope = search_scope->parent; } - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, continue_scope)) { is_comptime = ir_build_const_bool(ag, continue_scope, node, true); } else { @@ -7352,12 +7352,12 @@ static IrInstSrc *astgen_continue(Stage1AstGen *ag, Scope *continue_scope, AstNo return ir_build_br(ag, continue_scope, node, dest_block, is_comptime); } -static IrInstSrc *astgen_error_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_error_type(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeErrorType); return ir_build_const_type(ag, scope, node, ag->codegen->builtin_types.entry_global_error_set); } -static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { +static Stage1ZirInst *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { assert(node->type == NodeTypeDefer); ScopeDefer *defer_child_scope = create_defer_scope(ag->codegen, node, parent_scope); @@ -7369,7 +7369,7 @@ static IrInstSrc *astgen_defer(Stage1AstGen *ag, Scope *parent_scope, AstNode *n return ir_build_const_void(ag, parent_scope, node); } -static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { +static Stage1ZirInst *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeSliceExpr); AstNodeSliceExpr *slice_expr = &node->data.slice_expr; @@ -7378,15 +7378,15 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV AstNode *end_node = slice_expr->end; AstNode *sentinel_node = slice_expr->sentinel; - IrInstSrc *ptr_value = astgen_node_extra(ag, array_node, scope, LValPtr, nullptr); + Stage1ZirInst *ptr_value = astgen_node_extra(ag, array_node, scope, LValPtr, nullptr); if (ptr_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *start_value = astgen_node(ag, start_node, scope); + Stage1ZirInst *start_value = astgen_node(ag, start_node, scope); if (start_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *end_value; + Stage1ZirInst *end_value; if (end_node) { end_value = astgen_node(ag, end_node, scope); if (end_value == ag->codegen->invalid_inst_src) @@ -7395,7 +7395,7 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV end_value = nullptr; } - IrInstSrc *sentinel_value; + Stage1ZirInst *sentinel_value; if (sentinel_node) { sentinel_value = astgen_node(ag, sentinel_node, scope); if (sentinel_value == ag->codegen->invalid_inst_src) @@ -7404,12 +7404,12 @@ static IrInstSrc *astgen_slice(Stage1AstGen *ag, Scope *scope, AstNode *node, LV sentinel_value = nullptr; } - IrInstSrc *slice = ir_build_slice_src(ag, scope, node, ptr_value, start_value, end_value, + Stage1ZirInst *slice = ir_build_slice_src(ag, scope, node, ptr_value, start_value, end_value, sentinel_value, true, result_loc); return ir_lval_wrap(ag, scope, slice, lval, result_loc); } -static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeCatchExpr); @@ -7432,13 +7432,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n ScopeExpr *spill_scope = create_expr_scope(ag->codegen, op1_node, parent_scope); spill_scope->spill_harder = true; - IrInstSrc *err_union_ptr = astgen_node_extra(ag, op1_node, &spill_scope->base, LValPtr, nullptr); + Stage1ZirInst *err_union_ptr = astgen_node_extra(ag, op1_node, &spill_scope->base, LValPtr, nullptr); if (err_union_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *is_err = ir_build_test_err_src(ag, parent_scope, node, err_union_ptr, true, false); + Stage1ZirInst *is_err = ir_build_test_err_src(ag, parent_scope, node, err_union_ptr, true, false); - IrInstSrc *is_comptime; + Stage1ZirInst *is_comptime; if (ir_should_inline(ag->exec, parent_scope)) { is_comptime = ir_build_const_bool(ag, parent_scope, node, true); } else { @@ -7448,7 +7448,7 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n Stage1ZirBasicBlock *ok_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrOk"); Stage1ZirBasicBlock *err_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrError"); Stage1ZirBasicBlock *end_block = ir_create_basic_block(ag, parent_scope, "UnwrapErrEnd"); - IrInstSrc *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime); + Stage1ZirInst *cond_br_inst = ir_build_cond_br(ag, parent_scope, node, is_err, err_block, ok_block, is_comptime); ResultLocPeerParent *peer_parent = ir_build_binary_result_peers(ag, cond_br_inst, ok_block, end_block, result_loc, is_comptime); @@ -7464,13 +7464,13 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n ZigVar *var = ir_create_var(ag, node, subexpr_scope, var_name, is_const, is_const, is_shadowable, is_comptime); err_scope = var->child_scope; - IrInstSrc *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, node, err_union_ptr); - IrInstSrc *err_value = ir_build_load_ptr(ag, err_scope, var_node, err_ptr); + Stage1ZirInst *err_ptr = ir_build_unwrap_err_code_src(ag, err_scope, node, err_union_ptr); + Stage1ZirInst *err_value = ir_build_load_ptr(ag, err_scope, var_node, err_ptr); build_decl_var_and_init(ag, err_scope, var_node, var, err_value, buf_ptr(var_name), is_comptime); } else { err_scope = subexpr_scope; } - IrInstSrc *err_result = astgen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base); + Stage1ZirInst *err_result = astgen_node_extra(ag, op2_node, err_scope, LValNone, &peer_parent->peers.at(0)->base); if (err_result == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; Stage1ZirBasicBlock *after_err_block = ag->current_basic_block; @@ -7478,20 +7478,20 @@ static IrInstSrc *astgen_catch(Stage1AstGen *ag, Scope *parent_scope, AstNode *n ir_build_br(ag, parent_scope, node, end_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, ok_block); - IrInstSrc *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false); - IrInstSrc *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr); + Stage1ZirInst *unwrapped_ptr = ir_build_unwrap_err_payload_src(ag, parent_scope, node, err_union_ptr, false, false); + Stage1ZirInst *unwrapped_payload = ir_build_load_ptr(ag, parent_scope, node, unwrapped_ptr); ir_build_end_expr(ag, parent_scope, node, unwrapped_payload, &peer_parent->peers.at(1)->base); Stage1ZirBasicBlock *after_ok_block = ag->current_basic_block; ir_build_br(ag, parent_scope, node, end_block, is_comptime); ir_set_cursor_at_end_and_append_block(ag, end_block); - IrInstSrc **incoming_values = heap::c_allocator.allocate(2); + Stage1ZirInst **incoming_values = heap::c_allocator.allocate(2); incoming_values[0] = err_result; incoming_values[1] = unwrapped_payload; Stage1ZirBasicBlock **incoming_blocks = heap::c_allocator.allocate(2); incoming_blocks[0] = after_err_block; incoming_blocks[1] = after_ok_block; - IrInstSrc *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent); + Stage1ZirInst *phi = ir_build_phi(ag, parent_scope, node, 2, incoming_blocks, incoming_values, peer_parent); return ir_lval_wrap(ag, parent_scope, phi, lval, result_loc); } @@ -7540,7 +7540,7 @@ Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name } } -static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { +static Stage1ZirInst *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { assert(node->type == NodeTypeContainerDecl); ContainerKind kind = node->data.container_decl.kind; @@ -7569,7 +7569,7 @@ static IrInstSrc *astgen_container_decl(Stage1AstGen *ag, Scope *parent_scope, A return ir_build_const_type(ag, parent_scope, node, container_type); } -static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { +static Stage1ZirInst *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { assert(node->type == NodeTypeErrorSetDecl); uint32_t err_count = node->data.err_set_decl.decls.length; @@ -7620,11 +7620,11 @@ static IrInstSrc *astgen_err_set_decl(Stage1AstGen *ag, Scope *parent_scope, Ast return ir_build_const_type(ag, parent_scope, node, err_set_type); } -static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { +static Stage1ZirInst *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { assert(node->type == NodeTypeFnProto); size_t param_count = node->data.fn_proto.params.length; - IrInstSrc **param_types = heap::c_allocator.allocate(param_count); + Stage1ZirInst **param_types = heap::c_allocator.allocate(param_count); bool is_var_args = false; for (size_t i = 0; i < param_count; i += 1) { @@ -7635,7 +7635,7 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode } if (param_node->data.param_decl.anytype_token == 0) { AstNode *type_node = param_node->data.param_decl.type; - IrInstSrc *type_value = astgen_node(ag, type_node, parent_scope); + Stage1ZirInst *type_value = astgen_node(ag, type_node, parent_scope); if (type_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; param_types[i] = type_value; @@ -7644,21 +7644,21 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode } } - IrInstSrc *align_value = nullptr; + Stage1ZirInst *align_value = nullptr; if (node->data.fn_proto.align_expr != nullptr) { align_value = astgen_node(ag, node->data.fn_proto.align_expr, parent_scope); if (align_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; } - IrInstSrc *callconv_value = nullptr; + Stage1ZirInst *callconv_value = nullptr; if (node->data.fn_proto.callconv_expr != nullptr) { callconv_value = astgen_node(ag, node->data.fn_proto.callconv_expr, parent_scope); if (callconv_value == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; } - IrInstSrc *return_type; + Stage1ZirInst *return_type; if (node->data.fn_proto.return_type == nullptr) { return_type = ir_build_const_type(ag, parent_scope, node, ag->codegen->builtin_types.entry_void); } else { @@ -7670,17 +7670,17 @@ static IrInstSrc *astgen_fn_proto(Stage1AstGen *ag, Scope *parent_scope, AstNode return ir_build_fn_proto(ag, parent_scope, node, param_types, align_value, callconv_value, return_type, is_var_args); } -static IrInstSrc *astgen_resume(Stage1AstGen *ag, Scope *scope, AstNode *node) { +static Stage1ZirInst *astgen_resume(Stage1AstGen *ag, Scope *scope, AstNode *node) { assert(node->type == NodeTypeResume); - IrInstSrc *target_inst = astgen_node_extra(ag, node->data.resume_expr.expr, scope, LValPtr, nullptr); + Stage1ZirInst *target_inst = astgen_node_extra(ag, node->data.resume_expr.expr, scope, LValPtr, nullptr); if (target_inst == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; return ir_build_resume_src(ag, scope, node, target_inst); } -static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, +static Stage1ZirInst *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *node, LVal lval, ResultLoc *result_loc) { assert(node->type == NodeTypeAwaitExpr); @@ -7714,15 +7714,15 @@ static IrInstSrc *astgen_await_expr(Stage1AstGen *ag, Scope *scope, AstNode *nod return ag->codegen->invalid_inst_src; } - IrInstSrc *target_inst = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); + Stage1ZirInst *target_inst = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); if (target_inst == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *await_inst = ir_build_await_src(ag, scope, node, target_inst, result_loc, is_nosuspend); + Stage1ZirInst *await_inst = ir_build_await_src(ag, scope, node, target_inst, result_loc, is_nosuspend); return ir_lval_wrap(ag, scope, await_inst, lval, result_loc); } -static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { +static Stage1ZirInst *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode *node) { assert(node->type == NodeTypeSuspend); if (!ag->fn) { @@ -7744,10 +7744,10 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode return ag->codegen->invalid_inst_src; } - IrInstSrcSuspendBegin *begin = ir_build_suspend_begin_src(ag, parent_scope, node); + Stage1ZirInstSuspendBegin *begin = ir_build_suspend_begin_src(ag, parent_scope, node); ScopeSuspend *suspend_scope = create_suspend_scope(ag->codegen, node, parent_scope); Scope *child_scope = &suspend_scope->base; - IrInstSrc *susp_res = astgen_node(ag, node->data.suspend.block, child_scope); + Stage1ZirInst *susp_res = astgen_node(ag, node->data.suspend.block, child_scope); if (susp_res == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; ir_build_check_statement_is_void(ag, child_scope, node->data.suspend.block, susp_res); @@ -7755,7 +7755,7 @@ static IrInstSrc *astgen_suspend(Stage1AstGen *ag, Scope *parent_scope, AstNode return ir_build_suspend_finish_src(ag, parent_scope, node, begin); } -static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope, +static Stage1ZirInst *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval, ResultLoc *result_loc) { assert(scope); @@ -7804,13 +7804,13 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope, return astgen_return(ag, scope, node, lval, result_loc); case NodeTypeFieldAccessExpr: { - IrInstSrc *ptr_instruction = astgen_field_access(ag, scope, node); + Stage1ZirInst *ptr_instruction = astgen_field_access(ag, scope, node); if (ptr_instruction == ag->codegen->invalid_inst_src) return ptr_instruction; if (lval == LValPtr || lval == LValAssign) return ptr_instruction; - IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction); + Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, ptr_instruction); return ir_expr_wrap(ag, scope, load_ptr, result_loc); } case NodeTypePtrDeref: { @@ -7820,28 +7820,28 @@ static IrInstSrc *astgen_node_raw(Stage1AstGen *ag, AstNode *node, Scope *scope, if (child_lval == LValAssign) child_lval = LValPtr; - IrInstSrc *value = astgen_node_extra(ag, expr_node, scope, child_lval, nullptr); + Stage1ZirInst *value = astgen_node_extra(ag, expr_node, scope, child_lval, nullptr); if (value == ag->codegen->invalid_inst_src) return value; // We essentially just converted any lvalue from &(x.*) to (&x).*; // this inhibits checking that x is a pointer later, so we directly // record whether the pointer check is needed - IrInstSrc *un_op = ir_build_un_op_lval(ag, scope, node, IrUnOpDereference, value, lval, result_loc); + Stage1ZirInst *un_op = ir_build_un_op_lval(ag, scope, node, IrUnOpDereference, value, lval, result_loc); return ir_expr_wrap(ag, scope, un_op, result_loc); } case NodeTypeUnwrapOptional: { AstNode *expr_node = node->data.unwrap_optional.expr; - IrInstSrc *maybe_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); + Stage1ZirInst *maybe_ptr = astgen_node_extra(ag, expr_node, scope, LValPtr, nullptr); if (maybe_ptr == ag->codegen->invalid_inst_src) return ag->codegen->invalid_inst_src; - IrInstSrc *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, scope, node, maybe_ptr, true ); + Stage1ZirInst *unwrapped_ptr = ir_build_optional_unwrap_ptr(ag, scope, node, maybe_ptr, true ); if (lval == LValPtr || lval == LValAssign) return unwrapped_ptr; - IrInstSrc *load_ptr = ir_build_load_ptr(ag, scope, node, unwrapped_ptr); + Stage1ZirInst *load_ptr = ir_build_load_ptr(ag, scope, node, unwrapped_ptr); return ir_expr_wrap(ag, scope, load_ptr, result_loc); } case NodeTypeBoolLiteral: @@ -7915,7 +7915,7 @@ ResultLoc *no_result_loc(void) { return &result_loc_none->base; } -static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval, +static Stage1ZirInst *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scope, LVal lval, ResultLoc *result_loc) { if (lval == LValAssign) { @@ -8023,7 +8023,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop } else { child_scope = &create_expr_scope(ag->codegen, node, scope)->base; } - IrInstSrc *result = astgen_node_raw(ag, node, child_scope, lval, result_loc); + Stage1ZirInst *result = astgen_node_raw(ag, node, child_scope, lval, result_loc); if (result == ag->codegen->invalid_inst_src) { if (ag->exec->first_err_trace_msg == nullptr) { ag->exec->first_err_trace_msg = ag->codegen->trace_err; @@ -8032,7 +8032,7 @@ static IrInstSrc *astgen_node_extra(Stage1AstGen *ag, AstNode *node, Scope *scop return result; } -static IrInstSrc *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope) { +static Stage1ZirInst *astgen_node(Stage1AstGen *ag, AstNode *node, Scope *scope) { return astgen_node_extra(ag, node, scope, LValNone, nullptr); } @@ -8055,7 +8055,7 @@ bool stage1_astgen(CodeGen *codegen, AstNode *node, Scope *scope, Stage1Zir *sta // Entry block gets a reference because we enter it to begin. ir_ref_bb(ag->current_basic_block); - IrInstSrc *result = astgen_node_extra(ag, node, scope, LValNone, nullptr); + Stage1ZirInst *result = astgen_node_extra(ag, node, scope, LValNone, nullptr); if (result == ag->codegen->invalid_inst_src) return false; @@ -8113,8 +8113,8 @@ void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *e ir_add_call_stack_errors_gen(codegen, exec->parent_exec, err_msg, limit - 1); } -void IrInstSrc::src() { - IrInstSrc *inst = this; +void Stage1ZirInst::src() { + Stage1ZirInst *inst = this; if (inst->source_node != nullptr) { inst->source_node->src(); } else { diff --git a/src/stage1/astgen.hpp b/src/stage1/astgen.hpp index eb93fd5b73..d4bb6923a1 100644 --- a/src/stage1/astgen.hpp +++ b/src/stage1/astgen.hpp @@ -14,10 +14,10 @@ bool stage1_astgen(CodeGen *g, AstNode *node, Scope *scope, Stage1Zir *stage1_zi ZigFn *fn, bool in_c_import_scope); bool stage1_astgen_fn(CodeGen *g, ZigFn *fn_entry); -bool ir_inst_src_has_side_effects(IrInstSrc *inst); +bool ir_inst_src_has_side_effects(Stage1ZirInst *inst); ZigVar *create_local_var(CodeGen *codegen, AstNode *node, Scope *parent_scope, - Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, IrInstSrc *is_comptime, + Buf *name, bool src_is_const, bool gen_is_const, bool is_shadowable, Stage1ZirInst *is_comptime, bool skip_name_check); ResultLoc *no_result_loc(void); @@ -28,7 +28,7 @@ AstNode *ast_field_to_symbol_node(AstNode *err_set_field_node); void ir_add_call_stack_errors_gen(CodeGen *codegen, Stage1Air *exec, ErrorMsg *err_msg, int limit); -void destroy_instruction_src(IrInstSrc *inst); +void destroy_instruction_src(Stage1ZirInst *inst); bool ir_should_inline(Stage1Zir *exec, Scope *scope); Buf *get_anon_type_name(CodeGen *codegen, Stage1Zir *exec, const char *kind_name, diff --git a/src/stage1/codegen.cpp b/src/stage1/codegen.cpp index 213d8d647a..9ab0e269a2 100644 --- a/src/stage1/codegen.cpp +++ b/src/stage1/codegen.cpp @@ -84,7 +84,7 @@ static void generate_error_name_table(CodeGen *g); static bool value_is_all_undef(CodeGen *g, ZigValue *const_val); static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, LLVMValueRef ptr); static LLVMValueRef build_alloca(CodeGen *g, ZigType *type_entry, const char *name, uint32_t alignment); -static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr, +static LLVMValueRef gen_await_early_return(CodeGen *g, Stage1AirInst *source_instr, LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type, LLVMValueRef result_loc, bool non_async); @@ -906,14 +906,14 @@ static LLVMValueRef get_handle_value(CodeGen *g, LLVMValueRef ptr, ZigType *type } } -static void ir_assert_impl(bool ok, IrInstGen *source_instruction, const char *file, unsigned int line) { +static void ir_assert_impl(bool ok, Stage1AirInst *source_instruction, const char *file, unsigned int line) { if (ok) return; src_assert_impl(ok, source_instruction->source_node, file, line); } #define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__) -static bool ir_want_fast_math(CodeGen *g, IrInstGen *instruction) { +static bool ir_want_fast_math(CodeGen *g, Stage1AirInst *instruction) { // TODO memoize Scope *scope = instruction->scope; while (scope) { @@ -950,7 +950,7 @@ static bool ir_want_runtime_safety_scope(CodeGen *g, Scope *scope) { g->build_mode != BuildModeSmallRelease); } -static bool ir_want_runtime_safety(CodeGen *g, IrInstGen *instruction) { +static bool ir_want_runtime_safety(CodeGen *g, Stage1AirInst *instruction) { return ir_want_runtime_safety_scope(g, instruction->scope); } @@ -1077,7 +1077,7 @@ static void gen_assertion_scope(CodeGen *g, PanicMsgId msg_id, Scope *source_sco } } -static void gen_assertion(CodeGen *g, PanicMsgId msg_id, IrInstGen *source_instruction) { +static void gen_assertion(CodeGen *g, PanicMsgId msg_id, Stage1AirInst *source_instruction) { return gen_assertion_scope(g, msg_id, source_instruction->scope); } @@ -1816,7 +1816,7 @@ static void gen_var_debug_decl(CodeGen *g, ZigVar *var) { LLVMGetInsertBlock(g->builder)); } -static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) { +static LLVMValueRef ir_llvm_value(CodeGen *g, Stage1AirInst *instruction) { Error err; bool value_has_bits; @@ -1827,8 +1827,8 @@ static LLVMValueRef ir_llvm_value(CodeGen *g, IrInstGen *instruction) { return nullptr; if (!instruction->llvm_value) { - if (instruction->id == IrInstGenIdAwait) { - IrInstGenAwait *await = reinterpret_cast(instruction); + if (instruction->id == Stage1AirInstIdAwait) { + Stage1AirInstAwait *await = reinterpret_cast(instruction); if (await->result_loc != nullptr) { return get_handle_value(g, ir_llvm_value(g, await->result_loc), await->result_loc->value->type->data.pointer.child_type, await->result_loc->value->type); @@ -1921,7 +1921,7 @@ static bool iter_function_params_c_abi(CodeGen *g, ZigType *fn_type, FnWalk *fn_ case FnWalkIdCall: { if (src_i >= fn_walk->data.call.inst->arg_count) return false; - IrInstGen *arg = fn_walk->data.call.inst->args[src_i]; + Stage1AirInst *arg = fn_walk->data.call.inst->args[src_i]; ty = arg->value->type; source_node = arg->source_node; val = ir_llvm_value(g, arg); @@ -2228,10 +2228,10 @@ void walk_function_params(CodeGen *g, ZigType *fn_type, FnWalk *fn_walk) { return; } if (fn_walk->id == FnWalkIdCall) { - IrInstGenCall *instruction = fn_walk->data.call.inst; + Stage1AirInstCall *instruction = fn_walk->data.call.inst; bool is_var_args = fn_walk->data.call.is_var_args; for (size_t call_i = 0; call_i < instruction->arg_count; call_i += 1) { - IrInstGen *param_instruction = instruction->args[call_i]; + Stage1AirInst *param_instruction = instruction->args[call_i]; ZigType *param_type = param_instruction->value->type; if (is_var_args || type_has_bits(g, param_type)) { LLVMValueRef param_value = ir_llvm_value(g, param_instruction); @@ -2445,7 +2445,7 @@ static LLVMValueRef get_merge_err_ret_traces_fn_val(CodeGen *g) { } static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executable, - IrInstGenSaveErrRetAddr *save_err_ret_addr_instruction) + Stage1AirInstSaveErrRetAddr *save_err_ret_addr_instruction) { assert(g->have_err_ret_tracing); @@ -2466,7 +2466,7 @@ static LLVMValueRef ir_render_save_err_ret_addr(CodeGen *g, Stage1Air *executabl return nullptr; } -static void gen_assert_resume_id(CodeGen *g, IrInstGen *source_instr, ResumeId resume_id, PanicMsgId msg_id, +static void gen_assert_resume_id(CodeGen *g, Stage1AirInst *source_instr, ResumeId resume_id, PanicMsgId msg_id, LLVMBasicBlockRef end_bb) { LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type; @@ -2543,7 +2543,7 @@ static LLVMValueRef gen_maybe_atomic_op(CodeGen *g, LLVMAtomicRMWBinOp op, LLVMV } } -static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) { +static void gen_async_return(CodeGen *g, Stage1AirInstReturn *instruction) { LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type; ZigType *operand_type = (instruction->operand != nullptr) ? instruction->operand->value->type : nullptr; @@ -2637,7 +2637,7 @@ static void gen_async_return(CodeGen *g, IrInstGenReturn *instruction) { LLVMBuildRetVoid(g->builder); } -static LLVMValueRef ir_render_return(CodeGen *g, Stage1Air *executable, IrInstGenReturn *instruction) { +static LLVMValueRef ir_render_return(CodeGen *g, Stage1Air *executable, Stage1AirInstReturn *instruction) { if (fn_is_async(g->cur_fn)) { gen_async_return(g, instruction); return nullptr; @@ -3063,11 +3063,11 @@ static void gen_shift_rhs_check(CodeGen *g, ZigType *lhs_type, ZigType *rhs_type } static LLVMValueRef ir_render_bin_op(CodeGen *g, Stage1Air *executable, - IrInstGenBinOp *bin_op_instruction) + Stage1AirInstBinOp *bin_op_instruction) { IrBinOp op_id = bin_op_instruction->op_id; - IrInstGen *op1 = bin_op_instruction->op1; - IrInstGen *op2 = bin_op_instruction->op2; + Stage1AirInst *op1 = bin_op_instruction->op1; + Stage1AirInst *op2 = bin_op_instruction->op2; ZigType *operand_type = op1->value->type; ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ? operand_type->data.vector.elem_type : operand_type; @@ -3285,7 +3285,7 @@ static void add_error_range_check(CodeGen *g, ZigType *err_set_type, ZigType *in } static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable, - IrInstGenCast *cast_instruction) + Stage1AirInstCast *cast_instruction) { Error err; ZigType *actual_type = cast_instruction->value->value->type; @@ -3369,7 +3369,7 @@ static LLVMValueRef ir_render_cast(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *executable, - IrInstGenPtrOfArrayToSlice *instruction) + Stage1AirInstPtrOfArrayToSlice *instruction) { ZigType *actual_type = instruction->operand->value->type; ZigType *slice_type = instruction->base.value->type; @@ -3406,7 +3406,7 @@ static LLVMValueRef ir_render_ptr_of_array_to_slice(CodeGen *g, Stage1Air *execu } static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable, - IrInstGenPtrCast *instruction) + Stage1AirInstPtrCast *instruction) { ZigType *wanted_type = instruction->base.value->type; if (!type_has_bits(g, wanted_type)) { @@ -3432,7 +3432,7 @@ static LLVMValueRef ir_render_ptr_cast(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable, - IrInstGenBitCast *instruction) + Stage1AirInstBitCast *instruction) { ZigType *wanted_type = instruction->base.value->type; ZigType *actual_type = instruction->operand->value->type; @@ -3460,7 +3460,7 @@ static LLVMValueRef ir_render_bit_cast(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable, - IrInstGenWidenOrShorten *instruction) + Stage1AirInstWidenOrShorten *instruction) { ZigType *actual_type = instruction->target->value->type; // TODO instead of this logic, use the Noop instruction to change the type from @@ -3476,7 +3476,7 @@ static LLVMValueRef ir_render_widen_or_shorten(CodeGen *g, Stage1Air *executable instruction->base.value->type, target_val); } -static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrInstGenIntToPtr *instruction) { +static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToPtr *instruction) { ZigType *wanted_type = instruction->base.value->type; LLVMValueRef target_val = ir_llvm_value(g, instruction->target); const uint32_t align_bytes = get_ptr_align(g, wanted_type); @@ -3514,13 +3514,13 @@ static LLVMValueRef ir_render_int_to_ptr(CodeGen *g, Stage1Air *executable, IrIn return LLVMBuildIntToPtr(g->builder, target_val, get_llvm_type(g, wanted_type), ""); } -static LLVMValueRef ir_render_ptr_to_int(CodeGen *g, Stage1Air *executable, IrInstGenPtrToInt *instruction) { +static LLVMValueRef ir_render_ptr_to_int(CodeGen *g, Stage1Air *executable, Stage1AirInstPtrToInt *instruction) { ZigType *wanted_type = instruction->base.value->type; LLVMValueRef target_val = ir_llvm_value(g, instruction->target); return LLVMBuildPtrToInt(g->builder, target_val, get_llvm_type(g, wanted_type), ""); } -static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrInstGenIntToEnum *instruction) { +static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToEnum *instruction) { ZigType *wanted_type = instruction->base.value->type; assert(wanted_type->id == ZigTypeIdEnum); ZigType *tag_int_type = wanted_type->data.enumeration.tag_int_type; @@ -3560,7 +3560,7 @@ static LLVMValueRef ir_render_int_to_enum(CodeGen *g, Stage1Air *executable, IrI return tag_int_value; } -static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrInstGenIntToErr *instruction) { +static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, Stage1AirInstIntToErr *instruction) { ZigType *wanted_type = instruction->base.value->type; assert(wanted_type->id == ZigTypeIdErrorSet); @@ -3577,7 +3577,7 @@ static LLVMValueRef ir_render_int_to_err(CodeGen *g, Stage1Air *executable, IrIn return gen_widen_or_shorten(g, false, actual_type, g->err_tag_type, target_val); } -static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrInstGenErrToInt *instruction) { +static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, Stage1AirInstErrToInt *instruction) { ZigType *wanted_type = instruction->base.value->type; assert(wanted_type->id == ZigTypeIdInt); assert(!wanted_type->data.integral.is_signed); @@ -3604,7 +3604,7 @@ static LLVMValueRef ir_render_err_to_int(CodeGen *g, Stage1Air *executable, IrIn } static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable, - IrInstGenUnreachable *unreachable_instruction) + Stage1AirInstUnreachable *unreachable_instruction) { if (ir_want_runtime_safety(g, &unreachable_instruction->base)) { gen_safety_crash(g, PanicMsgIdUnreachable); @@ -3615,7 +3615,7 @@ static LLVMValueRef ir_render_unreachable(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable, - IrInstGenCondBr *cond_br_instruction) + Stage1AirInstCondBr *cond_br_instruction) { LLVMBuildCondBr(g->builder, ir_llvm_value(g, cond_br_instruction->condition), @@ -3624,19 +3624,19 @@ static LLVMValueRef ir_render_cond_br(CodeGen *g, Stage1Air *executable, return nullptr; } -static LLVMValueRef ir_render_br(CodeGen *g, Stage1Air *executable, IrInstGenBr *br_instruction) { +static LLVMValueRef ir_render_br(CodeGen *g, Stage1Air *executable, Stage1AirInstBr *br_instruction) { LLVMBuildBr(g->builder, br_instruction->dest_block->llvm_block); return nullptr; } static LLVMValueRef ir_render_binary_not(CodeGen *g, Stage1Air *executable, - IrInstGenBinaryNot *inst) + Stage1AirInstBinaryNot *inst) { LLVMValueRef operand = ir_llvm_value(g, inst->operand); return LLVMBuildNot(g->builder, operand, ""); } -static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *operand, bool wrapping) { +static LLVMValueRef ir_gen_negation(CodeGen *g, Stage1AirInst *inst, Stage1AirInst *operand, bool wrapping) { LLVMValueRef llvm_operand = ir_llvm_value(g, operand); ZigType *operand_type = operand->value->type; ZigType *scalar_type = (operand_type->id == ZigTypeIdVector) ? @@ -3662,12 +3662,12 @@ static LLVMValueRef ir_gen_negation(CodeGen *g, IrInstGen *inst, IrInstGen *oper } static LLVMValueRef ir_render_negation(CodeGen *g, Stage1Air *executable, - IrInstGenNegation *inst) + Stage1AirInstNegation *inst) { return ir_gen_negation(g, &inst->base, inst->operand, inst->wrapping); } -static LLVMValueRef ir_render_bool_not(CodeGen *g, Stage1Air *executable, IrInstGenBoolNot *instruction) { +static LLVMValueRef ir_render_bool_not(CodeGen *g, Stage1Air *executable, Stage1AirInstBoolNot *instruction) { LLVMValueRef value = ir_llvm_value(g, instruction->value); LLVMValueRef zero = LLVMConstNull(LLVMTypeOf(value)); return LLVMBuildICmp(g->builder, LLVMIntEQ, value, zero, ""); @@ -3681,7 +3681,7 @@ static void render_decl_var(CodeGen *g, ZigVar *var) { gen_var_debug_decl(g, var); } -static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInstGenDeclVar *instruction) { +static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, Stage1AirInstDeclVar *instruction) { instruction->var->ptr_instruction = instruction->var_ptr; instruction->var->did_the_decl_codegen = true; render_decl_var(g, instruction->var); @@ -3689,7 +3689,7 @@ static LLVMValueRef ir_render_decl_var(CodeGen *g, Stage1Air *executable, IrInst } static LLVMValueRef ir_render_load_ptr(CodeGen *g, Stage1Air *executable, - IrInstGenLoadPtr *instruction) + Stage1AirInstLoadPtr *instruction) { ZigType *child_type = instruction->base.value->type; if (!type_has_bits(g, child_type)) @@ -3896,7 +3896,7 @@ static void gen_undef_init(CodeGen *g, ZigType *ptr_type, ZigType *value_type, L gen_assign_raw(g, ptr, ptr_type, zero); } -static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrInstGenStorePtr *instruction) { +static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstStorePtr *instruction) { Error err; ZigType *ptr_type = instruction->ptr->value->type; @@ -3929,7 +3929,7 @@ static LLVMValueRef ir_render_store_ptr(CodeGen *g, Stage1Air *executable, IrIns } static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executable, - IrInstGenVectorStoreElem *instruction) + Stage1AirInstVectorStoreElem *instruction) { LLVMValueRef vector_ptr = ir_llvm_value(g, instruction->vector_ptr); LLVMValueRef index = ir_llvm_value(g, instruction->index); @@ -3941,7 +3941,7 @@ static LLVMValueRef ir_render_vector_store_elem(CodeGen *g, Stage1Air *executabl return nullptr; } -static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstGenVarPtr *instruction) { +static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstVarPtr *instruction) { Error err; ZigType *ptr_type = instruction->base.value->type; @@ -3969,7 +3969,7 @@ static LLVMValueRef ir_render_var_ptr(CodeGen *g, Stage1Air *executable, IrInstG } static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable, - IrInstGenReturnPtr *instruction) + Stage1AirInstReturnPtr *instruction) { if (!type_has_bits(g, instruction->base.value->type)) return nullptr; @@ -3977,7 +3977,7 @@ static LLVMValueRef ir_render_return_ptr(CodeGen *g, Stage1Air *executable, return g->cur_ret_ptr; } -static LLVMValueRef ir_render_elem_ptr(CodeGen *g, Stage1Air *executable, IrInstGenElemPtr *instruction) { +static LLVMValueRef ir_render_elem_ptr(CodeGen *g, Stage1Air *executable, Stage1AirInstElemPtr *instruction) { LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->array_ptr); ZigType *array_ptr_type = instruction->array_ptr->value->type; assert(array_ptr_type->id == ZigTypeIdPointer); @@ -4152,7 +4152,7 @@ static void render_async_spills(CodeGen *g) { ZigType *frame_type = g->cur_fn->frame_type->data.frame.locals_struct; for (size_t alloca_i = 0; alloca_i < g->cur_fn->alloca_gen_list.length; alloca_i += 1) { - IrInstGenAlloca *instruction = g->cur_fn->alloca_gen_list.at(alloca_i); + Stage1AirInstAlloca *instruction = g->cur_fn->alloca_gen_list.at(alloca_i); if (instruction->field_index == SIZE_MAX) continue; @@ -4229,7 +4229,7 @@ static void gen_init_stack_trace(CodeGen *g, LLVMValueRef trace_field_ptr, LLVMV LLVMBuildStore(g->builder, LLVMConstInt(usize_type_ref, stack_trace_ptr_count, false), addrs_len_ptr); } -static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenCall *instruction) { +static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, Stage1AirInstCall *instruction) { Error err; LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type; @@ -4579,7 +4579,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC return nullptr; if (result_loc != nullptr) { - if (instruction->result_loc->id == IrInstGenIdReturnPtr) { + if (instruction->result_loc->id == Stage1AirInstIdReturnPtr) { instruction->base.spill = nullptr; return g->cur_ret_ptr; } else { @@ -4650,7 +4650,7 @@ static LLVMValueRef ir_render_call(CodeGen *g, Stage1Air *executable, IrInstGenC } static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable, - IrInstGenStructFieldPtr *instruction) + Stage1AirInstStructFieldPtr *instruction) { Error err; @@ -4701,7 +4701,7 @@ static LLVMValueRef ir_render_struct_field_ptr(CodeGen *g, Stage1Air *executable } static LLVMValueRef ir_render_union_field_ptr(CodeGen *g, Stage1Air *executable, - IrInstGenUnionFieldPtr *instruction) + Stage1AirInstUnionFieldPtr *instruction) { if (instruction->base.value->special != ConstValSpecialRuntime) return nullptr; @@ -4800,7 +4800,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_ return SIZE_MAX; } -static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstGenAsm *instruction) { +static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, Stage1AirInstAsm *instruction) { AstNode *asm_node = instruction->base.source_node; assert(asm_node->type == NodeTypeAsmExpr); AstNodeAsmExpr *asm_expr = &asm_node->data.asm_expr; @@ -4885,7 +4885,7 @@ static LLVMValueRef ir_render_asm_gen(CodeGen *g, Stage1Air *executable, IrInstG for (size_t i = 0; i < asm_expr->input_list.length; i += 1, total_index += 1, param_index += 1) { AsmInput *asm_input = asm_expr->input_list.at(i); buf_replace(asm_input->constraint, ',', '|'); - IrInstGen *ir_input = instruction->input_list[i]; + Stage1AirInst *ir_input = instruction->input_list[i]; buf_append_buf(&constraint_buf, asm_input->constraint); if (total_index + 1 < total_constraint_count) { buf_append_char(&constraint_buf, ','); @@ -4978,13 +4978,13 @@ static LLVMValueRef gen_non_null_bit(CodeGen *g, ZigType *maybe_type, LLVMValueR } static LLVMValueRef ir_render_test_non_null(CodeGen *g, Stage1Air *executable, - IrInstGenTestNonNull *instruction) + Stage1AirInstTestNonNull *instruction) { return gen_non_null_bit(g, instruction->value->value->type, ir_llvm_value(g, instruction->value)); } static LLVMValueRef ir_render_optional_unwrap_ptr(CodeGen *g, Stage1Air *executable, - IrInstGenOptionalUnwrapPtr *instruction) + Stage1AirInstOptionalUnwrapPtr *instruction) { if (instruction->base.value->special != ConstValSpecialRuntime) return nullptr; @@ -5090,7 +5090,7 @@ static LLVMValueRef get_int_builtin_fn(CodeGen *g, ZigType *expr_type, BuiltinFn return fn_val; } -static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenClz *instruction) { +static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, Stage1AirInstClz *instruction) { ZigType *int_type = instruction->op->value->type; LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdClz); LLVMValueRef operand = ir_llvm_value(g, instruction->op); @@ -5102,7 +5102,7 @@ static LLVMValueRef ir_render_clz(CodeGen *g, Stage1Air *executable, IrInstGenCl return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int); } -static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCtz *instruction) { +static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, Stage1AirInstCtz *instruction) { ZigType *int_type = instruction->op->value->type; LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdCtz); LLVMValueRef operand = ir_llvm_value(g, instruction->op); @@ -5114,7 +5114,7 @@ static LLVMValueRef ir_render_ctz(CodeGen *g, Stage1Air *executable, IrInstGenCt return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int); } -static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, IrInstGenShuffleVector *instruction) { +static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, Stage1AirInstShuffleVector *instruction) { uint64_t len_a = instruction->a->value->type->data.vector.len; uint64_t len_mask = instruction->mask->value->type->data.vector.len; @@ -5123,7 +5123,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, // when changing code, so Zig uses negative numbers to index the // second vector. These start at -1 and go down, and are easiest to use // with the ~ operator. Here we convert between the two formats. - IrInstGen *mask = instruction->mask; + Stage1AirInst *mask = instruction->mask; LLVMValueRef *values = heap::c_allocator.allocate(len_mask); for (uint64_t i = 0; i < len_mask; i++) { if (mask->value->data.x_array.data.s_none.elements[i].special == ConstValSpecialUndef) { @@ -5144,7 +5144,7 @@ static LLVMValueRef ir_render_shuffle_vector(CodeGen *g, Stage1Air *executable, llvm_mask_value, ""); } -static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGenSplat *instruction) { +static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, Stage1AirInstSplat *instruction) { ZigType *result_type = instruction->base.value->type; ir_assert(result_type->id == ZigTypeIdVector, &instruction->base); uint32_t len = result_type->data.vector.len; @@ -5156,7 +5156,7 @@ static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, IrInstGen return LLVMBuildShuffleVector(g->builder, op_vector, undef_vector, LLVMConstNull(mask_llvm_type), ""); } -static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrInstGenPopCount *instruction) { +static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, Stage1AirInstPopCount *instruction) { ZigType *int_type = instruction->op->value->type; LLVMValueRef fn_val = get_int_builtin_fn(g, int_type, BuiltinFnIdPopCount); LLVMValueRef operand = ir_llvm_value(g, instruction->op); @@ -5164,7 +5164,7 @@ static LLVMValueRef ir_render_pop_count(CodeGen *g, Stage1Air *executable, IrIns return gen_widen_or_shorten(g, false, int_type, instruction->base.value->type, wrong_size_int); } -static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrInstGenSwitchBr *instruction) { +static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, Stage1AirInstSwitchBr *instruction) { ZigType *target_type = instruction->target_value->value->type; LLVMBasicBlockRef else_block = instruction->else_block->llvm_block; @@ -5178,7 +5178,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns (unsigned)instruction->case_count); for (size_t i = 0; i < instruction->case_count; i += 1) { - IrInstGenSwitchBrCase *this_case = &instruction->cases[i]; + Stage1AirInstSwitchBrCase *this_case = &instruction->cases[i]; LLVMValueRef case_value = ir_llvm_value(g, this_case->value); if (target_type->id == ZigTypeIdPointer) { @@ -5192,7 +5192,7 @@ static LLVMValueRef ir_render_switch_br(CodeGen *g, Stage1Air *executable, IrIns return nullptr; } -static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPhi *instruction) { +static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, Stage1AirInstPhi *instruction) { if (!type_has_bits(g, instruction->base.value->type)) return nullptr; @@ -5216,12 +5216,12 @@ static LLVMValueRef ir_render_phi(CodeGen *g, Stage1Air *executable, IrInstGenPh return phi; } -static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRef *instruction) { +static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, Stage1AirInstRef *instruction) { if (!type_has_bits(g, instruction->base.value->type)) { return nullptr; } - if (instruction->operand->id == IrInstGenIdCall) { - IrInstGenCall *call = reinterpret_cast(instruction->operand); + if (instruction->operand->id == Stage1AirInstIdCall) { + Stage1AirInstCall *call = reinterpret_cast(instruction->operand); if (call->result_loc != nullptr) { return ir_llvm_value(g, call->result_loc); } @@ -5236,7 +5236,7 @@ static LLVMValueRef ir_render_ref(CodeGen *g, Stage1Air *executable, IrInstGenRe } } -static LLVMValueRef ir_render_err_name(CodeGen *g, Stage1Air *executable, IrInstGenErrName *instruction) { +static LLVMValueRef ir_render_err_name(CodeGen *g, Stage1Air *executable, Stage1AirInstErrName *instruction) { assert(g->generate_error_name_table); assert(g->errors_by_index.length > 0); @@ -5363,7 +5363,7 @@ static LLVMValueRef get_enum_tag_name_function(CodeGen *g, ZigType *enum_type) { } static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable, - IrInstGenTagName *instruction) + Stage1AirInstTagName *instruction) { ZigType *enum_type = instruction->target->value->type; assert(enum_type->id == ZigTypeIdEnum); @@ -5376,7 +5376,7 @@ static LLVMValueRef ir_render_enum_tag_name(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable, - IrInstGenFieldParentPtr *instruction) + Stage1AirInstFieldParentPtr *instruction) { ZigType *container_ptr_type = instruction->base.value->type; assert(container_ptr_type->id == ZigTypeIdPointer); @@ -5402,7 +5402,7 @@ static LLVMValueRef ir_render_field_parent_ptr(CodeGen *g, Stage1Air *executable } } -static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrInstGenAlignCast *instruction) { +static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, Stage1AirInstAlignCast *instruction) { LLVMValueRef target_val = ir_llvm_value(g, instruction->target); assert(target_val); @@ -5466,7 +5466,7 @@ static LLVMValueRef ir_render_align_cast(CodeGen *g, Stage1Air *executable, IrIn } static LLVMValueRef ir_render_error_return_trace(CodeGen *g, Stage1Air *executable, - IrInstGenErrorReturnTrace *instruction) + Stage1AirInstErrorReturnTrace *instruction) { bool is_llvm_alloca; LLVMValueRef cur_err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca); @@ -5507,7 +5507,7 @@ static enum ZigLLVM_AtomicRMWBinOp to_ZigLLVMAtomicRMWBinOp(AtomicRmwOp op, bool zig_unreachable(); } -static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool RMWXchg) { +static LLVMTypeRef get_atomic_abi_type(CodeGen *g, Stage1AirInst *instruction, bool RMWXchg) { // If the operand type of an atomic operation is not byte sized we need to // widen it before using it and then truncate the result. // RMW exchange of floating-point values is bitcasted to same-sized integer @@ -5538,7 +5538,7 @@ static LLVMTypeRef get_atomic_abi_type(CodeGen *g, IrInstGen *instruction, bool } } -static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstGenCmpxchg *instruction) { +static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, Stage1AirInstCmpxchg *instruction) { LLVMValueRef ptr_val = ir_llvm_value(g, instruction->ptr); LLVMValueRef cmp_val = ir_llvm_value(g, instruction->cmp_value); LLVMValueRef new_val = ir_llvm_value(g, instruction->new_value); @@ -5600,7 +5600,7 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, Stage1Air *executable, IrInstG return result_loc; } -static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGenReduce *instruction) { +static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, Stage1AirInstReduce *instruction) { LLVMValueRef value = ir_llvm_value(g, instruction->value); ZigType *value_type = instruction->value->value->type; @@ -5664,13 +5664,13 @@ static LLVMValueRef ir_render_reduce(CodeGen *g, Stage1Air *executable, IrInstGe return result_val; } -static LLVMValueRef ir_render_fence(CodeGen *g, Stage1Air *executable, IrInstGenFence *instruction) { +static LLVMValueRef ir_render_fence(CodeGen *g, Stage1Air *executable, Stage1AirInstFence *instruction) { LLVMAtomicOrdering atomic_order = to_LLVMAtomicOrdering(instruction->order); LLVMBuildFence(g->builder, atomic_order, false, ""); return nullptr; } -static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInstGenTruncate *instruction) { +static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, Stage1AirInstTruncate *instruction) { LLVMValueRef target_val = ir_llvm_value(g, instruction->target); ZigType *dest_type = instruction->base.value->type; ZigType *src_type = instruction->target->value->type; @@ -5685,7 +5685,7 @@ static LLVMValueRef ir_render_truncate(CodeGen *g, Stage1Air *executable, IrInst } } -static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGenMemset *instruction) { +static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, Stage1AirInstMemset *instruction) { LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr); LLVMValueRef len_val = ir_llvm_value(g, instruction->count); @@ -5715,7 +5715,7 @@ static LLVMValueRef ir_render_memset(CodeGen *g, Stage1Air *executable, IrInstGe return nullptr; } -static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGenMemcpy *instruction) { +static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, Stage1AirInstMemcpy *instruction) { LLVMValueRef dest_ptr = ir_llvm_value(g, instruction->dest_ptr); LLVMValueRef src_ptr = ir_llvm_value(g, instruction->src_ptr); LLVMValueRef len_val = ir_llvm_value(g, instruction->count); @@ -5737,14 +5737,14 @@ static LLVMValueRef ir_render_memcpy(CodeGen *g, Stage1Air *executable, IrInstGe return nullptr; } -static LLVMValueRef ir_render_wasm_memory_size(CodeGen *g, Stage1Air *executable, IrInstGenWasmMemorySize *instruction) { +static LLVMValueRef ir_render_wasm_memory_size(CodeGen *g, Stage1Air *executable, Stage1AirInstWasmMemorySize *instruction) { // TODO adjust for wasm64 LLVMValueRef param = ir_llvm_value(g, instruction->index); LLVMValueRef val = LLVMBuildCall(g->builder, gen_wasm_memory_size(g), ¶m, 1, ""); return val; } -static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable, IrInstGenWasmMemoryGrow *instruction) { +static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable, Stage1AirInstWasmMemoryGrow *instruction) { // TODO adjust for wasm64 LLVMValueRef params[] = { ir_llvm_value(g, instruction->index), @@ -5754,7 +5754,7 @@ static LLVMValueRef ir_render_wasm_memory_grow(CodeGen *g, Stage1Air *executable return val; } -static LLVMValueRef ir_render_slice(CodeGen *g, Stage1Air *executable, IrInstGenSlice *instruction) { +static LLVMValueRef ir_render_slice(CodeGen *g, Stage1Air *executable, Stage1AirInstSlice *instruction) { Error err; LLVMValueRef array_ptr_ptr = ir_llvm_value(g, instruction->ptr); @@ -5991,13 +5991,13 @@ static LLVMValueRef get_trap_fn_val(CodeGen *g) { } -static LLVMValueRef ir_render_breakpoint(CodeGen *g, Stage1Air *executable, IrInstGenBreakpoint *instruction) { +static LLVMValueRef ir_render_breakpoint(CodeGen *g, Stage1Air *executable, Stage1AirInstBreakpoint *instruction) { LLVMBuildCall(g->builder, get_trap_fn_val(g), nullptr, 0, ""); return nullptr; } static LLVMValueRef ir_render_return_address(CodeGen *g, Stage1Air *executable, - IrInstGenReturnAddress *instruction) + Stage1AirInstReturnAddress *instruction) { if (target_is_wasm(g->zig_target) && g->zig_target->os != OsEmscripten) { // I got this error from LLVM 10: @@ -6025,18 +6025,18 @@ static LLVMValueRef get_frame_address_fn_val(CodeGen *g) { } static LLVMValueRef ir_render_frame_address(CodeGen *g, Stage1Air *executable, - IrInstGenFrameAddress *instruction) + Stage1AirInstFrameAddress *instruction) { LLVMValueRef zero = LLVMConstNull(g->builtin_types.entry_i32->llvm_type); LLVMValueRef ptr_val = LLVMBuildCall(g->builder, get_frame_address_fn_val(g), &zero, 1, ""); return LLVMBuildPtrToInt(g->builder, ptr_val, g->builtin_types.entry_usize->llvm_type, ""); } -static LLVMValueRef ir_render_handle(CodeGen *g, Stage1Air *executable, IrInstGenFrameHandle *instruction) { +static LLVMValueRef ir_render_handle(CodeGen *g, Stage1Air *executable, Stage1AirInstFrameHandle *instruction) { return g->cur_frame_ptr; } -static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *instruction) { +static LLVMValueRef render_shl_with_overflow(CodeGen *g, Stage1AirInstOverflowOp *instruction) { ZigType *int_type = instruction->result_ptr_type; assert(int_type->id == ZigTypeIdInt); @@ -6061,7 +6061,7 @@ static LLVMValueRef render_shl_with_overflow(CodeGen *g, IrInstGenOverflowOp *in return overflow_bit; } -static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrInstGenOverflowOp *instruction) { +static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, Stage1AirInstOverflowOp *instruction) { AddSubMul add_sub_mul; switch (instruction->op) { case IrOverflowOpAdd: @@ -6099,7 +6099,7 @@ static LLVMValueRef ir_render_overflow_op(CodeGen *g, Stage1Air *executable, IrI return overflow_bit; } -static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInstGenTestErr *instruction) { +static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, Stage1AirInstTestErr *instruction) { ZigType *err_union_type = instruction->err_union->value->type; ZigType *payload_type = err_union_type->data.error_union.payload_type; LLVMValueRef err_union_handle = ir_llvm_value(g, instruction->err_union); @@ -6117,7 +6117,7 @@ static LLVMValueRef ir_render_test_err(CodeGen *g, Stage1Air *executable, IrInst } static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable, - IrInstGenUnwrapErrCode *instruction) + Stage1AirInstUnwrapErrCode *instruction) { if (instruction->base.value->special != ConstValSpecialRuntime) return nullptr; @@ -6137,7 +6137,7 @@ static LLVMValueRef ir_render_unwrap_err_code(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executable, - IrInstGenUnwrapErrPayload *instruction) + Stage1AirInstUnwrapErrPayload *instruction) { Error err; @@ -6205,7 +6205,7 @@ static LLVMValueRef ir_render_unwrap_err_payload(CodeGen *g, Stage1Air *executab } } -static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, IrInstGenOptionalWrap *instruction) { +static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, Stage1AirInstOptionalWrap *instruction) { ZigType *wanted_type = instruction->base.value->type; assert(wanted_type->id == ZigTypeIdOptional); @@ -6241,7 +6241,7 @@ static LLVMValueRef ir_render_optional_wrap(CodeGen *g, Stage1Air *executable, I return result_loc; } -static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, IrInstGenErrWrapCode *instruction) { +static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, Stage1AirInstErrWrapCode *instruction) { ZigType *wanted_type = instruction->base.value->type; assert(wanted_type->id == ZigTypeIdErrorUnion); @@ -6261,7 +6261,7 @@ static LLVMValueRef ir_render_err_wrap_code(CodeGen *g, Stage1Air *executable, I return result_loc; } -static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable, IrInstGenErrWrapPayload *instruction) { +static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable, Stage1AirInstErrWrapPayload *instruction) { ZigType *wanted_type = instruction->base.value->type; assert(wanted_type->id == ZigTypeIdErrorUnion); @@ -6292,7 +6292,7 @@ static LLVMValueRef ir_render_err_wrap_payload(CodeGen *g, Stage1Air *executable return result_loc; } -static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrInstGenUnionTag *instruction) { +static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, Stage1AirInstUnionTag *instruction) { ZigType *union_type = instruction->value->value->type; ZigType *tag_type = union_type->data.unionation.tag_type; @@ -6310,7 +6310,7 @@ static LLVMValueRef ir_render_union_tag(CodeGen *g, Stage1Air *executable, IrIns return get_handle_value(g, tag_field_ptr, tag_type, ptr_type); } -static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGenPanic *instruction) { +static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, Stage1AirInstPanic *instruction) { bool is_llvm_alloca; LLVMValueRef err_ret_trace_val = get_cur_err_ret_trace_val(g, instruction->base.scope, &is_llvm_alloca); gen_panic(g, ir_llvm_value(g, instruction->msg), err_ret_trace_val, is_llvm_alloca); @@ -6318,7 +6318,7 @@ static LLVMValueRef ir_render_panic(CodeGen *g, Stage1Air *executable, IrInstGen } static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable, - IrInstGenAtomicRmw *instruction) + Stage1AirInstAtomicRmw *instruction) { bool is_signed; ZigType *operand_type = instruction->operand->value->type; @@ -6370,7 +6370,7 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable, - IrInstGenAtomicLoad *instruction) + Stage1AirInstAtomicLoad *instruction) { LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering); LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr); @@ -6391,7 +6391,7 @@ static LLVMValueRef ir_render_atomic_load(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable, - IrInstGenAtomicStore *instruction) + Stage1AirInstAtomicStore *instruction) { LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering); LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr); @@ -6413,13 +6413,13 @@ static LLVMValueRef ir_render_atomic_store(CodeGen *g, Stage1Air *executable, return nullptr; } -static LLVMValueRef ir_render_float_op(CodeGen *g, Stage1Air *executable, IrInstGenFloatOp *instruction) { +static LLVMValueRef ir_render_float_op(CodeGen *g, Stage1Air *executable, Stage1AirInstFloatOp *instruction) { LLVMValueRef operand = ir_llvm_value(g, instruction->operand); LLVMValueRef fn_val = get_float_fn(g, instruction->base.value->type, ZigLLVMFnIdFloatOp, instruction->fn_id); return LLVMBuildCall(g->builder, fn_val, &operand, 1, ""); } -static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstGenMulAdd *instruction) { +static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, Stage1AirInstMulAdd *instruction) { LLVMValueRef op1 = ir_llvm_value(g, instruction->op1); LLVMValueRef op2 = ir_llvm_value(g, instruction->op2); LLVMValueRef op3 = ir_llvm_value(g, instruction->op3); @@ -6434,7 +6434,7 @@ static LLVMValueRef ir_render_mul_add(CodeGen *g, Stage1Air *executable, IrInstG return LLVMBuildCall(g->builder, fn_val, args, 3, ""); } -static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGenBswap *instruction) { +static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, Stage1AirInstBswap *instruction) { LLVMValueRef op = ir_llvm_value(g, instruction->op); ZigType *expr_type = instruction->base.value->type; bool is_vector = expr_type->id == ZigTypeIdVector; @@ -6469,7 +6469,7 @@ static LLVMValueRef ir_render_bswap(CodeGen *g, Stage1Air *executable, IrInstGen } static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable, - IrInstGenExtern *instruction) + Stage1AirInstExtern *instruction) { ZigType *expr_type = instruction->base.value->type; assert(get_src_ptr_type(expr_type)); @@ -6492,7 +6492,7 @@ static LLVMValueRef ir_render_extern(CodeGen *g, Stage1Air *executable, return LLVMBuildBitCast(g->builder, global_value, get_llvm_type(g, expr_type), ""); } -static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrInstGenBitReverse *instruction) { +static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, Stage1AirInstBitReverse *instruction) { LLVMValueRef op = ir_llvm_value(g, instruction->op); ZigType *int_type = instruction->base.value->type; assert(int_type->id == ZigTypeIdInt); @@ -6501,7 +6501,7 @@ static LLVMValueRef ir_render_bit_reverse(CodeGen *g, Stage1Air *executable, IrI } static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable, - IrInstGenVectorToArray *instruction) + Stage1AirInstVectorToArray *instruction) { ZigType *array_type = instruction->base.value->type; assert(array_type->id == ZigTypeIdArray); @@ -6535,7 +6535,7 @@ static LLVMValueRef ir_render_vector_to_array(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable, - IrInstGenArrayToVector *instruction) + Stage1AirInstArrayToVector *instruction) { ZigType *vector_type = instruction->base.value->type; assert(vector_type->id == ZigTypeIdVector); @@ -6572,7 +6572,7 @@ static LLVMValueRef ir_render_array_to_vector(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable, - IrInstGenAssertZero *instruction) + Stage1AirInstAssertZero *instruction) { LLVMValueRef target = ir_llvm_value(g, instruction->target); ZigType *int_type = instruction->target->value->type; @@ -6583,7 +6583,7 @@ static LLVMValueRef ir_render_assert_zero(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable, - IrInstGenAssertNonNull *instruction) + Stage1AirInstAssertNonNull *instruction) { LLVMValueRef target = ir_llvm_value(g, instruction->target); ZigType *target_type = instruction->target->value->type; @@ -6608,7 +6608,7 @@ static LLVMValueRef ir_render_assert_non_null(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable, - IrInstGenSuspendBegin *instruction) + Stage1AirInstSuspendBegin *instruction) { if (fn_is_async(g->cur_fn)) { instruction->resume_bb = gen_suspend_begin(g, "SuspendResume"); @@ -6617,7 +6617,7 @@ static LLVMValueRef ir_render_suspend_begin(CodeGen *g, Stage1Air *executable, } static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable, - IrInstGenSuspendFinish *instruction) + Stage1AirInstSuspendFinish *instruction) { LLVMBuildRetVoid(g->builder); @@ -6629,7 +6629,7 @@ static LLVMValueRef ir_render_suspend_finish(CodeGen *g, Stage1Air *executable, return nullptr; } -static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr, +static LLVMValueRef gen_await_early_return(CodeGen *g, Stage1AirInst *source_instr, LLVMValueRef target_frame_ptr, ZigType *result_type, ZigType *ptr_result_type, LLVMValueRef result_loc, bool non_async) { @@ -6668,7 +6668,7 @@ static LLVMValueRef gen_await_early_return(CodeGen *g, IrInstGen *source_instr, } } -static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGenAwait *instruction) { +static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, Stage1AirInstAwait *instruction) { LLVMTypeRef usize_type_ref = g->builtin_types.entry_usize->llvm_type; LLVMValueRef zero = LLVMConstNull(usize_type_ref); LLVMValueRef target_frame_ptr = ir_llvm_value(g, instruction->frame); @@ -6755,7 +6755,7 @@ static LLVMValueRef ir_render_await(CodeGen *g, Stage1Air *executable, IrInstGen return nullptr; } -static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGenResume *instruction) { +static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, Stage1AirInstResume *instruction) { LLVMValueRef frame = ir_llvm_value(g, instruction->frame); ZigType *frame_type = instruction->frame->value->type; assert(frame_type->id == ZigTypeIdAnyFrame); @@ -6765,14 +6765,14 @@ static LLVMValueRef ir_render_resume(CodeGen *g, Stage1Air *executable, IrInstGe } static LLVMValueRef ir_render_frame_size(CodeGen *g, Stage1Air *executable, - IrInstGenFrameSize *instruction) + Stage1AirInstFrameSize *instruction) { LLVMValueRef fn_val = ir_llvm_value(g, instruction->fn); return gen_frame_size(g, fn_val); } static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable, - IrInstGenSpillBegin *instruction) + Stage1AirInstSpillBegin *instruction) { if (!fn_is_async(g->cur_fn)) return nullptr; @@ -6791,7 +6791,7 @@ static LLVMValueRef ir_render_spill_begin(CodeGen *g, Stage1Air *executable, zig_unreachable(); } -static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrInstGenSpillEnd *instruction) { +static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, Stage1AirInstSpillEnd *instruction) { if (!fn_is_async(g->cur_fn)) return ir_llvm_value(g, instruction->begin->operand); @@ -6808,14 +6808,14 @@ static LLVMValueRef ir_render_spill_end(CodeGen *g, Stage1Air *executable, IrIns } static LLVMValueRef ir_render_vector_extract_elem(CodeGen *g, Stage1Air *executable, - IrInstGenVectorExtractElem *instruction) + Stage1AirInstVectorExtractElem *instruction) { LLVMValueRef vector = ir_llvm_value(g, instruction->vector); LLVMValueRef index = ir_llvm_value(g, instruction->index); return LLVMBuildExtractElement(g->builder, vector, index, ""); } -static void set_debug_location(CodeGen *g, IrInstGen *instruction) { +static void set_debug_location(CodeGen *g, Stage1AirInst *instruction) { AstNode *source_node = instruction->source_node; Scope *scope = instruction->scope; @@ -6826,187 +6826,187 @@ static void set_debug_location(CodeGen *g, IrInstGen *instruction) { node_column_onebased(source_node), get_di_scope(g, scope)); } -static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, IrInstGen *instruction) { +static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, Stage1AirInst *instruction) { switch (instruction->id) { - case IrInstGenIdInvalid: - case IrInstGenIdConst: - case IrInstGenIdAlloca: + case Stage1AirInstIdInvalid: + case Stage1AirInstIdConst: + case Stage1AirInstIdAlloca: zig_unreachable(); - case IrInstGenIdDeclVar: - return ir_render_decl_var(g, executable, (IrInstGenDeclVar *)instruction); - case IrInstGenIdReturn: - return ir_render_return(g, executable, (IrInstGenReturn *)instruction); - case IrInstGenIdBinOp: - return ir_render_bin_op(g, executable, (IrInstGenBinOp *)instruction); - case IrInstGenIdCast: - return ir_render_cast(g, executable, (IrInstGenCast *)instruction); - case IrInstGenIdUnreachable: - return ir_render_unreachable(g, executable, (IrInstGenUnreachable *)instruction); - case IrInstGenIdCondBr: - return ir_render_cond_br(g, executable, (IrInstGenCondBr *)instruction); - case IrInstGenIdBr: - return ir_render_br(g, executable, (IrInstGenBr *)instruction); - case IrInstGenIdBinaryNot: - return ir_render_binary_not(g, executable, (IrInstGenBinaryNot *)instruction); - case IrInstGenIdNegation: - return ir_render_negation(g, executable, (IrInstGenNegation *)instruction); - case IrInstGenIdLoadPtr: - return ir_render_load_ptr(g, executable, (IrInstGenLoadPtr *)instruction); - case IrInstGenIdStorePtr: - return ir_render_store_ptr(g, executable, (IrInstGenStorePtr *)instruction); - case IrInstGenIdVectorStoreElem: - return ir_render_vector_store_elem(g, executable, (IrInstGenVectorStoreElem *)instruction); - case IrInstGenIdVarPtr: - return ir_render_var_ptr(g, executable, (IrInstGenVarPtr *)instruction); - case IrInstGenIdReturnPtr: - return ir_render_return_ptr(g, executable, (IrInstGenReturnPtr *)instruction); - case IrInstGenIdElemPtr: - return ir_render_elem_ptr(g, executable, (IrInstGenElemPtr *)instruction); - case IrInstGenIdCall: - return ir_render_call(g, executable, (IrInstGenCall *)instruction); - case IrInstGenIdStructFieldPtr: - return ir_render_struct_field_ptr(g, executable, (IrInstGenStructFieldPtr *)instruction); - case IrInstGenIdUnionFieldPtr: - return ir_render_union_field_ptr(g, executable, (IrInstGenUnionFieldPtr *)instruction); - case IrInstGenIdAsm: - return ir_render_asm_gen(g, executable, (IrInstGenAsm *)instruction); - case IrInstGenIdTestNonNull: - return ir_render_test_non_null(g, executable, (IrInstGenTestNonNull *)instruction); - case IrInstGenIdOptionalUnwrapPtr: - return ir_render_optional_unwrap_ptr(g, executable, (IrInstGenOptionalUnwrapPtr *)instruction); - case IrInstGenIdClz: - return ir_render_clz(g, executable, (IrInstGenClz *)instruction); - case IrInstGenIdCtz: - return ir_render_ctz(g, executable, (IrInstGenCtz *)instruction); - case IrInstGenIdPopCount: - return ir_render_pop_count(g, executable, (IrInstGenPopCount *)instruction); - case IrInstGenIdSwitchBr: - return ir_render_switch_br(g, executable, (IrInstGenSwitchBr *)instruction); - case IrInstGenIdBswap: - return ir_render_bswap(g, executable, (IrInstGenBswap *)instruction); - case IrInstGenIdBitReverse: - return ir_render_bit_reverse(g, executable, (IrInstGenBitReverse *)instruction); - case IrInstGenIdPhi: - return ir_render_phi(g, executable, (IrInstGenPhi *)instruction); - case IrInstGenIdRef: - return ir_render_ref(g, executable, (IrInstGenRef *)instruction); - case IrInstGenIdErrName: - return ir_render_err_name(g, executable, (IrInstGenErrName *)instruction); - case IrInstGenIdCmpxchg: - return ir_render_cmpxchg(g, executable, (IrInstGenCmpxchg *)instruction); - case IrInstGenIdFence: - return ir_render_fence(g, executable, (IrInstGenFence *)instruction); - case IrInstGenIdReduce: - return ir_render_reduce(g, executable, (IrInstGenReduce *)instruction); - case IrInstGenIdTruncate: - return ir_render_truncate(g, executable, (IrInstGenTruncate *)instruction); - case IrInstGenIdBoolNot: - return ir_render_bool_not(g, executable, (IrInstGenBoolNot *)instruction); - case IrInstGenIdMemset: - return ir_render_memset(g, executable, (IrInstGenMemset *)instruction); - case IrInstGenIdMemcpy: - return ir_render_memcpy(g, executable, (IrInstGenMemcpy *)instruction); - case IrInstGenIdSlice: - return ir_render_slice(g, executable, (IrInstGenSlice *)instruction); - case IrInstGenIdBreakpoint: - return ir_render_breakpoint(g, executable, (IrInstGenBreakpoint *)instruction); - case IrInstGenIdReturnAddress: - return ir_render_return_address(g, executable, (IrInstGenReturnAddress *)instruction); - case IrInstGenIdFrameAddress: - return ir_render_frame_address(g, executable, (IrInstGenFrameAddress *)instruction); - case IrInstGenIdFrameHandle: - return ir_render_handle(g, executable, (IrInstGenFrameHandle *)instruction); - case IrInstGenIdOverflowOp: - return ir_render_overflow_op(g, executable, (IrInstGenOverflowOp *)instruction); - case IrInstGenIdTestErr: - return ir_render_test_err(g, executable, (IrInstGenTestErr *)instruction); - case IrInstGenIdUnwrapErrCode: - return ir_render_unwrap_err_code(g, executable, (IrInstGenUnwrapErrCode *)instruction); - case IrInstGenIdUnwrapErrPayload: - return ir_render_unwrap_err_payload(g, executable, (IrInstGenUnwrapErrPayload *)instruction); - case IrInstGenIdOptionalWrap: - return ir_render_optional_wrap(g, executable, (IrInstGenOptionalWrap *)instruction); - case IrInstGenIdErrWrapCode: - return ir_render_err_wrap_code(g, executable, (IrInstGenErrWrapCode *)instruction); - case IrInstGenIdErrWrapPayload: - return ir_render_err_wrap_payload(g, executable, (IrInstGenErrWrapPayload *)instruction); - case IrInstGenIdUnionTag: - return ir_render_union_tag(g, executable, (IrInstGenUnionTag *)instruction); - case IrInstGenIdPtrCast: - return ir_render_ptr_cast(g, executable, (IrInstGenPtrCast *)instruction); - case IrInstGenIdBitCast: - return ir_render_bit_cast(g, executable, (IrInstGenBitCast *)instruction); - case IrInstGenIdWidenOrShorten: - return ir_render_widen_or_shorten(g, executable, (IrInstGenWidenOrShorten *)instruction); - case IrInstGenIdPtrToInt: - return ir_render_ptr_to_int(g, executable, (IrInstGenPtrToInt *)instruction); - case IrInstGenIdIntToPtr: - return ir_render_int_to_ptr(g, executable, (IrInstGenIntToPtr *)instruction); - case IrInstGenIdIntToEnum: - return ir_render_int_to_enum(g, executable, (IrInstGenIntToEnum *)instruction); - case IrInstGenIdIntToErr: - return ir_render_int_to_err(g, executable, (IrInstGenIntToErr *)instruction); - case IrInstGenIdErrToInt: - return ir_render_err_to_int(g, executable, (IrInstGenErrToInt *)instruction); - case IrInstGenIdPanic: - return ir_render_panic(g, executable, (IrInstGenPanic *)instruction); - case IrInstGenIdTagName: - return ir_render_enum_tag_name(g, executable, (IrInstGenTagName *)instruction); - case IrInstGenIdFieldParentPtr: - return ir_render_field_parent_ptr(g, executable, (IrInstGenFieldParentPtr *)instruction); - case IrInstGenIdAlignCast: - return ir_render_align_cast(g, executable, (IrInstGenAlignCast *)instruction); - case IrInstGenIdErrorReturnTrace: - return ir_render_error_return_trace(g, executable, (IrInstGenErrorReturnTrace *)instruction); - case IrInstGenIdAtomicRmw: - return ir_render_atomic_rmw(g, executable, (IrInstGenAtomicRmw *)instruction); - case IrInstGenIdAtomicLoad: - return ir_render_atomic_load(g, executable, (IrInstGenAtomicLoad *)instruction); - case IrInstGenIdAtomicStore: - return ir_render_atomic_store(g, executable, (IrInstGenAtomicStore *)instruction); - case IrInstGenIdSaveErrRetAddr: - return ir_render_save_err_ret_addr(g, executable, (IrInstGenSaveErrRetAddr *)instruction); - case IrInstGenIdFloatOp: - return ir_render_float_op(g, executable, (IrInstGenFloatOp *)instruction); - case IrInstGenIdMulAdd: - return ir_render_mul_add(g, executable, (IrInstGenMulAdd *)instruction); - case IrInstGenIdArrayToVector: - return ir_render_array_to_vector(g, executable, (IrInstGenArrayToVector *)instruction); - case IrInstGenIdVectorToArray: - return ir_render_vector_to_array(g, executable, (IrInstGenVectorToArray *)instruction); - case IrInstGenIdAssertZero: - return ir_render_assert_zero(g, executable, (IrInstGenAssertZero *)instruction); - case IrInstGenIdAssertNonNull: - return ir_render_assert_non_null(g, executable, (IrInstGenAssertNonNull *)instruction); - case IrInstGenIdPtrOfArrayToSlice: - return ir_render_ptr_of_array_to_slice(g, executable, (IrInstGenPtrOfArrayToSlice *)instruction); - case IrInstGenIdSuspendBegin: - return ir_render_suspend_begin(g, executable, (IrInstGenSuspendBegin *)instruction); - case IrInstGenIdSuspendFinish: - return ir_render_suspend_finish(g, executable, (IrInstGenSuspendFinish *)instruction); - case IrInstGenIdResume: - return ir_render_resume(g, executable, (IrInstGenResume *)instruction); - case IrInstGenIdFrameSize: - return ir_render_frame_size(g, executable, (IrInstGenFrameSize *)instruction); - case IrInstGenIdAwait: - return ir_render_await(g, executable, (IrInstGenAwait *)instruction); - case IrInstGenIdSpillBegin: - return ir_render_spill_begin(g, executable, (IrInstGenSpillBegin *)instruction); - case IrInstGenIdSpillEnd: - return ir_render_spill_end(g, executable, (IrInstGenSpillEnd *)instruction); - case IrInstGenIdShuffleVector: - return ir_render_shuffle_vector(g, executable, (IrInstGenShuffleVector *) instruction); - case IrInstGenIdSplat: - return ir_render_splat(g, executable, (IrInstGenSplat *) instruction); - case IrInstGenIdVectorExtractElem: - return ir_render_vector_extract_elem(g, executable, (IrInstGenVectorExtractElem *) instruction); - case IrInstGenIdWasmMemorySize: - return ir_render_wasm_memory_size(g, executable, (IrInstGenWasmMemorySize *) instruction); - case IrInstGenIdWasmMemoryGrow: - return ir_render_wasm_memory_grow(g, executable, (IrInstGenWasmMemoryGrow *) instruction); - case IrInstGenIdExtern: - return ir_render_extern(g, executable, (IrInstGenExtern *) instruction); + case Stage1AirInstIdDeclVar: + return ir_render_decl_var(g, executable, (Stage1AirInstDeclVar *)instruction); + case Stage1AirInstIdReturn: + return ir_render_return(g, executable, (Stage1AirInstReturn *)instruction); + case Stage1AirInstIdBinOp: + return ir_render_bin_op(g, executable, (Stage1AirInstBinOp *)instruction); + case Stage1AirInstIdCast: + return ir_render_cast(g, executable, (Stage1AirInstCast *)instruction); + case Stage1AirInstIdUnreachable: + return ir_render_unreachable(g, executable, (Stage1AirInstUnreachable *)instruction); + case Stage1AirInstIdCondBr: + return ir_render_cond_br(g, executable, (Stage1AirInstCondBr *)instruction); + case Stage1AirInstIdBr: + return ir_render_br(g, executable, (Stage1AirInstBr *)instruction); + case Stage1AirInstIdBinaryNot: + return ir_render_binary_not(g, executable, (Stage1AirInstBinaryNot *)instruction); + case Stage1AirInstIdNegation: + return ir_render_negation(g, executable, (Stage1AirInstNegation *)instruction); + case Stage1AirInstIdLoadPtr: + return ir_render_load_ptr(g, executable, (Stage1AirInstLoadPtr *)instruction); + case Stage1AirInstIdStorePtr: + return ir_render_store_ptr(g, executable, (Stage1AirInstStorePtr *)instruction); + case Stage1AirInstIdVectorStoreElem: + return ir_render_vector_store_elem(g, executable, (Stage1AirInstVectorStoreElem *)instruction); + case Stage1AirInstIdVarPtr: + return ir_render_var_ptr(g, executable, (Stage1AirInstVarPtr *)instruction); + case Stage1AirInstIdReturnPtr: + return ir_render_return_ptr(g, executable, (Stage1AirInstReturnPtr *)instruction); + case Stage1AirInstIdElemPtr: + return ir_render_elem_ptr(g, executable, (Stage1AirInstElemPtr *)instruction); + case Stage1AirInstIdCall: + return ir_render_call(g, executable, (Stage1AirInstCall *)instruction); + case Stage1AirInstIdStructFieldPtr: + return ir_render_struct_field_ptr(g, executable, (Stage1AirInstStructFieldPtr *)instruction); + case Stage1AirInstIdUnionFieldPtr: + return ir_render_union_field_ptr(g, executable, (Stage1AirInstUnionFieldPtr *)instruction); + case Stage1AirInstIdAsm: + return ir_render_asm_gen(g, executable, (Stage1AirInstAsm *)instruction); + case Stage1AirInstIdTestNonNull: + return ir_render_test_non_null(g, executable, (Stage1AirInstTestNonNull *)instruction); + case Stage1AirInstIdOptionalUnwrapPtr: + return ir_render_optional_unwrap_ptr(g, executable, (Stage1AirInstOptionalUnwrapPtr *)instruction); + case Stage1AirInstIdClz: + return ir_render_clz(g, executable, (Stage1AirInstClz *)instruction); + case Stage1AirInstIdCtz: + return ir_render_ctz(g, executable, (Stage1AirInstCtz *)instruction); + case Stage1AirInstIdPopCount: + return ir_render_pop_count(g, executable, (Stage1AirInstPopCount *)instruction); + case Stage1AirInstIdSwitchBr: + return ir_render_switch_br(g, executable, (Stage1AirInstSwitchBr *)instruction); + case Stage1AirInstIdBswap: + return ir_render_bswap(g, executable, (Stage1AirInstBswap *)instruction); + case Stage1AirInstIdBitReverse: + return ir_render_bit_reverse(g, executable, (Stage1AirInstBitReverse *)instruction); + case Stage1AirInstIdPhi: + return ir_render_phi(g, executable, (Stage1AirInstPhi *)instruction); + case Stage1AirInstIdRef: + return ir_render_ref(g, executable, (Stage1AirInstRef *)instruction); + case Stage1AirInstIdErrName: + return ir_render_err_name(g, executable, (Stage1AirInstErrName *)instruction); + case Stage1AirInstIdCmpxchg: + return ir_render_cmpxchg(g, executable, (Stage1AirInstCmpxchg *)instruction); + case Stage1AirInstIdFence: + return ir_render_fence(g, executable, (Stage1AirInstFence *)instruction); + case Stage1AirInstIdReduce: + return ir_render_reduce(g, executable, (Stage1AirInstReduce *)instruction); + case Stage1AirInstIdTruncate: + return ir_render_truncate(g, executable, (Stage1AirInstTruncate *)instruction); + case Stage1AirInstIdBoolNot: + return ir_render_bool_not(g, executable, (Stage1AirInstBoolNot *)instruction); + case Stage1AirInstIdMemset: + return ir_render_memset(g, executable, (Stage1AirInstMemset *)instruction); + case Stage1AirInstIdMemcpy: + return ir_render_memcpy(g, executable, (Stage1AirInstMemcpy *)instruction); + case Stage1AirInstIdSlice: + return ir_render_slice(g, executable, (Stage1AirInstSlice *)instruction); + case Stage1AirInstIdBreakpoint: + return ir_render_breakpoint(g, executable, (Stage1AirInstBreakpoint *)instruction); + case Stage1AirInstIdReturnAddress: + return ir_render_return_address(g, executable, (Stage1AirInstReturnAddress *)instruction); + case Stage1AirInstIdFrameAddress: + return ir_render_frame_address(g, executable, (Stage1AirInstFrameAddress *)instruction); + case Stage1AirInstIdFrameHandle: + return ir_render_handle(g, executable, (Stage1AirInstFrameHandle *)instruction); + case Stage1AirInstIdOverflowOp: + return ir_render_overflow_op(g, executable, (Stage1AirInstOverflowOp *)instruction); + case Stage1AirInstIdTestErr: + return ir_render_test_err(g, executable, (Stage1AirInstTestErr *)instruction); + case Stage1AirInstIdUnwrapErrCode: + return ir_render_unwrap_err_code(g, executable, (Stage1AirInstUnwrapErrCode *)instruction); + case Stage1AirInstIdUnwrapErrPayload: + return ir_render_unwrap_err_payload(g, executable, (Stage1AirInstUnwrapErrPayload *)instruction); + case Stage1AirInstIdOptionalWrap: + return ir_render_optional_wrap(g, executable, (Stage1AirInstOptionalWrap *)instruction); + case Stage1AirInstIdErrWrapCode: + return ir_render_err_wrap_code(g, executable, (Stage1AirInstErrWrapCode *)instruction); + case Stage1AirInstIdErrWrapPayload: + return ir_render_err_wrap_payload(g, executable, (Stage1AirInstErrWrapPayload *)instruction); + case Stage1AirInstIdUnionTag: + return ir_render_union_tag(g, executable, (Stage1AirInstUnionTag *)instruction); + case Stage1AirInstIdPtrCast: + return ir_render_ptr_cast(g, executable, (Stage1AirInstPtrCast *)instruction); + case Stage1AirInstIdBitCast: + return ir_render_bit_cast(g, executable, (Stage1AirInstBitCast *)instruction); + case Stage1AirInstIdWidenOrShorten: + return ir_render_widen_or_shorten(g, executable, (Stage1AirInstWidenOrShorten *)instruction); + case Stage1AirInstIdPtrToInt: + return ir_render_ptr_to_int(g, executable, (Stage1AirInstPtrToInt *)instruction); + case Stage1AirInstIdIntToPtr: + return ir_render_int_to_ptr(g, executable, (Stage1AirInstIntToPtr *)instruction); + case Stage1AirInstIdIntToEnum: + return ir_render_int_to_enum(g, executable, (Stage1AirInstIntToEnum *)instruction); + case Stage1AirInstIdIntToErr: + return ir_render_int_to_err(g, executable, (Stage1AirInstIntToErr *)instruction); + case Stage1AirInstIdErrToInt: + return ir_render_err_to_int(g, executable, (Stage1AirInstErrToInt *)instruction); + case Stage1AirInstIdPanic: + return ir_render_panic(g, executable, (Stage1AirInstPanic *)instruction); + case Stage1AirInstIdTagName: + return ir_render_enum_tag_name(g, executable, (Stage1AirInstTagName *)instruction); + case Stage1AirInstIdFieldParentPtr: + return ir_render_field_parent_ptr(g, executable, (Stage1AirInstFieldParentPtr *)instruction); + case Stage1AirInstIdAlignCast: + return ir_render_align_cast(g, executable, (Stage1AirInstAlignCast *)instruction); + case Stage1AirInstIdErrorReturnTrace: + return ir_render_error_return_trace(g, executable, (Stage1AirInstErrorReturnTrace *)instruction); + case Stage1AirInstIdAtomicRmw: + return ir_render_atomic_rmw(g, executable, (Stage1AirInstAtomicRmw *)instruction); + case Stage1AirInstIdAtomicLoad: + return ir_render_atomic_load(g, executable, (Stage1AirInstAtomicLoad *)instruction); + case Stage1AirInstIdAtomicStore: + return ir_render_atomic_store(g, executable, (Stage1AirInstAtomicStore *)instruction); + case Stage1AirInstIdSaveErrRetAddr: + return ir_render_save_err_ret_addr(g, executable, (Stage1AirInstSaveErrRetAddr *)instruction); + case Stage1AirInstIdFloatOp: + return ir_render_float_op(g, executable, (Stage1AirInstFloatOp *)instruction); + case Stage1AirInstIdMulAdd: + return ir_render_mul_add(g, executable, (Stage1AirInstMulAdd *)instruction); + case Stage1AirInstIdArrayToVector: + return ir_render_array_to_vector(g, executable, (Stage1AirInstArrayToVector *)instruction); + case Stage1AirInstIdVectorToArray: + return ir_render_vector_to_array(g, executable, (Stage1AirInstVectorToArray *)instruction); + case Stage1AirInstIdAssertZero: + return ir_render_assert_zero(g, executable, (Stage1AirInstAssertZero *)instruction); + case Stage1AirInstIdAssertNonNull: + return ir_render_assert_non_null(g, executable, (Stage1AirInstAssertNonNull *)instruction); + case Stage1AirInstIdPtrOfArrayToSlice: + return ir_render_ptr_of_array_to_slice(g, executable, (Stage1AirInstPtrOfArrayToSlice *)instruction); + case Stage1AirInstIdSuspendBegin: + return ir_render_suspend_begin(g, executable, (Stage1AirInstSuspendBegin *)instruction); + case Stage1AirInstIdSuspendFinish: + return ir_render_suspend_finish(g, executable, (Stage1AirInstSuspendFinish *)instruction); + case Stage1AirInstIdResume: + return ir_render_resume(g, executable, (Stage1AirInstResume *)instruction); + case Stage1AirInstIdFrameSize: + return ir_render_frame_size(g, executable, (Stage1AirInstFrameSize *)instruction); + case Stage1AirInstIdAwait: + return ir_render_await(g, executable, (Stage1AirInstAwait *)instruction); + case Stage1AirInstIdSpillBegin: + return ir_render_spill_begin(g, executable, (Stage1AirInstSpillBegin *)instruction); + case Stage1AirInstIdSpillEnd: + return ir_render_spill_end(g, executable, (Stage1AirInstSpillEnd *)instruction); + case Stage1AirInstIdShuffleVector: + return ir_render_shuffle_vector(g, executable, (Stage1AirInstShuffleVector *) instruction); + case Stage1AirInstIdSplat: + return ir_render_splat(g, executable, (Stage1AirInstSplat *) instruction); + case Stage1AirInstIdVectorExtractElem: + return ir_render_vector_extract_elem(g, executable, (Stage1AirInstVectorExtractElem *) instruction); + case Stage1AirInstIdWasmMemorySize: + return ir_render_wasm_memory_size(g, executable, (Stage1AirInstWasmMemorySize *) instruction); + case Stage1AirInstIdWasmMemoryGrow: + return ir_render_wasm_memory_grow(g, executable, (Stage1AirInstWasmMemoryGrow *) instruction); + case Stage1AirInstIdExtern: + return ir_render_extern(g, executable, (Stage1AirInstExtern *) instruction); } zig_unreachable(); } @@ -7018,14 +7018,14 @@ static void ir_render(CodeGen *g, ZigFn *fn_entry) { assert(executable->basic_block_list.length > 0); for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) { - IrBasicBlockGen *current_block = executable->basic_block_list.at(block_i); + Stage1AirBasicBlock *current_block = executable->basic_block_list.at(block_i); if (get_scope_typeof(current_block->scope) != nullptr) { LLVMBuildBr(g->builder, current_block->llvm_block); } assert(current_block->llvm_block); LLVMPositionBuilderAtEnd(g->builder, current_block->llvm_block); for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) { - IrInstGen *instruction = current_block->instruction_list.at(instr_i); + Stage1AirInst *instruction = current_block->instruction_list.at(instr_i); if (instruction->ref_count == 0 && !ir_inst_gen_has_side_effects(instruction)) continue; if (get_scope_typeof(instruction->scope) != nullptr) @@ -8021,7 +8021,7 @@ static void build_all_basic_blocks(CodeGen *g, ZigFn *fn) { g->cur_preamble_llvm_block = first_bb; } for (size_t block_i = 0; block_i < executable->basic_block_list.length; block_i += 1) { - IrBasicBlockGen *bb = executable->basic_block_list.at(block_i); + Stage1AirBasicBlock *bb = executable->basic_block_list.at(block_i); bb->llvm_block = LLVMAppendBasicBlock(fn_val, bb->name_hint); } if (first_bb == nullptr) { @@ -8243,10 +8243,10 @@ static void do_code_gen(CodeGen *g) { if (!is_async) { // allocate async frames for nosuspend calls & awaits to async functions ZigType *largest_call_frame_type = nullptr; - IrInstGen *all_calls_alloca = ir_create_alloca(g, &fn_table_entry->fndef_scope->base, + Stage1AirInst *all_calls_alloca = ir_create_alloca(g, &fn_table_entry->fndef_scope->base, fn_table_entry->body_node, fn_table_entry, g->builtin_types.entry_void, "@async_call_frame"); for (size_t i = 0; i < fn_table_entry->call_list.length; i += 1) { - IrInstGenCall *call = fn_table_entry->call_list.at(i); + Stage1AirInstCall *call = fn_table_entry->call_list.at(i); if (call->fn_entry == nullptr) continue; if (!fn_is_async(call->fn_entry)) @@ -8268,7 +8268,7 @@ static void do_code_gen(CodeGen *g) { } // allocate temporary stack data for (size_t alloca_i = 0; alloca_i < fn_table_entry->alloca_gen_list.length; alloca_i += 1) { - IrInstGenAlloca *instruction = fn_table_entry->alloca_gen_list.at(alloca_i); + Stage1AirInstAlloca *instruction = fn_table_entry->alloca_gen_list.at(alloca_i); ZigType *ptr_type = instruction->base.value->type; assert(ptr_type->id == ZigTypeIdPointer); ZigType *child_type = ptr_type->data.pointer.child_type; @@ -8422,7 +8422,7 @@ static void do_code_gen(CodeGen *g) { g->cur_async_switch_instr = switch_instr; LLVMValueRef zero = LLVMConstNull(usize_type_ref); - IrBasicBlockGen *entry_block = executable->basic_block_list.at(0); + Stage1AirBasicBlock *entry_block = executable->basic_block_list.at(0); LLVMAddCase(switch_instr, zero, entry_block->llvm_block); g->cur_resume_block_count += 1; @@ -9379,7 +9379,7 @@ static void init(CodeGen *g) { define_builtin_types(g); define_intern_values(g); - IrInstGen *sentinel_instructions = heap::c_allocator.allocate(2); + Stage1AirInst *sentinel_instructions = heap::c_allocator.allocate(2); g->invalid_inst_gen = &sentinel_instructions[0]; g->invalid_inst_gen->value = g->pass1_arena->create(); g->invalid_inst_gen->value->type = g->builtin_types.entry_invalid; @@ -9388,7 +9388,7 @@ static void init(CodeGen *g) { g->unreach_instruction->value = g->pass1_arena->create(); g->unreach_instruction->value->type = g->builtin_types.entry_unreachable; - g->invalid_inst_src = heap::c_allocator.create(); + g->invalid_inst_src = heap::c_allocator.create(); define_builtin_fns(g); Error err; diff --git a/src/stage1/ir.cpp b/src/stage1/ir.cpp index ab8aac9a91..e92512e9ca 100644 --- a/src/stage1/ir.cpp +++ b/src/stage1/ir.cpp @@ -25,10 +25,10 @@ struct IrBuilderGen { CodeGen *codegen; Stage1Air *exec; - IrBasicBlockGen *current_basic_block; + Stage1AirBasicBlock *current_basic_block; // track for immediate post-analysis destruction - mem::List constants; + mem::List constants; }; struct IrAnalyze { @@ -40,17 +40,17 @@ struct IrAnalyze { size_t instruction_index; ZigType *explicit_return_type; AstNode *explicit_return_type_source_node; - ZigList src_implicit_return_type_list; + ZigList src_implicit_return_type_list; ZigList resume_stack; Stage1ZirBasicBlock *const_predecessor_bb; size_t ref_count; size_t break_debug_id; // for debugging purposes - IrInstGen *return_ptr; + Stage1AirInst *return_ptr; Stage1Air *parent_exec; size_t *backward_branch_count; size_t *backward_branch_quota; ZigFn *fn; - IrInstSrc *suspend_source_instr; + Stage1ZirInst *suspend_source_instr; // For the purpose of using in a debugger void dump(); @@ -216,16 +216,16 @@ struct DbgIrBreakPoint { uint32_t line; }; -static IrInstGen *ir_implicit_cast(IrAnalyze *ira, IrInstGen *value, ZigType *expected_type); -static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, ZigType *expected_type); -static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr, +static Stage1AirInst *ir_implicit_cast(IrAnalyze *ira, Stage1AirInst *value, ZigType *expected_type); +static Stage1AirInst *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, ZigType *expected_type); +static Stage1AirInst *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr, ResultLoc *result_loc); -static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name, - Scope *scope, AstNode *source_node, IrInstGen *container_ptr, AstNode *container_ptr_src, +static Stage1AirInst *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name, + Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, AstNode *container_ptr_src, ZigType *container_type, bool initializing); -static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var); -static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op); +static Stage1AirInst *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var); +static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, Stage1AirInst *op); static ZigType *adjust_ptr_align(CodeGen *g, ZigType *ptr_type, uint32_t new_align); static ZigType *adjust_ptr_const(CodeGen *g, ZigType *ptr_type, bool is_const); static ZigType *adjust_slice_align(CodeGen *g, ZigType *slice_type, uint32_t new_align); @@ -233,40 +233,40 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou static void buf_write_value_bytes(CodeGen *codegen, uint8_t *buf, ZigValue *val); static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source_node, ZigValue *out_val, ZigValue *ptr_val); -static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src, +static Stage1AirInst *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src, bool safety_check_on, bool keep_bigger_alignment); -static ZigValue *ir_resolve_const(IrAnalyze *ira, IrInstGen *value, UndefAllowed undef_allowed); +static ZigValue *ir_resolve_const(IrAnalyze *ira, Stage1AirInst *value, UndefAllowed undef_allowed); static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_align); -static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *ptr_type); -static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *dest_type); -static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_source_instr, - ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, bool allow_discard); -static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_instr, - ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, bool allow_discard); -static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool safety_check_on, bool initializing); -static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool safety_check_on, bool initializing); -static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool initializing); -static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, IrInstGen *uncasted_value, bool allow_write_through_const); +static Stage1AirInst *ir_resolve_result_raw(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr, + ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard); +static Stage1AirInst *ir_resolve_result(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr, + ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard); +static Stage1AirInst *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool safety_check_on, bool initializing); +static Stage1AirInst *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool safety_check_on, bool initializing); +static Stage1AirInst *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool initializing); +static Stage1AirInst *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, Stage1AirInst *uncasted_value, bool allow_write_through_const); static void ir_reset_result(ResultLoc *result_loc); -static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - TypeStructField *field, IrInstGen *struct_ptr, ZigType *struct_type, bool initializing); -static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name, - Scope *scope, AstNode *source_node, IrInstGen *container_ptr, ZigType *container_type); -static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value); -static IrInstGen *ir_error_dependency_loop(IrAnalyze *ira, AstNode *source_node); -static IrInstGen *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty); -static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node, - AstNode *field_source_node, ZigType *union_type, Buf *field_name, IrInstGen *field_result_loc, - IrInstGen *result_loc); -static IrInstGen *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *struct_operand, TypeStructField *field); +static Stage1AirInst *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + TypeStructField *field, Stage1AirInst *struct_ptr, ZigType *struct_type, bool initializing); +static Stage1AirInst *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name, + Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, ZigType *container_type); +static Stage1AirInst *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value); +static Stage1AirInst *ir_error_dependency_loop(IrAnalyze *ira, AstNode *source_node); +static Stage1AirInst *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty); +static Stage1AirInst *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node, + AstNode *field_source_node, ZigType *union_type, Buf *field_name, Stage1AirInst *field_result_loc, + Stage1AirInst *result_loc); +static Stage1AirInst *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *struct_operand, TypeStructField *field); static bool value_cmp_numeric_val_any(ZigValue *left, Cmp predicate, ZigValue *right); static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *right); static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, TypeStructField *field); @@ -276,195 +276,195 @@ static Error ir_resolve_lazy_recurse(AstNode *source_node, ZigValue *val); static Error ir_resolve_lazy_recurse_array(AstNode *source_node, ZigValue *val, size_t len); -static void ir_assert_impl(bool ok, IrInstGen *source_instruction, char const *file, unsigned int line) { +static void ir_assert_impl(bool ok, Stage1AirInst *source_instruction, char const *file, unsigned int line) { if (ok) return; src_assert_impl(ok, source_instruction->source_node, file, line); } #define ir_assert(OK, SOURCE_INSTRUCTION) ir_assert_impl((OK), (SOURCE_INSTRUCTION), __FILE__, __LINE__) -void destroy_instruction_gen(IrInstGen *inst) { +void destroy_instruction_gen(Stage1AirInst *inst) { switch (inst->id) { - case IrInstGenIdInvalid: + case Stage1AirInstIdInvalid: zig_unreachable(); - case IrInstGenIdReturn: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdConst: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBinOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdCall: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdCondBr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdPhi: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdUnreachable: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdElemPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdVarPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdReturnPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdLoadPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdStorePtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdVectorStoreElem: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdStructFieldPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdUnionFieldPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAsm: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdTestNonNull: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdOptionalUnwrapPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdPopCount: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdClz: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdCtz: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBswap: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBitReverse: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSwitchBr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdUnionTag: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdRef: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdErrName: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdCmpxchg: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdFence: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdReduce: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdTruncate: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdShuffleVector: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSplat: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBoolNot: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdMemset: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdMemcpy: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSlice: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBreakpoint: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdReturnAddress: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdFrameAddress: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdFrameHandle: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdFrameSize: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdOverflowOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdTestErr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdUnwrapErrCode: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdUnwrapErrPayload: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdOptionalWrap: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdErrWrapCode: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdErrWrapPayload: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdPtrCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBitCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdWidenOrShorten: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdPtrToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdIntToPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdIntToEnum: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdIntToErr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdErrToInt: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdTagName: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdPanic: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdFieldParentPtr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAlignCast: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdErrorReturnTrace: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAtomicRmw: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSaveErrRetAddr: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdFloatOp: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdMulAdd: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAtomicLoad: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAtomicStore: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdDeclVar: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdArrayToVector: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdVectorToArray: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdPtrOfArrayToSlice: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAssertZero: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAssertNonNull: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAlloca: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSuspendBegin: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSuspendFinish: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdResume: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdAwait: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSpillBegin: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdSpillEnd: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdVectorExtractElem: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdBinaryNot: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdNegation: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdWasmMemorySize: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdWasmMemoryGrow: - return heap::c_allocator.destroy(reinterpret_cast(inst)); - case IrInstGenIdExtern: - return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdReturn: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdConst: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBinOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdCall: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdCondBr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdPhi: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdUnreachable: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdElemPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdVarPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdReturnPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdLoadPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdStorePtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdVectorStoreElem: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdStructFieldPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdUnionFieldPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAsm: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdTestNonNull: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdOptionalUnwrapPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdPopCount: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdClz: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdCtz: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBswap: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBitReverse: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSwitchBr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdUnionTag: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdRef: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdErrName: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdCmpxchg: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdFence: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdReduce: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdTruncate: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdShuffleVector: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSplat: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBoolNot: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdMemset: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdMemcpy: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSlice: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBreakpoint: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdReturnAddress: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdFrameAddress: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdFrameHandle: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdFrameSize: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdOverflowOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdTestErr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdUnwrapErrCode: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdUnwrapErrPayload: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdOptionalWrap: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdErrWrapCode: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdErrWrapPayload: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdPtrCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBitCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdWidenOrShorten: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdPtrToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdIntToPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdIntToEnum: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdIntToErr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdErrToInt: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdTagName: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdPanic: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdFieldParentPtr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAlignCast: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdErrorReturnTrace: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAtomicRmw: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSaveErrRetAddr: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdFloatOp: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdMulAdd: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAtomicLoad: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAtomicStore: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdDeclVar: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdArrayToVector: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdVectorToArray: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdPtrOfArrayToSlice: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAssertZero: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAssertNonNull: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAlloca: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSuspendBegin: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSuspendFinish: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdResume: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdAwait: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSpillBegin: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdSpillEnd: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdVectorExtractElem: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdBinaryNot: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdNegation: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdWasmMemorySize: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdWasmMemoryGrow: + return heap::c_allocator.destroy(reinterpret_cast(inst)); + case Stage1AirInstIdExtern: + return heap::c_allocator.destroy(reinterpret_cast(inst)); } zig_unreachable(); } @@ -476,7 +476,7 @@ static void ira_deref(IrAnalyze *ira) { if (ira->ref_count > 1) { ira->ref_count -= 1; - // immediate destruction of dangling IrInstGenConst is not possible + // immediate destruction of dangling Stage1AirInstConst is not possible // free tracking memory because it will never be used ira->new_irb.constants.deinit(&heap::c_allocator); return; @@ -486,7 +486,7 @@ static void ira_deref(IrAnalyze *ira) { for (size_t bb_i = 0; bb_i < ira->zir->basic_block_list.length; bb_i += 1) { Stage1ZirBasicBlock *pass1_bb = ira->zir->basic_block_list.items[bb_i]; for (size_t inst_i = 0; inst_i < pass1_bb->instruction_list.length; inst_i += 1) { - IrInstSrc *pass1_inst = pass1_bb->instruction_list.items[inst_i]; + Stage1ZirInst *pass1_inst = pass1_bb->instruction_list.items[inst_i]; destroy_instruction_src(pass1_inst); } heap::c_allocator.destroy(pass1_bb); @@ -497,7 +497,7 @@ static void ira_deref(IrAnalyze *ira) { ira->src_implicit_return_type_list.deinit(); ira->resume_stack.deinit(); - // destroy dangling IrInstGenConst + // destroy dangling Stage1AirInstConst for (size_t i = 0; i < ira->new_irb.constants.length; i += 1) { auto constant = ira->new_irb.constants.items[i]; if (constant->base.ref_count == 0 && !ir_inst_gen_has_side_effects(&constant->base)) @@ -675,7 +675,7 @@ static bool types_have_same_zig_comptime_repr(CodeGen *codegen, ZigType *expecte zig_unreachable(); } -static void ir_inst_gen_append(IrBasicBlockGen *basic_block, IrInstGen *instruction) { +static void ir_inst_gen_append(Stage1AirBasicBlock *basic_block, Stage1AirInst *instruction) { assert(basic_block); assert(instruction); basic_block->instruction_list.append(instruction); @@ -691,12 +691,12 @@ static bool value_is_comptime(ZigValue *const_val) { return const_val->special != ConstValSpecialRuntime; } -static bool instr_is_comptime(IrInstGen *instruction) { +static bool instr_is_comptime(Stage1AirInst *instruction) { return value_is_comptime(instruction->value); } -static void ir_ref_inst_gen(IrInstGen *instruction) { - assert(instruction->id != IrInstGenIdInvalid); +static void ir_ref_inst_gen(Stage1AirInst *instruction) { + assert(instruction->id != Stage1AirInstIdInvalid); instruction->ref_count += 1; } @@ -739,374 +739,374 @@ ZigType *ir_analyze_type_expr(IrAnalyze *ira, Scope *scope, AstNode *node) { return res_type; } -static IrBasicBlockGen *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope, const char *name_hint) { - IrBasicBlockGen *result = heap::c_allocator.create(); +static Stage1AirBasicBlock *ir_create_basic_block_gen(IrAnalyze *ira, Scope *scope, const char *name_hint) { + Stage1AirBasicBlock *result = heap::c_allocator.create(); result->scope = scope; result->name_hint = name_hint; result->debug_id = exec_next_debug_id_gen(ira->new_irb.exec); return result; } -static IrBasicBlockGen *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) { - IrBasicBlockGen *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint); +static Stage1AirBasicBlock *ir_build_bb_from(IrAnalyze *ira, Stage1ZirBasicBlock *other_bb) { + Stage1AirBasicBlock *new_bb = ir_create_basic_block_gen(ira, other_bb->scope, other_bb->name_hint); other_bb->child = new_bb; return new_bb; } -static constexpr IrInstGenId ir_inst_id(IrInstGenDeclVar *) { - return IrInstGenIdDeclVar; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstDeclVar *) { + return Stage1AirInstIdDeclVar; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBr *) { - return IrInstGenIdBr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBr *) { + return Stage1AirInstIdBr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenCondBr *) { - return IrInstGenIdCondBr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCondBr *) { + return Stage1AirInstIdCondBr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSwitchBr *) { - return IrInstGenIdSwitchBr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSwitchBr *) { + return Stage1AirInstIdSwitchBr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenPhi *) { - return IrInstGenIdPhi; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPhi *) { + return Stage1AirInstIdPhi; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBinaryNot *) { - return IrInstGenIdBinaryNot; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBinaryNot *) { + return Stage1AirInstIdBinaryNot; } -static constexpr IrInstGenId ir_inst_id(IrInstGenNegation *) { - return IrInstGenIdNegation; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstNegation *) { + return Stage1AirInstIdNegation; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBinOp *) { - return IrInstGenIdBinOp; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBinOp *) { + return Stage1AirInstIdBinOp; } -static constexpr IrInstGenId ir_inst_id(IrInstGenLoadPtr *) { - return IrInstGenIdLoadPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstLoadPtr *) { + return Stage1AirInstIdLoadPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenStorePtr *) { - return IrInstGenIdStorePtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstStorePtr *) { + return Stage1AirInstIdStorePtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenVectorStoreElem *) { - return IrInstGenIdVectorStoreElem; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorStoreElem *) { + return Stage1AirInstIdVectorStoreElem; } -static constexpr IrInstGenId ir_inst_id(IrInstGenStructFieldPtr *) { - return IrInstGenIdStructFieldPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstStructFieldPtr *) { + return Stage1AirInstIdStructFieldPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenUnionFieldPtr *) { - return IrInstGenIdUnionFieldPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnionFieldPtr *) { + return Stage1AirInstIdUnionFieldPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenElemPtr *) { - return IrInstGenIdElemPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstElemPtr *) { + return Stage1AirInstIdElemPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenVarPtr *) { - return IrInstGenIdVarPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVarPtr *) { + return Stage1AirInstIdVarPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenReturnPtr *) { - return IrInstGenIdReturnPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturnPtr *) { + return Stage1AirInstIdReturnPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenCall *) { - return IrInstGenIdCall; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCall *) { + return Stage1AirInstIdCall; } -static constexpr IrInstGenId ir_inst_id(IrInstGenReturn *) { - return IrInstGenIdReturn; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturn *) { + return Stage1AirInstIdReturn; } -static constexpr IrInstGenId ir_inst_id(IrInstGenCast *) { - return IrInstGenIdCast; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCast *) { + return Stage1AirInstIdCast; } -static constexpr IrInstGenId ir_inst_id(IrInstGenUnreachable *) { - return IrInstGenIdUnreachable; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnreachable *) { + return Stage1AirInstIdUnreachable; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAsm *) { - return IrInstGenIdAsm; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAsm *) { + return Stage1AirInstIdAsm; } -static constexpr IrInstGenId ir_inst_id(IrInstGenTestNonNull *) { - return IrInstGenIdTestNonNull; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTestNonNull *) { + return Stage1AirInstIdTestNonNull; } -static constexpr IrInstGenId ir_inst_id(IrInstGenOptionalUnwrapPtr *) { - return IrInstGenIdOptionalUnwrapPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOptionalUnwrapPtr *) { + return Stage1AirInstIdOptionalUnwrapPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenOptionalWrap *) { - return IrInstGenIdOptionalWrap; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOptionalWrap *) { + return Stage1AirInstIdOptionalWrap; } -static constexpr IrInstGenId ir_inst_id(IrInstGenUnionTag *) { - return IrInstGenIdUnionTag; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnionTag *) { + return Stage1AirInstIdUnionTag; } -static constexpr IrInstGenId ir_inst_id(IrInstGenClz *) { - return IrInstGenIdClz; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstClz *) { + return Stage1AirInstIdClz; } -static constexpr IrInstGenId ir_inst_id(IrInstGenCtz *) { - return IrInstGenIdCtz; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCtz *) { + return Stage1AirInstIdCtz; } -static constexpr IrInstGenId ir_inst_id(IrInstGenPopCount *) { - return IrInstGenIdPopCount; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPopCount *) { + return Stage1AirInstIdPopCount; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBswap *) { - return IrInstGenIdBswap; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBswap *) { + return Stage1AirInstIdBswap; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBitReverse *) { - return IrInstGenIdBitReverse; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBitReverse *) { + return Stage1AirInstIdBitReverse; } -static constexpr IrInstGenId ir_inst_id(IrInstGenRef *) { - return IrInstGenIdRef; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstRef *) { + return Stage1AirInstIdRef; } -static constexpr IrInstGenId ir_inst_id(IrInstGenErrName *) { - return IrInstGenIdErrName; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrName *) { + return Stage1AirInstIdErrName; } -static constexpr IrInstGenId ir_inst_id(IrInstGenCmpxchg *) { - return IrInstGenIdCmpxchg; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstCmpxchg *) { + return Stage1AirInstIdCmpxchg; } -static constexpr IrInstGenId ir_inst_id(IrInstGenFence *) { - return IrInstGenIdFence; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFence *) { + return Stage1AirInstIdFence; } -static constexpr IrInstGenId ir_inst_id(IrInstGenReduce *) { - return IrInstGenIdReduce; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReduce *) { + return Stage1AirInstIdReduce; } -static constexpr IrInstGenId ir_inst_id(IrInstGenTruncate *) { - return IrInstGenIdTruncate; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTruncate *) { + return Stage1AirInstIdTruncate; } -static constexpr IrInstGenId ir_inst_id(IrInstGenShuffleVector *) { - return IrInstGenIdShuffleVector; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstShuffleVector *) { + return Stage1AirInstIdShuffleVector; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSplat *) { - return IrInstGenIdSplat; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSplat *) { + return Stage1AirInstIdSplat; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBoolNot *) { - return IrInstGenIdBoolNot; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBoolNot *) { + return Stage1AirInstIdBoolNot; } -static constexpr IrInstGenId ir_inst_id(IrInstGenMemset *) { - return IrInstGenIdMemset; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMemset *) { + return Stage1AirInstIdMemset; } -static constexpr IrInstGenId ir_inst_id(IrInstGenMemcpy *) { - return IrInstGenIdMemcpy; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMemcpy *) { + return Stage1AirInstIdMemcpy; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSlice *) { - return IrInstGenIdSlice; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSlice *) { + return Stage1AirInstIdSlice; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBreakpoint *) { - return IrInstGenIdBreakpoint; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBreakpoint *) { + return Stage1AirInstIdBreakpoint; } -static constexpr IrInstGenId ir_inst_id(IrInstGenReturnAddress *) { - return IrInstGenIdReturnAddress; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstReturnAddress *) { + return Stage1AirInstIdReturnAddress; } -static constexpr IrInstGenId ir_inst_id(IrInstGenFrameAddress *) { - return IrInstGenIdFrameAddress; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameAddress *) { + return Stage1AirInstIdFrameAddress; } -static constexpr IrInstGenId ir_inst_id(IrInstGenFrameHandle *) { - return IrInstGenIdFrameHandle; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameHandle *) { + return Stage1AirInstIdFrameHandle; } -static constexpr IrInstGenId ir_inst_id(IrInstGenFrameSize *) { - return IrInstGenIdFrameSize; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFrameSize *) { + return Stage1AirInstIdFrameSize; } -static constexpr IrInstGenId ir_inst_id(IrInstGenOverflowOp *) { - return IrInstGenIdOverflowOp; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstOverflowOp *) { + return Stage1AirInstIdOverflowOp; } -static constexpr IrInstGenId ir_inst_id(IrInstGenTestErr *) { - return IrInstGenIdTestErr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTestErr *) { + return Stage1AirInstIdTestErr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenMulAdd *) { - return IrInstGenIdMulAdd; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstMulAdd *) { + return Stage1AirInstIdMulAdd; } -static constexpr IrInstGenId ir_inst_id(IrInstGenFloatOp *) { - return IrInstGenIdFloatOp; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFloatOp *) { + return Stage1AirInstIdFloatOp; } -static constexpr IrInstGenId ir_inst_id(IrInstGenUnwrapErrCode *) { - return IrInstGenIdUnwrapErrCode; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnwrapErrCode *) { + return Stage1AirInstIdUnwrapErrCode; } -static constexpr IrInstGenId ir_inst_id(IrInstGenUnwrapErrPayload *) { - return IrInstGenIdUnwrapErrPayload; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstUnwrapErrPayload *) { + return Stage1AirInstIdUnwrapErrPayload; } -static constexpr IrInstGenId ir_inst_id(IrInstGenErrWrapCode *) { - return IrInstGenIdErrWrapCode; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrWrapCode *) { + return Stage1AirInstIdErrWrapCode; } -static constexpr IrInstGenId ir_inst_id(IrInstGenErrWrapPayload *) { - return IrInstGenIdErrWrapPayload; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrWrapPayload *) { + return Stage1AirInstIdErrWrapPayload; } -static constexpr IrInstGenId ir_inst_id(IrInstGenPtrCast *) { - return IrInstGenIdPtrCast; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrCast *) { + return Stage1AirInstIdPtrCast; } -static constexpr IrInstGenId ir_inst_id(IrInstGenBitCast *) { - return IrInstGenIdBitCast; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstBitCast *) { + return Stage1AirInstIdBitCast; } -static constexpr IrInstGenId ir_inst_id(IrInstGenWidenOrShorten *) { - return IrInstGenIdWidenOrShorten; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWidenOrShorten *) { + return Stage1AirInstIdWidenOrShorten; } -static constexpr IrInstGenId ir_inst_id(IrInstGenIntToPtr *) { - return IrInstGenIdIntToPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToPtr *) { + return Stage1AirInstIdIntToPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenPtrToInt *) { - return IrInstGenIdPtrToInt; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrToInt *) { + return Stage1AirInstIdPtrToInt; } -static constexpr IrInstGenId ir_inst_id(IrInstGenIntToEnum *) { - return IrInstGenIdIntToEnum; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToEnum *) { + return Stage1AirInstIdIntToEnum; } -static constexpr IrInstGenId ir_inst_id(IrInstGenIntToErr *) { - return IrInstGenIdIntToErr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstIntToErr *) { + return Stage1AirInstIdIntToErr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenErrToInt *) { - return IrInstGenIdErrToInt; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrToInt *) { + return Stage1AirInstIdErrToInt; } -static constexpr IrInstGenId ir_inst_id(IrInstGenPanic *) { - return IrInstGenIdPanic; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPanic *) { + return Stage1AirInstIdPanic; } -static constexpr IrInstGenId ir_inst_id(IrInstGenTagName *) { - return IrInstGenIdTagName; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstTagName *) { + return Stage1AirInstIdTagName; } -static constexpr IrInstGenId ir_inst_id(IrInstGenFieldParentPtr *) { - return IrInstGenIdFieldParentPtr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstFieldParentPtr *) { + return Stage1AirInstIdFieldParentPtr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAlignCast *) { - return IrInstGenIdAlignCast; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAlignCast *) { + return Stage1AirInstIdAlignCast; } -static constexpr IrInstGenId ir_inst_id(IrInstGenErrorReturnTrace *) { - return IrInstGenIdErrorReturnTrace; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstErrorReturnTrace *) { + return Stage1AirInstIdErrorReturnTrace; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicRmw *) { - return IrInstGenIdAtomicRmw; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicRmw *) { + return Stage1AirInstIdAtomicRmw; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicLoad *) { - return IrInstGenIdAtomicLoad; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicLoad *) { + return Stage1AirInstIdAtomicLoad; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAtomicStore *) { - return IrInstGenIdAtomicStore; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAtomicStore *) { + return Stage1AirInstIdAtomicStore; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSaveErrRetAddr *) { - return IrInstGenIdSaveErrRetAddr; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSaveErrRetAddr *) { + return Stage1AirInstIdSaveErrRetAddr; } -static constexpr IrInstGenId ir_inst_id(IrInstGenVectorToArray *) { - return IrInstGenIdVectorToArray; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorToArray *) { + return Stage1AirInstIdVectorToArray; } -static constexpr IrInstGenId ir_inst_id(IrInstGenArrayToVector *) { - return IrInstGenIdArrayToVector; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstArrayToVector *) { + return Stage1AirInstIdArrayToVector; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAssertZero *) { - return IrInstGenIdAssertZero; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAssertZero *) { + return Stage1AirInstIdAssertZero; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAssertNonNull *) { - return IrInstGenIdAssertNonNull; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAssertNonNull *) { + return Stage1AirInstIdAssertNonNull; } -static constexpr IrInstGenId ir_inst_id(IrInstGenPtrOfArrayToSlice *) { - return IrInstGenIdPtrOfArrayToSlice; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstPtrOfArrayToSlice *) { + return Stage1AirInstIdPtrOfArrayToSlice; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSuspendBegin *) { - return IrInstGenIdSuspendBegin; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSuspendBegin *) { + return Stage1AirInstIdSuspendBegin; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSuspendFinish *) { - return IrInstGenIdSuspendFinish; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSuspendFinish *) { + return Stage1AirInstIdSuspendFinish; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAwait *) { - return IrInstGenIdAwait; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAwait *) { + return Stage1AirInstIdAwait; } -static constexpr IrInstGenId ir_inst_id(IrInstGenResume *) { - return IrInstGenIdResume; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstResume *) { + return Stage1AirInstIdResume; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSpillBegin *) { - return IrInstGenIdSpillBegin; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSpillBegin *) { + return Stage1AirInstIdSpillBegin; } -static constexpr IrInstGenId ir_inst_id(IrInstGenSpillEnd *) { - return IrInstGenIdSpillEnd; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstSpillEnd *) { + return Stage1AirInstIdSpillEnd; } -static constexpr IrInstGenId ir_inst_id(IrInstGenVectorExtractElem *) { - return IrInstGenIdVectorExtractElem; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstVectorExtractElem *) { + return Stage1AirInstIdVectorExtractElem; } -static constexpr IrInstGenId ir_inst_id(IrInstGenAlloca *) { - return IrInstGenIdAlloca; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstAlloca *) { + return Stage1AirInstIdAlloca; } -static constexpr IrInstGenId ir_inst_id(IrInstGenConst *) { - return IrInstGenIdConst; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstConst *) { + return Stage1AirInstIdConst; } -static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemorySize *) { - return IrInstGenIdWasmMemorySize; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWasmMemorySize *) { + return Stage1AirInstIdWasmMemorySize; } -static constexpr IrInstGenId ir_inst_id(IrInstGenWasmMemoryGrow *) { - return IrInstGenIdWasmMemoryGrow; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstWasmMemoryGrow *) { + return Stage1AirInstIdWasmMemoryGrow; } -static constexpr IrInstGenId ir_inst_id(IrInstGenExtern *) { - return IrInstGenIdExtern; +static constexpr Stage1AirInstId ir_inst_id(Stage1AirInstExtern *) { + return Stage1AirInstIdExtern; } template @@ -1155,11 +1155,11 @@ static T *ir_build_inst_void(IrBuilderGen *irb, Scope *scope, AstNode *source_no return special_instruction; } -IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn, +Stage1AirInst *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn, ZigType *var_type, const char *name_hint) { - IrInstGenAlloca *alloca_gen = heap::c_allocator.create(); - alloca_gen->base.id = IrInstGenIdAlloca; + Stage1AirInstAlloca *alloca_gen = heap::c_allocator.create(); + alloca_gen->base.id = Stage1AirInstIdAlloca; alloca_gen->base.source_node = source_node; alloca_gen->base.scope = scope; alloca_gen->base.value = g->pass1_arena->create(); @@ -1170,10 +1170,10 @@ IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigF return &alloca_gen->base; } -static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *dest_type, IrInstGen *value, CastOp cast_op) +static Stage1AirInst *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *dest_type, Stage1AirInst *value, CastOp cast_op) { - IrInstGenCast *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstCast *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = dest_type; inst->value = value; inst->cast_op = cast_op; @@ -1183,10 +1183,10 @@ static IrInstGen *ir_build_cast(IrAnalyze *ira, Scope *scope, AstNode *source_no return &inst->base; } -static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *condition, - IrBasicBlockGen *then_block, IrBasicBlockGen *else_block) +static Stage1AirInst *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *condition, + Stage1AirBasicBlock *then_block, Stage1AirBasicBlock *else_block) { - IrInstGenCondBr *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); + Stage1AirInstCondBr *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); inst->condition = condition; inst->then_block = then_block; inst->else_block = else_block; @@ -1196,8 +1196,8 @@ static IrInstGen *ir_build_cond_br_gen(IrAnalyze *ira, Scope *scope, AstNode *so return &inst->base; } -static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand) { - IrInstGenReturn *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand) { + Stage1AirInstReturn *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); inst->operand = operand; if (operand != nullptr) ir_ref_inst_gen(operand); @@ -1205,10 +1205,10 @@ static IrInstGen *ir_build_return_gen(IrAnalyze *ira, Scope *scope, AstNode *sou return &inst->base; } -static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *res_type, - IrBinOp op_id, IrInstGen *op1, IrInstGen *op2, bool safety_check_on) +static Stage1AirInst *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *res_type, + IrBinOp op_id, Stage1AirInst *op1, Stage1AirInst *op2, bool safety_check_on) { - IrInstGenBinOp *inst = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstBinOp *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = res_type; inst->op_id = op_id; @@ -1223,8 +1223,8 @@ static IrInstGen *ir_build_bin_op_gen(IrAnalyze *ira, Scope *scope, AstNode *sou } -static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) { - IrInstGenVarPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) { + Stage1AirInstVarPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->var = var; var->ref_count += 1; @@ -1232,16 +1232,16 @@ static IrInstGen *ir_build_var_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *so return &instruction->base; } -static IrInstGen *ir_build_return_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { - IrInstGenReturnPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_return_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { + Stage1AirInstReturnPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ty; return &instruction->base; } -static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *array_ptr, IrInstGen *elem_index, bool safety_check_on, ZigType *return_type) +static Stage1AirInst *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *array_ptr, Stage1AirInst *elem_index, bool safety_check_on, ZigType *return_type) { - IrInstGenElemPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstElemPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = return_type; instruction->array_ptr = array_ptr; instruction->elem_index = elem_index; @@ -1253,10 +1253,10 @@ static IrInstGen *ir_build_elem_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *struct_ptr, TypeStructField *field, ZigType *ptr_type) +static Stage1AirInst *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *struct_ptr, TypeStructField *field, ZigType *ptr_type) { - IrInstGenStructFieldPtr *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstStructFieldPtr *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ptr_type; inst->struct_ptr = struct_ptr; inst->field = field; @@ -1266,10 +1266,10 @@ static IrInstGen *ir_build_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNod return &inst->base; } -static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *union_ptr, TypeUnionField *field, bool safety_check_on, bool initializing, ZigType *ptr_type) +static Stage1AirInst *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *union_ptr, TypeUnionField *field, bool safety_check_on, bool initializing, ZigType *ptr_type) { - IrInstGenUnionFieldPtr *inst = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstUnionFieldPtr *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ptr_type; inst->initializing = initializing; @@ -1282,12 +1282,12 @@ static IrInstGen *ir_build_union_field_ptr(IrAnalyze *ira, Scope *scope, AstNode return &inst->base; } -static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigFn *fn_entry, IrInstGen *fn_ref, size_t arg_count, IrInstGen **args, - CallModifier modifier, IrInstGen *new_stack, bool is_async_call_builtin, - IrInstGen *result_loc, ZigType *return_type) +static Stage1AirInstCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigFn *fn_entry, Stage1AirInst *fn_ref, size_t arg_count, Stage1AirInst **args, + CallModifier modifier, Stage1AirInst *new_stack, bool is_async_call_builtin, + Stage1AirInst *result_loc, ZigType *return_type) { - IrInstGenCall *call_instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstCall *call_instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); call_instruction->base.value->type = return_type; call_instruction->fn_entry = fn_entry; @@ -1308,13 +1308,13 @@ static IrInstGenCall *ir_build_call_gen(IrAnalyze *ira, Scope *scope, AstNode *s return call_instruction; } -static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, size_t incoming_count, - IrBasicBlockGen **incoming_blocks, IrInstGen **incoming_values, ZigType *result_type) +static Stage1AirInst *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, size_t incoming_count, + Stage1AirBasicBlock **incoming_blocks, Stage1AirInst **incoming_values, ZigType *result_type) { assert(incoming_count != 0); assert(incoming_count != SIZE_MAX); - IrInstGenPhi *phi_instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstPhi *phi_instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); phi_instruction->base.value->type = result_type; phi_instruction->incoming_count = incoming_count; @@ -1328,15 +1328,15 @@ static IrInstGen *ir_build_phi_gen(IrAnalyze *ira, Scope *scope, AstNode *source return &phi_instruction->base; } -static IrInstGen *ir_build_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrBasicBlockGen *dest_block) { - IrInstGenBr *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirBasicBlock *dest_block) { + Stage1AirInstBr *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); inst->dest_block = dest_block; return &inst->base; } -static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand, ZigType *expr_type, bool wrapping) { - IrInstGenNegation *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand, ZigType *expr_type, bool wrapping) { + Stage1AirInstNegation *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = expr_type; instruction->operand = operand; @@ -1347,10 +1347,10 @@ static IrInstGen *ir_build_negation(IrAnalyze *ira, Scope *scope, AstNode *sourc return &instruction->base; } -static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand, +static Stage1AirInst *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand, ZigType *expr_type) { - IrInstGenBinaryNot *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstBinaryNot *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = expr_type; instruction->operand = operand; @@ -1360,13 +1360,13 @@ static IrInstGen *ir_build_binary_not(IrAnalyze *ira, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstGen *ir_build_unreachable_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenUnreachable *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_unreachable_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstUnreachable *inst = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); return &inst->base; } -static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr, IrInstGen *value) { - IrInstGenStorePtr *instruction = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr, Stage1AirInst *value) { + Stage1AirInstStorePtr *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->ptr = ptr; instruction->value = value; @@ -1377,10 +1377,10 @@ static IrInstGen *ir_build_store_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode * return &instruction->base; } -static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *vector_ptr, IrInstGen *index, IrInstGen *value) +static Stage1AirInst *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *vector_ptr, Stage1AirInst *index, Stage1AirInst *value) { - IrInstGenVectorStoreElem *inst = ir_build_inst_void( + Stage1AirInstVectorStoreElem *inst = ir_build_inst_void( &ira->new_irb, scope, source_node); inst->vector_ptr = vector_ptr; inst->index = index; @@ -1393,10 +1393,10 @@ static IrInstGen *ir_build_vector_store_elem(IrAnalyze *ira, Scope *scope, AstNo return &inst->base; } -static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigVar *var, IrInstGen *var_ptr) +static Stage1AirInst *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigVar *var, Stage1AirInst *var_ptr) { - IrInstGenDeclVar *inst = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstDeclVar *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->special = ConstValSpecialStatic; inst->base.value->type = ira->codegen->builtin_types.entry_void; @@ -1408,10 +1408,10 @@ static IrInstGen *ir_build_var_decl_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &inst->base; } -static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *name, +static Stage1AirInst *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *name, GlobalLinkageId linkage, bool is_thread_local, ZigType *expr_type) { - IrInstGenExtern *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstExtern *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = expr_type; instruction->name = name; @@ -1421,10 +1421,10 @@ static IrInstGen *ir_build_extern_gen(IrAnalyze *ira, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, ZigType *ty, IrInstGen *result_loc) +static Stage1AirInst *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, ZigType *ty, Stage1AirInst *result_loc) { - IrInstGenLoadPtr *instruction = ir_build_inst_gen( + Stage1AirInstLoadPtr *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = ty; instruction->ptr = ptr; @@ -1436,12 +1436,12 @@ static IrInstGen *ir_build_load_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, +static Stage1AirInst *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Buf *asm_template, AsmToken *token_list, size_t token_list_len, - IrInstGen **input_list, IrInstGen **output_types, ZigVar **output_vars, size_t return_count, + Stage1AirInst **input_list, Stage1AirInst **output_types, ZigVar **output_vars, size_t return_count, bool has_side_effects, ZigType *return_type) { - IrInstGenAsm *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstAsm *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = return_type; instruction->asm_template = asm_template; instruction->token_list = token_list; @@ -1454,20 +1454,20 @@ static IrInstGen *ir_build_asm_gen(IrAnalyze *ira, Scope *scope, AstNode *source assert(source_node->type == NodeTypeAsmExpr); for (size_t i = 0; i < source_node->data.asm_expr.output_list.length; i += 1) { - IrInstGen *output_type = output_types[i]; + Stage1AirInst *output_type = output_types[i]; if (output_type) ir_ref_inst_gen(output_type); } for (size_t i = 0; i < source_node->data.asm_expr.input_list.length; i += 1) { - IrInstGen *input_value = input_list[i]; + Stage1AirInst *input_value = input_list[i]; ir_ref_inst_gen(input_value); } return &instruction->base; } -static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) { - IrInstGenTestNonNull *inst = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) { + Stage1AirInstTestNonNull *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ira->codegen->builtin_types.entry_bool; inst->value = value; @@ -1477,10 +1477,10 @@ static IrInstGen *ir_build_test_non_null_gen(IrAnalyze *ira, Scope *scope, AstNo return &inst->base; } -static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool safety_check_on, bool initializing, ZigType *result_type) +static Stage1AirInst *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool safety_check_on, bool initializing, ZigType *result_type) { - IrInstGenOptionalUnwrapPtr *inst = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstOptionalUnwrapPtr *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->base_ptr = base_ptr; @@ -1492,10 +1492,10 @@ static IrInstGen *ir_build_optional_unwrap_ptr_gen(IrAnalyze *ira, Scope *scope, return &inst->base; } -static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_ty, - IrInstGen *operand, IrInstGen *result_loc) +static Stage1AirInst *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_ty, + Stage1AirInst *operand, Stage1AirInst *result_loc) { - IrInstGenOptionalWrap *instruction = ir_build_inst_gen( + Stage1AirInstOptionalWrap *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = result_ty; instruction->operand = operand; @@ -1507,10 +1507,10 @@ static IrInstGen *ir_build_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode * return &instruction->base; } -static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc) +static Stage1AirInst *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc) { - IrInstGenErrWrapPayload *instruction = ir_build_inst_gen( + Stage1AirInstErrWrapPayload *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->operand = operand; @@ -1522,10 +1522,10 @@ static IrInstGen *ir_build_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNod return &instruction->base; } -static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc) +static Stage1AirInst *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc) { - IrInstGenErrWrapCode *instruction = ir_build_inst_gen( + Stage1AirInstErrWrapCode *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->operand = operand; @@ -1537,8 +1537,8 @@ static IrInstGen *ir_build_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode * return &instruction->base; } -static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, IrInstGen *op) { - IrInstGenClz *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, Stage1AirInst *op) { + Stage1AirInstClz *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->op = op; @@ -1548,8 +1548,8 @@ static IrInstGen *ir_build_clz_gen(IrAnalyze *ira, Scope *scope, AstNode *source return &instruction->base; } -static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, IrInstGen *op) { - IrInstGenCtz *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, Stage1AirInst *op) { + Stage1AirInstCtz *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->op = op; @@ -1559,10 +1559,10 @@ static IrInstGen *ir_build_ctz_gen(IrAnalyze *ira, Scope *scope, AstNode *source return &instruction->base; } -static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, - IrInstGen *op) +static Stage1AirInst *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, + Stage1AirInst *op) { - IrInstGenPopCount *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstPopCount *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->op = op; @@ -1572,10 +1572,10 @@ static IrInstGen *ir_build_pop_count_gen(IrAnalyze *ira, Scope *scope, AstNode * return &instruction->base; } -static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *op_type, - IrInstGen *op) +static Stage1AirInst *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *op_type, + Stage1AirInst *op) { - IrInstGenBswap *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstBswap *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = op_type; instruction->op = op; @@ -1585,10 +1585,10 @@ static IrInstGen *ir_build_bswap_gen(IrAnalyze *ira, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *int_type, - IrInstGen *op) +static Stage1AirInst *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *int_type, + Stage1AirInst *op) { - IrInstGenBitReverse *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstBitReverse *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = int_type; instruction->op = op; @@ -1598,10 +1598,10 @@ static IrInstGen *ir_build_bit_reverse_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target_value, IrBasicBlockGen *else_block, size_t case_count, IrInstGenSwitchBrCase *cases) +static Stage1AirInstSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target_value, Stage1AirBasicBlock *else_block, size_t case_count, Stage1AirInstSwitchBrCase *cases) { - IrInstGenSwitchBr *instruction = ir_build_inst_noreturn(&ira->new_irb, + Stage1AirInstSwitchBr *instruction = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); instruction->target_value = target_value; instruction->else_block = else_block; @@ -1617,10 +1617,10 @@ static IrInstGenSwitchBr *ir_build_switch_br_gen(IrAnalyze *ira, Scope *scope, A return instruction; } -static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *tag_type) { - IrInstGenUnionTag *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstUnionTag *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->value = value; instruction->base.value->type = tag_type; @@ -1630,10 +1630,10 @@ static IrInstGen *ir_build_union_tag(IrAnalyze *ira, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, - IrInstGen *operand, IrInstGen *result_loc) +static Stage1AirInst *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, + Stage1AirInst *operand, Stage1AirInst *result_loc) { - IrInstGenRef *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstRef *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->operand = operand; @@ -1645,10 +1645,10 @@ static IrInstGen *ir_build_ref_gen(IrAnalyze *ira, Scope *scope, AstNode *source return &instruction->base; } -static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *str_type) { - IrInstGenErrName *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstErrName *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = str_type; instruction->value = value; @@ -1658,11 +1658,11 @@ static IrInstGen *ir_build_err_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, - IrInstGen *ptr, IrInstGen *cmp_value, IrInstGen *new_value, - AtomicOrder success_order, AtomicOrder failure_order, bool is_weak, IrInstGen *result_loc) +static Stage1AirInst *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, + Stage1AirInst *ptr, Stage1AirInst *cmp_value, Stage1AirInst *new_value, + AtomicOrder success_order, AtomicOrder failure_order, bool is_weak, Stage1AirInst *result_loc) { - IrInstGenCmpxchg *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstCmpxchg *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->ptr = ptr; @@ -1681,16 +1681,16 @@ static IrInstGen *ir_build_cmpxchg_gen(IrAnalyze *ira, Scope *scope, AstNode *so return &instruction->base; } -static IrInstGen *ir_build_fence_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, AtomicOrder order) { - IrInstGenFence *instruction = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_fence_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, AtomicOrder order) { + Stage1AirInstFence *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->order = order; return &instruction->base; } -static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ReduceOp op, IrInstGen *value, ZigType *result_type) { - IrInstGenReduce *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ReduceOp op, Stage1AirInst *value, ZigType *result_type) { + Stage1AirInstReduce *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->op = op; @@ -1701,38 +1701,38 @@ static IrInstGen *ir_build_reduce_gen(IrAnalyze *ira, Scope *scope, AstNode *sou return &instruction->base; } -static void ir_set_cursor_at_end_gen(IrBuilderGen *irb, IrBasicBlockGen *basic_block) { +static void ir_set_cursor_at_end_gen(IrBuilderGen *irb, Stage1AirBasicBlock *basic_block) { assert(basic_block); irb->current_basic_block = basic_block; } -static void ir_append_basic_block_gen(IrBuilderGen *irb, IrBasicBlockGen *bb) { +static void ir_append_basic_block_gen(IrBuilderGen *irb, Stage1AirBasicBlock *bb) { assert(!bb->already_appended); bb->already_appended = true; irb->exec->basic_block_list.append(bb); } -static void ir_set_cursor_at_end_and_append_block_gen(IrBuilderGen *irb, IrBasicBlockGen *basic_block) { +static void ir_set_cursor_at_end_and_append_block_gen(IrBuilderGen *irb, Stage1AirBasicBlock *basic_block) { ir_append_basic_block_gen(irb, basic_block); ir_set_cursor_at_end_gen(irb, basic_block); } -static IrInstGen *ir_build_suspend_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenSuspendBegin *inst = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_suspend_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstSuspendBegin *inst = ir_build_inst_void(&ira->new_irb, scope, source_node); return &inst->base; } -static IrInstGen *ir_build_save_err_ret_addr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenSaveErrRetAddr *inst = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_save_err_ret_addr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstSaveErrRetAddr *inst = ir_build_inst_void(&ira->new_irb, scope, source_node); return &inst->base; } -static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *dest_type, - IrInstGen *target) +static Stage1AirInst *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *dest_type, + Stage1AirInst *target) { - IrInstGenTruncate *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstTruncate *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = dest_type; instruction->target = target; @@ -1742,10 +1742,10 @@ static IrInstGen *ir_build_truncate_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *result_type, IrInstGen *a, IrInstGen *b, IrInstGen *mask) +static Stage1AirInst *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *result_type, Stage1AirInst *a, Stage1AirInst *b, Stage1AirInst *mask) { - IrInstGenShuffleVector *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstShuffleVector *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->a = a; inst->b = b; @@ -1758,10 +1758,10 @@ static IrInstGen *ir_build_shuffle_vector_gen(IrAnalyze *ira, Scope *scope, AstN return &inst->base; } -static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, - IrInstGen *scalar) +static Stage1AirInst *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *result_type, + Stage1AirInst *scalar) { - IrInstGenSplat *instruction = ir_build_inst_gen( + Stage1AirInstSplat *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->scalar = scalar; @@ -1771,8 +1771,8 @@ static IrInstGen *ir_build_splat_gen(IrAnalyze *ira, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) { - IrInstGenBoolNot *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) { + Stage1AirInstBoolNot *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_bool; instruction->value = value; @@ -1782,10 +1782,10 @@ static IrInstGen *ir_build_bool_not_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *dest_ptr, IrInstGen *byte, IrInstGen *count) +static Stage1AirInst *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *dest_ptr, Stage1AirInst *byte, Stage1AirInst *count) { - IrInstGenMemset *instruction = ir_build_inst_void(&ira->new_irb, + Stage1AirInstMemset *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->dest_ptr = dest_ptr; instruction->byte = byte; @@ -1798,10 +1798,10 @@ static IrInstGen *ir_build_memset_gen(IrAnalyze *ira, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *dest_ptr, IrInstGen *src_ptr, IrInstGen *count) +static Stage1AirInst *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *dest_ptr, Stage1AirInst *src_ptr, Stage1AirInst *count) { - IrInstGenMemcpy *instruction = ir_build_inst_void(&ira->new_irb, + Stage1AirInstMemcpy *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->dest_ptr = dest_ptr; instruction->src_ptr = src_ptr; @@ -1814,11 +1814,11 @@ static IrInstGen *ir_build_memcpy_gen(IrAnalyze *ira, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *slice_type, - IrInstGen *ptr, IrInstGen *start, IrInstGen *end, bool safety_check_on, IrInstGen *result_loc, +static Stage1AirInst *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *slice_type, + Stage1AirInst *ptr, Stage1AirInst *start, Stage1AirInst *end, bool safety_check_on, Stage1AirInst *result_loc, ZigValue *sentinel) { - IrInstGenSlice *instruction = ir_build_inst_gen( + Stage1AirInstSlice *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = slice_type; instruction->ptr = ptr; @@ -1836,33 +1836,33 @@ static IrInstGen *ir_build_slice_gen(IrAnalyze *ira, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstGen *ir_build_breakpoint_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenBreakpoint *instruction = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_breakpoint_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstBreakpoint *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); return &instruction->base; } -static IrInstGen *ir_build_return_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenReturnAddress *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_return_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstReturnAddress *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ira->codegen->builtin_types.entry_usize; return &inst->base; } -static IrInstGen *ir_build_frame_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenFrameAddress *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_frame_address_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstFrameAddress *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ira->codegen->builtin_types.entry_usize; return &inst->base; } -static IrInstGen *ir_build_handle_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { - IrInstGenFrameHandle *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_handle_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { + Stage1AirInstFrameHandle *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ty; return &inst->base; } -static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *fn) +static Stage1AirInst *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *fn) { - IrInstGenFrameSize *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstFrameSize *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ira->codegen->builtin_types.entry_usize; inst->fn = fn; @@ -1871,11 +1871,11 @@ static IrInstGen *ir_build_frame_size_gen(IrAnalyze *ira, Scope *scope, AstNode return &inst->base; } -static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrOverflowOp op, IrInstGen *op1, IrInstGen *op2, IrInstGen *result_ptr, +static Stage1AirInst *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + IrOverflowOp op, Stage1AirInst *op1, Stage1AirInst *op2, Stage1AirInst *result_ptr, ZigType *result_ptr_type) { - IrInstGenOverflowOp *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstOverflowOp *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_bool; instruction->op = op; @@ -1891,10 +1891,10 @@ static IrInstGen *ir_build_overflow_op_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand, +static Stage1AirInst *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand, BuiltinFnId fn_id, ZigType *operand_type) { - IrInstGenFloatOp *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstFloatOp *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = operand_type; instruction->operand = operand; @@ -1905,10 +1905,10 @@ static IrInstGen *ir_build_float_op_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *op1, IrInstGen *op2, - IrInstGen *op3, ZigType *expr_type) +static Stage1AirInst *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *op1, Stage1AirInst *op2, + Stage1AirInst *op3, ZigType *expr_type) { - IrInstGenMulAdd *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstMulAdd *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = expr_type; instruction->op1 = op1; @@ -1922,8 +1922,8 @@ static IrInstGen *ir_build_mul_add_gen(IrAnalyze *ira, Scope *scope, AstNode *so return &instruction->base; } -static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *err_union) { - IrInstGenTestErr *instruction = ir_build_inst_gen( +static Stage1AirInst *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *err_union) { + Stage1AirInstTestErr *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_bool; instruction->err_union = err_union; @@ -1933,10 +1933,10 @@ static IrInstGen *ir_build_test_err_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *err_union_ptr, ZigType *result_type) +static Stage1AirInst *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *err_union_ptr, ZigType *result_type) { - IrInstGenUnwrapErrCode *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstUnwrapErrCode *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->err_union_ptr = err_union_ptr; @@ -1945,10 +1945,10 @@ static IrInstGen *ir_build_unwrap_err_code_gen(IrAnalyze *ira, Scope *scope, Ast return &inst->base; } -static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, bool safety_check_on, bool initializing, ZigType *result_type) +static Stage1AirInst *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, bool safety_check_on, bool initializing, ZigType *result_type) { - IrInstGenUnwrapErrPayload *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstUnwrapErrPayload *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->value = value; inst->safety_check_on = safety_check_on; @@ -1959,10 +1959,10 @@ static IrInstGen *ir_build_unwrap_err_payload_gen(IrAnalyze *ira, Scope *scope, return &inst->base; } -static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *ptr_type, IrInstGen *ptr, bool safety_check_on) +static Stage1AirInst *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *ptr_type, Stage1AirInst *ptr, bool safety_check_on) { - IrInstGenPtrCast *instruction = ir_build_inst_gen( + Stage1AirInstPtrCast *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = ptr_type; instruction->ptr = ptr; @@ -1973,10 +1973,10 @@ static IrInstGen *ir_build_ptr_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *operand, ZigType *ty) +static Stage1AirInst *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *operand, ZigType *ty) { - IrInstGenBitCast *instruction = ir_build_inst_gen( + Stage1AirInstBitCast *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = ty; instruction->operand = operand; @@ -1986,10 +1986,10 @@ static IrInstGen *ir_build_bit_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *result_type) { - IrInstGenWidenOrShorten *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstWidenOrShorten *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->target = target; @@ -1998,10 +1998,10 @@ static IrInstGen *ir_build_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNod return &inst->base; } -static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target, ZigType *ptr_type) +static Stage1AirInst *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target, ZigType *ptr_type) { - IrInstGenIntToPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstIntToPtr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ptr_type; instruction->target = target; @@ -2010,8 +2010,8 @@ static IrInstGen *ir_build_int_to_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target) { - IrInstGenPtrToInt *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); +static Stage1AirInst *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target) { + Stage1AirInstPtrToInt *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = ira->codegen->builtin_types.entry_usize; inst->target = target; @@ -2020,10 +2020,10 @@ static IrInstGen *ir_build_ptr_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode return &inst->base; } -static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *dest_type, IrInstGen *target) +static Stage1AirInst *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *dest_type, Stage1AirInst *target) { - IrInstGenIntToEnum *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstIntToEnum *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = dest_type; instruction->target = target; @@ -2032,10 +2032,10 @@ static IrInstGen *ir_build_int_to_enum_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *wanted_type) { - IrInstGenIntToErr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstIntToErr *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = wanted_type; instruction->target = target; @@ -2044,10 +2044,10 @@ static IrInstGen *ir_build_int_to_err_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *wanted_type) { - IrInstGenErrToInt *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstErrToInt *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = wanted_type; instruction->target = target; @@ -2056,8 +2056,8 @@ static IrInstGen *ir_build_err_to_int_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *msg) { - IrInstGenPanic *instruction = ir_build_inst_noreturn(&ira->new_irb, +static Stage1AirInst *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *msg) { + Stage1AirInstPanic *instruction = ir_build_inst_noreturn(&ira->new_irb, scope, source_node); instruction->msg = msg; @@ -2066,10 +2066,10 @@ static IrInstGen *ir_build_panic_gen(IrAnalyze *ira, Scope *scope, AstNode *sour return &instruction->base; } -static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *result_type) { - IrInstGenTagName *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstTagName *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->target = target; @@ -2079,10 +2079,10 @@ static IrInstGen *ir_build_tag_name_gen(IrAnalyze *ira, Scope *scope, AstNode *s return &instruction->base; } -static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *field_ptr, TypeStructField *field, ZigType *result_type) +static Stage1AirInst *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *field_ptr, TypeStructField *field, ZigType *result_type) { - IrInstGenFieldParentPtr *inst = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstFieldParentPtr *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->field_ptr = field_ptr; @@ -2093,10 +2093,10 @@ static IrInstGen *ir_build_field_parent_ptr_gen(IrAnalyze *ira, Scope *scope, As return &inst->base; } -static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *result_type) { - IrInstGenAlignCast *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstAlignCast *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->target = target; @@ -2105,20 +2105,20 @@ static IrInstGen *ir_build_align_cast_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_error_return_trace_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, +static Stage1AirInst *ir_build_error_return_trace_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstErrorReturnTraceOptional optional, ZigType *result_type) { - IrInstGenErrorReturnTrace *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstErrorReturnTrace *inst = ir_build_inst_gen(&ira->new_irb, scope, source_node); inst->base.value->type = result_type; inst->optional = optional; return &inst->base; } -static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, IrInstGen *operand, AtomicRmwOp op, AtomicOrder ordering, ZigType *operand_type) +static Stage1AirInst *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, Stage1AirInst *operand, AtomicRmwOp op, AtomicOrder ordering, ZigType *operand_type) { - IrInstGenAtomicRmw *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); + Stage1AirInstAtomicRmw *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = operand_type; instruction->ptr = ptr; instruction->op = op; @@ -2131,10 +2131,10 @@ static IrInstGen *ir_build_atomic_rmw_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, AtomicOrder ordering, ZigType *operand_type) +static Stage1AirInst *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, AtomicOrder ordering, ZigType *operand_type) { - IrInstGenAtomicLoad *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstAtomicLoad *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = operand_type; instruction->ptr = ptr; @@ -2145,10 +2145,10 @@ static IrInstGen *ir_build_atomic_load_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, IrInstGen *value, AtomicOrder ordering) +static Stage1AirInst *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, Stage1AirInst *value, AtomicOrder ordering) { - IrInstGenAtomicStore *instruction = ir_build_inst_void(&ira->new_irb, + Stage1AirInstAtomicStore *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->ptr = ptr; instruction->value = value; @@ -2161,10 +2161,10 @@ static IrInstGen *ir_build_atomic_store_gen(IrAnalyze *ira, Scope *scope, AstNod } -static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *result_type, IrInstGen *vector, IrInstGen *result_loc) +static Stage1AirInst *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *result_type, Stage1AirInst *vector, Stage1AirInst *result_loc) { - IrInstGenVectorToArray *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstVectorToArray *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->vector = vector; @@ -2176,10 +2176,10 @@ static IrInstGen *ir_build_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *result_type, IrInstGen *operand, IrInstGen *result_loc) +static Stage1AirInst *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *result_type, Stage1AirInst *operand, Stage1AirInst *result_loc) { - IrInstGenPtrOfArrayToSlice *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstPtrOfArrayToSlice *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->operand = operand; @@ -2191,10 +2191,10 @@ static IrInstGen *ir_build_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, A return &instruction->base; } -static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *array, ZigType *result_type) +static Stage1AirInst *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *array, ZigType *result_type) { - IrInstGenArrayToVector *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstArrayToVector *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->array = array; @@ -2204,10 +2204,10 @@ static IrInstGen *ir_build_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target) +static Stage1AirInst *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target) { - IrInstGenAssertZero *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstAssertZero *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_void; instruction->target = target; @@ -2217,10 +2217,10 @@ static IrInstGen *ir_build_assert_zero(IrAnalyze *ira, Scope *scope, AstNode *so return &instruction->base; } -static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target) +static Stage1AirInst *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target) { - IrInstGenAssertNonNull *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstAssertNonNull *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_void; instruction->target = target; @@ -2230,10 +2230,10 @@ static IrInstGen *ir_build_assert_non_null(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, +static Stage1AirInstAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint32_t align, const char *name_hint) { - IrInstGenAlloca *instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstAlloca *instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); instruction->align = align; instruction->name_hint = name_hint; @@ -2241,8 +2241,8 @@ static IrInstGenAlloca *ir_build_alloca_gen(IrAnalyze *ira, Scope *scope, AstNod return instruction; } -static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGenSuspendBegin *begin) { - IrInstGenSuspendFinish *inst = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInstSuspendBegin *begin) { + Stage1AirInstSuspendFinish *inst = ir_build_inst_void(&ira->new_irb, scope, source_node); inst->begin = begin; @@ -2251,10 +2251,10 @@ static IrInstGen *ir_build_suspend_finish_gen(IrAnalyze *ira, Scope *scope, AstN return &inst->base; } -static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *frame, ZigType *result_type, IrInstGen *result_loc, bool is_nosuspend) +static Stage1AirInstAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *frame, ZigType *result_type, Stage1AirInst *result_loc, bool is_nosuspend) { - IrInstGenAwait *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstAwait *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->frame = frame; @@ -2267,8 +2267,8 @@ static IrInstGenAwait *ir_build_await_gen(IrAnalyze *ira, Scope *scope, AstNode return instruction; } -static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *frame) { - IrInstGenResume *instruction = ir_build_inst_void(&ira->new_irb, +static Stage1AirInst *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *frame) { + Stage1AirInstResume *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->frame = frame; @@ -2277,10 +2277,10 @@ static IrInstGen *ir_build_resume_gen(IrAnalyze *ira, Scope *scope, AstNode *sou return &instruction->base; } -static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *operand, +static Stage1AirInst *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *operand, SpillId spill_id) { - IrInstGenSpillBegin *instruction = ir_build_inst_void(&ira->new_irb, + Stage1AirInstSpillBegin *instruction = ir_build_inst_void(&ira->new_irb, scope, source_node); instruction->operand = operand; instruction->spill_id = spill_id; @@ -2290,10 +2290,10 @@ static IrInstGen *ir_build_spill_begin_gen(IrAnalyze *ira, Scope *scope, AstNode return &instruction->base; } -static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGenSpillBegin *begin, +static Stage1AirInst *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInstSpillBegin *begin, ZigType *result_type) { - IrInstGenSpillEnd *instruction = ir_build_inst_gen(&ira->new_irb, + Stage1AirInstSpillEnd *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = result_type; instruction->begin = begin; @@ -2303,10 +2303,10 @@ static IrInstGen *ir_build_spill_end_gen(IrAnalyze *ira, Scope *scope, AstNode * return &instruction->base; } -static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *vector, IrInstGen *index) +static Stage1AirInst *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *vector, Stage1AirInst *index) { - IrInstGenVectorExtractElem *instruction = ir_build_inst_gen( + Stage1AirInstVectorExtractElem *instruction = ir_build_inst_gen( &ira->new_irb, scope, source_node); instruction->base.value->type = vector->value->type->data.vector.elem_type; instruction->vector = vector; @@ -2318,8 +2318,8 @@ static IrInstGen *ir_build_vector_extract_elem(IrAnalyze *ira, Scope *scope, Ast return &instruction->base; } -static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *index) { - IrInstGenWasmMemorySize *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *index) { + Stage1AirInstWasmMemorySize *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_u32; instruction->index = index; @@ -2329,8 +2329,8 @@ static IrInstGen *ir_build_wasm_memory_size_gen(IrAnalyze *ira, Scope *scope, As return &instruction->base; } -static IrInstGen *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *index, IrInstGen *delta) { - IrInstGenWasmMemoryGrow *instruction = ir_build_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_build_wasm_memory_grow_gen(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *index, Stage1AirInst *delta) { + Stage1AirInstWasmMemoryGrow *instruction = ir_build_inst_gen(&ira->new_irb, scope, source_node); instruction->base.value->type = ira->codegen->builtin_types.entry_i32; instruction->index = index; @@ -2555,7 +2555,7 @@ static ErrorMsg *opt_ir_add_error_node(IrAnalyze *ira, CodeGen *codegen, AstNode return add_node_error(codegen, source_node, msg); } -static ErrorMsg *ir_add_error(IrAnalyze *ira, IrInstGen *source_instruction, Buf *msg) { +static ErrorMsg *ir_add_error(IrAnalyze *ira, Stage1AirInst *source_instruction, Buf *msg) { return ir_add_error_node(ira, source_instruction->source_node, msg); } @@ -2605,17 +2605,17 @@ ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_va } static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) { - IrBasicBlockGen *bb = exec->basic_block_list.at(0); + Stage1AirBasicBlock *bb = exec->basic_block_list.at(0); for (size_t i = 0; i < bb->instruction_list.length; i += 1) { - IrInstGen *instruction = bb->instruction_list.at(i); - if (instruction->id == IrInstGenIdReturn) { + Stage1AirInst *instruction = bb->instruction_list.at(i); + if (instruction->id == Stage1AirInstIdReturn) { return ErrorNone; } else if (ir_inst_gen_has_side_effects(instruction)) { if (instr_is_comptime(instruction)) { switch (instruction->id) { - case IrInstGenIdUnwrapErrPayload: - case IrInstGenIdOptionalUnwrapPtr: - case IrInstGenIdUnionFieldPtr: + case Stage1AirInstIdUnwrapErrPayload: + case Stage1AirInstIdOptionalUnwrapPtr: + case Stage1AirInstIdUnionFieldPtr: continue; default: break; @@ -2633,7 +2633,7 @@ static Error ir_exec_scan_for_side_effects(CodeGen *codegen, Stage1Air *exec) { zig_unreachable(); } -static bool ir_emit_global_runtime_side_effect(IrAnalyze *ira, IrInstSrc* source_instruction) { +static bool ir_emit_global_runtime_side_effect(IrAnalyze *ira, Stage1ZirInst* source_instruction) { if (ir_should_inline(ira->zir, source_instruction->scope)) { ir_add_error_node(ira, source_instruction->source_node, buf_sprintf("unable to evaluate constant expression")); return false; @@ -3423,7 +3423,7 @@ static void value_to_bigfloat(BigFloat *out, ZigValue *val) { } } -static bool ir_num_lit_fits_in_other_type(IrAnalyze *ira, IrInstGen *instruction, ZigType *other_type, +static bool ir_num_lit_fits_in_other_type(IrAnalyze *ira, Stage1AirInst *instruction, ZigType *other_type, bool explicit_cast) { if (type_is_invalid(other_type)) { @@ -4185,11 +4185,11 @@ static void update_errors_helper(CodeGen *g, ErrorTableEntry ***errors, size_t * } static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigType *expected_type, - IrInstGen **instructions, size_t instruction_count) + Stage1AirInst **instructions, size_t instruction_count) { Error err; assert(instruction_count >= 1); - IrInstGen *prev_inst; + Stage1AirInst *prev_inst; size_t i = 0; for (;;) { prev_inst = instructions[i]; @@ -4231,7 +4231,7 @@ static ZigType *ir_resolve_peer_types(IrAnalyze *ira, AstNode *source_node, ZigT bool make_the_slice_const = false; bool make_the_pointer_const = false; for (; i < instruction_count; i += 1) { - IrInstGen *cur_inst = instructions[i]; + Stage1AirInst *cur_inst = instructions[i]; ZigType *cur_type = cur_inst->value->type; ZigType *prev_type = prev_inst->value->type; @@ -5085,36 +5085,36 @@ static bool eval_const_expr_implicit_cast(IrAnalyze *ira, Scope *scope, AstNode return true; } -static IrInstGen *ir_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, +static Stage1AirInst *ir_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); - IrInstGen *new_instruction = &const_instruction->base; + Stage1AirInst *new_instruction = &const_instruction->base; new_instruction->value->type = ty; new_instruction->value->special = ConstValSpecialStatic; ira->new_irb.constants.append(&heap::c_allocator, const_instruction); return new_instruction; } -static IrInstGen *ir_const_noval(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGenConst *const_instruction = ir_create_inst_noval(&ira->new_irb, +static Stage1AirInst *ir_const_noval(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInstConst *const_instruction = ir_create_inst_noval(&ira->new_irb, scope, source_node); ira->new_irb.constants.append(&heap::c_allocator, const_instruction); return &const_instruction->base; } -// This function initializes the new IrInstGen with the provided ZigValue, +// This function initializes the new Stage1AirInst with the provided ZigValue, // rather than creating a new one. -static IrInstGen *ir_const_move(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *val) { - IrInstGen *result = ir_const_noval(ira, scope, source_node); +static Stage1AirInst *ir_const_move(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *val) { + Stage1AirInst *result = ir_const_noval(ira, scope, source_node); result->value = val; return result; } -static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type, CastOp cast_op) { if (instr_is_comptime(value) || !type_has_bits(ira->codegen, wanted_type)) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); ZigValue *val = ir_resolve_const(ira, value, UndefBad); if (val == nullptr) return ira->codegen->invalid_inst_gen; @@ -5131,8 +5131,8 @@ static IrInstGen *ir_resolve_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ } } -static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira, - Scope *scope, AstNode *source_node, IrInstGen *value, ZigType *wanted_type) +static Stage1AirInst *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira, + Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type) { src_assert(value->value->type->id == ZigTypeIdPointer, source_node); @@ -5157,7 +5157,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira, if (pointee == nullptr) return ira->codegen->invalid_inst_gen; if (pointee->special != ConstValSpecialRuntime) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->data.x_ptr.special = ConstPtrSpecialBaseArray; result->value->data.x_ptr.mut = val->data.x_ptr.mut; result->value->data.x_ptr.data.base_array.array_val = pointee; @@ -5170,8 +5170,8 @@ static IrInstGen *ir_resolve_ptr_of_array_to_unknown_len_ptr(IrAnalyze *ira, wanted_type, value, CastOpBitCast); } -static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *array_ptr, ZigType *wanted_type, ResultLoc *result_loc) +static Stage1AirInst *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *array_ptr, ZigType *wanted_type, ResultLoc *result_loc) { Error err; @@ -5190,7 +5190,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, // undef_array->special = ConstValSpecialUndef; // undef_array->type = array_type; - // IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + // Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); // init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr); // result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst; // result->value->type = wanted_type; @@ -5217,7 +5217,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, undef_array->special = ConstValSpecialUndef; undef_array->type = array_type; - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); init_const_slice(ira->codegen, result->value, undef_array, 0, 0, false, nullptr); result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = ConstPtrMutComptimeConst; result->value->type = wanted_type; @@ -5228,7 +5228,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, if (array_ptr_val->data.x_ptr.special == ConstPtrSpecialSubArray) { ZigValue *array_val = array_ptr_val->data.x_ptr.data.base_array.array_val; if (array_val->special != ConstValSpecialRuntime) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); init_const_slice(ira->codegen, result->value, array_val, array_ptr_val->data.x_ptr.data.base_array.elem_index, array_type->data.array.len, wanted_const, nullptr); @@ -5243,7 +5243,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, if (pointee->special != ConstValSpecialRuntime) { assert(array_ptr_val->type->id == ZigTypeIdPointer); - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); init_const_slice(ira->codegen, result->value, pointee, 0, array_type->data.array.len, wanted_const, nullptr); result->value->data.x_struct.fields[slice_ptr_index]->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut; result->value->type = wanted_type; @@ -5253,7 +5253,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, } if (result_loc == nullptr) result_loc = no_result_loc(); - IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, + Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true); if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) @@ -5263,7 +5263,7 @@ static IrInstGen *ir_resolve_ptr_of_array_to_slice(IrAnalyze *ira, Scope *scope, return ir_build_ptr_of_array_to_slice(ira, scope, source_node, wanted_type, array_ptr, result_loc_inst); } -static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInstSrc *ref_old_instruction) { +static Stage1AirBasicBlock *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirInst *ref_old_instruction) { assert(old_bb); if (old_bb->child) { @@ -5272,15 +5272,15 @@ static IrBasicBlockGen *ir_get_new_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_b } } - IrBasicBlockGen *new_bb = ir_build_bb_from(ira, old_bb); + Stage1AirBasicBlock *new_bb = ir_build_bb_from(ira, old_bb); new_bb->ref_instruction = ref_old_instruction; return new_bb; } -static IrBasicBlockGen *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, IrInstSrc *ref_old_instruction) { +static Stage1AirBasicBlock *ir_get_new_bb_runtime(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirInst *ref_old_instruction) { assert(ref_old_instruction != nullptr); - IrBasicBlockGen *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction); + Stage1AirBasicBlock *new_bb = ir_get_new_bb(ira, old_bb, ref_old_instruction); if (new_bb->must_be_comptime_source_node != nullptr) { ErrorMsg *msg = ir_add_error_node(ira, ref_old_instruction->source_node, buf_sprintf("control flow attempts to use compile-time variable at runtime")); @@ -5301,7 +5301,7 @@ static void ir_start_bb(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb, Stage1ZirBa ira->old_bb_index = old_bb->index; } -static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1ZirBasicBlock *next_bb, +static Stage1AirInst *ira_suspend(IrAnalyze *ira, Stage1ZirInst *old_instruction, Stage1ZirBasicBlock *next_bb, IrSuspendPosition *suspend_pos) { if (ira->codegen->verbose_ir) { @@ -5331,7 +5331,7 @@ static IrInstGen *ira_suspend(IrAnalyze *ira, IrInstSrc *old_instruction, Stage1 return ira->codegen->unreach_instruction; } -static IrInstGen *ira_resume(IrAnalyze *ira) { +static Stage1AirInst *ira_resume(IrAnalyze *ira) { IrSuspendPosition pos = ira->resume_stack.pop(); if (ira->codegen->verbose_ir) { fprintf(stderr, "resume (%zu,%zu) ", pos.basic_block_index, pos.instruction_index); @@ -5414,7 +5414,7 @@ static void ir_finish_bb(IrAnalyze *ira) { ir_start_next_bb(ira); } -static IrInstGen *ir_unreach_error(IrAnalyze *ira) { +static Stage1AirInst *ir_unreach_error(IrAnalyze *ira) { ira->old_bb_index = SIZE_MAX; if (ira->new_irb.exec->first_err_trace_msg == nullptr) { ira->new_irb.exec->first_err_trace_msg = ira->codegen->trace_err; @@ -5441,7 +5441,7 @@ static bool ir_emit_backward_branch(IrAnalyze *ira, AstNode* source_node) { return true; } -static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBasicBlock *old_bb) { +static Stage1AirInst *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBasicBlock *old_bb) { if (old_bb->debug_id <= ira->zir_current_basic_block->debug_id) { if (!ir_emit_backward_branch(ira, source_node)) return ir_unreach_error(ira); @@ -5452,14 +5452,14 @@ static IrInstGen *ir_inline_bb(IrAnalyze *ira, AstNode* source_node, Stage1ZirBa return ira->codegen->unreach_instruction; } -static IrInstGen *ir_finish_anal(IrAnalyze *ira, IrInstGen *instruction) { +static Stage1AirInst *ir_finish_anal(IrAnalyze *ira, Stage1AirInst *instruction) { if (instruction->value->type->id == ZigTypeIdUnreachable) ir_finish_bb(ira); return instruction; } -static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry) { - IrInstGen *result = ir_const(ira, scope, source_node, fn_entry->type_entry); +static Stage1AirInst *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry) { + Stage1AirInst *result = ir_const(ira, scope, source_node, fn_entry->type_entry); result->value->special = ConstValSpecialStatic; result->value->data.x_ptr.data.fn.fn_entry = fn_entry; result->value->data.x_ptr.mut = ConstPtrMutComptimeConst; @@ -5467,62 +5467,62 @@ static IrInstGen *ir_const_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node return result; } -static IrInstGen *ir_const_bound_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigFn *fn_entry, IrInstGen *first_arg, AstNode *first_arg_src) +static Stage1AirInst *ir_const_bound_fn(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigFn *fn_entry, Stage1AirInst *first_arg, AstNode *first_arg_src) { // This is unfortunately required to avoid improperly freeing first_arg_src ira_ref(ira); - IrInstGen *result = ir_const(ira, scope, source_node, get_bound_fn_type(ira->codegen, fn_entry)); + Stage1AirInst *result = ir_const(ira, scope, source_node, get_bound_fn_type(ira->codegen, fn_entry)); result->value->data.x_bound_fn.fn = fn_entry; result->value->data.x_bound_fn.first_arg = first_arg; result->value->data.x_bound_fn.first_arg_src = first_arg_src; return result; } -static IrInstGen *ir_const_type(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { - IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_type); +static Stage1AirInst *ir_const_type(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { + Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_type); result->value->data.x_type = ty; return result; } -static IrInstGen *ir_const_bool(IrAnalyze *ira, Scope *scope, AstNode *source_node, bool value) { - IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_bool); +static Stage1AirInst *ir_const_bool(IrAnalyze *ira, Scope *scope, AstNode *source_node, bool value) { + Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_bool); result->value->data.x_bool = value; return result; } -static IrInstGen *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { - IrInstGen *result = ir_const(ira, scope, source_node, ty); +static Stage1AirInst *ir_const_undef(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *ty) { + Stage1AirInst *result = ir_const(ira, scope, source_node, ty); result->value->special = ConstValSpecialUndef; return result; } -static IrInstGen *ir_const_unreachable(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGen *result = ir_const_noval(ira, scope, source_node); +static Stage1AirInst *ir_const_unreachable(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInst *result = ir_const_noval(ira, scope, source_node); result->value = ira->codegen->intern.for_unreachable(); return result; } -static IrInstGen *ir_const_void(IrAnalyze *ira, Scope *scope, AstNode *source_node) { - IrInstGen *result = ir_const_noval(ira, scope, source_node); +static Stage1AirInst *ir_const_void(IrAnalyze *ira, Scope *scope, AstNode *source_node) { + Stage1AirInst *result = ir_const_noval(ira, scope, source_node); result->value = ira->codegen->intern.for_void(); return result; } -static IrInstGen *ir_const_unsigned(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint64_t value) { - IrInstGen *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_num_lit_int); +static Stage1AirInst *ir_const_unsigned(IrAnalyze *ira, Scope *scope, AstNode *source_node, uint64_t value) { + Stage1AirInst *result = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_num_lit_int); bigint_init_unsigned(&result->value->data.x_bigint, value); return result; } -static IrInstGen *ir_get_const_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, +static Stage1AirInst *ir_get_const_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigValue *pointee, ZigType *pointee_type, ConstPtrMut ptr_mut, bool ptr_is_const, bool ptr_is_volatile, uint32_t ptr_align) { ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, pointee_type, ptr_is_const, ptr_is_volatile, PtrLenSingle, ptr_align, 0, 0, false); - IrInstGen *const_instr = ir_const(ira, scope, source_node, ptr_type); + Stage1AirInst *const_instr = ir_const(ira, scope, source_node, ptr_type); ZigValue *const_val = const_instr->value; const_val->data.x_ptr.special = ConstPtrSpecialRef; const_val->data.x_ptr.mut = ptr_mut; @@ -5564,7 +5564,7 @@ static Error ir_resolve_const_val(CodeGen *codegen, Stage1Air *exec, AstNode *so } } -static ZigValue *ir_resolve_const(IrAnalyze *ira, IrInstGen *value, UndefAllowed undef_allowed) { +static ZigValue *ir_resolve_const(IrAnalyze *ira, Stage1AirInst *value, UndefAllowed undef_allowed) { Error err; if ((err = ir_resolve_const_val(ira->codegen, ira->new_irb.exec, value->source_node, value->value, undef_allowed))) @@ -5640,7 +5640,7 @@ Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node, return ErrorNone; } -static ErrorTableEntry *ir_resolve_error(IrAnalyze *ira, IrInstGen *err_value) { +static ErrorTableEntry *ir_resolve_error(IrAnalyze *ira, Stage1AirInst *err_value) { if (type_is_invalid(err_value->value->type)) return nullptr; @@ -5669,7 +5669,7 @@ static ZigType *ir_resolve_const_type(CodeGen *codegen, Stage1Air *exec, AstNode return val->data.x_type; } -static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) { +static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, Stage1AirInst *type_value) { if (type_is_invalid(type_value->value->type)) return nullptr; @@ -5689,7 +5689,7 @@ static ZigValue *ir_resolve_type_lazy(IrAnalyze *ira, IrInstGen *type_value) { return type_value->value; } -static ZigType *ir_resolve_type(IrAnalyze *ira, IrInstGen *type_value) { +static ZigType *ir_resolve_type(IrAnalyze *ira, Stage1AirInst *type_value) { ZigValue *val = ir_resolve_type_lazy(ira, type_value); if (val == nullptr) return ira->codegen->builtin_types.entry_invalid; @@ -5711,7 +5711,7 @@ static Error ir_validate_vector_elem_type(IrAnalyze *ira, AstNode *source_node, return ErrorNone; } -static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type_value) { +static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, Stage1AirInst *elem_type_value) { Error err; ZigType *elem_type = ir_resolve_type(ira, elem_type_value); if (type_is_invalid(elem_type)) @@ -5721,7 +5721,7 @@ static ZigType *ir_resolve_vector_elem_type(IrAnalyze *ira, IrInstGen *elem_type return elem_type; } -static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) { +static ZigType *ir_resolve_int_type(IrAnalyze *ira, Stage1AirInst *type_value) { ZigType *ty = ir_resolve_type(ira, type_value); if (type_is_invalid(ty)) return ira->codegen->builtin_types.entry_invalid; @@ -5742,7 +5742,7 @@ static ZigType *ir_resolve_int_type(IrAnalyze *ira, IrInstGen *type_value) { return ty; } -static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, IrInstGen *type_value) { +static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Stage1AirInst *type_value) { if (type_is_invalid(type_value->value->type)) return ira->codegen->builtin_types.entry_invalid; @@ -5770,7 +5770,7 @@ static ZigType *ir_resolve_error_set_type(IrAnalyze *ira, AstNode *op_source, Ir return result_type; } -static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) { +static ZigFn *ir_resolve_fn(IrAnalyze *ira, Stage1AirInst *fn_value) { if (type_is_invalid(fn_value->value->type)) return nullptr; @@ -5791,14 +5791,14 @@ static ZigFn *ir_resolve_fn(IrAnalyze *ira, IrInstGen *fn_value) { return const_val->data.x_ptr.data.fn.fn_entry; } -static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, ZigType *wanted_type, ResultLoc *result_loc) +static Stage1AirInst *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc) { assert(wanted_type->id == ZigTypeIdOptional); if (instr_is_comptime(value)) { ZigType *payload_type = wanted_type->data.maybe.child_type; - IrInstGen *casted_payload = ir_implicit_cast(ira, value, payload_type); + Stage1AirInst *casted_payload = ir_implicit_cast(ira, value, payload_type); if (type_is_invalid(casted_payload->value->type)) return ira->codegen->invalid_inst_gen; @@ -5806,7 +5806,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode if (!val) return ira->codegen->invalid_inst_gen; - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); const_instruction->base.value->special = ConstValSpecialStatic; if (types_have_same_zig_comptime_repr(ira->codegen, wanted_type, payload_type)) { @@ -5821,7 +5821,7 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode if (result_loc == nullptr && handle_is_ptr(ira->codegen, wanted_type)) { result_loc = no_result_loc(); } - IrInstGen *result_loc_inst = nullptr; + Stage1AirInst *result_loc_inst = nullptr; if (result_loc != nullptr) { result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true); if (type_is_invalid(result_loc_inst->value->type) || @@ -5830,20 +5830,20 @@ static IrInstGen *ir_analyze_optional_wrap(IrAnalyze *ira, Scope *scope, AstNode return result_loc_inst; } } - IrInstGen *result = ir_build_optional_wrap(ira, scope, source_node, wanted_type, value, result_loc_inst); + Stage1AirInst *result = ir_build_optional_wrap(ira, scope, source_node, wanted_type, value, result_loc_inst); result->value->data.rh_maybe = RuntimeHintOptionalNonNull; return result; } -static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, ZigType *wanted_type, ResultLoc *result_loc) +static Stage1AirInst *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc) { assert(wanted_type->id == ZigTypeIdErrorUnion); ZigType *payload_type = wanted_type->data.error_union.payload_type; ZigType *err_set_type = wanted_type->data.error_union.err_set_type; if (instr_is_comptime(value)) { - IrInstGen *casted_payload = ir_implicit_cast(ira, value, payload_type); + Stage1AirInst *casted_payload = ir_implicit_cast(ira, value, payload_type); if (type_is_invalid(casted_payload->value->type)) return ira->codegen->invalid_inst_gen; @@ -5856,7 +5856,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN err_set_val->special = ConstValSpecialStatic; err_set_val->data.x_err_set = nullptr; - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); const_instruction->base.value->type = wanted_type; const_instruction->base.value->special = ConstValSpecialStatic; @@ -5865,7 +5865,7 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN return &const_instruction->base; } - IrInstGen *result_loc_inst; + Stage1AirInst *result_loc_inst; if (handle_is_ptr(ira->codegen, wanted_type)) { if (result_loc == nullptr) result_loc = no_result_loc(); result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true); @@ -5877,12 +5877,12 @@ static IrInstGen *ir_analyze_err_wrap_payload(IrAnalyze *ira, Scope *scope, AstN result_loc_inst = nullptr; } - IrInstGen *result = ir_build_err_wrap_payload(ira, scope, source_node, wanted_type, value, result_loc_inst); + Stage1AirInst *result = ir_build_err_wrap_payload(ira, scope, source_node, wanted_type, value, result_loc_inst); result->value->data.rh_error_union = RuntimeHintErrorUnionNonError; return result; } -static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type) { assert(value->value->type->id == ZigTypeIdErrorSet); @@ -5912,7 +5912,7 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode } } - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); const_instruction->base.value->type = wanted_type; const_instruction->base.value->special = ConstValSpecialStatic; @@ -5923,8 +5923,8 @@ static IrInstGen *ir_analyze_err_set_cast(IrAnalyze *ira, Scope *scope, AstNode return ir_build_cast(ira, scope, source_node, wanted_type, value, CastOpErrSet); } -static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *frame_ptr, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *frame_ptr, ZigType *wanted_type) { if (instr_is_comptime(frame_ptr)) { ZigValue *ptr_val = ir_resolve_const(ira, frame_ptr, UndefBad); @@ -5940,8 +5940,8 @@ static IrInstGen *ir_analyze_frame_ptr_to_anyframe(IrAnalyze *ira, Scope *scope, return ir_build_cast(ira, scope, source_node, wanted_type, frame_ptr, CastOpBitCast); } -static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, ZigType *wanted_type) { if (instr_is_comptime(value)) { zig_panic("TODO comptime anyframe->T to anyframe"); @@ -5951,12 +5951,12 @@ static IrInstGen *ir_analyze_anyframe_to_anyframe(IrAnalyze *ira, Scope *scope, } -static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type, ResultLoc *result_loc) { assert(wanted_type->id == ZigTypeIdErrorUnion); - IrInstGen *casted_value = ir_implicit_cast(ira, value, wanted_type->data.error_union.err_set_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, wanted_type->data.error_union.err_set_type); if (instr_is_comptime(casted_value)) { ZigValue *val = ir_resolve_const(ira, casted_value, UndefBad); @@ -5968,7 +5968,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode err_set_val->type = wanted_type->data.error_union.err_set_type; err_set_val->data.x_err_set = val->data.x_err_set; - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); const_instruction->base.value->type = wanted_type; const_instruction->base.value->special = ConstValSpecialStatic; @@ -5977,7 +5977,7 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode return &const_instruction->base; } - IrInstGen *result_loc_inst; + Stage1AirInst *result_loc_inst; if (handle_is_ptr(ira->codegen, wanted_type)) { if (result_loc == nullptr) result_loc = no_result_loc(); result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, wanted_type, nullptr, true, true); @@ -5991,19 +5991,19 @@ static IrInstGen *ir_analyze_err_wrap_code(IrAnalyze *ira, Scope *scope, AstNode } - IrInstGen *result = ir_build_err_wrap_code(ira, scope, source_node, wanted_type, value, result_loc_inst); + Stage1AirInst *result = ir_build_err_wrap_code(ira, scope, source_node, wanted_type, value, result_loc_inst); result->value->data.rh_error_union = RuntimeHintErrorUnionError; return result; } -static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, ZigType *wanted_type) { +static Stage1AirInst *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *wanted_type) { assert(wanted_type->id == ZigTypeIdOptional); assert(instr_is_comptime(value)); ZigValue *val = ir_resolve_const(ira, value, UndefBad); assert(val != nullptr); - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->special = ConstValSpecialStatic; if (get_src_ptr_type(wanted_type) != nullptr) { @@ -6016,8 +6016,8 @@ static IrInstGen *ir_analyze_null_to_maybe(IrAnalyze *ira, Scope *scope, AstNode return result; } -static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, ZigType *wanted_type) { assert(wanted_type->id == ZigTypeIdPointer); assert(wanted_type->data.pointer.ptr_len == PtrLenC); @@ -6026,13 +6026,13 @@ static IrInstGen *ir_analyze_null_to_c_pointer(IrAnalyze *ira, Scope *scope, Ast ZigValue *val = ir_resolve_const(ira, value, UndefBad); assert(val != nullptr); - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->data.x_ptr.special = ConstPtrSpecialNull; result->value->data.x_ptr.mut = ConstPtrMutComptimeConst; return result; } -static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *elem_type, bool is_const, bool is_volatile) { Error err; @@ -6054,19 +6054,19 @@ static IrInstGen *ir_get_ref2(IrAnalyze *ira, Scope *scope, AstNode *source_node if ((err = type_resolve(ira->codegen, ptr_type, ResolveStatusZeroBitsKnown))) return ira->codegen->invalid_inst_gen; - IrInstGen *result_loc; + Stage1AirInst *result_loc; if (type_has_bits(ira->codegen, ptr_type) && !handle_is_ptr(ira->codegen, elem_type)) { result_loc = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), elem_type, nullptr, true, true); } else { result_loc = nullptr; } - IrInstGen *new_instruction = ir_build_ref_gen(ira, scope, source_node, ptr_type, value, result_loc); + Stage1AirInst *new_instruction = ir_build_ref_gen(ira, scope, source_node, ptr_type, value, result_loc); new_instruction->value->data.rh_ptr = RuntimeHintPtrStack; return new_instruction; } -static IrInstGen *ir_get_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_get_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, bool is_const, bool is_volatile) { return ir_get_ref2(ira, scope, source_node, value, value->value->type, is_const, is_volatile); @@ -6103,10 +6103,10 @@ static bool can_fold_enum_type(ZigType *ty) { (tag_int_type->id == ZigTypeIdInt && tag_int_type->data.integral.bit_count == 0); } -static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target) { +static Stage1AirInst *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target) { Error err; - IrInstGen *enum_target; + Stage1AirInst *enum_target; ZigType *enum_type; if (target->value->type->id == ZigTypeIdUnion) { enum_type = ir_resolve_union_tag_type(ira, target->source_node, target->value->type); @@ -6132,7 +6132,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode * // If there is only one possible tag, then we know at comptime what it is. if (can_fold_enum_type(enum_type)) { - IrInstGen *result = ir_const(ira, scope, source_node, tag_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, tag_type); init_const_bigint(result->value, tag_type, &enum_type->data.enumeration.fields[0].value); return result; @@ -6142,7 +6142,7 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode * ZigValue *val = ir_resolve_const(ira, enum_target, UndefBad); if (!val) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, tag_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, tag_type); init_const_bigint(result->value, tag_type, &val->data.x_enum_tag); return result; } @@ -6150,8 +6150,8 @@ static IrInstGen *ir_analyze_enum_to_int(IrAnalyze *ira, Scope *scope, AstNode * return ir_build_widen_or_shorten(ira, scope, source_node, enum_target, tag_type); } -static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target, ZigType *wanted_type) { assert(target->value->type->id == ZigTypeIdUnion); assert(wanted_type->id == ZigTypeIdEnum); @@ -6161,7 +6161,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode ZigValue *val = ir_resolve_const(ira, target, UndefBad); if (!val) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->special = ConstValSpecialStatic; result->value->type = wanted_type; bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_union.tag); @@ -6170,7 +6170,7 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode // If there is only 1 possible tag, then we know at comptime what it is. if (can_fold_enum_type(wanted_type)) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->special = ConstValSpecialStatic; result->value->type = wanted_type; TypeEnumField *enum_field = target->value->type->data.unionation.fields[0].enum_field; @@ -6181,16 +6181,16 @@ static IrInstGen *ir_analyze_union_to_tag(IrAnalyze *ira, Scope *scope, AstNode return ir_build_union_tag(ira, scope, source_node, target, wanted_type); } -static IrInstGen *ir_analyze_undefined_to_anything(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_undefined_to_anything(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target, ZigType *wanted_type) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->special = ConstValSpecialUndef; return result; } -static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *uncasted_target, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *uncasted_target, ZigType *wanted_type) { Error err; assert(wanted_type->id == ZigTypeIdUnion); @@ -6198,7 +6198,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode if ((err = type_resolve(ira->codegen, wanted_type, ResolveStatusZeroBitsKnown))) return ira->codegen->invalid_inst_gen; - IrInstGen *target = ir_implicit_cast(ira, uncasted_target, wanted_type->data.unionation.tag_type); + Stage1AirInst *target = ir_implicit_cast(ira, uncasted_target, wanted_type->data.unionation.tag_type); if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -6240,7 +6240,7 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode break; } - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->special = ConstValSpecialStatic; result->value->type = wanted_type; bigint_init_bigint(&result->value->data.x_union.tag, &val->data.x_enum_tag); @@ -6287,8 +6287,8 @@ static IrInstGen *ir_analyze_enum_to_union(IrAnalyze *ira, Scope *scope, AstNode static bool value_numeric_fits_in_type(ZigValue *value, ZigType *type_entry); -static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target, ZigType *wanted_type) { ZigType *wanted_scalar_type = (target->value->type->id == ZigTypeIdVector) ? wanted_type->data.vector.elem_type : wanted_type; @@ -6314,7 +6314,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN } } - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->type = wanted_type; if (wanted_type->id == ZigTypeIdVector) { @@ -6351,7 +6351,7 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN assert(wanted_type->id == ZigTypeIdInt); assert(type_has_bits(ira->codegen, target->value->type)); ir_build_assert_zero(ira, scope, source_node, target); - IrInstGen *result = ir_const_unsigned(ira, scope, source_node, 0); + Stage1AirInst *result = ir_const_unsigned(ira, scope, source_node, 0); result->value->type = wanted_type; return result; } @@ -6359,8 +6359,8 @@ static IrInstGen *ir_analyze_widen_or_shorten(IrAnalyze *ira, Scope *scope, AstN return ir_build_widen_or_shorten(ira, scope, source_node, target, wanted_type); } -static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target, ZigType *wanted_type) { Error err; assert(wanted_type->id == ZigTypeIdEnum); @@ -6397,7 +6397,7 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode * return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); bigint_init_bigint(&result->value->data.x_enum_tag, &val->data.x_bigint); return result; } @@ -6405,14 +6405,14 @@ static IrInstGen *ir_analyze_int_to_enum(IrAnalyze *ira, Scope *scope, AstNode * return ir_build_int_to_enum_gen(ira, scope, source_node, wanted_type, target); } -static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *target, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *target, ZigType *wanted_type) { ZigValue *val = ir_resolve_const(ira, target, UndefBad); if (!val) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); if (wanted_type->id == ZigTypeIdComptimeFloat) { float_init_float(result->value, val); } else if (wanted_type->id == ZigTypeIdComptimeInt) { @@ -6423,7 +6423,7 @@ static IrInstGen *ir_analyze_number_to_literal(IrAnalyze *ira, Scope *scope, Ast return result; } -static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *wanted_type) { assert(target->value->type->id == ZigTypeIdInt); @@ -6435,7 +6435,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s if (!val) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); if (!resolve_inferred_error_set(ira->codegen, wanted_type, source_node)) { return ira->codegen->invalid_inst_gen; @@ -6485,7 +6485,7 @@ static IrInstGen *ir_analyze_int_to_err(IrAnalyze *ira, Scope *scope, AstNode *s return ir_build_int_to_err_gen(ira, scope, source_node, target, wanted_type); } -static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *wanted_type) { assert(wanted_type->id == ZigTypeIdInt); @@ -6497,7 +6497,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s if (!val) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); ErrorTableEntry *err; if (err_type->id == ZigTypeIdErrorUnion) { @@ -6536,11 +6536,11 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s return ira->codegen->invalid_inst_gen; } if (err_set_type->data.error_set.err_count == 0) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); bigint_init_unsigned(&result->value->data.x_bigint, 0); return result; } else if (err_set_type->data.error_set.err_count == 1) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); ErrorTableEntry *err = err_set_type->data.error_set.errors[0]; bigint_init_unsigned(&result->value->data.x_bigint, err->value); return result; @@ -6558,7 +6558,7 @@ static IrInstGen *ir_analyze_err_to_int(IrAnalyze *ira, Scope *scope, AstNode *s return ir_build_err_to_int_gen(ira, scope, source_node, target, wanted_type); } -static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *wanted_type) { assert(wanted_type->id == ZigTypeIdPointer); @@ -6589,7 +6589,7 @@ static IrInstGen *ir_analyze_ptr_to_array(IrAnalyze *ira, Scope *scope, AstNode array_val->parent.id = ConstParentIdScalar; array_val->parent.data.p_scalar.scalar_val = pointee; - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); const_instruction->base.value->type = wanted_type; const_instruction->base.value->special = ConstValSpecialStatic; @@ -6798,12 +6798,12 @@ static void report_recursive_error(IrAnalyze *ira, AstNode *source_node, ConstCa } } -static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *array, ZigType *vector_type) +static Stage1AirInst *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *array, ZigType *vector_type) { if (instr_is_comptime(array)) { // arrays and vectors have the same ZigValue representation - IrInstGen *result = ir_const(ira, scope, source_node, vector_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, vector_type); copy_const_val(ira->codegen, result->value, array->value); result->value->type = vector_type; return result; @@ -6811,12 +6811,12 @@ static IrInstGen *ir_analyze_array_to_vector(IrAnalyze *ira, Scope *scope, AstNo return ir_build_array_to_vector(ira, scope, source_node, array, vector_type); } -static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *vector, ZigType *array_type, ResultLoc *result_loc) +static Stage1AirInst *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *vector, ZigType *array_type, ResultLoc *result_loc) { if (instr_is_comptime(vector)) { // arrays and vectors have the same ZigValue representation - IrInstGen *result = ir_const(ira, scope, source_node, array_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, array_type); copy_const_val(ira->codegen, result->value, vector->value); result->value->type = array_type; return result; @@ -6824,17 +6824,17 @@ static IrInstGen *ir_analyze_vector_to_array(IrAnalyze *ira, Scope *scope, AstNo if (result_loc == nullptr) { result_loc = no_result_loc(); } - IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, array_type, nullptr, true, true); + Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, array_type, nullptr, true, true); if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) { return result_loc_inst; } return ir_build_vector_to_array(ira, scope, source_node, array_type, vector, result_loc_inst); } -static IrInstGen *ir_analyze_int_to_c_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *integer, ZigType *dest_type) +static Stage1AirInst *ir_analyze_int_to_c_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *integer, ZigType *dest_type) { - IrInstGen *unsigned_integer; + Stage1AirInst *unsigned_integer; if (instr_is_comptime(integer)) { unsigned_integer = integer; } else { @@ -6875,7 +6875,7 @@ static bool is_pointery_and_elem_is_not_pointery(ZigType *ty) { return false; } -static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *enum_type) { assert(enum_type->id == ZigTypeIdEnum); @@ -6892,14 +6892,14 @@ static IrInstGen *ir_analyze_enum_literal(IrAnalyze *ira, Scope *scope, AstNode buf_sprintf("'%s' declared here", buf_ptr(&enum_type->name))); return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_const(ira, scope, source_node, enum_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, enum_type); bigint_init_bigint(&result->value->data.x_enum_tag, &field->value); return result; } -static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *struct_ptr, ZigType *actual_type, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *struct_ptr, ZigType *actual_type, ZigType *wanted_type) { Error err; @@ -6918,20 +6918,20 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop // Determine if the struct_operand will be comptime. ZigValue *elem_values = heap::c_allocator.allocate(array_len); - IrInstGen **casted_fields = heap::c_allocator.allocate(array_len); - IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst **casted_fields = heap::c_allocator.allocate(array_len); + Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type); for (size_t i = 0; i < array_len; i += 1) { TypeStructField *src_field = actual_type->data.structure.fields[i]; - IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr, + Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr, actual_type, false); if (type_is_invalid(field_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr); + Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr); if (type_is_invalid(field_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_value = ir_implicit_cast(ira, field_value, elem_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, elem_type); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -6954,13 +6954,13 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop } if (is_comptime) { - IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type); const_result->value->data.x_array.special = ConstArraySpecialNone; const_result->value->data.x_array.data.s_none.elements = elem_values; return const_result; } - IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), + Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), wanted_type, nullptr, true, true); if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) { return ira->codegen->invalid_inst_gen; @@ -6968,12 +6968,12 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop ZigType *elem_type_ptr = get_pointer_to_type(ira->codegen, elem_type, false); for (size_t i = 0; i < array_len; i += 1) { - IrInstGen *index_val = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_usize); + Stage1AirInst *index_val = ir_const(ira, scope, source_node, ira->codegen->builtin_types.entry_usize); bigint_init_unsigned(&index_val->value->data.x_bigint, i); - IrInstGen *elem_ptr = ir_build_elem_ptr_gen(ira, scope, source_node, + Stage1AirInst *elem_ptr = ir_build_elem_ptr_gen(ira, scope, source_node, result_loc_inst, index_val, false, elem_type_ptr); - IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, elem_ptr, casted_fields[i], true); + Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, elem_ptr, casted_fields[i], true); if (type_is_invalid(store_ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; } @@ -6984,8 +6984,8 @@ static IrInstGen *ir_analyze_struct_literal_to_array(IrAnalyze *ira, Scope *scop return result_loc_inst; } -static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *struct_ptr, ZigType *actual_type, ZigType *wanted_type) +static Stage1AirInst *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *struct_ptr, ZigType *actual_type, ZigType *wanted_type) { Error err; @@ -7008,8 +7008,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco // Also emit compile errors for missing fields and duplicate fields. AstNode **field_assign_nodes = heap::c_allocator.allocate(actual_field_count); ZigValue **field_values = heap::c_allocator.allocate(actual_field_count); - IrInstGen **casted_fields = heap::c_allocator.allocate(actual_field_count); - IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst **casted_fields = heap::c_allocator.allocate(actual_field_count); + Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type); for (size_t i = 0; i < instr_field_count; i += 1) { TypeStructField *src_field = actual_type->data.structure.fields[i]; @@ -7046,14 +7046,14 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco } field_assign_nodes[dst_field->src_index] = src_field->decl_node; - IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr, + Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, src_field, struct_ptr, actual_type, false); if (type_is_invalid(field_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr); + Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr); if (type_is_invalid(field_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_value = ir_implicit_cast(ira, field_value, dst_field->type_entry); + Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, dst_field->type_entry); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -7103,12 +7103,12 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco if (is_comptime) { heap::c_allocator.deallocate(field_assign_nodes, actual_field_count); - IrInstGen *const_result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *const_result = ir_const(ira, scope, source_node, wanted_type); const_result->value->data.x_struct.fields = field_values; return const_result; } - IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), + Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), wanted_type, nullptr, true, true); if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) { return ira->codegen->invalid_inst_gen; @@ -7119,10 +7119,10 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco if (field->is_comptime) continue; - IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc_inst, wanted_type, true); + Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc_inst, wanted_type, true); if (type_is_invalid(field_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, field_ptr, casted_fields[i], true); + Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, field_ptr, casted_fields[i], true); if (type_is_invalid(store_ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; } @@ -7134,8 +7134,8 @@ static IrInstGen *ir_analyze_struct_literal_to_struct(IrAnalyze *ira, Scope *sco return result_loc_inst; } -static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *struct_ptr, ZigType *struct_type, ZigType *union_type) +static Stage1AirInst *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *struct_ptr, ZigType *struct_type, ZigType *union_type) { Error err; @@ -7160,15 +7160,15 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop if (payload_type == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, only_field, struct_ptr, + Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, only_field, struct_ptr, struct_type, false); if (type_is_invalid(field_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr); + Stage1AirInst *field_value = ir_get_deref(ira, scope, source_node, field_ptr, nullptr); if (type_is_invalid(field_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_value = ir_implicit_cast(ira, field_value, payload_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, field_value, payload_type); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -7177,7 +7177,7 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop if (val == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, union_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, union_type); bigint_init_bigint(&result->value->data.x_union.tag, &union_field->enum_field->value); result->value->data.x_union.payload = val; @@ -7187,18 +7187,18 @@ static IrInstGen *ir_analyze_struct_literal_to_union(IrAnalyze *ira, Scope *scop return result; } - IrInstGen *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), + Stage1AirInst *result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), union_type, nullptr, true, true); if (type_is_invalid(result_loc_inst->value->type) || result_loc_inst->value->type->id == ZigTypeIdUnreachable) { return ira->codegen->invalid_inst_gen; } - IrInstGen *payload_ptr = ir_analyze_container_field_ptr(ira, only_field->name, + Stage1AirInst *payload_ptr = ir_analyze_container_field_ptr(ira, only_field->name, scope, source_node, result_loc_inst, source_node, union_type, true); if (type_is_invalid(payload_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, payload_ptr, casted_value, false); + Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, payload_ptr, casted_value, false); if (type_is_invalid(store_ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; @@ -7243,30 +7243,30 @@ static Error ir_cast_ptr_align(IrAnalyze *ira, Scope *scope, AstNode *source_nod return ErrorNone; } -static IrInstGen *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *struct_operand, TypeStructField *field) +static Stage1AirInst *ir_analyze_struct_value_field_value(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *struct_operand, TypeStructField *field) { - IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, struct_operand, true, false); + Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, struct_operand, true, false); if (type_is_invalid(struct_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, struct_ptr, + Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, struct_ptr, struct_operand->value->type, false); if (type_is_invalid(field_ptr->value->type)) return ira->codegen->invalid_inst_gen; return ir_get_deref(ira, scope, source_node, field_ptr, nullptr); } -static IrInstGen *ir_analyze_optional_value_payload_value(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *optional_operand, bool safety_check_on) +static Stage1AirInst *ir_analyze_optional_value_payload_value(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *optional_operand, bool safety_check_on) { - IrInstGen *opt_ptr = ir_get_ref(ira, scope, source_node, optional_operand, true, false); - IrInstGen *payload_ptr = ir_analyze_unwrap_optional_payload(ira, scope, source_node, opt_ptr, + Stage1AirInst *opt_ptr = ir_get_ref(ira, scope, source_node, optional_operand, true, false); + Stage1AirInst *payload_ptr = ir_analyze_unwrap_optional_payload(ira, scope, source_node, opt_ptr, safety_check_on, false); return ir_get_deref(ira, scope, source_node, payload_ptr, nullptr); } -static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *wanted_type, IrInstGen *value) +static Stage1AirInst *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *wanted_type, Stage1AirInst *value) { Error err; ZigType *actual_type = value->value->type; @@ -7336,7 +7336,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ actual_type->data.pointer.child_type->data.array.child_type, source_node, !wanted_child_type->data.pointer.is_const).id == ConstCastResultIdOk) { - IrInstGen *cast1 = ir_resolve_ptr_of_array_to_unknown_len_ptr(ira, scope, source_node, value, + Stage1AirInst *cast1 = ir_resolve_ptr_of_array_to_unknown_len_ptr(ira, scope, source_node, value, wanted_child_type); if (type_is_invalid(cast1->value->type)) return ira->codegen->invalid_inst_gen; @@ -7373,11 +7373,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdComptimeFloat) { - IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.error_union.payload_type, value); + Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.error_union.payload_type, value); if (type_is_invalid(cast1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); + Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); if (type_is_invalid(cast2->value->type)) return ira->codegen->invalid_inst_gen; @@ -7394,13 +7394,13 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ wanted_type->id == ZigTypeIdFloat || wanted_type->id == ZigTypeIdComptimeFloat)) { if (value->value->special == ConstValSpecialUndef) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); result->value->special = ConstValSpecialUndef; return result; } if (ir_num_lit_fits_in_other_type(ira, value, wanted_type, true)) { if (wanted_type->id == ZigTypeIdComptimeInt || wanted_type->id == ZigTypeIdInt) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) { copy_const_val(ira->codegen, result->value, value->value); result->value->type = wanted_type; @@ -7409,7 +7409,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ } return result; } else if (wanted_type->id == ZigTypeIdComptimeFloat || wanted_type->id == ZigTypeIdFloat) { - IrInstGen *result = ir_const(ira, scope, source_node, wanted_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, wanted_type); if (actual_type->id == ZigTypeIdComptimeInt || actual_type->id == ZigTypeIdInt) { BigFloat bf; bigfloat_init_bigint(&bf, &value->value->data.x_bigint); @@ -7457,11 +7457,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ actual_type->data.pointer.ptr_len == PtrLenSingle && actual_type->data.pointer.child_type->id == ZigTypeIdArray) { - IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.maybe.child_type, value); + Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, wanted_type->data.maybe.child_type, value); if (type_is_invalid(cast1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); + Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); if (type_is_invalid(cast2->value->type)) return ira->codegen->invalid_inst_gen; @@ -7543,11 +7543,11 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ } if (ok_align) { if (wanted_type->id == ZigTypeIdErrorUnion) { - IrInstGen *cast1 = ir_analyze_cast(ira, scope, source_node, slice_type, value); + Stage1AirInst *cast1 = ir_analyze_cast(ira, scope, source_node, slice_type, value); if (type_is_invalid(cast1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); + Stage1AirInst *cast2 = ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); if (type_is_invalid(cast2->value->type)) return ira->codegen->invalid_inst_gen; @@ -7623,7 +7623,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ } } if (ok) { - IrInstGen *cast1 = ir_analyze_frame_ptr_to_anyframe(ira, scope, source_node, value, anyframe_type); + Stage1AirInst *cast1 = ir_analyze_frame_ptr_to_anyframe(ira, scope, source_node, value, anyframe_type); if (anyframe_type == wanted_type) return cast1; return ir_analyze_cast(ira, scope, source_node, wanted_type, cast1); @@ -7678,7 +7678,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ if (actual_type->id == ZigTypeIdEnumLiteral && (wanted_type->id == ZigTypeIdOptional && wanted_type->data.maybe.child_type->id == ZigTypeIdEnum)) { - IrInstGen *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.maybe.child_type); + Stage1AirInst *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.maybe.child_type); if (type_is_invalid(result->value->type)) return result; @@ -7689,7 +7689,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ if (actual_type->id == ZigTypeIdEnumLiteral && (wanted_type->id == ZigTypeIdErrorUnion && wanted_type->data.error_union.payload_type->id == ZigTypeIdEnum)) { - IrInstGen *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.error_union.payload_type); + Stage1AirInst *result = ir_analyze_enum_literal(ira, scope, source_node, value, wanted_type->data.error_union.payload_type); if (type_is_invalid(result->value->type)) return result; @@ -7751,7 +7751,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ slice_ptr_type->data.pointer.sentinel)))) { TypeStructField *ptr_field = actual_type->data.structure.fields[slice_ptr_index]; - IrInstGen *slice_ptr = ir_analyze_struct_value_field_value(ira, scope, source_node, value, ptr_field); + Stage1AirInst *slice_ptr = ir_analyze_struct_value_field_value(ira, scope, source_node, value, ptr_field); return ir_implicit_cast2(ira, scope, source_node, slice_ptr, wanted_type); } } @@ -7835,31 +7835,31 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ if (wanted_type->id == ZigTypeIdArray && (is_array_init || field_count == 0) && wanted_type->data.array.len == field_count) { - IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false); + Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false); if (type_is_invalid(struct_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr = ir_analyze_struct_literal_to_array(ira, scope, source_node, struct_ptr, actual_type, wanted_type); + Stage1AirInst *ptr = ir_analyze_struct_literal_to_array(ira, scope, source_node, struct_ptr, actual_type, wanted_type); if (ptr->value->type->id != ZigTypeIdPointer) return ptr; return ir_get_deref(ira, scope, source_node, ptr, nullptr); } else if (wanted_type->id == ZigTypeIdStruct && !is_slice(wanted_type) && (!is_array_init || field_count == 0)) { - IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false); + Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false); if (type_is_invalid(struct_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr = ir_analyze_struct_literal_to_struct(ira, scope, source_node, struct_ptr, actual_type, wanted_type); + Stage1AirInst *ptr = ir_analyze_struct_literal_to_struct(ira, scope, source_node, struct_ptr, actual_type, wanted_type); if (ptr->value->type->id != ZigTypeIdPointer) return ptr; return ir_get_deref(ira, scope, source_node, ptr, nullptr); } else if (wanted_type->id == ZigTypeIdUnion && !is_array_init && field_count == 1) { - IrInstGen *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false); + Stage1AirInst *struct_ptr = ir_get_ref(ira, scope, source_node, value, true, false); if (type_is_invalid(struct_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr = ir_analyze_struct_literal_to_union(ira, scope, source_node, struct_ptr, actual_type, wanted_type); + Stage1AirInst *ptr = ir_analyze_struct_literal_to_union(ira, scope, source_node, struct_ptr, actual_type, wanted_type); if (ptr->value->type->id != ZigTypeIdPointer) return ptr; return ir_get_deref(ira, scope, source_node, ptr, nullptr); @@ -7881,19 +7881,19 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ if (wanted_child->id == ZigTypeIdArray && (is_array_init || field_count == 0) && wanted_child->data.array.len == field_count && (const_ok || field_count == 0)) { - IrInstGen *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, wanted_child); + Stage1AirInst *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, wanted_child); if (res->value->type->id == ZigTypeIdPointer) return res; return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile); } else if (wanted_child->id == ZigTypeIdStruct && !is_slice(wanted_type) && (!is_array_init || field_count == 0) && const_ok) { - IrInstGen *res = ir_analyze_struct_literal_to_struct(ira, scope, source_node, value, anon_type, wanted_child); + Stage1AirInst *res = ir_analyze_struct_literal_to_struct(ira, scope, source_node, value, anon_type, wanted_child); if (res->value->type->id == ZigTypeIdPointer) return res; return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile); } else if (wanted_child->id == ZigTypeIdUnion && !is_array_init && field_count == 1 && const_ok) { - IrInstGen *res = ir_analyze_struct_literal_to_union(ira, scope, source_node, value, anon_type, wanted_child); + Stage1AirInst *res = ir_analyze_struct_literal_to_union(ira, scope, source_node, value, anon_type, wanted_child); if (res->value->type->id == ZigTypeIdPointer) return res; return ir_get_ref(ira, scope, source_node, res, actual_type->data.pointer.is_const, actual_type->data.pointer.is_volatile); @@ -7905,7 +7905,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ { ZigType *slice_child_type = slice_type->data.pointer.child_type; ZigType *slice_array_type = get_array_type(ira->codegen, slice_child_type, field_count, nullptr); - IrInstGen *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, slice_array_type); + Stage1AirInst *res = ir_analyze_struct_literal_to_array(ira, scope, source_node, value, anon_type, slice_array_type); if (type_is_invalid(res->value->type)) return ira->codegen->invalid_inst_gen; if (res->value->type->id != ZigTypeIdPointer) @@ -7923,7 +7923,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ // T to ?U, where T implicitly casts to U if (wanted_type->id == ZigTypeIdOptional && actual_type->id != ZigTypeIdOptional) { - IrInstGen *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.maybe.child_type); + Stage1AirInst *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.maybe.child_type); if (type_is_invalid(cast1->value->type)) return ira->codegen->invalid_inst_gen; return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type); @@ -7933,7 +7933,7 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ if (wanted_type->id == ZigTypeIdErrorUnion && actual_type->id != ZigTypeIdErrorUnion && actual_type->id != ZigTypeIdErrorSet) { - IrInstGen *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.error_union.payload_type); + Stage1AirInst *cast1 = ir_implicit_cast2(ira, scope, source_node, value, wanted_type->data.error_union.payload_type); if (type_is_invalid(cast1->value->type)) return ira->codegen->invalid_inst_gen; return ir_implicit_cast2(ira, scope, source_node, cast1, wanted_type); @@ -7947,8 +7947,8 @@ static IrInstGen *ir_analyze_cast(IrAnalyze *ira, Scope *scope, AstNode *source_ return ira->codegen->invalid_inst_gen; } -static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *value, ZigType *expected_type) +static Stage1AirInst *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *value, ZigType *expected_type) { assert(value); assert(!expected_type || !type_is_invalid(expected_type)); @@ -7964,11 +7964,11 @@ static IrInstGen *ir_implicit_cast2(IrAnalyze *ira, Scope *scope, AstNode *sourc return ir_analyze_cast(ira, scope, source_node, expected_type, value); } -static IrInstGen *ir_implicit_cast(IrAnalyze *ira, IrInstGen *value, ZigType *expected_type) { +static Stage1AirInst *ir_implicit_cast(IrAnalyze *ira, Stage1AirInst *value, ZigType *expected_type) { return ir_implicit_cast2(ira, value->scope, value->source_node, value, expected_type); } -static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) { +static ZigType *get_ptr_elem_type(CodeGen *g, Stage1AirInst *ptr) { ir_assert(ptr->value->type->id == ZigTypeIdPointer, ptr); ZigType *elem_type = ptr->value->type->data.pointer.child_type; if (elem_type != g->builtin_types.entry_anytype) @@ -7982,7 +7982,7 @@ static ZigType *get_ptr_elem_type(CodeGen *g, IrInstGen *ptr) { return pointee->type; } -static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *ptr, +static Stage1AirInst *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *ptr, ResultLoc *result_loc) { Error err; @@ -8027,7 +8027,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod child_type = pointee->type; } if (pointee->special != ConstValSpecialRuntime) { - IrInstGen *result = ir_const(ira, scope, source_node, child_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, child_type); if ((err = ir_read_const_ptr(ira, ira->codegen, source_node, result->value, ptr->value))) @@ -8041,25 +8041,25 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod } // if the instruction is a const ref instruction we can skip it - if (ptr->id == IrInstGenIdRef) { - IrInstGenRef *ref_inst = reinterpret_cast(ptr); + if (ptr->id == Stage1AirInstIdRef) { + Stage1AirInstRef *ref_inst = reinterpret_cast(ptr); return ref_inst->operand; } // If the instruction is a element pointer instruction to a vector, we emit // vector element extract instruction rather than load pointer. If the // pointer type has non-VECTOR_INDEX_RUNTIME value, it would have been - // possible to implement this in the codegen for IrInstGenLoadPtr. + // possible to implement this in the codegen for Stage1AirInstLoadPtr. // However if it has VECTOR_INDEX_RUNTIME then we must emit a compile error // if the vector index cannot be determined right here, right now, because // the type information does not contain enough information to actually // perform a dereference. if (ptr_type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) { - if (ptr->id == IrInstGenIdElemPtr) { - IrInstGenElemPtr *elem_ptr = (IrInstGenElemPtr *)ptr; - IrInstGen *vector_loaded = ir_get_deref(ira, elem_ptr->array_ptr->scope, + if (ptr->id == Stage1AirInstIdElemPtr) { + Stage1AirInstElemPtr *elem_ptr = (Stage1AirInstElemPtr *)ptr; + Stage1AirInst *vector_loaded = ir_get_deref(ira, elem_ptr->array_ptr->scope, elem_ptr->array_ptr->source_node, elem_ptr->array_ptr, nullptr); - IrInstGen *elem_index = elem_ptr->elem_index; + Stage1AirInst *elem_index = elem_ptr->elem_index; return ir_build_vector_extract_elem(ira, scope, source_node, vector_loaded, elem_index); } ir_add_error(ira, ptr, @@ -8067,7 +8067,7 @@ static IrInstGen *ir_get_deref(IrAnalyze *ira, Scope *scope, AstNode *source_nod return ira->codegen->invalid_inst_gen; } - IrInstGen *result_loc_inst; + Stage1AirInst *result_loc_inst; if (ptr_type->data.pointer.host_int_bytes != 0 && handle_is_ptr(ira->codegen, child_type)) { if (result_loc == nullptr) result_loc = no_result_loc(); result_loc_inst = ir_resolve_result(ira, ira->suspend_source_instr, result_loc, child_type, nullptr, true, true); @@ -8104,7 +8104,7 @@ static bool ir_resolve_const_align(CodeGen *codegen, Stage1Air *exec, AstNode *s return true; } -static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_type, uint32_t *out) { +static bool ir_resolve_align(IrAnalyze *ira, Stage1AirInst *value, ZigType *elem_type, uint32_t *out) { if (type_is_invalid(value->value->type)) return false; @@ -8125,7 +8125,7 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ } } - IrInstGen *casted_value = ir_implicit_cast(ira, value, get_align_amt_type(ira->codegen)); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, get_align_amt_type(ira->codegen)); if (type_is_invalid(casted_value->value->type)) return false; @@ -8133,11 +8133,11 @@ static bool ir_resolve_align(IrAnalyze *ira, IrInstGen *value, ZigType *elem_typ casted_value->value, out); } -static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_type, uint64_t *out) { +static bool ir_resolve_unsigned(IrAnalyze *ira, Stage1AirInst *value, ZigType *int_type, uint64_t *out) { if (type_is_invalid(value->value->type)) return false; - IrInstGen *casted_value = ir_implicit_cast(ira, value, int_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, int_type); if (type_is_invalid(casted_value->value->type)) return false; @@ -8149,15 +8149,15 @@ static bool ir_resolve_unsigned(IrAnalyze *ira, IrInstGen *value, ZigType *int_t return true; } -static bool ir_resolve_usize(IrAnalyze *ira, IrInstGen *value, uint64_t *out) { +static bool ir_resolve_usize(IrAnalyze *ira, Stage1AirInst *value, uint64_t *out) { return ir_resolve_unsigned(ira, value, ira->codegen->builtin_types.entry_usize, out); } -static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) { +static bool ir_resolve_bool(IrAnalyze *ira, Stage1AirInst *value, bool *out) { if (type_is_invalid(value->value->type)) return false; - IrInstGen *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_bool); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_bool); if (type_is_invalid(casted_value->value->type)) return false; @@ -8169,7 +8169,7 @@ static bool ir_resolve_bool(IrAnalyze *ira, IrInstGen *value, bool *out) { return true; } -static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) { +static bool ir_resolve_comptime(IrAnalyze *ira, Stage1AirInst *value, bool *out) { if (!value) { *out = false; return true; @@ -8177,13 +8177,13 @@ static bool ir_resolve_comptime(IrAnalyze *ira, IrInstGen *value, bool *out) { return ir_resolve_bool(ira, value, out); } -static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out) { +static bool ir_resolve_reduce_op(IrAnalyze *ira, Stage1AirInst *value, ReduceOp *out) { if (type_is_invalid(value->value->type)) return false; ZigType *reduce_op_type = get_builtin_type(ira->codegen, "ReduceOp"); - IrInstGen *casted_value = ir_implicit_cast(ira, value, reduce_op_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, reduce_op_type); if (type_is_invalid(casted_value->value->type)) return false; @@ -8195,13 +8195,13 @@ static bool ir_resolve_reduce_op(IrAnalyze *ira, IrInstGen *value, ReduceOp *out return true; } -static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrder *out) { +static bool ir_resolve_atomic_order(IrAnalyze *ira, Stage1AirInst *value, AtomicOrder *out) { if (type_is_invalid(value->value->type)) return false; ZigType *atomic_order_type = get_builtin_type(ira->codegen, "AtomicOrder"); - IrInstGen *casted_value = ir_implicit_cast(ira, value, atomic_order_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, atomic_order_type); if (type_is_invalid(casted_value->value->type)) return false; @@ -8213,13 +8213,13 @@ static bool ir_resolve_atomic_order(IrAnalyze *ira, IrInstGen *value, AtomicOrde return true; } -static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmwOp *out) { +static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, Stage1AirInst *value, AtomicRmwOp *out) { if (type_is_invalid(value->value->type)) return false; ZigType *atomic_rmw_op_type = get_builtin_type(ira->codegen, "AtomicRmwOp"); - IrInstGen *casted_value = ir_implicit_cast(ira, value, atomic_rmw_op_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, atomic_rmw_op_type); if (type_is_invalid(casted_value->value->type)) return false; @@ -8231,13 +8231,13 @@ static bool ir_resolve_atomic_rmw_op(IrAnalyze *ira, IrInstGen *value, AtomicRmw return true; } -static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLinkageId *out) { +static bool ir_resolve_global_linkage(IrAnalyze *ira, Stage1AirInst *value, GlobalLinkageId *out) { if (type_is_invalid(value->value->type)) return false; ZigType *global_linkage_type = get_builtin_type(ira->codegen, "GlobalLinkage"); - IrInstGen *casted_value = ir_implicit_cast(ira, value, global_linkage_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, global_linkage_type); if (type_is_invalid(casted_value->value->type)) return false; @@ -8249,13 +8249,13 @@ static bool ir_resolve_global_linkage(IrAnalyze *ira, IrInstGen *value, GlobalLi return true; } -static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *out) { +static bool ir_resolve_float_mode(IrAnalyze *ira, Stage1AirInst *value, FloatMode *out) { if (type_is_invalid(value->value->type)) return false; ZigType *float_mode_type = get_builtin_type(ira->codegen, "FloatMode"); - IrInstGen *casted_value = ir_implicit_cast(ira, value, float_mode_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, float_mode_type); if (type_is_invalid(casted_value->value->type)) return false; @@ -8267,14 +8267,14 @@ static bool ir_resolve_float_mode(IrAnalyze *ira, IrInstGen *value, FloatMode *o return true; } -static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) { +static Buf *ir_resolve_str(IrAnalyze *ira, Stage1AirInst *value) { if (type_is_invalid(value->value->type)) return nullptr; ZigType *ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8, true, false, PtrLenUnknown, 0, 0, 0, false); ZigType *str_type = get_slice_type(ira->codegen, ptr_type); - IrInstGen *casted_value = ir_implicit_cast(ira, value, str_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, str_type); if (type_is_invalid(casted_value->value->type)) return nullptr; @@ -8309,10 +8309,10 @@ static Buf *ir_resolve_str(IrAnalyze *ira, IrInstGen *value) { return result; } -static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira, - IrInstSrcAddImplicitReturnType *instruction) +static Stage1AirInst *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira, + Stage1ZirInstAddImplicitReturnType *instruction) { - IrInstGen *value = instruction->value->child; + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ir_unreach_error(ira); @@ -8323,18 +8323,18 @@ static IrInstGen *ir_analyze_instruction_add_implicit_return_type(IrAnalyze *ira return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn *instruction) { +static Stage1AirInst *ir_analyze_instruction_return(IrAnalyze *ira, Stage1ZirInstReturn *instruction) { if (instruction->operand == nullptr) { // result location mechanism took care of it. - IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr); return ir_finish_anal(ira, result); } - IrInstGen *operand = instruction->operand->child; + Stage1AirInst *operand = instruction->operand->child; if (type_is_invalid(operand->value->type)) return ir_unreach_error(ira); - IrInstGen *casted_operand = ir_implicit_cast(ira, operand, ira->explicit_return_type); + Stage1AirInst *casted_operand = ir_implicit_cast(ira, operand, ira->explicit_return_type); if (type_is_invalid(casted_operand->value->type)) { AstNode *source_node = ira->explicit_return_type_source_node; if (source_node != nullptr) { @@ -8349,7 +8349,7 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn handle_is_ptr(ira->codegen, ira->explicit_return_type)) { // result location mechanism took care of it. - IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, nullptr); return ir_finish_anal(ira, result); } @@ -8362,30 +8362,30 @@ static IrInstGen *ir_analyze_instruction_return(IrAnalyze *ira, IrInstSrcReturn return ir_unreach_error(ira); } - IrInstGen *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, casted_operand); + Stage1AirInst *result = ir_build_return_gen(ira, instruction->base.scope, instruction->base.source_node, casted_operand); return ir_finish_anal(ira, result); } -static IrInstGen *ir_analyze_instruction_const(IrAnalyze *ira, IrInstSrcConst *instruction) { +static Stage1AirInst *ir_analyze_instruction_const(IrAnalyze *ira, Stage1ZirInstConst *instruction) { return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, instruction->value); } -static IrInstGen *ir_analyze_bin_op_bool(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) { - IrInstGen *op1 = bin_op_instruction->op1->child; +static Stage1AirInst *ir_analyze_bin_op_bool(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) { + Stage1AirInst *op1 = bin_op_instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = bin_op_instruction->op2->child; + Stage1AirInst *op2 = bin_op_instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; ZigType *bool_type = ira->codegen->builtin_types.entry_bool; - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, bool_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, bool_type); if (type_is_invalid(casted_op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, bool_type); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, bool_type); if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -8465,7 +8465,7 @@ static void set_optional_payload(ZigValue *opt_val, ZigValue *payload) { } } -static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type, +static Stage1AirInst *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type, ZigValue *op1_val, ZigValue *op2_val, Scope *scope, AstNode *source_node, IrBinOp op_id, bool one_possible_value) { @@ -8508,7 +8508,7 @@ static IrInstGen *ir_evaluate_bin_op_cmp(IrAnalyze *ira, ZigType *resolved_type, zig_unreachable(); } -static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *op1, IrInstGen *op2, +static Stage1AirInst *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *op1, Stage1AirInst *op2, ZigType *resolved_type, IrBinOp op_id) { assert(op1->value->type == resolved_type && op2->value->type == resolved_type); @@ -8533,14 +8533,14 @@ static IrInstGen *ir_try_evaluate_bin_op_cmp_const(IrAnalyze *ira, Scope *scope, return ira->codegen->invalid_inst_gen; if (resolved_type->id != ZigTypeIdVector) return ir_evaluate_bin_op_cmp(ira, resolved_type, op1_val, op2_val, scope, source_node, op_id, one_possible_value); - IrInstGen *result = ir_const(ira, scope, source_node, + Stage1AirInst *result = ir_const(ira, scope, source_node, get_vector_type(ira->codegen, resolved_type->data.vector.len, ira->codegen->builtin_types.entry_bool)); result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate(resolved_type->data.vector.len); expand_undef_array(ira->codegen, result->value); for (size_t i = 0;i < resolved_type->data.vector.len;i++) { - IrInstGen *cur_res = ir_evaluate_bin_op_cmp(ira, resolved_type->data.vector.elem_type, + Stage1AirInst *cur_res = ir_evaluate_bin_op_cmp(ira, resolved_type->data.vector.elem_type, &op1_val->data.x_array.data.s_none.elements[i], &op2_val->data.x_array.data.s_none.elements[i], scope, source_node, op_id, one_possible_value); @@ -8708,14 +8708,14 @@ never_mind_just_calculate_it_normally: return nullptr; } if (op1_val->type->id == ZigTypeIdComptimeFloat) { - IrInstGen *tmp = ir_const_noval(ira, scope, source_node); + Stage1AirInst *tmp = ir_const_noval(ira, scope, source_node); tmp->value = op1_val; - IrInstGen *casted = ir_implicit_cast(ira, tmp, op2_val->type); + Stage1AirInst *casted = ir_implicit_cast(ira, tmp, op2_val->type); op1_val = casted->value; } else if (op2_val->type->id == ZigTypeIdComptimeFloat) { - IrInstGen *tmp = ir_const_noval(ira, scope, source_node); + Stage1AirInst *tmp = ir_const_noval(ira, scope, source_node); tmp->value = op2_val; - IrInstGen *casted = ir_implicit_cast(ira, tmp, op1_val->type); + Stage1AirInst *casted = ir_implicit_cast(ira, tmp, op1_val->type); op2_val = casted->value; } Cmp cmp_result = float_cmp(op1_val, op2_val); @@ -8768,8 +8768,8 @@ never_mind_just_calculate_it_normally: return nullptr; } -static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *op1, IrInstGen *op2, IrBinOp op_id) +static Stage1AirInst *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *op1, Stage1AirInst *op2, IrBinOp op_id) { Error err; @@ -8833,7 +8833,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As if (((opv_op1 || instr_is_comptime(op1)) && (opv_op2 || instr_is_comptime(op2))) || (have_op1_cmp_zero && have_op2_cmp_zero)) { - IrInstGen *result_instruction = ir_const(ira, scope, source_node, result_type); + Stage1AirInst *result_instruction = ir_const(ira, scope, source_node, result_type); ZigValue *out_val = result_instruction->value; if (result_type->id == ZigTypeIdVector) { size_t len = result_type->data.vector.len; @@ -8954,8 +8954,8 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As } ZigType *dest_type = (result_type->id == ZigTypeIdVector) ? get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type; - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type); - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, dest_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, dest_type); if (type_is_invalid(casted_op1->value->type) || type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true); @@ -9071,10 +9071,10 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, Scope *scope, As ZigType *dest_type = (result_type->id == ZigTypeIdVector) ? get_vector_type(ira->codegen, result_type->data.vector.len, dest_scalar_type) : dest_scalar_type; - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type); if (type_is_invalid(casted_op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, dest_type); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, dest_type); if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; return ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, casted_op1, casted_op2, true); @@ -9128,8 +9128,8 @@ static bool type_is_self_comparable(ZigType *ty, bool is_equality_cmp) { zig_unreachable(); } -static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type, - IrInstGen *optional, IrInstGen *non_optional, IrBinOp op_id) +static Stage1AirInst *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type, + Stage1AirInst *optional, Stage1AirInst *non_optional, IrBinOp op_id) { assert(optional->value->type->id == ZigTypeIdOptional); assert(optional->value->type->data.maybe.child_type == non_optional->value->type); @@ -9148,12 +9148,12 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira } if (!optional_value_is_null(optional_val)) { - IrInstGen *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false); + Stage1AirInst *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false); if (type_is_invalid(optional_unwrapped->value->type)) { return ira->codegen->invalid_inst_gen; } - IrInstGen *ret = ir_try_evaluate_bin_op_cmp_const(ira, scope, source_node, optional_unwrapped, non_optional, child_type, op_id); + Stage1AirInst *ret = ir_try_evaluate_bin_op_cmp_const(ira, scope, source_node, optional_unwrapped, non_optional, child_type, op_id); assert(ret != nullptr); return ret; } @@ -9163,8 +9163,8 @@ static IrInstGen *ir_try_evaluate_cmp_optional_non_optional_const(IrAnalyze *ira } } -static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type, - IrInstGen *optional, IrInstGen *non_optional, IrBinOp op_id) +static Stage1AirInst *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *child_type, + Stage1AirInst *optional, Stage1AirInst *non_optional, IrBinOp op_id) { assert(optional->value->type->id == ZigTypeIdOptional); assert(optional->value->type->data.maybe.child_type == non_optional->value->type); @@ -9174,47 +9174,47 @@ static IrInstGen *ir_evaluate_cmp_optional_non_optional(IrAnalyze *ira, Scope *s ZigType *result_type = ira->codegen->builtin_types.entry_bool; ir_append_basic_block_gen(&ira->new_irb, ira->new_irb.current_basic_block); - IrBasicBlockGen *null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNull"); - IrBasicBlockGen *non_null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNotNull"); - IrBasicBlockGen *end_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalEnd"); + Stage1AirBasicBlock *null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNull"); + Stage1AirBasicBlock *non_null_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalOptionalNotNull"); + Stage1AirBasicBlock *end_block = ir_create_basic_block_gen(ira, scope, "CmpOptionalNonOptionalEnd"); - IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, scope, source_node, optional); + Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, scope, source_node, optional); ir_build_cond_br_gen(ira, scope, source_node, is_non_null, non_null_block, null_block); ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, non_null_block); - IrInstGen *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false); + Stage1AirInst *optional_unwrapped = ir_analyze_optional_value_payload_value(ira, scope, source_node, optional, false); if (type_is_invalid(optional_unwrapped->value->type)) { return ira->codegen->invalid_inst_gen; } - IrInstGen *non_null_cmp_result = ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, + Stage1AirInst *non_null_cmp_result = ir_build_bin_op_gen(ira, scope, source_node, result_type, op_id, optional_unwrapped, non_optional, false); // safety check unnecessary for comparison operators ir_build_br_gen(ira, scope, source_node, end_block); ir_set_cursor_at_end_and_append_block_gen(&ira->new_irb, null_block); - IrInstGen *null_result = ir_const_bool(ira, scope, source_node, (op_id != IrBinOpCmpEq)); + Stage1AirInst *null_result = ir_const_bool(ira, scope, source_node, (op_id != IrBinOpCmpEq)); ir_build_br_gen(ira, scope, source_node, end_block); ir_set_cursor_at_end_gen(&ira->new_irb, end_block); int incoming_count = 2; - IrBasicBlockGen **incoming_blocks = heap::c_allocator.allocate_nonzero(incoming_count); + Stage1AirBasicBlock **incoming_blocks = heap::c_allocator.allocate_nonzero(incoming_count); incoming_blocks[0] = null_block; incoming_blocks[1] = non_null_block; - IrInstGen **incoming_values = heap::c_allocator.allocate_nonzero(incoming_count); + Stage1AirInst **incoming_values = heap::c_allocator.allocate_nonzero(incoming_count); incoming_values[0] = null_result; incoming_values[1] = non_null_cmp_result; return ir_build_phi_gen(ira, scope, source_node, incoming_count, incoming_blocks, incoming_values, result_type); } -static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *op1, IrInstGen *op2, IrInstGen *optional, IrBinOp op_id) +static Stage1AirInst *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *op1, Stage1AirInst *op2, Stage1AirInst *optional, IrBinOp op_id) { assert(op_id == IrBinOpCmpEq || op_id == IrBinOpCmpNotEq); assert(optional->value->type->id == ZigTypeIdOptional); assert(get_src_ptr_type(optional->value->type) == nullptr); - IrInstGen *non_optional; + Stage1AirInst *non_optional; if (op1 == optional) { non_optional = op2; } else if (op2 == optional) { @@ -9253,7 +9253,7 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc return ira->codegen->invalid_inst_gen; } - if (IrInstGen *const_result = ir_try_evaluate_cmp_optional_non_optional_const(ira, scope, source_node, child_type, + if (Stage1AirInst *const_result = ir_try_evaluate_cmp_optional_non_optional_const(ira, scope, source_node, child_type, optional, non_optional, op_id)) { return const_result; @@ -9262,12 +9262,12 @@ static IrInstGen *ir_analyze_cmp_optional_non_optional(IrAnalyze *ira, Scope *sc return ir_evaluate_cmp_optional_non_optional(ira, scope, source_node, child_type, optional, non_optional, op_id); } -static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) { - IrInstGen *op1 = bin_op_instruction->op1->child; +static Stage1AirInst *ir_analyze_bin_op_cmp(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) { + Stage1AirInst *op1 = bin_op_instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = bin_op_instruction->op2->child; + Stage1AirInst *op2 = bin_op_instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -9282,7 +9282,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i ((op1->value->type->id == ZigTypeIdNull && op2->value->type->id == ZigTypeIdOptional) || (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdOptional))) { - IrInstGen *maybe_op; + Stage1AirInst *maybe_op; if (op1->value->type->id == ZigTypeIdNull) { maybe_op = op2; } else if (op2->value->type->id == ZigTypeIdNull) { @@ -9300,7 +9300,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i bin_op_instruction->base.source_node, bool_result); } - IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, + Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, maybe_op); if (op_id == IrBinOpCmpEq) { @@ -9315,7 +9315,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i (op2->value->type->id == ZigTypeIdNull && op1->value->type->id == ZigTypeIdPointer && op1->value->type->data.pointer.ptr_len == PtrLenC))) { - IrInstGen *c_ptr_op; + Stage1AirInst *c_ptr_op; if (op1->value->type->id == ZigTypeIdNull) { c_ptr_op = op2; } else if (op2->value->type->id == ZigTypeIdNull) { @@ -9335,7 +9335,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i bool bool_result = (op_id == IrBinOpCmpEq) ? is_null : !is_null; return ir_const_bool(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, bool_result); } - IrInstGen *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, c_ptr_op); + Stage1AirInst *is_non_null = ir_build_test_non_null_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, c_ptr_op); if (op_id == IrBinOpCmpEq) { return ir_build_bool_not_gen(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, is_non_null); @@ -9360,8 +9360,8 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i (op2->value->type->id == ZigTypeIdEnumLiteral && op1->value->type->id == ZigTypeIdUnion))) { // Support equality comparison between a union's tag value and a enum literal - IrInstGen *union_val = op1->value->type->id == ZigTypeIdUnion ? op1 : op2; - IrInstGen *enum_val = op1->value->type->id == ZigTypeIdUnion ? op2 : op1; + Stage1AirInst *union_val = op1->value->type->id == ZigTypeIdUnion ? op1 : op2; + Stage1AirInst *enum_val = op1->value->type->id == ZigTypeIdUnion ? op2 : op1; if (!is_tagged_union(union_val->value->type)) { ErrorMsg *msg = ir_add_error_node(ira, source_node, @@ -9375,11 +9375,11 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i ZigType *tag_type = union_val->value->type->data.unionation.tag_type; assert(tag_type != nullptr); - IrInstGen *casted_union = ir_implicit_cast(ira, union_val, tag_type); + Stage1AirInst *casted_union = ir_implicit_cast(ira, union_val, tag_type); if (type_is_invalid(casted_union->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_val = ir_implicit_cast(ira, enum_val, tag_type); + Stage1AirInst *casted_val = ir_implicit_cast(ira, enum_val, tag_type); if (type_is_invalid(casted_val->value->type)) return ira->codegen->invalid_inst_gen; @@ -9486,7 +9486,7 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i return ir_analyze_bin_op_cmp_numeric(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, op1, op2, op_id); } - IrInstGen *instructions[] = {op1, op2}; + Stage1AirInst *instructions[] = {op1, op2}; ZigType *resolved_type = ir_resolve_peer_types(ira, source_node, nullptr, instructions, 2); if (type_is_invalid(resolved_type)) return ira->codegen->invalid_inst_gen; @@ -9499,15 +9499,15 @@ static IrInstGen *ir_analyze_bin_op_cmp(IrAnalyze *ira, IrInstSrcBinOp *bin_op_i return ira->codegen->invalid_inst_gen; } - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, resolved_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, resolved_type); if (type_is_invalid(casted_op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, resolved_type); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, resolved_type); if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *resolve_const_result = ir_try_evaluate_bin_op_cmp_const(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, casted_op1, + Stage1AirInst *resolve_const_result = ir_try_evaluate_bin_op_cmp_const(ira, bin_op_instruction->base.scope, bin_op_instruction->base.source_node, casted_op1, casted_op2, resolved_type, op_id); if (resolve_const_result != nullptr) { return resolve_const_result; @@ -9700,10 +9700,10 @@ static ErrorMsg *ir_eval_math_op_scalar(IrAnalyze *ira, Scope *scope, AstNode *s } // This works on operands that have already been checked to be comptime known. -static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *source_node, +static Stage1AirInst *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *type_entry, ZigValue *op1_val, IrBinOp op_id, ZigValue *op2_val) { - IrInstGen *result_instruction = ir_const(ira, scope, source_node, type_entry); + Stage1AirInst *result_instruction = ir_const(ira, scope, source_node, type_entry); ZigValue *out_val = result_instruction->value; if (type_entry->id == ZigTypeIdVector) { expand_undef_array(ira->codegen, op1_val); @@ -9736,12 +9736,12 @@ static IrInstGen *ir_analyze_math_op(IrAnalyze *ira, Scope *scope, AstNode *sour return ir_implicit_cast(ira, result_instruction, type_entry); } -static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) { - IrInstGen *op1 = bin_op_instruction->op1->child; +static Stage1AirInst *ir_analyze_bit_shift(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) { + Stage1AirInst *op1 = bin_op_instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = bin_op_instruction->op2->child; + Stage1AirInst *op2 = bin_op_instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -9781,7 +9781,7 @@ static IrInstGen *ir_analyze_bit_shift(IrAnalyze *ira, IrInstSrcBinOp *bin_op_in return ira->codegen->invalid_inst_gen; } - IrInstGen *casted_op2; + Stage1AirInst *casted_op2; IrBinOp op_id = bin_op_instruction->op_id; if (op1_scalar_type->id == ZigTypeIdComptimeInt) { // comptime_int has no finite bit width @@ -10005,14 +10005,14 @@ static bool value_cmp_numeric_val_all(ZigValue *left, Cmp predicate, ZigValue *r return value_cmp_numeric_val(left, predicate, right, false); } -static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruction) { +static Stage1AirInst *ir_analyze_bin_op_math(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) { Error err; - IrInstGen *op1 = instruction->op1->child; + Stage1AirInst *op1 = instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = instruction->op2->child; + Stage1AirInst *op2 = instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -10020,7 +10020,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc // look for pointer math if (is_pointer_arithmetic_allowed(op1->value->type, op_id)) { - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, ira->codegen->builtin_types.entry_usize); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, ira->codegen->builtin_types.entry_usize); if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -10095,7 +10095,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc } else { zig_unreachable(); } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); result->value->data.x_ptr.special = ConstPtrSpecialHardCodedAddr; result->value->data.x_ptr.mut = ConstPtrMutRuntimeVar; result->value->data.x_ptr.data.hard_coded_addr.addr = new_addr; @@ -10105,7 +10105,7 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc return ir_build_bin_op_gen(ira, instruction->base.scope, instruction->base.source_node, result_type, op_id, op1, casted_op2, true); } - IrInstGen *instructions[] = {op1, op2}; + Stage1AirInst *instructions[] = {op1, op2}; ZigType *resolved_type = ir_resolve_peer_types(ira, instruction->base.source_node, nullptr, instructions, 2); if (type_is_invalid(resolved_type)) return ira->codegen->invalid_inst_gen; @@ -10125,11 +10125,11 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc return ira->codegen->invalid_inst_gen; } - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, resolved_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, resolved_type); if (type_is_invalid(casted_op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, resolved_type); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, resolved_type); if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -10170,17 +10170,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc // division function ambiguity problem. ok = true; } else { - IrInstGen *trunc_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, + Stage1AirInst *trunc_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, op1_val, IrBinOpDivTrunc, op2_val); if (type_is_invalid(trunc_val->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *floor_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, + Stage1AirInst *floor_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, op1_val, IrBinOpDivFloor, op2_val); if (type_is_invalid(floor_val->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node, + Stage1AirInst *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node, trunc_val, floor_val, IrBinOpCmpEq); if (type_is_invalid(cmp_val->value->type)) return ira->codegen->invalid_inst_gen; @@ -10209,17 +10209,17 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc // division function ambiguity problem. ok = true; } else { - IrInstGen *rem_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, + Stage1AirInst *rem_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, op1_val, IrBinOpRemRem, op2_val); if (type_is_invalid(rem_val->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *mod_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, + Stage1AirInst *mod_val = ir_analyze_math_op(ira, instruction->base.scope, instruction->base.source_node, resolved_type, op1_val, IrBinOpRemMod, op2_val); if (type_is_invalid(mod_val->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node, + Stage1AirInst *cmp_val = ir_analyze_bin_op_cmp_numeric(ira, instruction->base.scope, instruction->base.source_node, rem_val, mod_val, IrBinOpCmpEq); if (type_is_invalid(cmp_val->value->type)) return ira->codegen->invalid_inst_gen; @@ -10273,8 +10273,8 @@ static IrInstGen *ir_analyze_bin_op_math(IrAnalyze *ira, IrInstSrcBinOp *instruc op_id, casted_op1, casted_op2, instruction->safety_check_on); } -static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *op1, IrInstGen *op2) +static Stage1AirInst *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *op1, Stage1AirInst *op2) { Error err; ZigType *op1_type = op1->value->type; @@ -10296,7 +10296,7 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so new_type->data.structure.fields = realloc_type_struct_fields(new_type->data.structure.fields, 0, new_field_count); - IrInstGen *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), + Stage1AirInst *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), new_type, nullptr, false, true); for (uint32_t i = 0; i < new_field_count; i += 1) { @@ -10318,10 +10318,10 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown))) return ira->codegen->invalid_inst_gen; - ZigList const_ptrs = {}; + ZigList const_ptrs = {}; for (uint32_t i = 0; i < new_field_count; i += 1) { TypeStructField *dst_field = new_type->data.structure.fields[i]; - IrInstGen *src_struct_op; + Stage1AirInst *src_struct_op; TypeStructField *src_field; if (i < op1_field_count) { src_field = op1_type->data.structure.fields[i]; @@ -10330,18 +10330,18 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so src_field = op2_type->data.structure.fields[i - op1_field_count]; src_struct_op = op2; } - IrInstGen *field_value = ir_analyze_struct_value_field_value(ira, scope, source_node, + Stage1AirInst *field_value = ir_analyze_struct_value_field_value(ira, scope, source_node, src_struct_op, src_field); if (type_is_invalid(field_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *dest_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, dst_field, + Stage1AirInst *dest_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, dst_field, new_struct_ptr, new_type, true); if (type_is_invalid(dest_ptr->value->type)) return ira->codegen->invalid_inst_gen; if (instr_is_comptime(field_value)) { const_ptrs.append(dest_ptr); } - IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, dest_ptr, field_value, + Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, scope, source_node, dest_ptr, field_value, true); if (type_is_invalid(store_ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; @@ -10349,13 +10349,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so if (const_ptrs.length != new_field_count) { new_struct_ptr->value->special = ConstValSpecialRuntime; for (size_t i = 0; i < const_ptrs.length; i += 1) { - IrInstGen *elem_result_loc = const_ptrs.at(i); + Stage1AirInst *elem_result_loc = const_ptrs.at(i); assert(elem_result_loc->value->special == ConstValSpecialStatic); if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) { // This field will be generated comptime; no need to do this. continue; } - IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope, + Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope, elem_result_loc->source_node, elem_result_loc, nullptr); if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) { elem_result_loc->value->special = ConstValSpecialRuntime; @@ -10369,13 +10369,13 @@ static IrInstGen *ir_analyze_tuple_cat(IrAnalyze *ira, Scope *scope, AstNode *so return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr); } -static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instruction) { - IrInstGen *op1 = instruction->op1->child; +static Stage1AirInst *ir_analyze_array_cat(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) { + Stage1AirInst *op1 = instruction->op1->child; ZigType *op1_type = op1->value->type; if (type_is_invalid(op1_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = instruction->op2->child; + Stage1AirInst *op2 = instruction->op2->child; ZigType *op2_type = op2->value->type; if (type_is_invalid(op2_type)) return ira->codegen->invalid_inst_gen; @@ -10510,7 +10510,7 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi } // The type of result is populated in the following if blocks - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); ZigValue *out_val = result->value; ZigValue *out_array_val; @@ -10598,8 +10598,8 @@ static IrInstGen *ir_analyze_array_cat(IrAnalyze *ira, IrInstSrcBinOp *instructi return result; } -static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *op1, IrInstGen *op2) +static Stage1AirInst *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *op1, Stage1AirInst *op2) { Error err; ZigType *op1_type = op1->value->type; @@ -10626,7 +10626,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s new_type->data.structure.fields = realloc_type_struct_fields( new_type->data.structure.fields, 0, new_field_count); - IrInstGen *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), + Stage1AirInst *new_struct_ptr = ir_resolve_result(ira, ira->suspend_source_instr, no_result_loc(), new_type, nullptr, false, true); for (uint64_t i = 0; i < new_field_count; i += 1) { @@ -10645,17 +10645,17 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s if ((err = type_resolve(ira->codegen, new_type, ResolveStatusZeroBitsKnown))) return ira->codegen->invalid_inst_gen; - ZigList const_ptrs = {}; + ZigList const_ptrs = {}; for (uint64_t i = 0; i < new_field_count; i += 1) { TypeStructField *src_field = op1_type->data.structure.fields[i % op1_field_count]; TypeStructField *dst_field = new_type->data.structure.fields[i]; - IrInstGen *field_value = ir_analyze_struct_value_field_value( + Stage1AirInst *field_value = ir_analyze_struct_value_field_value( ira, scope, source_node, op1, src_field); if (type_is_invalid(field_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *dest_ptr = ir_analyze_struct_field_ptr( + Stage1AirInst *dest_ptr = ir_analyze_struct_field_ptr( ira, scope, source_node, dst_field, new_struct_ptr, new_type, true); if (type_is_invalid(dest_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -10664,7 +10664,7 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s const_ptrs.append(dest_ptr); } - IrInstGen *store_ptr_inst = ir_analyze_store_ptr( + Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr( ira, scope, source_node, dest_ptr, field_value, true); if (type_is_invalid(store_ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; @@ -10673,18 +10673,18 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s if (const_ptrs.length != new_field_count) { new_struct_ptr->value->special = ConstValSpecialRuntime; for (size_t i = 0; i < const_ptrs.length; i += 1) { - IrInstGen *elem_result_loc = const_ptrs.at(i); + Stage1AirInst *elem_result_loc = const_ptrs.at(i); assert(elem_result_loc->value->special == ConstValSpecialStatic); if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) { // This field will be generated comptime; no need to do this. continue; } - IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope, + Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope, elem_result_loc->source_node, elem_result_loc, nullptr); if (!type_requires_comptime(ira->codegen, elem_result_loc->value->type->data.pointer.child_type)) { elem_result_loc->value->special = ConstValSpecialRuntime; } - IrInstGen *store_ptr_inst = ir_analyze_store_ptr(ira, elem_result_loc->scope, + Stage1AirInst *store_ptr_inst = ir_analyze_store_ptr(ira, elem_result_loc->scope, elem_result_loc->source_node, elem_result_loc, deref, true); if (type_is_invalid(store_ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; @@ -10696,12 +10696,12 @@ static IrInstGen *ir_analyze_tuple_mult(IrAnalyze *ira, Scope *scope, AstNode *s return ir_get_deref(ira, scope, source_node, new_struct_ptr, nullptr); } -static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruction) { - IrInstGen *op1 = instruction->op1->child; +static Stage1AirInst *ir_analyze_array_mult(IrAnalyze *ira, Stage1ZirInstBinOp *instruction) { + Stage1AirInst *op1 = instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = instruction->op2->child; + Stage1AirInst *op2 = instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; @@ -10718,7 +10718,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct op1->value->type->data.pointer.child_type->id == ZigTypeIdArray) { array_type = op1->value->type->data.pointer.child_type; - IrInstGen *array_inst = ir_get_deref(ira, op1->scope, op1->source_node, op1, nullptr); + Stage1AirInst *array_inst = ir_get_deref(ira, op1->scope, op1->source_node, op1, nullptr); if (type_is_invalid(array_inst->value->type)) return ira->codegen->invalid_inst_gen; array_val = ir_resolve_const(ira, array_inst, UndefOk); @@ -10748,7 +10748,7 @@ static IrInstGen *ir_analyze_array_mult(IrAnalyze *ira, IrInstSrcBinOp *instruct ZigType *result_array_type = get_array_type(ira->codegen, child_type, new_array_len, array_type->data.array.sentinel); - IrInstGen *array_result; + Stage1AirInst *array_result; if (array_val->special == ConstValSpecialUndef || array_val->data.x_array.special == ConstArraySpecialUndef) { array_result = ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, result_array_type); } else { @@ -10799,8 +10799,8 @@ skip_computation: } } -static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira, - IrInstSrcMergeErrSets *instruction) +static Stage1AirInst *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira, + Stage1ZirInstMergeErrSets *instruction) { ZigType *op1_type = ir_resolve_error_set_type(ira, instruction->base.source_node, instruction->op1->child); if (type_is_invalid(op1_type)) @@ -10838,7 +10838,7 @@ static IrInstGen *ir_analyze_instruction_merge_err_sets(IrAnalyze *ira, } -static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp *bin_op_instruction) { +static Stage1AirInst *ir_analyze_instruction_bin_op(IrAnalyze *ira, Stage1ZirInstBinOp *bin_op_instruction) { IrBinOp op_id = bin_op_instruction->op_id; switch (op_id) { case IrBinOpInvalid: @@ -10883,12 +10883,12 @@ static IrInstGen *ir_analyze_instruction_bin_op(IrAnalyze *ira, IrInstSrcBinOp * zig_unreachable(); } -static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclVar *decl_var_instruction) { +static Stage1AirInst *ir_analyze_instruction_decl_var(IrAnalyze *ira, Stage1ZirInstDeclVar *decl_var_instruction) { Error err; ZigVar *var = decl_var_instruction->var; ZigType *explicit_type = nullptr; - IrInstGen *var_type = nullptr; + Stage1AirInst *var_type = nullptr; if (decl_var_instruction->var_type != nullptr) { var_type = decl_var_instruction->var_type->child; ZigType *proposed_type = ir_resolve_type(ira, var_type); @@ -10905,7 +10905,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV bool var_class_requires_const = false; - IrInstGen *var_ptr = decl_var_instruction->ptr->child; + Stage1AirInst *var_ptr = decl_var_instruction->ptr->child; // if this is null, a compiler error happened and did not initialize the variable. // if there are no compile errors there may be a missing ir_expr_wrap in pass1 IR generation. if (var_ptr == nullptr || type_is_invalid(var_ptr->value->type)) { @@ -11022,7 +11022,7 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV // we need a runtime ptr but we have a comptime val. // since it's a comptime val there are no instructions for it. // we memcpy the init value here - IrInstGen *deref = ir_get_deref(ira, var_ptr->scope, var_ptr->source_node, var_ptr, nullptr); + Stage1AirInst *deref = ir_get_deref(ira, var_ptr->scope, var_ptr->source_node, var_ptr, nullptr); if (type_is_invalid(deref->value->type)) { var->var_type = ira->codegen->builtin_types.entry_invalid; return ira->codegen->invalid_inst_gen; @@ -11051,12 +11051,12 @@ static IrInstGen *ir_analyze_instruction_decl_var(IrAnalyze *ira, IrInstSrcDeclV return ir_build_var_decl_gen(ira, decl_var_instruction->base.scope, decl_var_instruction->base.source_node, var, var_ptr); } -static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport *instruction) { - IrInstGen *target = instruction->target->child; +static Stage1AirInst *ir_analyze_instruction_export(IrAnalyze *ira, Stage1ZirInstExport *instruction) { + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *options = instruction->options->child; + Stage1AirInst *options = instruction->options->child; if (type_is_invalid(options->value->type)) return ira->codegen->invalid_inst_gen; @@ -11065,29 +11065,29 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name")); src_assert(name_field != nullptr, instruction->base.source_node); - IrInstGen *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field); + Stage1AirInst *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field); if (type_is_invalid(name_inst->value->type)) return ira->codegen->invalid_inst_gen; TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage")); src_assert(linkage_field != nullptr, instruction->base.source_node); - IrInstGen *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field); + Stage1AirInst *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field); if (type_is_invalid(linkage_inst->value->type)) return ira->codegen->invalid_inst_gen; TypeStructField *section_field = find_struct_type_field(options_type, buf_create_from_str("section")); src_assert(section_field != nullptr, instruction->base.source_node); - IrInstGen *section_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, section_field); + Stage1AirInst *section_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, section_field); if (type_is_invalid(section_inst->value->type)) return ira->codegen->invalid_inst_gen; // The `section` field is optional, we have to unwrap it first - IrInstGen *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, section_inst); + Stage1AirInst *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, section_inst); bool is_non_null; if (!ir_resolve_bool(ira, non_null_check, &is_non_null)) return ira->codegen->invalid_inst_gen; - IrInstGen *section_str_inst = nullptr; + Stage1AirInst *section_str_inst = nullptr; if (is_non_null) { section_str_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, section_inst, false); if (type_is_invalid(section_str_inst->value->type)) @@ -11307,10 +11307,10 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport } // TODO audit the various ways to use @export - if (want_var_export && target->id == IrInstGenIdLoadPtr) { - IrInstGenLoadPtr *load_ptr = reinterpret_cast(target); - if (load_ptr->ptr->id == IrInstGenIdVarPtr) { - IrInstGenVarPtr *var_ptr = reinterpret_cast(load_ptr->ptr); + if (want_var_export && target->id == Stage1AirInstIdLoadPtr) { + Stage1AirInstLoadPtr *load_ptr = reinterpret_cast(target); + if (load_ptr->ptr->id == Stage1AirInstIdVarPtr) { + Stage1AirInstVarPtr *var_ptr = reinterpret_cast(load_ptr->ptr); ZigVar *var = var_ptr->var; add_var_export(ira->codegen, var, buf_ptr(symbol_name), global_linkage_id); var->section_name = section_name; @@ -11322,12 +11322,12 @@ static IrInstGen *ir_analyze_instruction_export(IrAnalyze *ira, IrInstSrcExport static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name, AstNode *source_node); -static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern *instruction) { - IrInstGen *type_inst = instruction->type->child; +static Stage1AirInst *ir_analyze_instruction_extern(IrAnalyze *ira, Stage1ZirInstExtern *instruction) { + Stage1AirInst *type_inst = instruction->type->child; if (type_is_invalid(type_inst->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *options = instruction->options->child; + Stage1AirInst *options = instruction->options->child; if (type_is_invalid(options->value->type)) return ira->codegen->invalid_inst_gen; @@ -11336,35 +11336,35 @@ static IrInstGen *ir_analyze_instruction_extern(IrAnalyze *ira, IrInstSrcExtern TypeStructField *name_field = find_struct_type_field(options_type, buf_create_from_str("name")); src_assert(name_field != nullptr, instruction->base.source_node); - IrInstGen *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field); + Stage1AirInst *name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, name_field); if (type_is_invalid(name_inst->value->type)) return ira->codegen->invalid_inst_gen; TypeStructField *linkage_field = find_struct_type_field(options_type, buf_create_from_str("linkage")); src_assert(linkage_field != nullptr, instruction->base.source_node); - IrInstGen *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field); + Stage1AirInst *linkage_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, linkage_field); if (type_is_invalid(linkage_inst->value->type)) return ira->codegen->invalid_inst_gen; TypeStructField *is_thread_local_field = find_struct_type_field(options_type, buf_create_from_str("is_thread_local")); src_assert(is_thread_local_field != nullptr, instruction->base.source_node); - IrInstGen *is_thread_local_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, is_thread_local_field); + Stage1AirInst *is_thread_local_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, is_thread_local_field); if (type_is_invalid(is_thread_local_inst->value->type)) return ira->codegen->invalid_inst_gen; TypeStructField *library_name_field = find_struct_type_field(options_type, buf_create_from_str("library_name")); src_assert(library_name_field != nullptr, instruction->base.source_node); - IrInstGen *library_name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, library_name_field); + Stage1AirInst *library_name_inst = ir_analyze_struct_value_field_value(ira, instruction->base.scope, instruction->base.source_node, options, library_name_field); if (type_is_invalid(library_name_inst->value->type)) return ira->codegen->invalid_inst_gen; // The `library_name` field is optional, we have to unwrap it first - IrInstGen *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, library_name_inst); + Stage1AirInst *non_null_check = ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, library_name_inst); bool is_non_null; if (!ir_resolve_bool(ira, non_null_check, &is_non_null)) return ira->codegen->invalid_inst_gen; - IrInstGen *library_name_val_inst = nullptr; + Stage1AirInst *library_name_val_inst = nullptr; if (is_non_null) { library_name_val_inst = ir_analyze_optional_value_payload_value(ira, instruction->base.scope, instruction->base.source_node, library_name_inst, false); if (type_is_invalid(library_name_val_inst->value->type)) @@ -11445,14 +11445,14 @@ static bool ira_has_err_ret_trace(IrAnalyze *ira) { return fn != nullptr && fn->calls_or_awaits_errorable_fn && ira->codegen->have_err_ret_tracing; } -static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira, - IrInstSrcErrorReturnTrace *instruction) +static Stage1AirInst *ir_analyze_instruction_error_return_trace(IrAnalyze *ira, + Stage1ZirInstErrorReturnTrace *instruction) { ZigType *ptr_to_stack_trace_type = get_pointer_to_type(ira->codegen, get_stack_trace_type(ira->codegen), false); if (instruction->optional == IrInstErrorReturnTraceNull) { ZigType *optional_type = get_optional_type(ira->codegen, ptr_to_stack_trace_type); if (!ira_has_err_ret_trace(ira)) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, optional_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, optional_type); ZigValue *out_val = result->value; assert(get_src_ptr_type(optional_type) != nullptr); out_val->data.x_ptr.special = ConstPtrSpecialHardCodedAddr; @@ -11468,8 +11468,8 @@ static IrInstGen *ir_analyze_instruction_error_return_trace(IrAnalyze *ira, } } -static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcErrorUnion *instruction) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); +static Stage1AirInst *ir_analyze_instruction_error_union(IrAnalyze *ira, Stage1ZirInstErrorUnion *instruction) { + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; LazyValueErrUnionType *lazy_err_union_type = heap::c_allocator.create(); @@ -11488,7 +11488,7 @@ static IrInstGen *ir_analyze_instruction_error_union(IrAnalyze *ira, IrInstSrcEr return result; } -static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *var_type, +static Stage1AirInst *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigType *var_type, uint32_t align, const char *name_hint, bool force_comptime) { Error err; @@ -11497,7 +11497,7 @@ static IrInstGen *ir_analyze_alloca(IrAnalyze *ira, Scope *scope, AstNode *sourc pointee->special = ConstValSpecialUndef; pointee->llvm_align = align; - IrInstGenAlloca *result = ir_build_alloca_gen(ira, scope, source_node, align, name_hint); + Stage1AirInstAlloca *result = ir_build_alloca_gen(ira, scope, source_node, align, name_hint); result->base.value->special = ConstValSpecialStatic; result->base.value->data.x_ptr.special = ConstPtrSpecialRef; result->base.value->data.x_ptr.mut = force_comptime ? ConstPtrMutComptimeVar : ConstPtrMutInfer; @@ -11572,7 +11572,7 @@ static bool type_can_bit_cast(ZigType *t) { } } -static void set_up_result_loc_for_inferred_comptime(IrAnalyze *ira, IrInstGen *ptr) { +static void set_up_result_loc_for_inferred_comptime(IrAnalyze *ira, Stage1AirInst *ptr) { ZigValue *undef_child = ira->codegen->pass1_arena->create(); undef_child->type = ptr->value->type->data.pointer.child_type; undef_child->special = ConstValSpecialUndef; @@ -11611,12 +11611,12 @@ static Error ir_result_has_type(IrAnalyze *ira, ResultLoc *result_loc, bool *out zig_unreachable(); } -static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_source_instr, +static Stage1AirInst *ir_resolve_no_result_loc(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr, ResultLoc *result_loc, ZigType *value_type) { if (type_is_invalid(value_type)) return ira->codegen->invalid_inst_gen; - IrInstGenAlloca *alloca_gen = ir_build_alloca_gen(ira, suspend_source_instr->scope, + Stage1AirInstAlloca *alloca_gen = ir_build_alloca_gen(ira, suspend_source_instr->scope, suspend_source_instr->source_node, 0, ""); alloca_gen->base.value->type = get_pointer_to_type_extra(ira->codegen, value_type, false, false, PtrLenSingle, 0, 0, 0, false); @@ -11632,9 +11632,9 @@ static IrInstGen *ir_resolve_no_result_loc(IrAnalyze *ira, IrInstSrc *suspend_so static bool result_loc_is_discard(ResultLoc *result_loc_pass1) { if (result_loc_pass1->id == ResultLocIdInstruction && - result_loc_pass1->source_instruction->id == IrInstSrcIdConst) + result_loc_pass1->source_instruction->id == Stage1ZirInstIdConst) { - IrInstSrcConst *const_inst = reinterpret_cast(result_loc_pass1->source_instruction); + Stage1ZirInstConst *const_inst = reinterpret_cast(result_loc_pass1->source_instruction); if (value_is_comptime(const_inst->value) && const_inst->value->type->id == ZigTypeIdPointer && const_inst->value->data.x_ptr.special == ConstPtrSpecialDiscard) @@ -11646,8 +11646,8 @@ static bool result_loc_is_discard(ResultLoc *result_loc_pass1) { } // when calling this function, at the callsite must check for result type noreturn and propagate it up -static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_source_instr, - ResultLoc *result_loc, ZigType *value_type, IrInstGen *value, bool force_runtime, +static Stage1AirInst *ir_resolve_result_raw(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr, + ResultLoc *result_loc, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard) { Error err; @@ -11672,8 +11672,8 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc } case ResultLocIdVar: { ResultLocVar *result_loc_var = reinterpret_cast(result_loc); - assert(result_loc->source_instruction->id == IrInstSrcIdAlloca); - IrInstSrcAlloca *alloca_src = reinterpret_cast(result_loc->source_instruction); + assert(result_loc->source_instruction->id == Stage1ZirInstIdAlloca); + Stage1ZirInstAlloca *alloca_src = reinterpret_cast(result_loc->source_instruction); ZigVar *var = result_loc_var->var; if (var->var_type != nullptr && !ir_get_var_is_comptime(var)) { @@ -11702,7 +11702,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc if (alloca_src->align != nullptr && !ir_resolve_align(ira, alloca_src->align->child, nullptr, &align)) { return ira->codegen->invalid_inst_gen; } - IrInstGen *alloca_gen = ir_analyze_alloca(ira, + Stage1AirInst *alloca_gen = ir_analyze_alloca(ira, result_loc->source_instruction->scope, result_loc->source_instruction->source_node, value_type, align, alloca_src->name_hint, force_comptime); @@ -11739,7 +11739,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc ResultLocPeerParent *peer_parent = result_peer->parent; if (peer_parent->peers.length == 1) { - IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent, + Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent, value_type, value, force_runtime, true); result_peer->suspend_pos.basic_block_index = SIZE_MAX; result_peer->suspend_pos.instruction_index = SIZE_MAX; @@ -11766,7 +11766,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc return ira->codegen->invalid_inst_gen; if (peer_parent_has_type) { peer_parent->skipped = true; - IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent, + Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent, value_type, value, force_runtime || !is_condition_comptime, true); if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable) @@ -11783,7 +11783,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc if (peer_parent->end_bb->suspend_instruction_ref == nullptr) { peer_parent->end_bb->suspend_instruction_ref = suspend_source_instr; } - IrInstGen *unreach_inst = ira_suspend(ira, suspend_source_instr, result_peer->next_bb, + Stage1AirInst *unreach_inst = ira_suspend(ira, suspend_source_instr, result_peer->next_bb, &result_peer->suspend_pos); if (result_peer->next_bb == nullptr) { ir_start_next_bb(ira); @@ -11791,7 +11791,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc return unreach_inst; } - IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent, + Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, peer_parent->parent, peer_parent->resolved_type, nullptr, force_runtime, true); if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable) @@ -11814,7 +11814,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc return ir_resolve_no_result_loc(ira, suspend_source_instr, result_loc, value_type); } - IrInstGen *casted_value; + Stage1AirInst *casted_value; if (value != nullptr) { casted_value = ir_implicit_cast2(ira, suspend_source_instr->scope, suspend_source_instr->source_node, value, dest_type); @@ -11825,7 +11825,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc casted_value = nullptr; } - IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_cast->parent, + Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_cast->parent, dest_type, casted_value, force_runtime, true); if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable) @@ -11922,7 +11922,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc return ira->codegen->invalid_inst_gen; } - IrInstGen *bitcasted_value; + Stage1AirInst *bitcasted_value; if (value != nullptr) { bitcasted_value = ir_analyze_bit_cast(ira, result_loc->source_instruction->scope, result_loc->source_instruction->source_node, value, dest_type); @@ -11936,7 +11936,7 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc } bool parent_was_written = result_bit_cast->parent->written; - IrInstGen *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_bit_cast->parent, + Stage1AirInst *parent_result_loc = ir_resolve_result(ira, suspend_source_instr, result_bit_cast->parent, dest_type, bitcasted_value, force_runtime, true); if (parent_result_loc == nullptr || type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable) @@ -11987,15 +11987,15 @@ static IrInstGen *ir_resolve_result_raw(IrAnalyze *ira, IrInstSrc *suspend_sourc zig_unreachable(); } -static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_instr, - ResultLoc *result_loc_pass1, ZigType *value_type, IrInstGen *value, bool force_runtime, +static Stage1AirInst *ir_resolve_result(IrAnalyze *ira, Stage1ZirInst *suspend_source_instr, + ResultLoc *result_loc_pass1, ZigType *value_type, Stage1AirInst *value, bool force_runtime, bool allow_discard) { if (!allow_discard && result_loc_is_discard(result_loc_pass1)) { result_loc_pass1 = no_result_loc(); } bool was_written = result_loc_pass1->written; - IrInstGen *result_loc = ir_resolve_result_raw(ira, suspend_source_instr, result_loc_pass1, value_type, + Stage1AirInst *result_loc = ir_resolve_result_raw(ira, suspend_source_instr, result_loc_pass1, value_type, value, force_runtime, allow_discard); if (result_loc == nullptr || result_loc->value->type->id == ZigTypeIdUnreachable || type_is_invalid(result_loc->value->type)) @@ -12012,7 +12012,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in InferredStructField *isf = result_loc->value->type->data.pointer.inferred_struct_field; if (isf != nullptr) { TypeStructField *field; - IrInstGen *casted_ptr; + Stage1AirInst *casted_ptr; if (isf->already_resolved) { field = find_struct_type_field(isf->inferred_struct_type, isf->field_name); casted_ptr = result_loc; @@ -12102,7 +12102,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in return ir_analyze_unwrap_err_code(ira, suspend_source_instr->scope, suspend_source_instr->source_node, result_loc, true); } else { - IrInstGen *unwrapped_err_ptr = ir_analyze_unwrap_error_payload(ira, + Stage1AirInst *unwrapped_err_ptr = ir_analyze_unwrap_error_payload(ira, suspend_source_instr->scope, suspend_source_instr->source_node, result_loc, false, true); ZigType *actual_payload_type = actual_elem_type->data.error_union.payload_type; @@ -12119,7 +12119,7 @@ static IrInstGen *ir_resolve_result(IrAnalyze *ira, IrInstSrc *suspend_source_in return result_loc; } -static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSrcResolveResult *instruction) { +static Stage1AirInst *ir_analyze_instruction_resolve_result(IrAnalyze *ira, Stage1ZirInstResolveResult *instruction) { ZigType *implicit_elem_type; if (instruction->ty == nullptr) { if (instruction->result_loc->id == ResultLocIdCast) { @@ -12158,7 +12158,7 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr if (type_is_invalid(implicit_elem_type)) return ira->codegen->invalid_inst_gen; } - IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, + Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, implicit_elem_type, nullptr, false, true); if (result_loc != nullptr) return result_loc; @@ -12178,9 +12178,9 @@ static IrInstGen *ir_analyze_instruction_resolve_result(IrAnalyze *ira, IrInstSr return result_loc; } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, implicit_elem_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, implicit_elem_type); result->value->special = ConstValSpecialUndef; - IrInstGen *ptr = ir_get_ref(ira, instruction->base.scope, instruction->base.source_node, result, false, false); + Stage1AirInst *ptr = ir_get_ref(ira, instruction->base.scope, instruction->base.source_node, result, false, false); ptr->value->data.x_ptr.mut = ConstPtrMutComptimeVar; return ptr; } @@ -12204,7 +12204,7 @@ static void ir_reset_result(ResultLoc *result_loc) { break; } case ResultLocIdVar: { - IrInstSrcAlloca *alloca_src = reinterpret_cast(result_loc->source_instruction); + Stage1ZirInstAlloca *alloca_src = reinterpret_cast(result_loc->source_instruction); alloca_src->base.child = nullptr; break; } @@ -12220,14 +12220,14 @@ static void ir_reset_result(ResultLoc *result_loc) { } } -static IrInstGen *ir_analyze_instruction_reset_result(IrAnalyze *ira, IrInstSrcResetResult *instruction) { +static Stage1AirInst *ir_analyze_instruction_reset_result(IrAnalyze *ira, Stage1ZirInstResetResult *instruction) { ir_reset_result(instruction->result_loc); return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *fn_ret_type, bool is_async_call_builtin, IrInstGen **args_ptr, size_t args_len, - IrInstGen *ret_ptr_uncasted) +static Stage1AirInst *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *fn_ret_type, bool is_async_call_builtin, Stage1AirInst **args_ptr, size_t args_len, + Stage1AirInst *ret_ptr_uncasted) { src_assert(is_async_call_builtin, source_node); if (type_is_invalid(ret_ptr_uncasted->value->type)) @@ -12239,9 +12239,9 @@ static IrInstGen *get_async_call_result_loc(IrAnalyze *ira, Scope *scope, AstNod return ir_implicit_cast(ira, ret_ptr_uncasted, get_pointer_to_type(ira->codegen, fn_ret_type, false)); } -static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry, - ZigType *fn_type, IrInstGen *fn_ref, IrInstGen **casted_args, size_t arg_count, - IrInstGen *casted_new_stack, bool is_async_call_builtin, IrInstGen *ret_ptr_uncasted, +static Stage1AirInst *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigFn *fn_entry, + ZigType *fn_type, Stage1AirInst *fn_ref, Stage1AirInst **casted_args, size_t arg_count, + Stage1AirInst *casted_new_stack, bool is_async_call_builtin, Stage1AirInst *ret_ptr_uncasted, ResultLoc *call_result_loc) { if (fn_entry == nullptr) { @@ -12257,20 +12257,20 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s } if (casted_new_stack != nullptr) { ZigType *fn_ret_type = fn_type->data.fn.fn_type_id.return_type; - IrInstGen *ret_ptr = get_async_call_result_loc(ira, scope, source_node, fn_ret_type, is_async_call_builtin, + Stage1AirInst *ret_ptr = get_async_call_result_loc(ira, scope, source_node, fn_ret_type, is_async_call_builtin, casted_args, arg_count, ret_ptr_uncasted); if (ret_ptr != nullptr && type_is_invalid(ret_ptr->value->type)) return ira->codegen->invalid_inst_gen; ZigType *anyframe_type = get_any_frame_type(ira->codegen, fn_ret_type); - IrInstGenCall *call_gen = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref, + Stage1AirInstCall *call_gen = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref, arg_count, casted_args, CallModifierAsync, casted_new_stack, is_async_call_builtin, ret_ptr, anyframe_type); return &call_gen->base; } else { ZigType *frame_type = get_fn_frame_type(ira->codegen, fn_entry); - IrInstGen *result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc, + Stage1AirInst *result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc, frame_type, nullptr, true, false); if (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable) { return result_loc; @@ -12285,12 +12285,12 @@ static IrInstGen *ir_analyze_async_call(IrAnalyze *ira, Scope *scope, AstNode *s } } static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node, - IrInstGen *arg, Scope **exec_scope, size_t *next_proto_i) + Stage1AirInst *arg, Scope **exec_scope, size_t *next_proto_i) { AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i); assert(param_decl_node->type == NodeTypeParamDecl); - IrInstGen *casted_arg; + Stage1AirInst *casted_arg; if (param_decl_node->data.param_decl.anytype_token == 0) { AstNode *param_type_node = param_decl_node->data.param_decl.type; ZigType *param_type = ir_analyze_type_expr(ira, *exec_scope, param_type_node); @@ -12318,15 +12318,15 @@ static bool ir_analyze_fn_call_inline_arg(IrAnalyze *ira, AstNode *fn_proto_node } static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_node, - IrInstGen *arg, AstNode *arg_src, Scope **child_scope, size_t *next_proto_i, - GenericFnTypeId *generic_id, FnTypeId *fn_type_id, IrInstGen **casted_args, + Stage1AirInst *arg, AstNode *arg_src, Scope **child_scope, size_t *next_proto_i, + GenericFnTypeId *generic_id, FnTypeId *fn_type_id, Stage1AirInst **casted_args, ZigFn *impl_fn) { AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(*next_proto_i); assert(param_decl_node->type == NodeTypeParamDecl); bool is_var_args = param_decl_node->data.param_decl.is_var_args; bool arg_part_of_generic_id = false; - IrInstGen *casted_arg; + Stage1AirInst *casted_arg; ZigType *param_info_type = nullptr; if (is_var_args) { @@ -12414,7 +12414,7 @@ static bool ir_analyze_fn_call_generic_arg(IrAnalyze *ira, AstNode *fn_proto_nod return true; } -static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) { +static Stage1AirInst *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, ZigVar *var) { while (var->next_var != nullptr) { var = var->next_var; } @@ -12433,7 +12433,7 @@ static IrInstGen *ir_get_var_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_n bool comptime_var_mem = ir_get_var_is_comptime(var); bool linkage_makes_it_runtime = var->decl_node->data.variable_declaration.is_extern; - IrInstGen *result = ir_build_var_ptr_gen(ira, scope, source_node, var); + Stage1AirInst *result = ir_build_var_ptr_gen(ira, scope, source_node, var); result->value->type = var_ptr_type; if (!linkage_makes_it_runtime && !var->is_thread_local && value_is_comptime(var->const_value)) { @@ -12482,8 +12482,8 @@ static void mark_comptime_value_escape(IrAnalyze *ira, Scope *scope, AstNode *so } } -static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, IrInstGen *uncasted_value, bool allow_write_through_const) +static Stage1AirInst *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, Stage1AirInst *uncasted_value, bool allow_write_through_const) { assert(ptr->value->type->id == ZigTypeIdPointer); @@ -12503,7 +12503,7 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so } ZigType *child_type = ptr->value->type->data.pointer.child_type; - IrInstGen *value = ir_implicit_cast(ira, uncasted_value, child_type); + Stage1AirInst *value = ir_implicit_cast(ira, uncasted_value, child_type); if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; @@ -12583,14 +12583,14 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so } // If this is a store to a pointer with a runtime-known vector index, - // we have to figure out the IrInstGen which represents the index and - // emit a IrInstGenVectorStoreElem, or emit a compile error + // we have to figure out the Stage1AirInst which represents the index and + // emit a Stage1AirInstVectorStoreElem, or emit a compile error // explaining why it is impossible for this store to work. Which is that // the pointer address is of the vector; without the element index being known // we cannot properly perform the insertion. if (ptr->value->type->data.pointer.vector_index == VECTOR_INDEX_RUNTIME) { - if (ptr->id == IrInstGenIdElemPtr) { - IrInstGenElemPtr *elem_ptr = (IrInstGenElemPtr *)ptr; + if (ptr->id == Stage1AirInstIdElemPtr) { + Stage1AirInstElemPtr *elem_ptr = (Stage1AirInstElemPtr *)ptr; return ir_build_vector_store_elem(ira, scope, source_node, elem_ptr->array_ptr, elem_ptr->elem_index, value); } @@ -12603,8 +12603,8 @@ static IrInstGen *ir_analyze_store_ptr(IrAnalyze *ira, Scope *scope, AstNode *so return ir_build_store_ptr_gen(ira, scope, source_node, ptr, value); } -static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, ZigFn *fn_entry) +static Stage1AirInst *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, ZigFn *fn_entry) { if (new_stack == nullptr) return nullptr; @@ -12637,11 +12637,11 @@ static IrInstGen *analyze_casted_new_stack(IrAnalyze *ira, Scope *scope, AstNode } } -static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigFn *fn_entry, ZigType *fn_type, IrInstGen *fn_ref, - IrInstGen *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier, - IrInstGen *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, - IrInstGen **args_ptr, size_t args_len, IrInstGen *ret_ptr, ResultLoc *call_result_loc) +static Stage1AirInst *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigFn *fn_entry, ZigType *fn_type, Stage1AirInst *fn_ref, + Stage1AirInst *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier, + Stage1AirInst *new_stack, AstNode *new_stack_src, bool is_async_call_builtin, + Stage1AirInst **args_ptr, size_t args_len, Stage1AirInst *ret_ptr, ResultLoc *call_result_loc) { Error err; FnTypeId *fn_type_id = &fn_type->data.fn.fn_type_id; @@ -12729,7 +12729,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour first_arg_known_bare = param_type->id != ZigTypeIdPointer; } - IrInstGen *first_arg; + Stage1AirInst *first_arg; if (!first_arg_known_bare) { first_arg = first_arg_ptr; } else { @@ -12743,7 +12743,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour } for (size_t call_i = 0; call_i < args_len; call_i += 1) { - IrInstGen *old_arg = args_ptr[call_i]; + Stage1AirInst *old_arg = args_ptr[call_i]; if (!ir_analyze_fn_call_inline_arg(ira, fn_proto_node, old_arg, &exec_scope, &next_proto_i)) return ira->codegen->invalid_inst_gen; @@ -12841,7 +12841,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour } } - IrInstGen *new_instruction = ir_const_move(ira, scope, source_node, result); + Stage1AirInst *new_instruction = ir_const_move(ira, scope, source_node, result); return ir_finish_anal(ira, new_instruction); } @@ -12854,7 +12854,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour size_t new_fn_arg_count = first_arg_1_or_0 + args_len; - IrInstGen **casted_args = heap::c_allocator.allocate(new_fn_arg_count); + Stage1AirInst **casted_args = heap::c_allocator.allocate(new_fn_arg_count); // Fork a scope of the function with known values for the parameters. Scope *parent_scope = fn_entry->fndef_scope->base.parent; @@ -12887,7 +12887,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour first_arg_known_bare = param_type->id != ZigTypeIdPointer; } - IrInstGen *first_arg; + Stage1AirInst *first_arg; if (!first_arg_known_bare) { first_arg = first_arg_ptr; } else { @@ -12907,7 +12907,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour ZigFn *parent_fn_entry = ira->fn; assert(parent_fn_entry); for (size_t call_i = 0; call_i < args_len; call_i += 1) { - IrInstGen *arg = args_ptr[call_i]; + Stage1AirInst *arg = args_ptr[call_i]; AstNode *param_decl_node = fn_proto_node->data.fn_proto.params.at(next_proto_i); assert(param_decl_node->type == NodeTypeParamDecl); @@ -12932,7 +12932,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour { return ira->codegen->invalid_inst_gen; } - IrInstGenConst *const_instruction = ir_create_inst_noval(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_noval(&ira->new_irb, impl_fn->child_scope, fn_proto_node->data.fn_proto.align_expr); const_instruction->base.value = align_result; @@ -13015,20 +13015,20 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour parent_fn_entry->calls_or_awaits_errorable_fn = true; } - IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, + Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src, is_async_call_builtin, impl_fn); if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type)) return ira->codegen->invalid_inst_gen; size_t impl_param_count = impl_fn_type_id->param_count; if (modifier == CallModifierAsync) { - IrInstGen *result = ir_analyze_async_call(ira, scope, source_node, impl_fn, impl_fn->type_entry, + Stage1AirInst *result = ir_analyze_async_call(ira, scope, source_node, impl_fn, impl_fn->type_entry, nullptr, casted_args, impl_param_count, casted_new_stack, is_async_call_builtin, ret_ptr, call_result_loc); return ir_finish_anal(ira, result); } - IrInstGen *result_loc; + Stage1AirInst *result_loc; if (handle_is_ptr(ira->codegen, impl_fn_type_id->return_type)) { result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc, impl_fn_type_id->return_type, nullptr, true, false); @@ -13041,9 +13041,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour return ira->codegen->invalid_inst_gen; } - IrInstGen *dummy_value = ir_const(ira, scope, source_node, impl_fn_type_id->return_type); + Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, impl_fn_type_id->return_type); dummy_value->value->special = ConstValSpecialRuntime; - IrInstGen *dummy_result = ir_implicit_cast2(ira, scope, source_node, + Stage1AirInst *dummy_result = ir_implicit_cast2(ira, scope, source_node, dummy_value, result_loc->value->type->data.pointer.child_type); if (type_is_invalid(dummy_result->value->type)) return ira->codegen->invalid_inst_gen; @@ -13073,7 +13073,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour parent_fn_entry->inferred_async_fn = impl_fn; } - IrInstGenCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, + Stage1AirInstCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, impl_fn, nullptr, impl_param_count, casted_args, modifier, casted_new_stack, is_async_call_builtin, result_loc, impl_fn_type_id->return_type); @@ -13092,7 +13092,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour } - IrInstGen **casted_args = heap::c_allocator.allocate(call_param_count); + Stage1AirInst **casted_args = heap::c_allocator.allocate(call_param_count); size_t next_arg_index = 0; if (first_arg_ptr) { assert(first_arg_ptr->value->type->id == ZigTypeIdPointer); @@ -13101,7 +13101,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour if (type_is_invalid(param_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *first_arg; + Stage1AirInst *first_arg; if (param_type->id == ZigTypeIdPointer) { first_arg = first_arg_ptr; } else { @@ -13111,7 +13111,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour return ira->codegen->invalid_inst_gen; } - IrInstGen *casted_arg = ir_implicit_cast2(ira, first_arg->scope, first_arg_ptr_src, first_arg, param_type); + Stage1AirInst *casted_arg = ir_implicit_cast2(ira, first_arg->scope, first_arg_ptr_src, first_arg, param_type); if (type_is_invalid(casted_arg->value->type)) return ira->codegen->invalid_inst_gen; @@ -13119,11 +13119,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour next_arg_index += 1; } for (size_t call_i = 0; call_i < args_len; call_i += 1) { - IrInstGen *old_arg = args_ptr[call_i]; + Stage1AirInst *old_arg = args_ptr[call_i]; if (type_is_invalid(old_arg->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_arg; + Stage1AirInst *casted_arg; if (next_arg_index < src_param_count) { ZigType *param_type = fn_type_id->param_info[next_arg_index].type; if (type_is_invalid(param_type)) @@ -13151,13 +13151,13 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour return ira->codegen->invalid_inst_gen; } - IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src, + Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack, new_stack_src, is_async_call_builtin, fn_entry); if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type)) return ira->codegen->invalid_inst_gen; if (modifier == CallModifierAsync) { - IrInstGen *result = ir_analyze_async_call(ira, scope, source_node, fn_entry, fn_type, fn_ref, + Stage1AirInst *result = ir_analyze_async_call(ira, scope, source_node, fn_entry, fn_type, fn_ref, casted_args, call_param_count, casted_new_stack, is_async_call_builtin, ret_ptr, call_result_loc); return ir_finish_anal(ira, result); } @@ -13170,7 +13170,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour parent_fn_entry->inferred_async_fn = fn_entry; } - IrInstGen *result_loc; + Stage1AirInst *result_loc; if (handle_is_ptr(ira->codegen, return_type)) { result_loc = ir_resolve_result(ira, ira->suspend_source_instr, call_result_loc, return_type, nullptr, true, false); @@ -13185,9 +13185,9 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour ZigType *expected_return_type = result_loc->value->type->data.pointer.child_type; - IrInstGen *dummy_value = ir_const(ira, scope, source_node, return_type); + Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, return_type); dummy_value->value->special = ConstValSpecialRuntime; - IrInstGen *dummy_result = ir_implicit_cast2(ira, scope, source_node, + Stage1AirInst *dummy_result = ir_implicit_cast2(ira, scope, source_node, dummy_value, expected_return_type); if (type_is_invalid(dummy_result->value->type)) { if ((return_type->id == ZigTypeIdErrorUnion || return_type->id == ZigTypeIdErrorSet) && @@ -13220,7 +13220,7 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour result_loc = nullptr; } - IrInstGenCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref, + Stage1AirInstCall *new_call_instruction = ir_build_call_gen(ira, scope, source_node, fn_entry, fn_ref, call_param_count, casted_args, modifier, casted_new_stack, is_async_call_builtin, result_loc, return_type); if (get_scope_typeof(scope) == nullptr) { @@ -13229,11 +13229,11 @@ static IrInstGen *ir_analyze_fn_call(IrAnalyze *ira, Scope *scope, AstNode *sour return ir_finish_anal(ira, &new_call_instruction->base); } -static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_instruction, - ZigFn *fn_entry, ZigType *fn_type, IrInstGen *fn_ref, - IrInstGen *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier) +static Stage1AirInst *ir_analyze_fn_call_src(IrAnalyze *ira, Stage1ZirInstCall *call_instruction, + ZigFn *fn_entry, ZigType *fn_type, Stage1AirInst *fn_ref, + Stage1AirInst *first_arg_ptr, AstNode *first_arg_ptr_src, CallModifier modifier) { - IrInstGen *new_stack = nullptr; + Stage1AirInst *new_stack = nullptr; AstNode *new_stack_src = nullptr; if (call_instruction->new_stack) { new_stack = call_instruction->new_stack->child; @@ -13241,19 +13241,19 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins return ira->codegen->invalid_inst_gen; new_stack_src = call_instruction->new_stack->source_node; } - IrInstGen **args_ptr = heap::c_allocator.allocate(call_instruction->arg_count); + Stage1AirInst **args_ptr = heap::c_allocator.allocate(call_instruction->arg_count); for (size_t i = 0; i < call_instruction->arg_count; i += 1) { args_ptr[i] = call_instruction->args[i]->child; if (type_is_invalid(args_ptr[i]->value->type)) return ira->codegen->invalid_inst_gen; } - IrInstGen *ret_ptr = nullptr; + Stage1AirInst *ret_ptr = nullptr; if (call_instruction->ret_ptr != nullptr) { ret_ptr = call_instruction->ret_ptr->child; if (type_is_invalid(ret_ptr->value->type)) return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_analyze_fn_call(ira, call_instruction->base.scope, + Stage1AirInst *result = ir_analyze_fn_call(ira, call_instruction->base.scope, call_instruction->base.source_node, fn_entry, fn_type, fn_ref, first_arg_ptr, first_arg_ptr_src, modifier, new_stack, new_stack_src, call_instruction->is_async_call_builtin, args_ptr, call_instruction->arg_count, ret_ptr, @@ -13262,21 +13262,21 @@ static IrInstGen *ir_analyze_fn_call_src(IrAnalyze *ira, IrInstSrcCall *call_ins return result; } -static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstSrc *pass1_options, IrInstSrc *pass1_fn_ref, IrInstGen **args_ptr, size_t args_len, +static Stage1AirInst *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1ZirInst *pass1_options, Stage1ZirInst *pass1_fn_ref, Stage1AirInst **args_ptr, size_t args_len, ResultLoc *result_loc) { - IrInstGen *options = pass1_options->child; + Stage1AirInst *options = pass1_options->child; if (type_is_invalid(options->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *fn_ref = pass1_fn_ref->child; + Stage1AirInst *fn_ref = pass1_fn_ref->child; if (type_is_invalid(fn_ref->value->type)) return ira->codegen->invalid_inst_gen; TypeStructField *modifier_field = find_struct_type_field(options->value->type, buf_create_from_str("modifier")); src_assert(modifier_field != nullptr, source_node); - IrInstGen *modifier_inst = ir_analyze_struct_value_field_value(ira, scope, source_node, options, modifier_field); + Stage1AirInst *modifier_inst = ir_analyze_struct_value_field_value(ira, scope, source_node, options, modifier_field); ZigValue *modifier_val = ir_resolve_const(ira, modifier_inst, UndefBad); if (modifier_val == nullptr) return ira->codegen->invalid_inst_gen; @@ -13307,7 +13307,7 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s } } - IrInstGen *first_arg_ptr = nullptr; + Stage1AirInst *first_arg_ptr = nullptr; AstNode *first_arg_ptr_src = nullptr; ZigFn *fn = nullptr; if (instr_is_comptime(fn_ref)) { @@ -13342,16 +13342,16 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s TypeStructField *stack_field = find_struct_type_field(options->value->type, buf_create_from_str("stack")); src_assert(stack_field != nullptr, source_node); - IrInstGen *opt_stack = ir_analyze_struct_value_field_value(ira, scope, source_node, options, stack_field); + Stage1AirInst *opt_stack = ir_analyze_struct_value_field_value(ira, scope, source_node, options, stack_field); if (type_is_invalid(opt_stack->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *stack_is_non_null_inst = ir_analyze_test_non_null(ira, scope, source_node, opt_stack); + Stage1AirInst *stack_is_non_null_inst = ir_analyze_test_non_null(ira, scope, source_node, opt_stack); bool stack_is_non_null; if (!ir_resolve_bool(ira, stack_is_non_null_inst, &stack_is_non_null)) return ira->codegen->invalid_inst_gen; - IrInstGen *stack = nullptr; + Stage1AirInst *stack = nullptr; AstNode *stack_src = nullptr; if (stack_is_non_null) { stack = ir_analyze_optional_value_payload_value(ira, scope, source_node, opt_stack, false); @@ -13364,10 +13364,10 @@ static IrInstGen *ir_analyze_call_extra(IrAnalyze *ira, Scope *scope, AstNode *s modifier, stack, stack_src, false, args_ptr, args_len, nullptr, result_loc); } -static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, CallModifier modifier, - IrInstSrc *pass1_fn_ref, IrInstSrc *ret_ptr, IrInstSrc *new_stack, IrInstGen **args_ptr, size_t args_len, ResultLoc *result_loc) +static Stage1AirInst *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstNode *source_node, CallModifier modifier, + Stage1ZirInst *pass1_fn_ref, Stage1ZirInst *ret_ptr, Stage1ZirInst *new_stack, Stage1AirInst **args_ptr, size_t args_len, ResultLoc *result_loc) { - IrInstGen *fn_ref = pass1_fn_ref->child; + Stage1AirInst *fn_ref = pass1_fn_ref->child; if (type_is_invalid(fn_ref->value->type)) return ira->codegen->invalid_inst_gen; @@ -13376,7 +13376,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN return ira->codegen->invalid_inst_gen; } - IrInstGen *first_arg_ptr = nullptr; + Stage1AirInst *first_arg_ptr = nullptr; AstNode *first_arg_ptr_src = nullptr; ZigFn *fn = nullptr; if (instr_is_comptime(fn_ref)) { @@ -13392,7 +13392,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN } } - IrInstGen *ret_ptr_uncasted = nullptr; + Stage1AirInst *ret_ptr_uncasted = nullptr; if (ret_ptr != nullptr) { ret_ptr_uncasted = ret_ptr->child; if (type_is_invalid(ret_ptr_uncasted->value->type)) @@ -13400,7 +13400,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN } ZigType *fn_type = (fn != nullptr) ? fn->type_entry : fn_ref->value->type; - IrInstGen *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, + Stage1AirInst *casted_new_stack = analyze_casted_new_stack(ira, scope, source_node, new_stack->child, new_stack->source_node, true, fn); if (casted_new_stack != nullptr && type_is_invalid(casted_new_stack->value->type)) return ira->codegen->invalid_inst_gen; @@ -13410,7 +13410,7 @@ static IrInstGen *ir_analyze_async_call_extra(IrAnalyze *ira, Scope *scope, AstN args_len, ret_ptr_uncasted, result_loc); } -static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *args, IrInstGen ***args_ptr, size_t *args_len) { +static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *args, Stage1AirInst ***args_ptr, size_t *args_len) { ZigType *args_type = args->value->type; if (type_is_invalid(args_type)) return false; @@ -13423,7 +13423,7 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so if (is_tuple(args_type)) { *args_len = args_type->data.structure.src_field_count; - *args_ptr = heap::c_allocator.allocate(*args_len); + *args_ptr = heap::c_allocator.allocate(*args_len); for (size_t i = 0; i < *args_len; i += 1) { TypeStructField *arg_field = args_type->data.structure.fields[i]; (*args_ptr)[i] = ir_analyze_struct_value_field_value(ira, scope, source_node, args, arg_field); @@ -13437,50 +13437,50 @@ static bool ir_extract_tuple_call_args(IrAnalyze *ira, Scope *scope, AstNode *so return true; } -static IrInstGen *ir_analyze_instruction_call_extra(IrAnalyze *ira, IrInstSrcCallExtra *instruction) { - IrInstGen *args = instruction->args->child; - IrInstGen **args_ptr = nullptr; +static Stage1AirInst *ir_analyze_instruction_call_extra(IrAnalyze *ira, Stage1ZirInstCallExtra *instruction) { + Stage1AirInst *args = instruction->args->child; + Stage1AirInst **args_ptr = nullptr; size_t args_len = 0; if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) { return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options, + Stage1AirInst *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options, instruction->fn_ref, args_ptr, args_len, instruction->result_loc); heap::c_allocator.deallocate(args_ptr, args_len); return result; } -static IrInstGen *ir_analyze_instruction_async_call_extra(IrAnalyze *ira, IrInstSrcAsyncCallExtra *instruction) { - IrInstGen *args = instruction->args->child; - IrInstGen **args_ptr = nullptr; +static Stage1AirInst *ir_analyze_instruction_async_call_extra(IrAnalyze *ira, Stage1ZirInstAsyncCallExtra *instruction) { + Stage1AirInst *args = instruction->args->child; + Stage1AirInst **args_ptr = nullptr; size_t args_len = 0; if (!ir_extract_tuple_call_args(ira, instruction->base.scope, instruction->base.source_node, args, &args_ptr, &args_len)) { return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_analyze_async_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->modifier, + Stage1AirInst *result = ir_analyze_async_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->modifier, instruction->fn_ref, instruction->ret_ptr, instruction->new_stack, args_ptr, args_len, instruction->result_loc); heap::c_allocator.deallocate(args_ptr, args_len); return result; } -static IrInstGen *ir_analyze_instruction_call_args(IrAnalyze *ira, IrInstSrcCallArgs *instruction) { - IrInstGen **args_ptr = heap::c_allocator.allocate(instruction->args_len); +static Stage1AirInst *ir_analyze_instruction_call_args(IrAnalyze *ira, Stage1ZirInstCallArgs *instruction) { + Stage1AirInst **args_ptr = heap::c_allocator.allocate(instruction->args_len); for (size_t i = 0; i < instruction->args_len; i += 1) { args_ptr[i] = instruction->args_ptr[i]->child; if (type_is_invalid(args_ptr[i]->value->type)) return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options, + Stage1AirInst *result = ir_analyze_call_extra(ira, instruction->base.scope, instruction->base.source_node, instruction->options, instruction->fn_ref, args_ptr, instruction->args_len, instruction->result_loc); heap::c_allocator.deallocate(args_ptr, instruction->args_len); return result; } -static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *call_instruction) { - IrInstGen *fn_ref = call_instruction->fn_ref->child; +static Stage1AirInst *ir_analyze_instruction_call(IrAnalyze *ira, Stage1ZirInstCall *call_instruction) { + Stage1AirInst *fn_ref = call_instruction->fn_ref->child; if (type_is_invalid(fn_ref->value->type)) return ira->codegen->invalid_inst_gen; @@ -13507,7 +13507,7 @@ static IrInstGen *ir_analyze_instruction_call(IrAnalyze *ira, IrInstSrcCall *cal } else if (fn_ref->value->type->id == ZigTypeIdBoundFn) { assert(fn_ref->value->special == ConstValSpecialStatic); ZigFn *fn_table_entry = fn_ref->value->data.x_bound_fn.fn; - IrInstGen *first_arg_ptr = fn_ref->value->data.x_bound_fn.first_arg; + Stage1AirInst *first_arg_ptr = fn_ref->value->data.x_bound_fn.first_arg; AstNode *first_arg_ptr_src = fn_ref->value->data.x_bound_fn.first_arg_src; CallModifier modifier = is_comptime ? CallModifierCompileTime : call_instruction->modifier; return ir_analyze_fn_call_src(ira, call_instruction, fn_table_entry, fn_table_entry->type_entry, @@ -13641,8 +13641,8 @@ static Error ir_read_const_ptr(IrAnalyze *ira, CodeGen *codegen, AstNode *source zig_unreachable(); } -static IrInstGen *ir_analyze_optional_type(IrAnalyze *ira, IrInstSrcUnOp *instruction) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); +static Stage1AirInst *ir_analyze_optional_type(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) { + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; LazyValueOptType *lazy_opt_type = heap::c_allocator.create(); @@ -13692,8 +13692,8 @@ static ErrorMsg *ir_eval_negation_scalar(IrAnalyze *ira, Scope *scope, AstNode * return nullptr; } -static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_negation(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) { + Stage1AirInst *value = instruction->value->child; ZigType *expr_type = value->value->type; if (type_is_invalid(expr_type)) return ira->codegen->invalid_inst_gen; @@ -13723,7 +13723,7 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction if (!operand_val) return ira->codegen->invalid_inst_gen; - IrInstGen *result_instruction = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type); + Stage1AirInst *result_instruction = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type); ZigValue *out_val = result_instruction->value; if (expr_type->id == ZigTypeIdVector) { expand_undef_array(ira->codegen, operand_val); @@ -13758,8 +13758,8 @@ static IrInstGen *ir_analyze_negation(IrAnalyze *ira, IrInstSrcUnOp *instruction return ir_build_negation(ira, instruction->base.scope, instruction->base.source_node, value, expr_type, is_wrap_op); } -static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_bin_not(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) { + Stage1AirInst *value = instruction->value->child; ZigType *expr_type = value->value->type; if (type_is_invalid(expr_type)) return ira->codegen->invalid_inst_gen; @@ -13778,7 +13778,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction) if (expr_val == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type); if (expr_type->id == ZigTypeIdVector) { expand_undef_array(ira->codegen, expr_val); @@ -13805,7 +13805,7 @@ static IrInstGen *ir_analyze_bin_not(IrAnalyze *ira, IrInstSrcUnOp *instruction) return ir_build_binary_not(ira, instruction->base.scope, instruction->base.source_node, value, expr_type); } -static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *instruction) { +static Stage1AirInst *ir_analyze_instruction_un_op(IrAnalyze *ira, Stage1ZirInstUnOp *instruction) { IrUnOp op_id = instruction->op_id; switch (op_id) { case IrUnOpInvalid: @@ -13816,7 +13816,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in case IrUnOpNegationWrap: return ir_analyze_negation(ira, instruction); case IrUnOpDereference: { - IrInstGen *ptr = instruction->value->child; + Stage1AirInst *ptr = instruction->value->child; if (type_is_invalid(ptr->value->type)) return ira->codegen->invalid_inst_gen; ZigType *ptr_type = ptr->value->type; @@ -13827,7 +13827,7 @@ static IrInstGen *ir_analyze_instruction_un_op(IrAnalyze *ira, IrInstSrcUnOp *in return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_get_deref(ira, instruction->base.scope, + Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, ptr, instruction->result_loc); if (type_is_invalid(result->value->type)) return ira->codegen->invalid_inst_gen; @@ -13860,7 +13860,7 @@ static void ir_push_resume_block(IrAnalyze *ira, Stage1ZirBasicBlock *old_bb) { } } -static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_instruction) { +static Stage1AirInst *ir_analyze_instruction_br(IrAnalyze *ira, Stage1ZirInstBr *br_instruction) { Stage1ZirBasicBlock *old_dest_block = br_instruction->dest_block; bool is_comptime; @@ -13870,18 +13870,18 @@ static IrInstGen *ir_analyze_instruction_br(IrAnalyze *ira, IrInstSrcBr *br_inst if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr)) return ir_inline_bb(ira, br_instruction->base.source_node, old_dest_block); - IrBasicBlockGen *new_bb = ir_get_new_bb_runtime(ira, old_dest_block, &br_instruction->base); + Stage1AirBasicBlock *new_bb = ir_get_new_bb_runtime(ira, old_dest_block, &br_instruction->base); if (new_bb == nullptr) return ir_unreach_error(ira); ir_push_resume_block(ira, old_dest_block); - IrInstGen *result = ir_build_br_gen(ira, br_instruction->base.scope, br_instruction->base.source_node, new_bb); + Stage1AirInst *result = ir_build_br_gen(ira, br_instruction->base.scope, br_instruction->base.source_node, new_bb); return ir_finish_anal(ira, result); } -static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr *cond_br_instruction) { - IrInstGen *condition = cond_br_instruction->condition->child; +static Stage1AirInst *ir_analyze_instruction_cond_br(IrAnalyze *ira, Stage1ZirInstCondBr *cond_br_instruction) { + Stage1AirInst *condition = cond_br_instruction->condition->child; if (type_is_invalid(condition->value->type)) return ir_unreach_error(ira); @@ -13890,7 +13890,7 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr return ir_unreach_error(ira); ZigType *bool_type = ira->codegen->builtin_types.entry_bool; - IrInstGen *casted_condition = ir_implicit_cast(ira, condition, bool_type); + Stage1AirInst *casted_condition = ir_implicit_cast(ira, condition, bool_type); if (type_is_invalid(casted_condition->value->type)) return ir_unreach_error(ira); @@ -13905,37 +13905,37 @@ static IrInstGen *ir_analyze_instruction_cond_br(IrAnalyze *ira, IrInstSrcCondBr if (is_comptime || (old_dest_block->ref_count == 1 && old_dest_block->suspend_instruction_ref == nullptr)) return ir_inline_bb(ira, cond_br_instruction->base.source_node, old_dest_block); - IrBasicBlockGen *new_dest_block = ir_get_new_bb_runtime(ira, old_dest_block, &cond_br_instruction->base); + Stage1AirBasicBlock *new_dest_block = ir_get_new_bb_runtime(ira, old_dest_block, &cond_br_instruction->base); if (new_dest_block == nullptr) return ir_unreach_error(ira); ir_push_resume_block(ira, old_dest_block); - IrInstGen *result = ir_build_br_gen(ira, cond_br_instruction->base.scope, + Stage1AirInst *result = ir_build_br_gen(ira, cond_br_instruction->base.scope, cond_br_instruction->base.source_node, new_dest_block); return ir_finish_anal(ira, result); } assert(cond_br_instruction->then_block != cond_br_instruction->else_block); - IrBasicBlockGen *new_then_block = ir_get_new_bb_runtime(ira, cond_br_instruction->then_block, &cond_br_instruction->base); + Stage1AirBasicBlock *new_then_block = ir_get_new_bb_runtime(ira, cond_br_instruction->then_block, &cond_br_instruction->base); if (new_then_block == nullptr) return ir_unreach_error(ira); - IrBasicBlockGen *new_else_block = ir_get_new_bb_runtime(ira, cond_br_instruction->else_block, &cond_br_instruction->base); + Stage1AirBasicBlock *new_else_block = ir_get_new_bb_runtime(ira, cond_br_instruction->else_block, &cond_br_instruction->base); if (new_else_block == nullptr) return ir_unreach_error(ira); ir_push_resume_block(ira, cond_br_instruction->else_block); ir_push_resume_block(ira, cond_br_instruction->then_block); - IrInstGen *result = ir_build_cond_br_gen(ira, cond_br_instruction->base.scope, + Stage1AirInst *result = ir_build_cond_br_gen(ira, cond_br_instruction->base.scope, cond_br_instruction->base.source_node, casted_condition, new_then_block, new_else_block); return ir_finish_anal(ira, result); } -static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira, - IrInstSrcUnreachable *unreachable_instruction) +static Stage1AirInst *ir_analyze_instruction_unreachable(IrAnalyze *ira, + Stage1ZirInstUnreachable *unreachable_instruction) { if (ir_should_inline(ira->zir, unreachable_instruction->base.scope)) { ir_add_error_node(ira, unreachable_instruction->base.source_node, @@ -13943,12 +13943,12 @@ static IrInstGen *ir_analyze_instruction_unreachable(IrAnalyze *ira, return ir_unreach_error(ira); } - IrInstGen *result = ir_build_unreachable_gen(ira, unreachable_instruction->base.scope, + Stage1AirInst *result = ir_build_unreachable_gen(ira, unreachable_instruction->base.scope, unreachable_instruction->base.source_node); return ir_finish_anal(ira, result); } -static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_instruction) { +static Stage1AirInst *ir_analyze_instruction_phi(IrAnalyze *ira, Stage1ZirInstPhi *phi_instruction) { Error err; if (ira->const_predecessor_bb) { @@ -13956,13 +13956,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i]; if (predecessor != ira->const_predecessor_bb) continue; - IrInstGen *value = phi_instruction->incoming_values[i]->child; + Stage1AirInst *value = phi_instruction->incoming_values[i]->child; assert(value->value->type); if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; if (value->value->special != ConstValSpecialRuntime) { - IrInstGen *result = ir_const(ira, phi_instruction->base.scope, + Stage1AirInst *result = ir_const(ira, phi_instruction->base.scope, phi_instruction->base.source_node, nullptr); copy_const_val(ira->codegen, result->value, value->value); return result; @@ -13978,11 +13978,11 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i peer_parent->peers.length >= 2) { if (peer_parent->resolved_type == nullptr) { - IrInstGen **instructions = heap::c_allocator.allocate(peer_parent->peers.length); + Stage1AirInst **instructions = heap::c_allocator.allocate(peer_parent->peers.length); for (size_t i = 0; i < peer_parent->peers.length; i += 1) { ResultLocPeer *this_peer = peer_parent->peers.at(i); - IrInstGen *gen_instruction = this_peer->base.gen_instruction; + Stage1AirInst *gen_instruction = this_peer->base.gen_instruction; if (gen_instruction == nullptr) { // unreachable instructions will cause implicit_elem_type to be null if (this_peer->base.implicit_elem_type == nullptr) { @@ -14010,7 +14010,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i phi_instruction->base.source_node); // In case resolving the parent activates a suspend, do it now - IrInstGen *parent_result_loc = ir_resolve_result(ira, &phi_instruction->base, peer_parent->parent, + Stage1AirInst *parent_result_loc = ir_resolve_result(ira, &phi_instruction->base, peer_parent->parent, peer_parent->resolved_type, nullptr, false, true); if (parent_result_loc != nullptr && (type_is_invalid(parent_result_loc->value->type) || parent_result_loc->value->type->id == ZigTypeIdUnreachable)) @@ -14019,13 +14019,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i } // If the above code generated any instructions in the current basic block, we need // to move them to the peer parent predecessor. - ZigList instrs_to_move = {}; + ZigList instrs_to_move = {}; while (ira->new_irb.current_basic_block->instruction_list.length != 0) { instrs_to_move.append(ira->new_irb.current_basic_block->instruction_list.pop()); } if (instrs_to_move.length != 0) { - IrBasicBlockGen *predecessor = peer_parent->base.source_instruction->child->owner_bb; - IrInstGen *branch_instruction = predecessor->instruction_list.pop(); + Stage1AirBasicBlock *predecessor = peer_parent->base.source_instruction->child->owner_bb; + Stage1AirInst *branch_instruction = predecessor->instruction_list.pop(); src_assert(branch_instruction->value->type->id == ZigTypeIdUnreachable, phi_instruction->base.source_node); while (instrs_to_move.length != 0) { @@ -14053,8 +14053,8 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i return ira_resume(ira); } - ZigList new_incoming_blocks = {0}; - ZigList new_incoming_values = {0}; + ZigList new_incoming_blocks = {0}; + ZigList new_incoming_values = {0}; for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) { Stage1ZirBasicBlock *predecessor = phi_instruction->incoming_blocks[i]; @@ -14062,9 +14062,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i continue; - IrInstSrc *old_value = phi_instruction->incoming_values[i]; + Stage1ZirInst *old_value = phi_instruction->incoming_values[i]; assert(old_value); - IrInstGen *new_value = old_value->child; + Stage1AirInst *new_value = old_value->child; if (!new_value || new_value->value->type->id == ZigTypeIdUnreachable || predecessor->child == nullptr) continue; @@ -14078,13 +14078,13 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i } if (new_incoming_blocks.length == 0) { - IrInstGen *result = ir_build_unreachable_gen(ira, phi_instruction->base.scope, + Stage1AirInst *result = ir_build_unreachable_gen(ira, phi_instruction->base.scope, phi_instruction->base.source_node); return ir_finish_anal(ira, result); } if (new_incoming_blocks.length == 1) { - IrInstGen *incoming_value = new_incoming_values.at(0); + Stage1AirInst *incoming_value = new_incoming_values.at(0); new_incoming_blocks.deinit(); new_incoming_values.deinit(); return incoming_value; @@ -14145,14 +14145,14 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i // cast all values to the resolved type. however we can't put cast instructions in front of the phi instruction. // so we go back and insert the casts as the last instruction in the corresponding predecessor blocks, and // then make sure the branch instruction is preserved. - IrBasicBlockGen *cur_bb = ira->new_irb.current_basic_block; + Stage1AirBasicBlock *cur_bb = ira->new_irb.current_basic_block; for (size_t i = 0; i < new_incoming_values.length; i += 1) { - IrInstGen *new_value = new_incoming_values.at(i); - IrBasicBlockGen *predecessor = new_incoming_blocks.at(i); + Stage1AirInst *new_value = new_incoming_values.at(i); + Stage1AirBasicBlock *predecessor = new_incoming_blocks.at(i); src_assert(predecessor->instruction_list.length != 0, phi_instruction->base.source_node); - IrInstGen *branch_instruction = predecessor->instruction_list.pop(); + Stage1AirInst *branch_instruction = predecessor->instruction_list.pop(); ir_set_cursor_at_end_gen(&ira->new_irb, predecessor); - IrInstGen *casted_value = ir_implicit_cast(ira, new_value, resolved_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, new_value, resolved_type); if (type_is_invalid(casted_value->value->type)) { return ira->codegen->invalid_inst_gen; } @@ -14167,7 +14167,7 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i } ir_set_cursor_at_end_gen(&ira->new_irb, cur_bb); - IrInstGen *result = ir_build_phi_gen(ira, phi_instruction->base.scope, + Stage1AirInst *result = ir_build_phi_gen(ira, phi_instruction->base.scope, phi_instruction->base.source_node, new_incoming_blocks.length, new_incoming_blocks.items, new_incoming_values.items, resolved_type); @@ -14179,9 +14179,9 @@ static IrInstGen *ir_analyze_instruction_phi(IrAnalyze *ira, IrInstSrcPhi *phi_i return result; } -static IrInstGen *ir_analyze_instruction_var_ptr(IrAnalyze *ira, IrInstSrcVarPtr *instruction) { +static Stage1AirInst *ir_analyze_instruction_var_ptr(IrAnalyze *ira, Stage1ZirInstVarPtr *instruction) { ZigVar *var = instruction->var; - IrInstGen *result = ir_get_var_ptr(ira, instruction->base.scope, instruction->base.source_node, var); + Stage1AirInst *result = ir_get_var_ptr(ira, instruction->base.scope, instruction->base.source_node, var); if (instruction->crossed_fndef_scope != nullptr && !instr_is_comptime(result)) { ErrorMsg *msg = ir_add_error_node(ira, instruction->base.source_node, buf_sprintf("'%s' not accessible from inner function", var->name)); @@ -14309,13 +14309,13 @@ static Error compute_elem_align(IrAnalyze *ira, ZigType *elem_type, uint32_t bas return ErrorNone; } -static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemPtr *elem_ptr_instruction) { +static Stage1AirInst *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, Stage1ZirInstElemPtr *elem_ptr_instruction) { Error err; - IrInstGen *array_ptr = elem_ptr_instruction->array_ptr->child; + Stage1AirInst *array_ptr = elem_ptr_instruction->array_ptr->child; if (type_is_invalid(array_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *elem_index = elem_ptr_instruction->elem_index->child; + Stage1AirInst *elem_index = elem_ptr_instruction->elem_index->child; if (type_is_invalid(elem_index->value->type)) return ira->codegen->invalid_inst_gen; @@ -14337,7 +14337,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP array_type->data.pointer.ptr_len == PtrLenSingle && array_type->data.pointer.child_type->id == ZigTypeIdArray) { - IrInstGen *ptr_value = ir_get_deref(ira, elem_ptr_instruction->base.scope, + Stage1AirInst *ptr_value = ir_get_deref(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, array_ptr, nullptr); if (type_is_invalid(ptr_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -14392,7 +14392,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP array_type->data.structure.resolve_status == ResolveStatusBeingInferred) { ZigType *usize = ira->codegen->builtin_types.entry_usize; - IrInstGen *casted_elem_index = ir_implicit_cast(ira, elem_index, usize); + Stage1AirInst *casted_elem_index = ir_implicit_cast(ira, elem_index, usize); if (type_is_invalid(casted_elem_index->value->type)) return ira->codegen->invalid_inst_gen; src_assert(instr_is_comptime(casted_elem_index), elem_ptr_instruction->base.source_node); @@ -14421,7 +14421,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP } ZigType *usize = ira->codegen->builtin_types.entry_usize; - IrInstGen *casted_elem_index = ir_implicit_cast(ira, elem_index, usize); + Stage1AirInst *casted_elem_index = ir_implicit_cast(ira, elem_index, usize); if (type_is_invalid(casted_elem_index->value->type)) return ira->codegen->invalid_inst_gen; @@ -14553,7 +14553,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP return ira->codegen->invalid_inst_gen; } if (array_type->id == ZigTypeIdPointer) { - IrInstGen *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type); + Stage1AirInst *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type); ZigValue *out_val = result->value; out_val->data.x_ptr.mut = array_ptr_val->data.x_ptr.mut; size_t new_index; @@ -14639,7 +14639,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP return_type); } ZigValue *len_field = array_ptr_val->data.x_struct.fields[slice_len_index]; - IrInstGen *result = ir_const(ira, elem_ptr_instruction->base.scope, + Stage1AirInst *result = ir_const(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, return_type); ZigValue *out_val = result->value; ZigType *slice_ptr_type = array_type->data.structure.fields[slice_ptr_index]->type_entry; @@ -14699,7 +14699,7 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP } else if (array_type->id == ZigTypeIdArray || array_type->id == ZigTypeIdVector) { expand_undef_array(ira->codegen, array_ptr_val); - IrInstGen *result; + Stage1AirInst *result; if (orig_array_ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_elem_ptr_gen(ira, elem_ptr_instruction->base.scope, elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index, @@ -14766,9 +14766,9 @@ static IrInstGen *ir_analyze_instruction_elem_ptr(IrAnalyze *ira, IrInstSrcElemP elem_ptr_instruction->base.source_node, array_ptr, casted_elem_index, safety_check_on, return_type); } -static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira, +static Stage1AirInst *ir_analyze_container_member_access_inner(IrAnalyze *ira, ZigType *bare_struct_type, Buf *field_name, Scope *scope, AstNode *source_node, - IrInstGen *container_ptr, AstNode *container_ptr_src, ZigType *container_type) + Stage1AirInst *container_ptr, AstNode *container_ptr_src, ZigType *container_type) { if (!is_slice(bare_struct_type)) { ScopeDecls *container_scope = get_container_scope(bare_struct_type); @@ -14798,7 +14798,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira, if (type_is_invalid(fn_entry->type_entry)) return ira->codegen->invalid_inst_gen; - IrInstGen *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn_entry, container_ptr, + Stage1AirInst *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn_entry, container_ptr, container_ptr_src); return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false); } else if (tld->id == TldIdVar) { @@ -14818,7 +14818,7 @@ static IrInstGen *ir_analyze_container_member_access_inner(IrAnalyze *ira, if (var->const_value->type->id == ZigTypeIdFn) { src_assert(var->const_value->data.x_ptr.special == ConstPtrSpecialFunction, source_node); ZigFn *fn = var->const_value->data.x_ptr.data.fn.fn_entry; - IrInstGen *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn, container_ptr, + Stage1AirInst *bound_fn_value = ir_const_bound_fn(ira, scope, source_node, fn, container_ptr, container_ptr_src); return ir_get_ref(ira, scope, source_node, bound_fn_value, true, false); } @@ -14857,15 +14857,15 @@ static void memoize_field_init_val(CodeGen *codegen, ZigType *container_type, Ty field->type_entry, nullptr, UndefOk); } -static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, - TypeStructField *field, IrInstGen *struct_ptr, ZigType *struct_type, bool initializing) +static Stage1AirInst *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, + TypeStructField *field, Stage1AirInst *struct_ptr, ZigType *struct_type, bool initializing) { Error err; ZigType *field_type = resolve_struct_field_type(ira->codegen, field); if (field_type == nullptr) return ira->codegen->invalid_inst_gen; if (field->is_comptime) { - IrInstGen *elem = ir_const(ira, scope, source_node, field_type); + Stage1AirInst *elem = ir_const(ira, scope, source_node, field_type); memoize_field_init_val(ira->codegen, struct_type, field); if(field->init_val != nullptr && type_is_invalid(field->init_val->type)){ return ira->codegen->invalid_inst_gen; @@ -14877,7 +14877,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN case OnePossibleValueInvalid: return ira->codegen->invalid_inst_gen; case OnePossibleValueYes: { - IrInstGen *elem = ir_const_move(ira, scope, source_node, + Stage1AirInst *elem = ir_const_move(ira, scope, source_node, get_the_one_possible_value(ira->codegen, field_type)); return ir_get_ref(ira, scope, source_node, elem, struct_ptr->value->type->data.pointer.is_const, @@ -14941,7 +14941,7 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN field_val->parent.data.p_struct.field_index = i; } } - IrInstGen *result; + Stage1AirInst *result; if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type); result->value->special = ConstValSpecialStatic; @@ -14959,8 +14959,8 @@ static IrInstGen *ir_analyze_struct_field_ptr(IrAnalyze *ira, Scope *scope, AstN return ir_build_struct_field_ptr(ira, scope, source_node, struct_ptr, field, ptr_type); } -static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name, - Scope *scope, AstNode *source_node, IrInstGen *container_ptr, ZigType *container_type) +static Stage1AirInst *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name, + Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, ZigType *container_type) { // The type of the field is not available until a store using this pointer happens. // So, here we create a special pointer type which has the inferred struct type and @@ -14985,7 +14985,7 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name, if (ptr_val == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *result; + Stage1AirInst *result; if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_cast(ira, scope, source_node, container_ptr_type, container_ptr, CastOpNoop); } else { @@ -14999,8 +14999,8 @@ static IrInstGen *ir_analyze_inferred_field_ptr(IrAnalyze *ira, Buf *field_name, return ir_build_cast(ira, scope, source_node, field_ptr_type, container_ptr, CastOpNoop); } -static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name, - Scope *scope, AstNode *source_node, IrInstGen *container_ptr, AstNode *container_ptr_src, +static Stage1AirInst *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name, + Scope *scope, AstNode *source_node, Stage1AirInst *container_ptr, AstNode *container_ptr_src, ZigType *container_type, bool initializing) { Error err; @@ -15108,7 +15108,7 @@ static IrInstGen *ir_analyze_container_field_ptr(IrAnalyze *ira, Buf *field_name ZigValue *payload_val = union_val->data.x_union.payload; assert(payload_val); - IrInstGen *result; + Stage1AirInst *result; if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_union_field_ptr(ira, scope, source_node, container_ptr, field, true, initializing, ptr_type); @@ -15139,12 +15139,12 @@ static void add_link_lib_symbol(IrAnalyze *ira, Buf *lib_name, Buf *symbol_name, } } -static IrInstGen *ir_error_dependency_loop(IrAnalyze *ira, AstNode* source_node) { +static Stage1AirInst *ir_error_dependency_loop(IrAnalyze *ira, AstNode* source_node) { ir_add_error_node(ira, source_node, buf_sprintf("dependency loop detected")); return ira->codegen->invalid_inst_gen; } -static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Tld *tld) { +static Stage1AirInst *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *source_node, Tld *tld) { resolve_top_level_decl(ira->codegen, tld, source_node, true); if (tld->resolution == TldResolutionInvalid) { return ira->codegen->invalid_inst_gen; @@ -15181,7 +15181,7 @@ static IrInstGen *ir_analyze_decl_ref(IrAnalyze *ira, Scope *scope, AstNode *sou add_link_lib_symbol(ira, tld_fn->extern_lib_name, &fn_entry->symbol_name, source_node); } - IrInstGen *fn_inst = ir_const_fn(ira, scope, source_node, fn_entry); + Stage1AirInst *fn_inst = ir_const_fn(ira, scope, source_node, fn_entry); return ir_get_ref(ira, scope, source_node, fn_inst, true, false); } } @@ -15199,9 +15199,9 @@ static ErrorTableEntry *find_err_table_entry(ZigType *err_set_type, Buf *field_n return nullptr; } -static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFieldPtr *field_ptr_instruction) { +static Stage1AirInst *ir_analyze_instruction_field_ptr(IrAnalyze *ira, Stage1ZirInstFieldPtr *field_ptr_instruction) { Error err; - IrInstGen *container_ptr = field_ptr_instruction->container_ptr->child; + Stage1AirInst *container_ptr = field_ptr_instruction->container_ptr->child; if (type_is_invalid(container_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -15209,7 +15209,7 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel Buf *field_name = field_ptr_instruction->field_name_buffer; if (!field_name) { - IrInstGen *field_name_expr = field_ptr_instruction->field_name_expr->child; + Stage1AirInst *field_name_expr = field_ptr_instruction->field_name_expr->child; field_name = ir_resolve_str(ira, field_name_expr); if (!field_name) return ira->codegen->invalid_inst_gen; @@ -15221,22 +15221,22 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel if (type_is_invalid(container_type)) { return ira->codegen->invalid_inst_gen; } else if (is_tuple(container_type) && !field_ptr_instruction->initializing && buf_eql_str(field_name, "len")) { - IrInstGen *len_inst = ir_const_unsigned(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, + Stage1AirInst *len_inst = ir_const_unsigned(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, container_type->data.structure.src_field_count); return ir_get_ref(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, len_inst, true, false); } else if (is_slice(container_type) || is_container_ref(container_type)) { assert(container_ptr->value->type->id == ZigTypeIdPointer); if (container_type->id == ZigTypeIdPointer) { ZigType *bare_type = container_ref_type(container_type); - IrInstGen *container_child = ir_get_deref(ira, field_ptr_instruction->base.scope, + Stage1AirInst *container_child = ir_get_deref(ira, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, container_ptr, nullptr); - IrInstGen *result = ir_analyze_container_field_ptr(ira, field_name, + Stage1AirInst *result = ir_analyze_container_field_ptr(ira, field_name, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, container_child, field_ptr_instruction->container_ptr->source_node, bare_type, field_ptr_instruction->initializing); return result; } else { - IrInstGen *result = ir_analyze_container_field_ptr(ira, field_name, + Stage1AirInst *result = ir_analyze_container_field_ptr(ira, field_name, field_ptr_instruction->base.scope, field_ptr_instruction->base.source_node, container_ptr, field_ptr_instruction->container_ptr->source_node, container_type, field_ptr_instruction->initializing); @@ -15390,26 +15390,26 @@ static IrInstGen *ir_analyze_instruction_field_ptr(IrAnalyze *ira, IrInstSrcFiel } } -static IrInstGen *ir_analyze_instruction_store_ptr(IrAnalyze *ira, IrInstSrcStorePtr *instruction) { - IrInstGen *ptr = instruction->ptr->child; +static Stage1AirInst *ir_analyze_instruction_store_ptr(IrAnalyze *ira, Stage1ZirInstStorePtr *instruction) { + Stage1AirInst *ptr = instruction->ptr->child; if (type_is_invalid(ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *value = instruction->value->child; + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, ptr, value, instruction->allow_write_through_const); } -static IrInstGen *ir_analyze_instruction_load_ptr(IrAnalyze *ira, IrInstSrcLoadPtr *instruction) { - IrInstGen *ptr = instruction->ptr->child; +static Stage1AirInst *ir_analyze_instruction_load_ptr(IrAnalyze *ira, Stage1ZirInstLoadPtr *instruction) { + Stage1AirInst *ptr = instruction->ptr->child; if (type_is_invalid(ptr->value->type)) return ira->codegen->invalid_inst_gen; return ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, ptr, nullptr); } -static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf *typeof_instruction) { +static Stage1AirInst *ir_analyze_instruction_typeof(IrAnalyze *ira, Stage1ZirInstTypeOf *typeof_instruction) { ZigType *type_entry; const size_t value_count = typeof_instruction->value_count; @@ -15418,9 +15418,9 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf if (value_count < 2) { type_entry = typeof_instruction->value.scalar->child->value->type; } else { - IrInstGen **args = heap::c_allocator.allocate(value_count); + Stage1AirInst **args = heap::c_allocator.allocate(value_count); for (size_t i = 0; i < value_count; i += 1) { - IrInstGen *value = typeof_instruction->value.list[i]->child; + Stage1AirInst *value = typeof_instruction->value.list[i]->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; args[i] = value; @@ -15438,13 +15438,13 @@ static IrInstGen *ir_analyze_instruction_typeof(IrAnalyze *ira, IrInstSrcTypeOf return ir_const_type(ira, typeof_instruction->base.scope, typeof_instruction->base.source_node, type_entry); } -static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCold *instruction) { +static Stage1AirInst *ir_analyze_instruction_set_cold(IrAnalyze *ira, Stage1ZirInstSetCold *instruction) { if (ira->new_irb.exec->is_inline) { // ignore setCold when running functions at compile time return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } - IrInstGen *is_cold_value = instruction->is_cold->child; + Stage1AirInst *is_cold_value = instruction->is_cold->child; bool want_cold; if (!ir_resolve_bool(ira, is_cold_value, &want_cold)) return ira->codegen->invalid_inst_gen; @@ -15467,8 +15467,8 @@ static IrInstGen *ir_analyze_instruction_set_cold(IrAnalyze *ira, IrInstSrcSetCo return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira, - IrInstSrcSetRuntimeSafety *set_runtime_safety_instruction) +static Stage1AirInst *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira, + Stage1ZirInstSetRuntimeSafety *set_runtime_safety_instruction) { if (ira->new_irb.exec->is_inline) { // ignore setRuntimeSafety when running functions at compile time @@ -15505,7 +15505,7 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira, } assert(scope != nullptr); - IrInstGen *safety_on_value = set_runtime_safety_instruction->safety_on->child; + Stage1AirInst *safety_on_value = set_runtime_safety_instruction->safety_on->child; bool want_runtime_safety; if (!ir_resolve_bool(ira, safety_on_value, &want_runtime_safety)) return ira->codegen->invalid_inst_gen; @@ -15524,8 +15524,8 @@ static IrInstGen *ir_analyze_instruction_set_runtime_safety(IrAnalyze *ira, set_runtime_safety_instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira, - IrInstSrcSetFloatMode *instruction) +static Stage1AirInst *ir_analyze_instruction_set_float_mode(IrAnalyze *ira, + Stage1ZirInstSetFloatMode *instruction) { if (ira->new_irb.exec->is_inline) { // ignore setFloatMode when running functions at compile time @@ -15561,7 +15561,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira, } assert(scope != nullptr); - IrInstGen *float_mode_value = instruction->mode_value->child; + Stage1AirInst *float_mode_value = instruction->mode_value->child; FloatMode float_mode_scalar; if (!ir_resolve_float_mode(ira, float_mode_value, &float_mode_scalar)) return ira->codegen->invalid_inst_gen; @@ -15579,7 +15579,7 @@ static IrInstGen *ir_analyze_instruction_set_float_mode(IrAnalyze *ira, return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSrcAnyFrameType *instruction) { +static Stage1AirInst *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, Stage1ZirInstAnyFrameType *instruction) { ZigType *payload_type = nullptr; if (instruction->payload_type != nullptr) { payload_type = ir_resolve_type(ira, instruction->payload_type->child); @@ -15591,8 +15591,8 @@ static IrInstGen *ir_analyze_instruction_any_frame_type(IrAnalyze *ira, IrInstSr return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, any_frame_type); } -static IrInstGen *ir_analyze_instruction_slice_type(IrAnalyze *ira, IrInstSrcSliceType *slice_type_instruction) { - IrInstGen *result = ir_const(ira, slice_type_instruction->base.scope, +static Stage1AirInst *ir_analyze_instruction_slice_type(IrAnalyze *ira, Stage1ZirInstSliceType *slice_type_instruction) { + Stage1AirInst *result = ir_const(ira, slice_type_instruction->base.scope, slice_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; @@ -15643,7 +15643,7 @@ static size_t find_asm_index(CodeGen *g, AstNode *node, AsmToken *tok, Buf *src_ return SIZE_MAX; } -static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_instruction) { +static Stage1AirInst *ir_analyze_instruction_asm(IrAnalyze *ira, Stage1ZirInstAsm *asm_instruction) { Error err; assert(asm_instruction->base.source_node->type == NodeTypeAsmExpr); @@ -15688,8 +15688,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i // TODO validate the output types and variable types - IrInstGen **input_list = heap::c_allocator.allocate(asm_expr->input_list.length); - IrInstGen **output_types = heap::c_allocator.allocate(asm_expr->output_list.length); + Stage1AirInst **input_list = heap::c_allocator.allocate(asm_expr->input_list.length); + Stage1AirInst **output_types = heap::c_allocator.allocate(asm_expr->output_list.length); ZigType *return_type = ira->codegen->builtin_types.entry_void; for (size_t i = 0; i < asm_expr->output_list.length; i += 1) { @@ -15703,7 +15703,7 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i } for (size_t i = 0; i < asm_expr->input_list.length; i += 1) { - IrInstGen *const input_value = asm_instruction->input_list[i]->child; + Stage1AirInst *const input_value = asm_instruction->input_list[i]->child; if (type_is_invalid(input_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -15724,8 +15724,8 @@ static IrInstGen *ir_analyze_instruction_asm(IrAnalyze *ira, IrInstSrcAsm *asm_i asm_instruction->has_side_effects, return_type); } -static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArrayType *array_type_instruction) { - IrInstGen *result = ir_const(ira, array_type_instruction->base.scope, +static Stage1AirInst *ir_analyze_instruction_array_type(IrAnalyze *ira, Stage1ZirInstArrayType *array_type_instruction) { + Stage1AirInst *result = ir_const(ira, array_type_instruction->base.scope, array_type_instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; @@ -15750,8 +15750,8 @@ static IrInstGen *ir_analyze_instruction_array_type(IrAnalyze *ira, IrInstSrcArr return result; } -static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf *instruction) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int); +static Stage1AirInst *ir_analyze_instruction_size_of(IrAnalyze *ira, Stage1ZirInstSizeOf *instruction) { + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int); result->value->special = ConstValSpecialLazy; LazyValueSizeOf *lazy_size_of = heap::c_allocator.create(); @@ -15767,7 +15767,7 @@ static IrInstGen *ir_analyze_instruction_size_of(IrAnalyze *ira, IrInstSrcSizeOf return result; } -static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) { +static Stage1AirInst *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) { ZigType *type_entry = value->value->type; if (type_entry->id == ZigTypeIdPointer && type_entry->data.pointer.allow_zero) { @@ -15803,16 +15803,16 @@ static IrInstGen *ir_analyze_test_non_null(IrAnalyze *ira, Scope *scope, AstNode } } -static IrInstGen *ir_analyze_instruction_test_non_null(IrAnalyze *ira, IrInstSrcTestNonNull *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_instruction_test_non_null(IrAnalyze *ira, Stage1ZirInstTestNonNull *instruction) { + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_test_non_null(ira, instruction->base.scope, instruction->base.source_node, value); } -static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool safety_check_on, bool initializing) +static Stage1AirInst *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool safety_check_on, bool initializing) { Error err; @@ -15841,7 +15841,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop } if (!safety_check_on) return base_ptr; - IrInstGen *c_ptr_val = ir_get_deref(ira, scope, source_node, base_ptr, nullptr); + Stage1AirInst *c_ptr_val = ir_get_deref(ira, scope, source_node, base_ptr, nullptr); ir_build_assert_non_null(ira, scope, source_node, c_ptr_val); return base_ptr; } @@ -15900,7 +15900,7 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop } } - IrInstGen *result; + Stage1AirInst *result; if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_optional_unwrap_ptr_gen(ira, scope, source_node, base_ptr, false, initializing, result_type); @@ -15935,10 +15935,10 @@ static IrInstGen *ir_analyze_unwrap_optional_payload(IrAnalyze *ira, Scope *scop initializing, result_type); } -static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira, - IrInstSrcOptionalUnwrapPtr *instruction) +static Stage1AirInst *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira, + Stage1ZirInstOptionalUnwrapPtr *instruction) { - IrInstGen *base_ptr = instruction->base_ptr->child; + Stage1AirInst *base_ptr = instruction->base_ptr->child; if (type_is_invalid(base_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -15946,12 +15946,12 @@ static IrInstGen *ir_analyze_instruction_optional_unwrap_ptr(IrAnalyze *ira, instruction->safety_check_on, false); } -static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instruction) { +static Stage1AirInst *ir_analyze_instruction_ctz(IrAnalyze *ira, Stage1ZirInstCtz *instruction) { ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child); if (type_is_invalid(int_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type); + Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type); if (type_is_invalid(op->value->type)) return ira->codegen->invalid_inst_gen; @@ -15972,12 +15972,12 @@ static IrInstGen *ir_analyze_instruction_ctz(IrAnalyze *ira, IrInstSrcCtz *instr return ir_build_ctz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op); } -static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instruction) { +static Stage1AirInst *ir_analyze_instruction_clz(IrAnalyze *ira, Stage1ZirInstClz *instruction) { ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child); if (type_is_invalid(int_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type); + Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type); if (type_is_invalid(op->value->type)) return ira->codegen->invalid_inst_gen; @@ -15998,12 +15998,12 @@ static IrInstGen *ir_analyze_instruction_clz(IrAnalyze *ira, IrInstSrcClz *instr return ir_build_clz_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op); } -static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopCount *instruction) { +static Stage1AirInst *ir_analyze_instruction_pop_count(IrAnalyze *ira, Stage1ZirInstPopCount *instruction) { ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child); if (type_is_invalid(int_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type); + Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type); if (type_is_invalid(op->value->type)) return ira->codegen->invalid_inst_gen; @@ -16029,7 +16029,7 @@ static IrInstGen *ir_analyze_instruction_pop_count(IrAnalyze *ira, IrInstSrcPopC return ir_build_pop_count_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, op); } -static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value) { +static Stage1AirInst *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value) { if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; @@ -16055,7 +16055,7 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so if (!val) return ira->codegen->invalid_inst_gen; - IrInstGenConst *const_instruction = ir_create_inst_gen(&ira->new_irb, + Stage1AirInstConst *const_instruction = ir_create_inst_gen(&ira->new_irb, scope, source_node); const_instruction->base.value->type = tag_type; const_instruction->base.value->special = ConstValSpecialStatic; @@ -16066,10 +16066,10 @@ static IrInstGen *ir_analyze_union_tag(IrAnalyze *ira, Scope *scope, AstNode *so return ir_build_union_tag(ira, scope, source_node, value, tag_type); } -static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira, - IrInstSrcSwitchBr *switch_br_instruction) +static Stage1AirInst *ir_analyze_instruction_switch_br(IrAnalyze *ira, + Stage1ZirInstSwitchBr *switch_br_instruction) { - IrInstGen *target_value = switch_br_instruction->target_value->child; + Stage1AirInst *target_value = switch_br_instruction->target_value->child; if (type_is_invalid(target_value->value->type)) return ir_unreach_error(ira); @@ -16093,12 +16093,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira, Stage1ZirBasicBlock *old_dest_block = switch_br_instruction->else_block; for (size_t i = 0; i < case_count; i += 1) { - IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i]; - IrInstGen *case_value = old_case->value->child; + Stage1ZirInstSwitchBrCase *old_case = &switch_br_instruction->cases[i]; + Stage1AirInst *case_value = old_case->value->child; if (type_is_invalid(case_value->value->type)) return ir_unreach_error(ira); - IrInstGen *casted_case_value = ir_implicit_cast(ira, case_value, target_value->value->type); + Stage1AirInst *casted_case_value = ir_implicit_cast(ira, case_value, target_value->value->type); if (type_is_invalid(casted_case_value->value->type)) return ir_unreach_error(ira); @@ -16115,17 +16115,17 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira, if (is_comptime || old_dest_block->ref_count == 1) { return ir_inline_bb(ira, switch_br_instruction->base.source_node, old_dest_block); } else { - IrBasicBlockGen *new_dest_block = ir_get_new_bb(ira, old_dest_block, &switch_br_instruction->base); - IrInstGen *result = ir_build_br_gen(ira, switch_br_instruction->base.scope, + Stage1AirBasicBlock *new_dest_block = ir_get_new_bb(ira, old_dest_block, &switch_br_instruction->base); + Stage1AirInst *result = ir_build_br_gen(ira, switch_br_instruction->base.scope, switch_br_instruction->base.source_node, new_dest_block); return ir_finish_anal(ira, result); } } - IrInstGenSwitchBrCase *cases = heap::c_allocator.allocate(case_count); + Stage1AirInstSwitchBrCase *cases = heap::c_allocator.allocate(case_count); for (size_t i = 0; i < case_count; i += 1) { - IrInstSrcSwitchBrCase *old_case = &switch_br_instruction->cases[i]; - IrInstGenSwitchBrCase *new_case = &cases[i]; + Stage1ZirInstSwitchBrCase *old_case = &switch_br_instruction->cases[i]; + Stage1AirInstSwitchBrCase *new_case = &cases[i]; new_case->block = ir_get_new_bb(ira, old_case->block, &switch_br_instruction->base); new_case->value = ira->codegen->invalid_inst_gen; @@ -16135,12 +16135,12 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira, // it back after the loop. new_case->block->ref_instruction = nullptr; - IrInstSrc *old_value = old_case->value; - IrInstGen *new_value = old_value->child; + Stage1ZirInst *old_value = old_case->value; + Stage1AirInst *new_value = old_value->child; if (type_is_invalid(new_value->value->type)) continue; - IrInstGen *casted_new_value = ir_implicit_cast(ira, new_value, target_value->value->type); + Stage1AirInst *casted_new_value = ir_implicit_cast(ira, new_value, target_value->value->type); if (type_is_invalid(casted_new_value->value->type)) continue; @@ -16151,23 +16151,23 @@ static IrInstGen *ir_analyze_instruction_switch_br(IrAnalyze *ira, } for (size_t i = 0; i < case_count; i += 1) { - IrInstGenSwitchBrCase *new_case = &cases[i]; + Stage1AirInstSwitchBrCase *new_case = &cases[i]; if (type_is_invalid(new_case->value->value->type)) return ir_unreach_error(ira); new_case->block->ref_instruction = &switch_br_instruction->base; } - IrBasicBlockGen *new_else_block = ir_get_new_bb(ira, switch_br_instruction->else_block, &switch_br_instruction->base); - IrInstGenSwitchBr *switch_br = ir_build_switch_br_gen(ira, switch_br_instruction->base.scope, + Stage1AirBasicBlock *new_else_block = ir_get_new_bb(ira, switch_br_instruction->else_block, &switch_br_instruction->base); + Stage1AirInstSwitchBr *switch_br = ir_build_switch_br_gen(ira, switch_br_instruction->base.scope, switch_br_instruction->base.source_node, target_value, new_else_block, case_count, cases); return ir_finish_anal(ira, &switch_br->base); } -static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira, - IrInstSrcSwitchTarget *switch_target_instruction) +static Stage1AirInst *ir_analyze_instruction_switch_target(IrAnalyze *ira, + Stage1ZirInstSwitchTarget *switch_target_instruction) { Error err; - IrInstGen *target_value_ptr = switch_target_instruction->target_value_ptr->child; + Stage1AirInst *target_value_ptr = switch_target_instruction->target_value_ptr->child; if (type_is_invalid(target_value_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -16207,14 +16207,14 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira, case ZigTypeIdFn: case ZigTypeIdErrorSet: { if (pointee_val) { - IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, + Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, nullptr); copy_const_val(ira->codegen, result->value, pointee_val); result->value->type = target_type; return result; } - IrInstGen *result = ir_get_deref(ira, switch_target_instruction->base.scope, + Stage1AirInst *result = ir_get_deref(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_value_ptr, nullptr); result->value->type = target_type; return result; @@ -16234,19 +16234,19 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira, assert(tag_type != nullptr); assert(tag_type->id == ZigTypeIdEnum); if (pointee_val) { - IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type); + Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type); bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_union.tag); return result; } if (can_fold_enum_type(tag_type)) { - IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type); + Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, tag_type); TypeEnumField *only_field = &tag_type->data.enumeration.fields[0]; bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value); return result; } - IrInstGen *union_value = ir_get_deref(ira, switch_target_instruction->base.scope, + Stage1AirInst *union_value = ir_get_deref(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_value_ptr, nullptr); union_value->value->type = target_type; @@ -16258,18 +16258,18 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira, if (can_fold_enum_type(target_type)) { TypeEnumField *only_field = &target_type->data.enumeration.fields[0]; - IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type); + Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type); bigint_init_bigint(&result->value->data.x_enum_tag, &only_field->value); return result; } if (pointee_val) { - IrInstGen *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type); + Stage1AirInst *result = ir_const(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_type); bigint_init_bigint(&result->value->data.x_enum_tag, &pointee_val->data.x_enum_tag); return result; } - IrInstGen *enum_value = ir_get_deref(ira, switch_target_instruction->base.scope, + Stage1AirInst *enum_value = ir_get_deref(ira, switch_target_instruction->base.scope, switch_target_instruction->base.source_node, target_value_ptr, nullptr); enum_value->value->type = target_type; return enum_value; @@ -16293,8 +16293,8 @@ static IrInstGen *ir_analyze_instruction_switch_target(IrAnalyze *ira, zig_unreachable(); } -static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwitchVar *instruction) { - IrInstGen *target_value_ptr = instruction->target_value_ptr->child; +static Stage1AirInst *ir_analyze_instruction_switch_var(IrAnalyze *ira, Stage1ZirInstSwitchVar *instruction) { + Stage1AirInst *target_value_ptr = instruction->target_value_ptr->child; if (type_is_invalid(target_value_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -16307,11 +16307,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi assert(enum_type->id == ZigTypeIdEnum); assert(instruction->prongs_len > 0); - IrInstGen *first_prong_value = instruction->prongs_ptr[0]->child; + Stage1AirInst *first_prong_value = instruction->prongs_ptr[0]->child; if (type_is_invalid(first_prong_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *first_casted_prong_value = ir_implicit_cast(ira, first_prong_value, enum_type); + Stage1AirInst *first_casted_prong_value = ir_implicit_cast(ira, first_prong_value, enum_type); if (type_is_invalid(first_casted_prong_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -16323,11 +16323,11 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi ErrorMsg *invalid_payload_msg = nullptr; for (size_t prong_i = 1; prong_i < instruction->prongs_len; prong_i += 1) { - IrInstGen *this_prong_inst = instruction->prongs_ptr[prong_i]->child; + Stage1AirInst *this_prong_inst = instruction->prongs_ptr[prong_i]->child; if (type_is_invalid(this_prong_inst->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *this_casted_prong_value = ir_implicit_cast(ira, this_prong_inst, enum_type); + Stage1AirInst *this_casted_prong_value = ir_implicit_cast(ira, this_prong_inst, enum_type); if (type_is_invalid(this_casted_prong_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -16362,7 +16362,7 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi if (pointee_val == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, get_pointer_to_type(ira->codegen, first_field->type_entry, target_val_ptr->type->data.pointer.is_const)); ZigValue *out_val = result->value; @@ -16416,10 +16416,10 @@ static IrInstGen *ir_analyze_instruction_switch_var(IrAnalyze *ira, IrInstSrcSwi } } -static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira, - IrInstSrcSwitchElseVar *instruction) +static Stage1AirInst *ir_analyze_instruction_switch_else_var(IrAnalyze *ira, + Stage1ZirInstSwitchElseVar *instruction) { - IrInstGen *target_value_ptr = instruction->target_value_ptr->child; + Stage1AirInst *target_value_ptr = instruction->target_value_ptr->child; if (type_is_invalid(target_value_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -16441,8 +16441,8 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira, // We may not have any case in the switch if this is a lone else const size_t switch_cases = instruction->switch_br ? instruction->switch_br->case_count : 0; for (size_t case_i = 0; case_i < switch_cases; case_i += 1) { - IrInstSrcSwitchBrCase *br_case = &instruction->switch_br->cases[case_i]; - IrInstGen *case_expr = br_case->value->child; + Stage1ZirInstSwitchBrCase *br_case = &instruction->switch_br->cases[case_i]; + Stage1AirInst *case_expr = br_case->value->child; if (case_expr->value->type->id == ZigTypeIdErrorSet) { ErrorTableEntry *err = ir_resolve_error(ira, case_expr); if (err == nullptr) @@ -16498,10 +16498,10 @@ static IrInstGen *ir_analyze_instruction_switch_else_var(IrAnalyze *ira, return target_value_ptr; } -static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport *import_instruction) { +static Stage1AirInst *ir_analyze_instruction_import(IrAnalyze *ira, Stage1ZirInstImport *import_instruction) { Error err; - IrInstGen *name_value = import_instruction->name->child; + Stage1AirInst *name_value = import_instruction->name->child; Buf *import_target_str = ir_resolve_str(ira, name_value); if (!import_target_str) return ira->codegen->invalid_inst_gen; @@ -16534,8 +16534,8 @@ static IrInstGen *ir_analyze_instruction_import(IrAnalyze *ira, IrInstSrcImport return ir_const_type(ira, import_instruction->base.scope, import_instruction->base.source_node, target_import); } -static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_instruction) { - IrInstGen *value = ref_instruction->value->child; +static Stage1AirInst *ir_analyze_instruction_ref(IrAnalyze *ira, Stage1ZirInstRef *ref_instruction) { + Stage1AirInst *value = ref_instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; @@ -16550,9 +16550,9 @@ static IrInstGen *ir_analyze_instruction_ref(IrAnalyze *ira, IrInstSrcRef *ref_i return ir_get_ref(ira, ref_instruction->base.scope, ref_instruction->base.source_node, value, is_const, is_volatile); } -static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node, - AstNode *field_source_node, ZigType *union_type, Buf *field_name, IrInstGen *field_result_loc, - IrInstGen *result_loc) +static Stage1AirInst *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *source_node, + AstNode *field_source_node, ZigType *union_type, Buf *field_name, Stage1AirInst *field_result_loc, + Stage1AirInst *result_loc) { Error err; assert(union_type->id == ZigTypeIdUnion); @@ -16584,7 +16584,7 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s bool is_comptime = ir_should_inline(ira->zir, scope) || type_requires_comptime(ira->codegen, union_type) == ReqCompTimeYes; - IrInstGen *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr); + Stage1AirInst *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr); if (is_comptime && !instr_is_comptime(result)) { ir_add_error(ira, field_result_loc, buf_sprintf("unable to evaluate constant expression")); @@ -16593,9 +16593,9 @@ static IrInstGen *ir_analyze_union_init(IrAnalyze *ira, Scope *scope, AstNode *s return result; } -static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *container_type, size_t instr_field_count, IrInstSrcContainerInitFieldsField *fields, - IrInstGen *result_loc) +static Stage1AirInst *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *container_type, size_t instr_field_count, Stage1ZirInstContainerInitFieldsField *fields, + Stage1AirInst *result_loc) { Error err; if (container_type->id == ZigTypeIdUnion) { @@ -16604,8 +16604,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, buf_sprintf("union initialization expects exactly one field")); return ira->codegen->invalid_inst_gen; } - IrInstSrcContainerInitFieldsField *field = &fields[0]; - IrInstGen *field_result_loc = field->result_loc->child; + Stage1ZirInstContainerInitFieldsField *field = &fields[0]; + Stage1AirInst *field_result_loc = field->result_loc->child; if (type_is_invalid(field_result_loc->value->type)) return ira->codegen->invalid_inst_gen; @@ -16629,10 +16629,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, size_t actual_field_count = container_type->data.structure.src_field_count; - IrInstGen *first_non_const_instruction = nullptr; + Stage1AirInst *first_non_const_instruction = nullptr; AstNode **field_assign_nodes = heap::c_allocator.allocate(actual_field_count); - ZigList const_ptrs = {}; + ZigList const_ptrs = {}; bool is_comptime = ir_should_inline(ira->zir, scope) || type_requires_comptime(ira->codegen, container_type) == ReqCompTimeYes; @@ -16650,9 +16650,9 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, // comptime-known values. for (size_t i = 0; i < instr_field_count; i += 1) { - IrInstSrcContainerInitFieldsField *field = &fields[i]; + Stage1ZirInstContainerInitFieldsField *field = &fields[i]; - IrInstGen *field_result_loc = field->result_loc->child; + Stage1AirInst *field_result_loc = field->result_loc->child; if (type_is_invalid(field_result_loc->value->type)) return ira->codegen->invalid_inst_gen; @@ -16701,10 +16701,10 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, if (type_is_invalid(field->init_val->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *runtime_inst = ir_const(ira, scope, source_node, field->init_val->type); + Stage1AirInst *runtime_inst = ir_const(ira, scope, source_node, field->init_val->type); copy_const_val(ira->codegen, runtime_inst->value, field->init_val); - IrInstGen *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc, + Stage1AirInst *field_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, field, result_loc, container_type, true); ir_analyze_store_ptr(ira, scope, source_node, field_ptr, runtime_inst, false); if (instr_is_comptime(field_ptr) && field_ptr->value->data.x_ptr.mut != ConstPtrMutRuntimeVar) { @@ -16721,8 +16721,8 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, if (const_ptrs.length != actual_field_count) { result_loc->value->special = ConstValSpecialRuntime; for (size_t i = 0; i < const_ptrs.length; i += 1) { - IrInstGen *field_result_loc = const_ptrs.at(i); - IrInstGen *deref = ir_get_deref(ira, field_result_loc->scope, + Stage1AirInst *field_result_loc = const_ptrs.at(i); + Stage1AirInst *deref = ir_get_deref(ira, field_result_loc->scope, field_result_loc->source_node, field_result_loc, nullptr); field_result_loc->value->special = ConstValSpecialRuntime; ir_analyze_store_ptr(ira, field_result_loc->scope, field_result_loc->source_node, @@ -16732,7 +16732,7 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, } const_ptrs.deinit(); - IrInstGen *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr); + Stage1AirInst *result = ir_get_deref(ira, scope, source_node, result_loc, nullptr); if (is_comptime && !instr_is_comptime(result)) { ir_add_error_node(ira, first_non_const_instruction->source_node, @@ -16743,11 +16743,11 @@ static IrInstGen *ir_analyze_container_init_fields(IrAnalyze *ira, Scope *scope, return result; } -static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, - IrInstSrcContainerInitList *instruction) +static Stage1AirInst *ir_analyze_instruction_container_init_list(IrAnalyze *ira, + Stage1ZirInstContainerInitList *instruction) { src_assert(instruction->result_loc != nullptr, instruction->base.source_node); - IrInstGen *result_loc = instruction->result_loc->child; + Stage1AirInst *result_loc = instruction->result_loc->child; if (type_is_invalid(result_loc->value->type)) return result_loc; @@ -16778,7 +16778,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, if (container_type->id == ZigTypeIdStruct && elem_count == 0) { src_assert(instruction->result_loc != nullptr, instruction->base.source_node); - IrInstGen *result_loc = instruction->result_loc->child; + Stage1AirInst *result_loc = instruction->result_loc->child; if (type_is_invalid(result_loc->value->type)) return result_loc; return ir_analyze_container_init_fields(ira, instruction->base.scope, instruction->base.source_node, container_type, 0, nullptr, result_loc); @@ -16830,7 +16830,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, break; } - IrInstGen *first_non_const_instruction = nullptr; + Stage1AirInst *first_non_const_instruction = nullptr; // The Result Location Mechanism has already emitted runtime instructions to // initialize runtime elements and has omitted instructions for the comptime @@ -16839,10 +16839,10 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, // array initialization can be a comptime value, overwrite ConstPtrMutInfer with // ConstPtrMutComptimeConst. Otherwise, emit instructions to runtime-initialize the // elements that have comptime-known values. - ZigList const_ptrs = {}; + ZigList const_ptrs = {}; for (size_t i = 0; i < elem_count; i += 1) { - IrInstGen *elem_result_loc = instruction->elem_result_loc_list[i]->child; + Stage1AirInst *elem_result_loc = instruction->elem_result_loc_list[i]->child; if (type_is_invalid(elem_result_loc->value->type)) return ira->codegen->invalid_inst_gen; @@ -16861,13 +16861,13 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, if (const_ptrs.length != elem_count) { result_loc->value->special = ConstValSpecialRuntime; for (size_t i = 0; i < const_ptrs.length; i += 1) { - IrInstGen *elem_result_loc = const_ptrs.at(i); + Stage1AirInst *elem_result_loc = const_ptrs.at(i); assert(elem_result_loc->value->special == ConstValSpecialStatic); if (elem_result_loc->value->type->data.pointer.inferred_struct_field != nullptr) { // This field will be generated comptime; no need to do this. continue; } - IrInstGen *deref = ir_get_deref(ira, elem_result_loc->scope, + Stage1AirInst *deref = ir_get_deref(ira, elem_result_loc->scope, elem_result_loc->source_node, elem_result_loc, nullptr); elem_result_loc->value->special = ConstValSpecialRuntime; ir_analyze_store_ptr(ira, elem_result_loc->scope, elem_result_loc->source_node, @@ -16878,7 +16878,7 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, const_ptrs.deinit(); - IrInstGen *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, + Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, result_loc, nullptr); // If the result is a tuple, we are allowed to return a struct that uses ConstValSpecialRuntime fields at comptime. if (instr_is_comptime(result) || is_tuple(container_type)) @@ -16902,11 +16902,11 @@ static IrInstGen *ir_analyze_instruction_container_init_list(IrAnalyze *ira, return result; } -static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira, - IrInstSrcContainerInitFields *instruction) +static Stage1AirInst *ir_analyze_instruction_container_init_fields(IrAnalyze *ira, + Stage1ZirInstContainerInitFields *instruction) { src_assert(instruction->result_loc != nullptr, instruction->base.source_node); - IrInstGen *result_loc = instruction->result_loc->child; + Stage1AirInst *result_loc = instruction->result_loc->child; if (type_is_invalid(result_loc->value->type)) return result_loc; @@ -16922,8 +16922,8 @@ static IrInstGen *ir_analyze_instruction_container_init_fields(IrAnalyze *ira, instruction->field_count, instruction->fields, result_loc); } -static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCompileErr *instruction) { - IrInstGen *msg_value = instruction->msg->child; +static Stage1AirInst *ir_analyze_instruction_compile_err(IrAnalyze *ira, Stage1ZirInstCompileErr *instruction) { + Stage1AirInst *msg_value = instruction->msg->child; Buf *msg_buf = ir_resolve_str(ira, msg_value); if (!msg_buf) return ira->codegen->invalid_inst_gen; @@ -16933,11 +16933,11 @@ static IrInstGen *ir_analyze_instruction_compile_err(IrAnalyze *ira, IrInstSrcCo return ira->codegen->invalid_inst_gen; } -static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCompileLog *instruction) { +static Stage1AirInst *ir_analyze_instruction_compile_log(IrAnalyze *ira, Stage1ZirInstCompileLog *instruction) { Buf buf = BUF_INIT; fprintf(stderr, "| "); for (size_t i = 0; i < instruction->msg_count; i += 1) { - IrInstGen *msg = instruction->msg_list[i]->child; + Stage1AirInst *msg = instruction->msg_list[i]->child; if (type_is_invalid(msg->value->type)) return ira->codegen->invalid_inst_gen; buf_resize(&buf, 0); @@ -16963,12 +16963,12 @@ static IrInstGen *ir_analyze_instruction_compile_log(IrAnalyze *ira, IrInstSrcCo return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrName *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_instruction_err_name(IrAnalyze *ira, Stage1ZirInstErrName *instruction) { + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_global_error_set); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, ira->codegen->builtin_types.entry_global_error_set); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -16982,7 +16982,7 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa ira->codegen, &err->name, ira->codegen->intern.for_zero_byte()); } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); result->value = err->cached_error_name_val; return result; } @@ -16996,16 +16996,16 @@ static IrInstGen *ir_analyze_instruction_err_name(IrAnalyze *ira, IrInstSrcErrNa return ir_build_err_name_gen(ira, instruction->base.scope, instruction->base.source_node, value, str_type); } -static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrcTagName *instruction) { +static Stage1AirInst *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, Stage1ZirInstTagName *instruction) { Error err; - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; ZigType *target_type = target->value->type; if (target_type->id == ZigTypeIdEnumLiteral) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); Buf *field_name = target->value->data.x_enum_literal; result->value = create_sentineled_str_lit( ira->codegen, field_name, @@ -17028,7 +17028,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc if (can_fold_enum_type(target_type)) { TypeEnumField *only_field = &target_type->data.enumeration.fields[0]; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); result->value = create_sentineled_str_lit( ira->codegen, only_field->name, ira->codegen->intern.for_zero_byte()); @@ -17047,7 +17047,7 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc buf_sprintf("no tag by value %s", buf_ptr(int_buf))); return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); result->value = create_sentineled_str_lit( ira->codegen, field->name, ira->codegen->intern.for_zero_byte()); @@ -17062,21 +17062,21 @@ static IrInstGen *ir_analyze_instruction_enum_tag_name(IrAnalyze *ira, IrInstSrc return ir_build_tag_name_gen(ira, instruction->base.scope, instruction->base.source_node, target, result_type); } -static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira, - IrInstSrcFieldParentPtr *instruction) +static Stage1AirInst *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira, + Stage1ZirInstFieldParentPtr *instruction) { Error err; - IrInstGen *type_value = instruction->type_value->child; + Stage1AirInst *type_value = instruction->type_value->child; ZigType *container_type = ir_resolve_type(ira, type_value); if (type_is_invalid(container_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_name_value = instruction->field_name->child; + Stage1AirInst *field_name_value = instruction->field_name->child; Buf *field_name = ir_resolve_str(ira, field_name_value); if (!field_name) return ira->codegen->invalid_inst_gen; - IrInstGen *field_ptr = instruction->field_ptr->child; + Stage1AirInst *field_ptr = instruction->field_ptr->child; if (type_is_invalid(field_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -17112,7 +17112,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira, field_ptr->value->type->data.pointer.is_volatile, PtrLenSingle, field_ptr_align, 0, 0, false); - IrInstGen *casted_field_ptr = ir_implicit_cast(ira, field_ptr, field_ptr_type); + Stage1AirInst *casted_field_ptr = ir_implicit_cast(ira, field_ptr, field_ptr_type); if (type_is_invalid(casted_field_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -17141,7 +17141,7 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira, return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); ZigValue *out_val = result->value; out_val->data.x_ptr.special = ConstPtrSpecialRef; out_val->data.x_ptr.data.ref.pointee = field_ptr_val->data.x_ptr.data.base_struct.struct_val; @@ -17153,8 +17153,8 @@ static IrInstGen *ir_analyze_instruction_field_parent_ptr(IrAnalyze *ira, } static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira, - IrInstGen *type_value, - IrInstGen *field_name_value, + Stage1AirInst *type_value, + Stage1AirInst *field_name_value, size_t *byte_offset) { ZigType *container_type = ir_resolve_type(ira, type_value); @@ -17194,12 +17194,12 @@ static TypeStructField *validate_host_int_byte_offset(IrAnalyze *ira, return field; } -static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffsetOf *instruction) { - IrInstGen *type_value = instruction->type_value->child; +static Stage1AirInst *ir_analyze_instruction_offset_of(IrAnalyze *ira, Stage1ZirInstOffsetOf *instruction) { + Stage1AirInst *type_value = instruction->type_value->child; if (type_is_invalid(type_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_name_value = instruction->field_name->child; + Stage1AirInst *field_name_value = instruction->field_name->child; size_t host_int_byte_offset = 0; TypeStructField *field = nullptr; if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset))) @@ -17209,11 +17209,11 @@ static IrInstGen *ir_analyze_instruction_offset_of(IrAnalyze *ira, IrInstSrcOffs return ir_const_unsigned(ira, instruction->base.scope, instruction->base.source_node, byte_offset); } -static IrInstGen *ir_analyze_instruction_bit_offset_of(IrAnalyze *ira, IrInstSrcBitOffsetOf *instruction) { - IrInstGen *type_value = instruction->type_value->child; +static Stage1AirInst *ir_analyze_instruction_bit_offset_of(IrAnalyze *ira, Stage1ZirInstBitOffsetOf *instruction) { + Stage1AirInst *type_value = instruction->type_value->child; if (type_is_invalid(type_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *field_name_value = instruction->field_name->child; + Stage1AirInst *field_name_value = instruction->field_name->child; size_t host_int_byte_offset = 0; TypeStructField *field = nullptr; if (!(field = validate_host_int_byte_offset(ira, type_value, field_name_value, &host_int_byte_offset))) @@ -18275,9 +18275,9 @@ static Error ir_make_type_info_value(IrAnalyze *ira, Scope *scope, AstNode *sour return ErrorNone; } -static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcTypeInfo *instruction) { +static Stage1AirInst *ir_analyze_instruction_type_info(IrAnalyze *ira, Stage1ZirInstTypeInfo *instruction) { Error err; - IrInstGen *type_value = instruction->type_value->child; + Stage1AirInst *type_value = instruction->type_value->child; ZigType *type_entry = ir_resolve_type(ira, type_value); if (type_is_invalid(type_entry)) return ira->codegen->invalid_inst_gen; @@ -18288,7 +18288,7 @@ static IrInstGen *ir_analyze_instruction_type_info(IrAnalyze *ira, IrInstSrcType if ((err = ir_make_type_info_value(ira, instruction->base.scope, instruction->base.source_node, type_entry, &payload))) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); ZigValue *out_val = result->value; bigint_init_unsigned(&out_val->data.x_union.tag, type_id_index(type_entry)); out_val->data.x_union.payload = payload; @@ -18321,8 +18321,8 @@ static Error get_const_field_sentinel(IrAnalyze *ira, Scope *scope, AstNode *sou if (field_val == nullptr) return ErrorSemanticAnalyzeFail; - IrInstGen *field_inst = ir_const_move(ira, scope, source_node, field_val); - IrInstGen *casted_field_inst = ir_implicit_cast(ira, field_inst, + Stage1AirInst *field_inst = ir_const_move(ira, scope, source_node, field_val); + Stage1AirInst *casted_field_inst = ir_implicit_cast(ira, field_inst, get_optional_type(ira->codegen, elem_type)); if (type_is_invalid(casted_field_inst->value->type)) return ErrorSemanticAnalyzeFail; @@ -19065,12 +19065,12 @@ static ZigType *type_info_to_type(IrAnalyze *ira, Scope *scope, AstNode *source_ zig_unreachable(); } -static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *instruction) { - IrInstGen *uncasted_type_info = instruction->type_info->child; +static Stage1AirInst *ir_analyze_instruction_type(IrAnalyze *ira, Stage1ZirInstType *instruction) { + Stage1AirInst *uncasted_type_info = instruction->type_info->child; if (type_is_invalid(uncasted_type_info->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *type_info = ir_implicit_cast(ira, uncasted_type_info, ir_type_info_get_type(ira, nullptr, nullptr)); + Stage1AirInst *type_info = ir_implicit_cast(ira, uncasted_type_info, ir_type_info_get_type(ira, nullptr, nullptr)); if (type_is_invalid(type_info->value->type)) return ira->codegen->invalid_inst_gen; @@ -19085,8 +19085,8 @@ static IrInstGen *ir_analyze_instruction_type(IrAnalyze *ira, IrInstSrcType *ins return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, type); } -static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira, - IrInstSrcSetEvalBranchQuota *instruction) +static Stage1AirInst *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira, + Stage1ZirInstSetEvalBranchQuota *instruction) { uint64_t new_quota; if (!ir_resolve_unsigned(ira, instruction->new_quota->child, ira->codegen->builtin_types.entry_u32, &new_quota)) @@ -19099,8 +19099,8 @@ static IrInstGen *ir_analyze_instruction_set_eval_branch_quota(IrAnalyze *ira, return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcTypeName *instruction) { - IrInstGen *type_value = instruction->type_value->child; +static Stage1AirInst *ir_analyze_instruction_type_name(IrAnalyze *ira, Stage1ZirInstTypeName *instruction) { + Stage1AirInst *type_value = instruction->type_value->child; ZigType *type_entry = ir_resolve_type(ira, type_value); if (type_is_invalid(type_entry)) return ira->codegen->invalid_inst_gen; @@ -19108,12 +19108,12 @@ static IrInstGen *ir_analyze_instruction_type_name(IrAnalyze *ira, IrInstSrcType if (!type_entry->cached_const_name_val) { type_entry->cached_const_name_val = create_const_str_lit(ira->codegen, type_bare_name(type_entry)); } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); copy_const_val(ira->codegen, result->value, type_entry->cached_const_name_val); return result; } -static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImport *instruction) { +static Stage1AirInst *ir_analyze_instruction_c_import(IrAnalyze *ira, Stage1ZirInstCImport *instruction) { Error err; AstNode *node = instruction->base.source_node; assert(node->type == NodeTypeFnCallExpr); @@ -19195,8 +19195,8 @@ static IrInstGen *ir_analyze_instruction_c_import(IrAnalyze *ira, IrInstSrcCImpo return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, child_import); } -static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInclude *instruction) { - IrInstGen *name_value = instruction->name->child; +static Stage1AirInst *ir_analyze_instruction_c_include(IrAnalyze *ira, Stage1ZirInstCInclude *instruction) { + Stage1AirInst *name_value = instruction->name->child; if (type_is_invalid(name_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -19213,8 +19213,8 @@ static IrInstGen *ir_analyze_instruction_c_include(IrAnalyze *ira, IrInstSrcCInc return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefine *instruction) { - IrInstGen *name = instruction->name->child; +static Stage1AirInst *ir_analyze_instruction_c_define(IrAnalyze *ira, Stage1ZirInstCDefine *instruction) { + Stage1AirInst *name = instruction->name->child; if (type_is_invalid(name->value->type)) return ira->codegen->invalid_inst_gen; @@ -19222,7 +19222,7 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi if (!define_name) return ira->codegen->invalid_inst_gen; - IrInstGen *value = instruction->value->child; + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; @@ -19244,8 +19244,8 @@ static IrInstGen *ir_analyze_instruction_c_define(IrAnalyze *ira, IrInstSrcCDefi return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef *instruction) { - IrInstGen *name = instruction->name->child; +static Stage1AirInst *ir_analyze_instruction_c_undef(IrAnalyze *ira, Stage1ZirInstCUndef *instruction) { + Stage1AirInst *name = instruction->name->child; if (type_is_invalid(name->value->type)) return ira->codegen->invalid_inst_gen; @@ -19262,8 +19262,8 @@ static IrInstGen *ir_analyze_instruction_c_undef(IrAnalyze *ira, IrInstSrcCUndef return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmbedFile *instruction) { - IrInstGen *name = instruction->name->child; +static Stage1AirInst *ir_analyze_instruction_embed_file(IrAnalyze *ira, Stage1ZirInstEmbedFile *instruction) { + Stage1AirInst *name = instruction->name->child; if (type_is_invalid(name->value->type)) return ira->codegen->invalid_inst_gen; @@ -19298,12 +19298,12 @@ static IrInstGen *ir_analyze_instruction_embed_file(IrAnalyze *ira, IrInstSrcEmb } } - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, nullptr); init_const_str_lit(ira->codegen, result->value, file_contents, true); return result; } -static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxchg *instruction) { +static Stage1AirInst *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, Stage1ZirInstCmpxchg *instruction) { ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->type_value->child); if (type_is_invalid(operand_type)) return ira->codegen->invalid_inst_gen; @@ -19314,26 +19314,26 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch return ira->codegen->invalid_inst_gen; } - IrInstGen *ptr = instruction->ptr->child; + Stage1AirInst *ptr = instruction->ptr->child; if (type_is_invalid(ptr->value->type)) return ira->codegen->invalid_inst_gen; // TODO let this be volatile ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false); - IrInstGen *casted_ptr = ir_implicit_cast2(ira, instruction->ptr->scope, + Stage1AirInst *casted_ptr = ir_implicit_cast2(ira, instruction->ptr->scope, instruction->ptr->source_node, ptr, ptr_type); if (type_is_invalid(casted_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *cmp_value = instruction->cmp_value->child; + Stage1AirInst *cmp_value = instruction->cmp_value->child; if (type_is_invalid(cmp_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *new_value = instruction->new_value->child; + Stage1AirInst *new_value = instruction->new_value->child; if (type_is_invalid(new_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *success_order_value = instruction->success_order_value->child; + Stage1AirInst *success_order_value = instruction->success_order_value->child; if (type_is_invalid(success_order_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -19341,7 +19341,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch if (!ir_resolve_atomic_order(ira, success_order_value, &success_order)) return ira->codegen->invalid_inst_gen; - IrInstGen *failure_order_value = instruction->failure_order_value->child; + Stage1AirInst *failure_order_value = instruction->failure_order_value->child; if (type_is_invalid(failure_order_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -19349,12 +19349,12 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch if (!ir_resolve_atomic_order(ira, failure_order_value, &failure_order)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_cmp_value = ir_implicit_cast2(ira, instruction->cmp_value->scope, + Stage1AirInst *casted_cmp_value = ir_implicit_cast2(ira, instruction->cmp_value->scope, instruction->cmp_value->source_node, cmp_value, operand_type); if (type_is_invalid(casted_cmp_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_new_value = ir_implicit_cast2(ira, instruction->new_value->scope, + Stage1AirInst *casted_new_value = ir_implicit_cast2(ira, instruction->new_value->scope, instruction->new_value->source_node, new_value, operand_type); if (type_is_invalid(casted_new_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -19387,7 +19387,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch case OnePossibleValueInvalid: return ira->codegen->invalid_inst_gen; case OnePossibleValueYes: { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); set_optional_value_to_null(result->value); return result; } @@ -19414,7 +19414,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch return ira->codegen->invalid_inst_gen; bool eql = const_values_equal(ira->codegen, stored_val, expected_val); - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, result_type); if (eql) { copy_const_val(ira->codegen, stored_val, new_val); set_optional_value_to_null(result->value); @@ -19424,7 +19424,7 @@ static IrInstGen *ir_analyze_instruction_cmpxchg(IrAnalyze *ira, IrInstSrcCmpxch return result; } - IrInstGen *result_loc; + Stage1AirInst *result_loc; if (handle_is_ptr(ira->codegen, result_type)) { result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, result_type, nullptr, true, true); @@ -19568,12 +19568,12 @@ static ErrorMsg *ir_eval_reduce(IrAnalyze *ira, Scope *scope, AstNode *source_no return nullptr; } -static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce *instruction) { - IrInstGen *op_inst = instruction->op->child; +static Stage1AirInst *ir_analyze_instruction_reduce(IrAnalyze *ira, Stage1ZirInstReduce *instruction) { + Stage1AirInst *op_inst = instruction->op->child; if (type_is_invalid(op_inst->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *value_inst = instruction->value->child; + Stage1AirInst *value_inst = instruction->value->child; if (type_is_invalid(value_inst->value->type)) return ira->codegen->invalid_inst_gen; @@ -19624,7 +19624,7 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce } if (instr_is_comptime(value_inst)) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, elem_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, elem_type); if (ir_eval_reduce(ira, instruction->base.scope, instruction->base.source_node, op, value_inst->value, result->value)) return ira->codegen->invalid_inst_gen; return result; @@ -19633,8 +19633,8 @@ static IrInstGen *ir_analyze_instruction_reduce(IrAnalyze *ira, IrInstSrcReduce return ir_build_reduce_gen(ira, instruction->base.scope, instruction->base.source_node, op, value_inst, elem_type); } -static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *instruction) { - IrInstGen *order_inst = instruction->order->child; +static Stage1AirInst *ir_analyze_instruction_fence(IrAnalyze *ira, Stage1ZirInstFence *instruction) { + Stage1AirInst *order_inst = instruction->order->child; if (type_is_invalid(order_inst->value->type)) return ira->codegen->invalid_inst_gen; @@ -19651,8 +19651,8 @@ static IrInstGen *ir_analyze_instruction_fence(IrAnalyze *ira, IrInstSrcFence *i return ir_build_fence_gen(ira, instruction->base.scope, instruction->base.source_node, order); } -static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTruncate *instruction) { - IrInstGen *dest_type_value = instruction->dest_type->child; +static Stage1AirInst *ir_analyze_instruction_truncate(IrAnalyze *ira, Stage1ZirInstTruncate *instruction) { + Stage1AirInst *dest_type_value = instruction->dest_type->child; ZigType *dest_type = ir_resolve_type(ira, dest_type_value); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -19664,7 +19664,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; ZigType *src_type = target->value->type; if (type_is_invalid(src_type)) return ira->codegen->invalid_inst_gen; @@ -19697,14 +19697,14 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc if (val == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type); bigint_truncate(&result->value->data.x_bigint, &val->data.x_bigint, dest_type->data.integral.bit_count, dest_type->data.integral.is_signed); return result; } if (src_type->data.integral.bit_count == 0 || dest_type->data.integral.bit_count == 0) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, dest_type); bigint_init_unsigned(&result->value->data.x_bigint, 0); return result; } @@ -19712,7 +19712,7 @@ static IrInstGen *ir_analyze_instruction_truncate(IrAnalyze *ira, IrInstSrcTrunc return ir_build_truncate_gen(ira, instruction->base.scope, instruction->base.source_node, dest_type, target); } -static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCast *instruction) { +static Stage1AirInst *ir_analyze_instruction_int_cast(IrAnalyze *ira, Stage1ZirInstIntCast *instruction) { ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -19726,7 +19726,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -19750,7 +19750,7 @@ static IrInstGen *ir_analyze_instruction_int_cast(IrAnalyze *ira, IrInstSrcIntCa return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type); } -static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFloatCast *instruction) { +static Stage1AirInst *ir_analyze_instruction_float_cast(IrAnalyze *ira, Stage1ZirInstFloatCast *instruction) { ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -19761,7 +19761,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -19800,7 +19800,7 @@ static IrInstGen *ir_analyze_instruction_float_cast(IrAnalyze *ira, IrInstSrcFlo return ir_analyze_widen_or_shorten(ira, instruction->base.scope, instruction->base.source_node, target, dest_type); } -static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcErrSetCast *instruction) { +static Stage1AirInst *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, Stage1ZirInstErrSetCast *instruction) { ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -19811,7 +19811,7 @@ static IrInstGen *ir_analyze_instruction_err_set_cast(IrAnalyze *ira, IrInstSrcE return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -19849,7 +19849,7 @@ static Error resolve_ptr_align(IrAnalyze *ira, ZigType *ty, uint32_t *result_ali return ErrorNone; } -static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcIntToFloat *instruction) { +static Stage1AirInst *ir_analyze_instruction_int_to_float(IrAnalyze *ira, Stage1ZirInstIntToFloat *instruction) { ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -19860,7 +19860,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -19873,7 +19873,7 @@ static IrInstGen *ir_analyze_instruction_int_to_float(IrAnalyze *ira, IrInstSrcI return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpIntToFloat); } -static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcFloatToInt *instruction) { +static Stage1AirInst *ir_analyze_instruction_float_to_int(IrAnalyze *ira, Stage1ZirInstFloatToInt *instruction) { ZigType *dest_type = ir_resolve_type(ira, instruction->dest_type->child); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -19884,7 +19884,7 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -19901,12 +19901,12 @@ static IrInstGen *ir_analyze_instruction_float_to_int(IrAnalyze *ira, IrInstSrcF return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, dest_type, CastOpFloatToInt); } -static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErrToInt *instruction) { - IrInstGen *target = instruction->target->child; +static Stage1AirInst *ir_analyze_instruction_err_to_int(IrAnalyze *ira, Stage1ZirInstErrToInt *instruction) { + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_target; + Stage1AirInst *casted_target; if (target->value->type->id == ZigTypeIdErrorSet) { casted_target = target; } else { @@ -19918,20 +19918,20 @@ static IrInstGen *ir_analyze_instruction_err_to_int(IrAnalyze *ira, IrInstSrcErr return ir_analyze_err_to_int(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->err_tag_type); } -static IrInstGen *ir_analyze_instruction_int_to_err(IrAnalyze *ira, IrInstSrcIntToErr *instruction) { - IrInstGen *target = instruction->target->child; +static Stage1AirInst *ir_analyze_instruction_int_to_err(IrAnalyze *ira, Stage1ZirInstIntToErr *instruction) { + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_target = ir_implicit_cast(ira, target, ira->codegen->err_tag_type); + Stage1AirInst *casted_target = ir_implicit_cast(ira, target, ira->codegen->err_tag_type); if (type_is_invalid(casted_target->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_int_to_err(ira, instruction->base.scope, instruction->base.source_node, casted_target, ira->codegen->builtin_types.entry_global_error_set); } -static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBoolToInt *instruction) { - IrInstGen *target = instruction->target->child; +static Stage1AirInst *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, Stage1ZirInstBoolToInt *instruction) { + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -19953,7 +19953,7 @@ static IrInstGen *ir_analyze_instruction_bool_to_int(IrAnalyze *ira, IrInstSrcBo return ir_resolve_cast(ira, instruction->base.scope, instruction->base.source_node, target, u1_type, CastOpBoolToInt); } -static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVectorType *instruction) { +static Stage1AirInst *ir_analyze_instruction_vector_type(IrAnalyze *ira, Stage1ZirInstVectorType *instruction) { uint64_t len; if (!ir_resolve_unsigned(ira, instruction->len->child, ira->codegen->builtin_types.entry_u32, &len)) return ira->codegen->invalid_inst_gen; @@ -19967,8 +19967,8 @@ static IrInstGen *ir_analyze_instruction_vector_type(IrAnalyze *ira, IrInstSrcVe return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, vector_type); } -static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node, - ZigType *scalar_type, IrInstGen *a, IrInstGen *b, IrInstGen *mask) +static Stage1AirInst *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNode *source_node, + ZigType *scalar_type, Stage1AirInst *a, Stage1AirInst *b, Stage1AirInst *mask) { Error err; src_assert(source_node && scalar_type && a && b && mask, source_node); @@ -20056,7 +20056,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod continue; int32_t v_i32 = bigint_as_signed(&mask_elem_val->data.x_bigint); uint32_t v; - IrInstGen *chosen_operand; + Stage1AirInst *chosen_operand; if (v_i32 >= 0) { v = (uint32_t)v_i32; chosen_operand = a; @@ -20091,7 +20091,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod expand_undef_array(ira->codegen, a_val); expand_undef_array(ira->codegen, b_val); - IrInstGen *result = ir_const(ira, scope, source_node, result_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, result_type); result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate(len_mask); for (uint32_t i = 0; i < mask_val->type->data.vector.len; i += 1) { ZigValue *mask_elem_val = &mask_val->data.x_array.data.s_none.elements[i]; @@ -20123,7 +20123,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod uint32_t len_min = min(len_a, len_b); uint32_t len_max = max(len_a, len_b); - IrInstGen *expand_mask = ir_const(ira, mask->scope, mask->source_node, + Stage1AirInst *expand_mask = ir_const(ira, mask->scope, mask->source_node, get_vector_type(ira->codegen, len_max, ira->codegen->builtin_types.entry_i32)); expand_mask->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate(len_max); uint32_t i = 0; @@ -20132,7 +20132,7 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod for (; i < len_max; i += 1) bigint_init_signed(&expand_mask->value->data.x_array.data.s_none.elements[i].data.x_bigint, -1); - IrInstGen *undef = ir_const_undef(ira, scope, source_node, + Stage1AirInst *undef = ir_const_undef(ira, scope, source_node, get_vector_type(ira->codegen, len_min, scalar_type)); if (len_b < len_a) { @@ -20146,34 +20146,34 @@ static IrInstGen *ir_analyze_shuffle_vector(IrAnalyze *ira, Scope *scope, AstNod result_type, a, b, mask); } -static IrInstGen *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, IrInstSrcShuffleVector *instruction) { +static Stage1AirInst *ir_analyze_instruction_shuffle_vector(IrAnalyze *ira, Stage1ZirInstShuffleVector *instruction) { ZigType *scalar_type = ir_resolve_vector_elem_type(ira, instruction->scalar_type->child); if (type_is_invalid(scalar_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *a = instruction->a->child; + Stage1AirInst *a = instruction->a->child; if (type_is_invalid(a->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *b = instruction->b->child; + Stage1AirInst *b = instruction->b->child; if (type_is_invalid(b->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *mask = instruction->mask->child; + Stage1AirInst *mask = instruction->mask->child; if (type_is_invalid(mask->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_shuffle_vector(ira, instruction->base.scope, instruction->base.source_node, scalar_type, a, b, mask); } -static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *instruction) { +static Stage1AirInst *ir_analyze_instruction_splat(IrAnalyze *ira, Stage1ZirInstSplat *instruction) { Error err; - IrInstGen *len = instruction->len->child; + Stage1AirInst *len = instruction->len->child; if (type_is_invalid(len->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *scalar = instruction->scalar->child; + Stage1AirInst *scalar = instruction->scalar->child; if (type_is_invalid(scalar->value->type)) return ira->codegen->invalid_inst_gen; @@ -20194,7 +20194,7 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i if (scalar_val->special == ConstValSpecialUndef) return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, return_type); - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type); result->value->data.x_array.data.s_none.elements = ira->codegen->pass1_arena->allocate(len_int); for (uint32_t i = 0; i < len_int; i += 1) { copy_const_val(ira->codegen, &result->value->data.x_array.data.s_none.elements[i], scalar_val); @@ -20205,14 +20205,14 @@ static IrInstGen *ir_analyze_instruction_splat(IrAnalyze *ira, IrInstSrcSplat *i return ir_build_splat_gen(ira, instruction->base.scope, instruction->base.source_node, return_type, scalar); } -static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolNot *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_instruction_bool_not(IrAnalyze *ira, Stage1ZirInstBoolNot *instruction) { + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; ZigType *bool_type = ira->codegen->builtin_types.entry_bool; - IrInstGen *casted_value = ir_implicit_cast(ira, value, bool_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, bool_type); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -20227,18 +20227,18 @@ static IrInstGen *ir_analyze_instruction_bool_not(IrAnalyze *ira, IrInstSrcBoolN return ir_build_bool_not_gen(ira, instruction->base.scope, instruction->base.source_node, casted_value); } -static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset *instruction) { +static Stage1AirInst *ir_analyze_instruction_memset(IrAnalyze *ira, Stage1ZirInstMemset *instruction) { Error err; - IrInstGen *dest_ptr = instruction->dest_ptr->child; + Stage1AirInst *dest_ptr = instruction->dest_ptr->child; if (type_is_invalid(dest_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *byte_value = instruction->byte->child; + Stage1AirInst *byte_value = instruction->byte->child; if (type_is_invalid(byte_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *count_value = instruction->count->child; + Stage1AirInst *count_value = instruction->count->child; if (type_is_invalid(count_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -20258,15 +20258,15 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset ZigType *u8_ptr = get_pointer_to_type_extra(ira->codegen, u8, false, dest_is_volatile, PtrLenUnknown, dest_align, 0, 0, false); - IrInstGen *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr); + Stage1AirInst *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr); if (type_is_invalid(casted_dest_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_byte = ir_implicit_cast(ira, byte_value, u8); + Stage1AirInst *casted_byte = ir_implicit_cast(ira, byte_value, u8); if (type_is_invalid(casted_byte->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_count = ir_implicit_cast(ira, count_value, usize); + Stage1AirInst *casted_count = ir_implicit_cast(ira, count_value, usize); if (type_is_invalid(casted_count->value->type)) return ira->codegen->invalid_inst_gen; @@ -20346,18 +20346,18 @@ static IrInstGen *ir_analyze_instruction_memset(IrAnalyze *ira, IrInstSrcMemset return ir_build_memset_gen(ira, instruction->base.scope, instruction->base.source_node, casted_dest_ptr, casted_byte, casted_count); } -static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy *instruction) { +static Stage1AirInst *ir_analyze_instruction_memcpy(IrAnalyze *ira, Stage1ZirInstMemcpy *instruction) { Error err; - IrInstGen *dest_ptr = instruction->dest_ptr->child; + Stage1AirInst *dest_ptr = instruction->dest_ptr->child; if (type_is_invalid(dest_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *src_ptr = instruction->src_ptr->child; + Stage1AirInst *src_ptr = instruction->src_ptr->child; if (type_is_invalid(src_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *count_value = instruction->count->child; + Stage1AirInst *count_value = instruction->count->child; if (type_is_invalid(count_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -20391,15 +20391,15 @@ static IrInstGen *ir_analyze_instruction_memcpy(IrAnalyze *ira, IrInstSrcMemcpy ZigType *u8_ptr_const = get_pointer_to_type_extra(ira->codegen, u8, true, src_is_volatile, PtrLenUnknown, src_align, 0, 0, false); - IrInstGen *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr_mut); + Stage1AirInst *casted_dest_ptr = ir_implicit_cast(ira, dest_ptr, u8_ptr_mut); if (type_is_invalid(casted_dest_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_src_ptr = ir_implicit_cast(ira, src_ptr, u8_ptr_const); + Stage1AirInst *casted_src_ptr = ir_implicit_cast(ira, src_ptr, u8_ptr_const); if (type_is_invalid(casted_src_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_count = ir_implicit_cast(ira, count_value, usize); + Stage1AirInst *casted_count = ir_implicit_cast(ira, count_value, usize); if (type_is_invalid(casted_count->value->type)) return ira->codegen->invalid_inst_gen; @@ -20534,10 +20534,10 @@ static ZigType *get_result_loc_type(IrAnalyze *ira, ResultLoc *result_loc) { return nullptr; } -static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *instruction) { +static Stage1AirInst *ir_analyze_instruction_slice(IrAnalyze *ira, Stage1ZirInstSlice *instruction) { Error err; - IrInstGen *ptr_ptr = instruction->ptr->child; + Stage1AirInst *ptr_ptr = instruction->ptr->child; if (type_is_invalid(ptr_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -20545,16 +20545,16 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i assert(ptr_ptr_type->id == ZigTypeIdPointer); ZigType *array_type = ptr_ptr_type->data.pointer.child_type; - IrInstGen *start = instruction->start->child; + Stage1AirInst *start = instruction->start->child; if (type_is_invalid(start->value->type)) return ira->codegen->invalid_inst_gen; ZigType *usize = ira->codegen->builtin_types.entry_usize; - IrInstGen *casted_start = ir_implicit_cast(ira, start, usize); + Stage1AirInst *casted_start = ir_implicit_cast(ira, start, usize); if (type_is_invalid(casted_start->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *end; + Stage1AirInst *end; if (instruction->end) { end = instruction->end->child; if (type_is_invalid(end->value->type)) @@ -20626,10 +20626,10 @@ static IrInstGen *ir_analyze_instruction_slice(IrAnalyze *ira, IrInstSrcSlice *i ZigValue *sentinel_val = nullptr; if (instruction->sentinel) { - IrInstGen *uncasted_sentinel = instruction->sentinel->child; + Stage1AirInst *uncasted_sentinel = instruction->sentinel->child; if (type_is_invalid(uncasted_sentinel->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *sentinel = ir_implicit_cast(ira, uncasted_sentinel, elem_type); + Stage1AirInst *sentinel = ir_implicit_cast(ira, uncasted_sentinel, elem_type); if (type_is_invalid(sentinel->value->type)) return ira->codegen->invalid_inst_gen; sentinel_val = ir_resolve_const(ira, sentinel, UndefBad); @@ -20990,7 +20990,7 @@ done_with_return_type: } exit_check_sentinel: - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type); ZigValue *ptr_val; if (return_type->id == ZigTypeIdPointer) { @@ -21061,7 +21061,7 @@ done_with_return_type: } if (generate_non_null_assert) { - IrInstGen *ptr_val = ir_get_deref(ira, instruction->base.scope, + Stage1AirInst *ptr_val = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, ptr_ptr, nullptr); if (type_is_invalid(ptr_val->value->type)) @@ -21070,7 +21070,7 @@ done_with_return_type: ir_build_assert_non_null(ira, instruction->base.scope, instruction->base.source_node, ptr_val); } - IrInstGen *result_loc = nullptr; + Stage1AirInst *result_loc = nullptr; if (return_type->id != ZigTypeIdPointer) { result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, @@ -21086,9 +21086,9 @@ done_with_return_type: return ira->codegen->invalid_inst_gen; } - IrInstGen *dummy_value = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type); + Stage1AirInst *dummy_value = ir_const(ira, instruction->base.scope, instruction->base.source_node, return_type); dummy_value->value->special = ConstValSpecialRuntime; - IrInstGen *dummy_result = ir_implicit_cast2(ira, + Stage1AirInst *dummy_result = ir_implicit_cast2(ira, instruction->base.scope, instruction->base.source_node, dummy_value, result_loc->value->type->data.pointer.child_type); if (type_is_invalid(dummy_result->value->type)) @@ -21100,7 +21100,7 @@ done_with_return_type: casted_start, end, instruction->safety_check_on, result_loc, sentinel_val); } -static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasField *instruction) { +static Stage1AirInst *ir_analyze_instruction_has_field(IrAnalyze *ira, Stage1ZirInstHasField *instruction) { Error err; ZigType *container_type = ir_resolve_type(ira, instruction->container_type->child); if (type_is_invalid(container_type)) @@ -21128,7 +21128,7 @@ static IrInstGen *ir_analyze_instruction_has_field(IrAnalyze *ira, IrInstSrcHasF return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, result); } -static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInstSrcWasmMemorySize *instruction) { +static Stage1AirInst *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, Stage1ZirInstWasmMemorySize *instruction) { // TODO generate compile error for target_arch different than 32bit if (!target_is_wasm(ira->codegen->zig_target)) { ir_add_error_node(ira, instruction->base.source_node, @@ -21136,20 +21136,20 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_size(IrAnalyze *ira, IrInst return ira->codegen->invalid_inst_gen; } - IrInstGen *index = instruction->index->child; + Stage1AirInst *index = instruction->index->child; if (type_is_invalid(index->value->type)) return ira->codegen->invalid_inst_gen; ZigType *u32 = ira->codegen->builtin_types.entry_u32; - IrInstGen *casted_index = ir_implicit_cast(ira, index, u32); + Stage1AirInst *casted_index = ir_implicit_cast(ira, index, u32); if (type_is_invalid(casted_index->value->type)) return ira->codegen->invalid_inst_gen; return ir_build_wasm_memory_size_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index); } -static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInstSrcWasmMemoryGrow *instruction) { +static Stage1AirInst *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, Stage1ZirInstWasmMemoryGrow *instruction) { // TODO generate compile error for target_arch different than 32bit if (!target_is_wasm(ira->codegen->zig_target)) { ir_add_error_node(ira, instruction->base.source_node, @@ -21157,40 +21157,40 @@ static IrInstGen *ir_analyze_instruction_wasm_memory_grow(IrAnalyze *ira, IrInst return ira->codegen->invalid_inst_gen; } - IrInstGen *index = instruction->index->child; + Stage1AirInst *index = instruction->index->child; if (type_is_invalid(index->value->type)) return ira->codegen->invalid_inst_gen; ZigType *u32 = ira->codegen->builtin_types.entry_u32; - IrInstGen *casted_index = ir_implicit_cast(ira, index, u32); + Stage1AirInst *casted_index = ir_implicit_cast(ira, index, u32); if (type_is_invalid(casted_index->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *delta = instruction->delta->child; + Stage1AirInst *delta = instruction->delta->child; if (type_is_invalid(delta->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_delta = ir_implicit_cast(ira, delta, u32); + Stage1AirInst *casted_delta = ir_implicit_cast(ira, delta, u32); if (type_is_invalid(casted_delta->value->type)) return ira->codegen->invalid_inst_gen; return ir_build_wasm_memory_grow_gen(ira, instruction->base.scope, instruction->base.source_node, casted_index, casted_delta); } -static IrInstGen *ir_analyze_instruction_breakpoint(IrAnalyze *ira, IrInstSrcBreakpoint *instruction) { +static Stage1AirInst *ir_analyze_instruction_breakpoint(IrAnalyze *ira, Stage1ZirInstBreakpoint *instruction) { return ir_build_breakpoint_gen(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_return_address(IrAnalyze *ira, IrInstSrcReturnAddress *instruction) { +static Stage1AirInst *ir_analyze_instruction_return_address(IrAnalyze *ira, Stage1ZirInstReturnAddress *instruction) { return ir_build_return_address_gen(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_frame_address(IrAnalyze *ira, IrInstSrcFrameAddress *instruction) { +static Stage1AirInst *ir_analyze_instruction_frame_address(IrAnalyze *ira, Stage1ZirInstFrameAddress *instruction) { return ir_build_frame_address_gen(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcFrameHandle *instruction) { +static Stage1AirInst *ir_analyze_instruction_frame_handle(IrAnalyze *ira, Stage1ZirInstFrameHandle *instruction) { ZigFn *fn = ira->fn; src_assert(fn != nullptr, instruction->base.source_node); @@ -21204,7 +21204,7 @@ static IrInstGen *ir_analyze_instruction_frame_handle(IrAnalyze *ira, IrInstSrcF return ir_build_handle_gen(ira, instruction->base.scope, instruction->base.source_node, ptr_frame_type); } -static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFrameType *instruction) { +static Stage1AirInst *ir_analyze_instruction_frame_type(IrAnalyze *ira, Stage1ZirInstFrameType *instruction) { ZigFn *fn = ir_resolve_fn(ira, instruction->fn->child); if (fn == nullptr) return ira->codegen->invalid_inst_gen; @@ -21219,8 +21219,8 @@ static IrInstGen *ir_analyze_instruction_frame_type(IrAnalyze *ira, IrInstSrcFra return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, ty); } -static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFrameSize *instruction) { - IrInstGen *fn = instruction->fn->child; +static Stage1AirInst *ir_analyze_instruction_frame_size(IrAnalyze *ira, Stage1ZirInstFrameSize *instruction) { + Stage1AirInst *fn = instruction->fn->child; if (type_is_invalid(fn->value->type)) return ira->codegen->invalid_inst_gen; @@ -21235,13 +21235,13 @@ static IrInstGen *ir_analyze_instruction_frame_size(IrAnalyze *ira, IrInstSrcFra return ir_build_frame_size_gen(ira, instruction->base.scope, instruction->base.source_node, fn); } -static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlignOf *instruction) { +static Stage1AirInst *ir_analyze_instruction_align_of(IrAnalyze *ira, Stage1ZirInstAlignOf *instruction) { // Here we create a lazy value in order to avoid resolving the alignment of the type // immediately. This avoids false positive dependency loops such as: // const Node = struct { // field: []align(@alignOf(Node)) Node, // }; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_num_lit_int); result->value->special = ConstValSpecialLazy; LazyValueAlignOf *lazy_align_of = heap::c_allocator.create(); @@ -21256,10 +21256,10 @@ static IrInstGen *ir_analyze_instruction_align_of(IrAnalyze *ira, IrInstSrcAlign return result; } -static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOverflowOp *instruction) { +static Stage1AirInst *ir_analyze_instruction_overflow_op(IrAnalyze *ira, Stage1ZirInstOverflowOp *instruction) { Error err; - IrInstGen *type_value = instruction->type_value->child; + Stage1AirInst *type_value = instruction->type_value->child; if (type_is_invalid(type_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -21273,19 +21273,19 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv return ira->codegen->invalid_inst_gen; } - IrInstGen *op1 = instruction->op1->child; + Stage1AirInst *op1 = instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, dest_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, dest_type); if (type_is_invalid(casted_op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = instruction->op2->child; + Stage1AirInst *op2 = instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op2; + Stage1AirInst *casted_op2; if (instruction->op == IrOverflowOpShl) { ZigType *shift_amt_type = get_smallest_unsigned_int_type(ira->codegen, dest_type->data.integral.bit_count - 1); @@ -21296,7 +21296,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *result_ptr = instruction->result_ptr->child; + Stage1AirInst *result_ptr = instruction->result_ptr->child; if (type_is_invalid(result_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -21313,7 +21313,7 @@ static IrInstGen *ir_analyze_instruction_overflow_op(IrAnalyze *ira, IrInstSrcOv expected_ptr_type = get_pointer_to_type(ira->codegen, dest_type, false); } - IrInstGen *casted_result_ptr = ir_implicit_cast(ira, result_ptr, expected_ptr_type); + Stage1AirInst *casted_result_ptr = ir_implicit_cast(ira, result_ptr, expected_ptr_type); if (type_is_invalid(casted_result_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -21403,8 +21403,8 @@ static void ir_eval_mul_add(IrAnalyze *ira, ZigType *float_type, } } -static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd *instruction) { - IrInstGen *type_value = instruction->type_value->child; +static Stage1AirInst *ir_analyze_instruction_mul_add(IrAnalyze *ira, Stage1ZirInstMulAdd *instruction) { + Stage1AirInst *type_value = instruction->type_value->child; if (type_is_invalid(type_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -21420,27 +21420,27 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd return ira->codegen->invalid_inst_gen; } - IrInstGen *op1 = instruction->op1->child; + Stage1AirInst *op1 = instruction->op1->child; if (type_is_invalid(op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op1 = ir_implicit_cast(ira, op1, expr_type); + Stage1AirInst *casted_op1 = ir_implicit_cast(ira, op1, expr_type); if (type_is_invalid(casted_op1->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op2 = instruction->op2->child; + Stage1AirInst *op2 = instruction->op2->child; if (type_is_invalid(op2->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op2 = ir_implicit_cast(ira, op2, expr_type); + Stage1AirInst *casted_op2 = ir_implicit_cast(ira, op2, expr_type); if (type_is_invalid(casted_op2->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op3 = instruction->op3->child; + Stage1AirInst *op3 = instruction->op3->child; if (type_is_invalid(op3->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_op3 = ir_implicit_cast(ira, op3, expr_type); + Stage1AirInst *casted_op3 = ir_implicit_cast(ira, op3, expr_type); if (type_is_invalid(casted_op3->value->type)) return ira->codegen->invalid_inst_gen; @@ -21457,7 +21457,7 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd if (!op3_const) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, expr_type); ZigValue *out_val = result->value; if (expr_type->id == ZigTypeIdVector) { @@ -21491,12 +21491,12 @@ static IrInstGen *ir_analyze_instruction_mul_add(IrAnalyze *ira, IrInstSrcMulAdd return ir_build_mul_add_gen(ira, instruction->base.scope, instruction->base.source_node, casted_op1, casted_op2, casted_op3, expr_type); } -static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestErr *instruction) { - IrInstGen *base_ptr = instruction->base_ptr->child; +static Stage1AirInst *ir_analyze_instruction_test_err(IrAnalyze *ira, Stage1ZirInstTestErr *instruction) { + Stage1AirInst *base_ptr = instruction->base_ptr->child; if (type_is_invalid(base_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *value; + Stage1AirInst *value; if (instruction->base_ptr_is_payload) { value = base_ptr; } else { @@ -21540,8 +21540,8 @@ static IrInstGen *ir_analyze_instruction_test_err(IrAnalyze *ira, IrInstSrcTestE } } -static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool initializing) +static Stage1AirInst *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool initializing) { ZigType *ptr_type = base_ptr->value->type; @@ -21595,7 +21595,7 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo } src_assert(err_union_val->special != ConstValSpecialRuntime, source_node); - IrInstGen *result; + Stage1AirInst *result; if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_unwrap_err_code_gen(ira, scope, source_node, base_ptr, result_type); @@ -21614,15 +21614,15 @@ static IrInstGen *ir_analyze_unwrap_err_code(IrAnalyze *ira, Scope *scope, AstNo return ir_build_unwrap_err_code_gen(ira, scope, source_node, base_ptr, result_type); } -static IrInstGen *ir_analyze_instruction_unwrap_err_code(IrAnalyze *ira, IrInstSrcUnwrapErrCode *instruction) { - IrInstGen *base_ptr = instruction->err_union_ptr->child; +static Stage1AirInst *ir_analyze_instruction_unwrap_err_code(IrAnalyze *ira, Stage1ZirInstUnwrapErrCode *instruction) { + Stage1AirInst *base_ptr = instruction->err_union_ptr->child; if (type_is_invalid(base_ptr->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_unwrap_err_code(ira, instruction->base.scope, instruction->base.source_node, base_ptr, false); } -static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *base_ptr, bool safety_check_on, bool initializing) +static Stage1AirInst *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *base_ptr, bool safety_check_on, bool initializing) { ZigType *ptr_type = base_ptr->value->type; @@ -21680,7 +21680,7 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, return ira->codegen->invalid_inst_gen; } - IrInstGen *result; + Stage1AirInst *result; if (ptr_val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_unwrap_err_payload_gen(ira, scope, source_node, base_ptr, safety_check_on, initializing, result_type); @@ -21700,22 +21700,22 @@ static IrInstGen *ir_analyze_unwrap_error_payload(IrAnalyze *ira, Scope *scope, base_ptr, safety_check_on, initializing, result_type); } -static IrInstGen *ir_analyze_instruction_unwrap_err_payload(IrAnalyze *ira, - IrInstSrcUnwrapErrPayload *instruction) +static Stage1AirInst *ir_analyze_instruction_unwrap_err_payload(IrAnalyze *ira, + Stage1ZirInstUnwrapErrPayload *instruction) { assert(instruction->value->child); - IrInstGen *value = instruction->value->child; + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_unwrap_error_payload(ira, instruction->base.scope, instruction->base.source_node, value, instruction->safety_check_on, false); } -static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnProto *instruction) { +static Stage1AirInst *ir_analyze_instruction_fn_proto(IrAnalyze *ira, Stage1ZirInstFnProto *instruction) { AstNode *proto_node = instruction->base.source_node; assert(proto_node->type == NodeTypeFnProto); - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; LazyValueFnType *lazy_fn_type = heap::c_allocator.create(); @@ -21733,7 +21733,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro if (instruction->callconv_value != nullptr) { ZigType *cc_enum_type = get_builtin_type(ira->codegen, "CallingConvention"); - IrInstGen *casted_value = ir_implicit_cast(ira, instruction->callconv_value->child, cc_enum_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, instruction->callconv_value->child, cc_enum_type); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -21746,7 +21746,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro size_t param_count = proto_node->data.fn_proto.params.length; lazy_fn_type->proto_node = proto_node; - lazy_fn_type->param_types = heap::c_allocator.allocate(param_count); + lazy_fn_type->param_types = heap::c_allocator.allocate(param_count); for (size_t param_index = 0; param_index < param_count; param_index += 1) { AstNode *param_node = proto_node->data.fn_proto.params.at(param_index); @@ -21770,7 +21770,7 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro return result; } - IrInstGen *param_type_value = instruction->param_types[param_index]->child; + Stage1AirInst *param_type_value = instruction->param_types[param_index]->child; if (type_is_invalid(param_type_value->value->type)) return ira->codegen->invalid_inst_gen; if (ir_resolve_const(ira, param_type_value, LazyOk) == nullptr) @@ -21791,23 +21791,23 @@ static IrInstGen *ir_analyze_instruction_fn_proto(IrAnalyze *ira, IrInstSrcFnPro return result; } -static IrInstGen *ir_analyze_instruction_test_comptime(IrAnalyze *ira, IrInstSrcTestComptime *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_instruction_test_comptime(IrAnalyze *ira, Stage1ZirInstTestComptime *instruction) { + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; return ir_const_bool(ira, instruction->base.scope, instruction->base.source_node, instr_is_comptime(value)); } -static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, - IrInstSrcCheckSwitchProngs *instruction, bool have_underscore_prong) +static Stage1AirInst *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, + Stage1ZirInstCheckSwitchProngs *instruction, bool have_underscore_prong) { - IrInstGen *target_value = instruction->target_value->child; + Stage1AirInst *target_value = instruction->target_value->child; ZigType *switch_type = target_value->value->type; if (type_is_invalid(switch_type)) return ira->codegen->invalid_inst_gen; - ZigValue *original_value = ((IrInstSrcSwitchTarget *)(instruction->target_value))->target_value_ptr->child->value; + ZigValue *original_value = ((Stage1ZirInstSwitchTarget *)(instruction->target_value))->target_value_ptr->child->value; bool target_is_originally_union = original_value->type->id == ZigTypeIdPointer && original_value->type->data.pointer.child_type->id == ZigTypeIdUnion; @@ -21816,19 +21816,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, field_prev_uses.init(switch_type->data.enumeration.src_field_count); for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) { - IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i]; + Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i]; - IrInstGen *start_value_uncasted = range->start->child; + Stage1AirInst *start_value_uncasted = range->start->child; if (type_is_invalid(start_value_uncasted->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type); + Stage1AirInst *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type); if (type_is_invalid(start_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *end_value_uncasted = range->end->child; + Stage1AirInst *end_value_uncasted = range->end->child; if (type_is_invalid(end_value_uncasted->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type); + Stage1AirInst *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type); if (type_is_invalid(end_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -21914,19 +21914,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, AstNode **field_prev_uses = heap::c_allocator.allocate(field_prev_uses_count); for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) { - IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i]; + Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i]; - IrInstGen *start_value_uncasted = range->start->child; + Stage1AirInst *start_value_uncasted = range->start->child; if (type_is_invalid(start_value_uncasted->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type); + Stage1AirInst *start_value = ir_implicit_cast(ira, start_value_uncasted, switch_type); if (type_is_invalid(start_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *end_value_uncasted = range->end->child; + Stage1AirInst *end_value_uncasted = range->end->child; if (type_is_invalid(end_value_uncasted->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type); + Stage1AirInst *end_value = ir_implicit_cast(ira, end_value_uncasted, switch_type); if (type_is_invalid(end_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -21972,19 +21972,19 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, } else if (switch_type->id == ZigTypeIdInt) { RangeSet rs = {0}; for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) { - IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i]; + Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i]; - IrInstGen *start_value = range->start->child; + Stage1AirInst *start_value = range->start->child; if (type_is_invalid(start_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_start_value = ir_implicit_cast(ira, start_value, switch_type); + Stage1AirInst *casted_start_value = ir_implicit_cast(ira, start_value, switch_type); if (type_is_invalid(casted_start_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *end_value = range->end->child; + Stage1AirInst *end_value = range->end->child; if (type_is_invalid(end_value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_end_value = ir_implicit_cast(ira, end_value, switch_type); + Stage1AirInst *casted_end_value = ir_implicit_cast(ira, end_value, switch_type); if (type_is_invalid(casted_end_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -22030,11 +22030,11 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, int seenTrue = 0; int seenFalse = 0; for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) { - IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i]; + Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i]; - IrInstGen *value = range->start->child; + Stage1AirInst *value = range->start->child; - IrInstGen *casted_value = ir_implicit_cast(ira, value, switch_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, switch_type); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -22070,15 +22070,15 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, buf_sprintf("else prong required when switching on type '%s'", buf_ptr(&switch_type->name))); return ira->codegen->invalid_inst_gen; } else if(switch_type->id == ZigTypeIdMetaType) { - HashMap prevs; + HashMap prevs; // HashMap doubles capacity when reaching 60% capacity, // because we know the size at init we can avoid reallocation by doubling it here prevs.init(instruction->range_count * 2); for (size_t range_i = 0; range_i < instruction->range_count; range_i += 1) { - IrInstSrcCheckSwitchProngsRange *range = &instruction->ranges[range_i]; + Stage1ZirInstCheckSwitchProngsRange *range = &instruction->ranges[range_i]; - IrInstGen *value = range->start->child; - IrInstGen *casted_value = ir_implicit_cast(ira, value, switch_type); + Stage1AirInst *value = range->start->child; + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, switch_type); if (type_is_invalid(casted_value->value->type)) { prevs.deinit(); return ira->codegen->invalid_inst_gen; @@ -22103,10 +22103,10 @@ static IrInstGen *ir_analyze_instruction_check_switch_prongs(IrAnalyze *ira, return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira, - IrInstSrcCheckStatementIsVoid *instruction) +static Stage1AirInst *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira, + Stage1ZirInstCheckStatementIsVoid *instruction) { - IrInstGen *statement_value = instruction->statement_value->child; + Stage1AirInst *statement_value = instruction->statement_value->child; ZigType *statement_type = statement_value->value->type; if (type_is_invalid(statement_type)) return ira->codegen->invalid_inst_gen; @@ -22122,8 +22122,8 @@ static IrInstGen *ir_analyze_instruction_check_statement_is_void(IrAnalyze *ira, return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *instruction) { - IrInstGen *msg = instruction->msg->child; +static Stage1AirInst *ir_analyze_instruction_panic(IrAnalyze *ira, Stage1ZirInstPanic *instruction) { + Stage1AirInst *msg = instruction->msg->child; if (type_is_invalid(msg->value->type)) return ir_unreach_error(ira); @@ -22135,15 +22135,15 @@ static IrInstGen *ir_analyze_instruction_panic(IrAnalyze *ira, IrInstSrcPanic *i ZigType *u8_ptr_type = get_pointer_to_type_extra(ira->codegen, ira->codegen->builtin_types.entry_u8, true, false, PtrLenUnknown, 0, 0, 0, false); ZigType *str_type = get_slice_type(ira->codegen, u8_ptr_type); - IrInstGen *casted_msg = ir_implicit_cast(ira, msg, str_type); + Stage1AirInst *casted_msg = ir_implicit_cast(ira, msg, str_type); if (type_is_invalid(casted_msg->value->type)) return ir_unreach_error(ira); - IrInstGen *new_instruction = ir_build_panic_gen(ira, instruction->base.scope, instruction->base.source_node, casted_msg); + Stage1AirInst *new_instruction = ir_build_panic_gen(ira, instruction->base.scope, instruction->base.source_node, casted_msg); return ir_finish_anal(ira, new_instruction); } -static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t align_bytes, bool safety_check_on) { +static Stage1AirInst *ir_align_cast(IrAnalyze *ira, Stage1AirInst *target, uint32_t align_bytes, bool safety_check_on) { Error err; ZigType *target_type = target->value->type; @@ -22224,7 +22224,7 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_const(ira, target->scope, target->source_node, result_type); + Stage1AirInst *result = ir_const(ira, target->scope, target->source_node, result_type); copy_const_val(ira->codegen, result->value, val); result->value->type = result_type; return result; @@ -22237,8 +22237,8 @@ static IrInstGen *ir_align_cast(IrAnalyze *ira, IrInstGen *target, uint32_t alig } } -static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src, +static Stage1AirInst *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *ptr, AstNode *ptr_src, ZigType *dest_type, AstNode *dest_type_src, bool safety_check_on, bool keep_bigger_alignment) { Error err; @@ -22312,8 +22312,8 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou // For slices, follow the `ptr` field. if (is_slice(src_type)) { TypeStructField *ptr_field = src_type->data.structure.fields[slice_ptr_index]; - IrInstGen *ptr_ref = ir_get_ref(ira, scope, source_node, ptr, true, false); - IrInstGen *ptr_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, ptr_field, ptr_ref, src_type, false); + Stage1AirInst *ptr_ref = ir_get_ref(ira, scope, source_node, ptr, true, false); + Stage1AirInst *ptr_ptr = ir_analyze_struct_field_ptr(ira, scope, source_node, ptr_field, ptr_ref, src_type, false); ptr = ir_get_deref(ira, scope, source_node, ptr_ptr, nullptr); } @@ -22335,7 +22335,7 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou } } - IrInstGen *result; + Stage1AirInst *result; if (val->data.x_ptr.mut == ConstPtrMutInfer) { result = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on); } else { @@ -22380,10 +22380,10 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou return ira->codegen->invalid_inst_gen; } - IrInstGen *casted_ptr = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on); + Stage1AirInst *casted_ptr = ir_build_ptr_cast_gen(ira, scope, source_node, dest_type, ptr, safety_check_on); // Keep the bigger alignment, it can only help- unless the target is zero bits. - IrInstGen *result; + Stage1AirInst *result; if (keep_bigger_alignment && src_align_bytes > dest_align_bytes && type_has_bits(ira->codegen, dest_type)) { result = ir_align_cast(ira, casted_ptr, src_align_bytes, false); if (type_is_invalid(result->value->type)) @@ -22394,13 +22394,13 @@ static IrInstGen *ir_analyze_ptr_cast(IrAnalyze *ira, Scope *scope, AstNode *sou return result; } -static IrInstGen *ir_analyze_instruction_ptr_cast(IrAnalyze *ira, IrInstSrcPtrCast *instruction) { - IrInstGen *dest_type_value = instruction->dest_type->child; +static Stage1AirInst *ir_analyze_instruction_ptr_cast(IrAnalyze *ira, Stage1ZirInstPtrCast *instruction) { + Stage1AirInst *dest_type_value = instruction->dest_type->child; ZigType *dest_type = ir_resolve_type(ira, dest_type_value); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr = instruction->ptr->child; + Stage1AirInst *ptr = instruction->ptr->child; ZigType *src_type = ptr->value->type; if (type_is_invalid(src_type)) return ira->codegen->invalid_inst_gen; @@ -22762,7 +22762,7 @@ static Error buf_read_value_bytes(IrAnalyze *ira, CodeGen *codegen, AstNode *sou zig_unreachable(); } -static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *value, +static Stage1AirInst *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *value, ZigType *dest_type) { Error err; @@ -22813,7 +22813,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou if (!val) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, dest_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, dest_type); uint8_t *buf = heap::c_allocator.allocate_nonzero(src_size_bytes); buf_write_value_bytes(ira->codegen, buf, val); if ((err = buf_read_value_bytes(ira, ira->codegen, source_node, buf, result->value))) @@ -22830,7 +22830,7 @@ static IrInstGen *ir_analyze_bit_cast(IrAnalyze *ira, Scope *scope, AstNode *sou return ir_build_bit_cast_gen(ira, scope, source_node, value, dest_type); } -static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, IrInstGen *target, +static Stage1AirInst *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *source_node, Stage1AirInst *target, ZigType *ptr_type) { Error err; @@ -22838,7 +22838,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s src_assert(get_src_ptr_type(ptr_type) != nullptr, source_node); src_assert(type_has_bits(ira->codegen, ptr_type), source_node); - IrInstGen *casted_int = ir_implicit_cast(ira, target, ira->codegen->builtin_types.entry_usize); + Stage1AirInst *casted_int = ir_implicit_cast(ira, target, ira->codegen->builtin_types.entry_usize); if (type_is_invalid(casted_int->value->type)) return ira->codegen->invalid_inst_gen; @@ -22865,7 +22865,7 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s return ira->codegen->invalid_inst_gen; } - IrInstGen *result = ir_const(ira, scope, source_node, ptr_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, ptr_type); if (ptr_type->id == ZigTypeIdOptional && addr == 0) { result->value->data.x_ptr.special = ConstPtrSpecialNull; result->value->data.x_ptr.mut = ConstPtrMutComptimeConst; @@ -22881,9 +22881,9 @@ static IrInstGen *ir_analyze_int_to_ptr(IrAnalyze *ira, Scope *scope, AstNode *s return ir_build_int_to_ptr_gen(ira, scope, source_node, casted_int, ptr_type); } -static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcIntToPtr *instruction) { +static Stage1AirInst *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, Stage1ZirInstIntToPtr *instruction) { Error err; - IrInstGen *dest_type_value = instruction->dest_type->child; + Stage1AirInst *dest_type_value = instruction->dest_type->child; ZigType *dest_type = ir_resolve_type(ira, dest_type_value); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -22904,15 +22904,15 @@ static IrInstGen *ir_analyze_instruction_int_to_ptr(IrAnalyze *ira, IrInstSrcInt return ira->codegen->invalid_inst_gen; } - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_int_to_ptr(ira, instruction->base.scope, instruction->base.source_node, target, dest_type); } -static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclRef *instruction) { - IrInstGen *ref_instruction = ir_analyze_decl_ref(ira, instruction->base.scope, instruction->base.source_node, instruction->tld); +static Stage1AirInst *ir_analyze_instruction_decl_ref(IrAnalyze *ira, Stage1ZirInstDeclRef *instruction) { + Stage1AirInst *ref_instruction = ir_analyze_decl_ref(ira, instruction->base.scope, instruction->base.source_node, instruction->tld); if (type_is_invalid(ref_instruction->value->type)) { return ira->codegen->invalid_inst_gen; } @@ -22924,9 +22924,9 @@ static IrInstGen *ir_analyze_instruction_decl_ref(IrAnalyze *ira, IrInstSrcDeclR } } -static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtrToInt *instruction) { +static Stage1AirInst *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, Stage1ZirInstPtrToInt *instruction) { Error err; - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -22957,12 +22957,12 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr // Since we've already run this type trough get_src_ptr_type it is // safe to access the x_ptr fields if (val->data.x_ptr.special == ConstPtrSpecialHardCodedAddr) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize); bigint_init_unsigned(&result->value->data.x_bigint, val->data.x_ptr.data.hard_coded_addr.addr); result->value->type = usize; return result; } else if (val->data.x_ptr.special == ConstPtrSpecialNull) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, usize); bigint_init_unsigned(&result->value->data.x_bigint, 0); result->value->type = usize; return result; @@ -22972,10 +22972,10 @@ static IrInstGen *ir_analyze_instruction_ptr_to_int(IrAnalyze *ira, IrInstSrcPtr return ir_build_ptr_to_int_gen(ira, instruction->base.scope, instruction->base.source_node, target); } -static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira, - IrInstSrcPtrTypeSimple *instruction, bool is_const) +static Stage1AirInst *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira, + Stage1ZirInstPtrTypeSimple *instruction, bool is_const) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; LazyValuePtrTypeSimple *lazy_ptr_type = heap::c_allocator.create(); @@ -22990,8 +22990,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type_simple(IrAnalyze *ira, return result; } -static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrType *instruction) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); +static Stage1AirInst *ir_analyze_instruction_ptr_type(IrAnalyze *ira, Stage1ZirInstPtrType *instruction) { + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, ira->codegen->builtin_types.entry_type); result->value->special = ConstValSpecialLazy; LazyValuePtrType *lazy_ptr_type = heap::c_allocator.create(); @@ -23031,8 +23031,8 @@ static IrInstGen *ir_analyze_instruction_ptr_type(IrAnalyze *ira, IrInstSrcPtrTy return result; } -static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAlignCast *instruction) { - IrInstGen *target = instruction->target->child; +static Stage1AirInst *ir_analyze_instruction_align_cast(IrAnalyze *ira, Stage1ZirInstAlignCast *instruction) { + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; @@ -23045,20 +23045,20 @@ static IrInstGen *ir_analyze_instruction_align_cast(IrAnalyze *ira, IrInstSrcAli } uint32_t align_bytes; - IrInstGen *align_bytes_inst = instruction->align_bytes->child; + Stage1AirInst *align_bytes_inst = instruction->align_bytes->child; if (!ir_resolve_align(ira, align_bytes_inst, elem_type, &align_bytes)) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_align_cast(ira, target, align_bytes, true); + Stage1AirInst *result = ir_align_cast(ira, target, align_bytes, true); if (type_is_invalid(result->value->type)) return ira->codegen->invalid_inst_gen; return result; } -static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstSrcSetAlignStack *instruction) { +static Stage1AirInst *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, Stage1ZirInstSetAlignStack *instruction) { uint32_t align_bytes; - IrInstGen *align_bytes_inst = instruction->align_bytes->child; + Stage1AirInst *align_bytes_inst = instruction->align_bytes->child; if (!ir_resolve_align(ira, align_bytes_inst, nullptr, &align_bytes)) return ira->codegen->invalid_inst_gen; @@ -23095,15 +23095,15 @@ static IrInstGen *ir_analyze_instruction_set_align_stack(IrAnalyze *ira, IrInstS return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgType *instruction, +static Stage1AirInst *ir_analyze_instruction_arg_type(IrAnalyze *ira, Stage1ZirInstArgType *instruction, bool allow_var) { - IrInstGen *fn_type_inst = instruction->fn_type->child; + Stage1AirInst *fn_type_inst = instruction->fn_type->child; ZigType *fn_type = ir_resolve_type(ira, fn_type_inst); if (type_is_invalid(fn_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *arg_index_inst = instruction->arg_index->child; + Stage1AirInst *arg_index_inst = instruction->arg_index->child; uint64_t arg_index; if (!ir_resolve_usize(ira, arg_index_inst, &arg_index)) return ira->codegen->invalid_inst_gen; @@ -23146,7 +23146,7 @@ static IrInstGen *ir_analyze_instruction_arg_type(IrAnalyze *ira, IrInstSrcArgTy return ir_const_type(ira, instruction->base.scope, instruction->base.source_node, result_type); } -static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) { +static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, Stage1AirInst *op) { ZigType *operand_type = ir_resolve_type(ira, op); if (type_is_invalid(operand_type)) return ira->codegen->builtin_types.entry_invalid; @@ -23193,18 +23193,18 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) { return operand_type; } -static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAtomicRmw *instruction) { +static Stage1AirInst *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, Stage1ZirInstAtomicRmw *instruction) { ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child); if (type_is_invalid(operand_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr_inst = instruction->ptr->child; + Stage1AirInst *ptr_inst = instruction->ptr->child; if (type_is_invalid(ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; // TODO let this be volatile ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false); - IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); + Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); if (type_is_invalid(casted_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -23227,11 +23227,11 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto return ira->codegen->invalid_inst_gen; } - IrInstGen *operand = instruction->operand->child; + Stage1AirInst *operand = instruction->operand->child; if (type_is_invalid(operand->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_operand = ir_implicit_cast(ira, operand, operand_type); + Stage1AirInst *casted_operand = ir_implicit_cast(ira, operand, operand_type); if (type_is_invalid(casted_operand->value->type)) return ira->codegen->invalid_inst_gen; @@ -23269,7 +23269,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto if (op2_val == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *result = ir_const(ira, scope, source_node, operand_type); + Stage1AirInst *result = ir_const(ira, scope, source_node, operand_type); copy_const_val(ira->codegen, result->value, op1_val); if (op == AtomicRmwOp_xchg) { copy_const_val(ira->codegen, op1_val, op2_val); @@ -23292,7 +23292,7 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto // store op2 if op2 > op1 bin_op = IrBinOpCmpLessThan; - IrInstGen *dummy_value = ir_const(ira, scope, source_node, operand_type); + Stage1AirInst *dummy_value = ir_const(ira, scope, source_node, operand_type); msg = ir_eval_bin_op_cmp_scalar(ira, scope, source_node, op1_val, bin_op, op2_val, dummy_value->value); if (msg != nullptr) { return ira->codegen->invalid_inst_gen; @@ -23345,17 +23345,17 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto ordering, operand_type); } -static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAtomicLoad *instruction) { +static Stage1AirInst *ir_analyze_instruction_atomic_load(IrAnalyze *ira, Stage1ZirInstAtomicLoad *instruction) { ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child); if (type_is_invalid(operand_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr_inst = instruction->ptr->child; + Stage1AirInst *ptr_inst = instruction->ptr->child; if (type_is_invalid(ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, true); - IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); + Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); if (type_is_invalid(casted_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -23371,7 +23371,7 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt } if (instr_is_comptime(casted_ptr)) { - IrInstGen *result = ir_get_deref(ira, instruction->base.scope, + Stage1AirInst *result = ir_get_deref(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, nullptr); src_assert(result->value->type != nullptr, instruction->base.source_node); return result; @@ -23380,25 +23380,25 @@ static IrInstGen *ir_analyze_instruction_atomic_load(IrAnalyze *ira, IrInstSrcAt return ir_build_atomic_load_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, ordering, operand_type); } -static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcAtomicStore *instruction) { +static Stage1AirInst *ir_analyze_instruction_atomic_store(IrAnalyze *ira, Stage1ZirInstAtomicStore *instruction) { ZigType *operand_type = ir_resolve_atomic_operand_type(ira, instruction->operand_type->child); if (type_is_invalid(operand_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *ptr_inst = instruction->ptr->child; + Stage1AirInst *ptr_inst = instruction->ptr->child; if (type_is_invalid(ptr_inst->value->type)) return ira->codegen->invalid_inst_gen; ZigType *ptr_type = get_pointer_to_type(ira->codegen, operand_type, false); - IrInstGen *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); + Stage1AirInst *casted_ptr = ir_implicit_cast(ira, ptr_inst, ptr_type); if (type_is_invalid(casted_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *value = instruction->value->child; + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_value = ir_implicit_cast(ira, value, operand_type); + Stage1AirInst *casted_value = ir_implicit_cast(ira, value, operand_type); if (type_is_invalid(casted_value->value->type)) return ira->codegen->invalid_inst_gen; @@ -23425,7 +23425,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA } if (instr_is_comptime(casted_value) && instr_is_comptime(casted_ptr)) { - IrInstGen *result = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, value, false); + Stage1AirInst *result = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, value, false); result->value->type = ira->codegen->builtin_types.entry_void; return result; } @@ -23433,7 +23433,7 @@ static IrInstGen *ir_analyze_instruction_atomic_store(IrAnalyze *ira, IrInstSrcA return ir_build_atomic_store_gen(ira, instruction->base.scope, instruction->base.source_node, casted_ptr, casted_value, ordering); } -static IrInstGen *ir_analyze_instruction_save_err_ret_addr(IrAnalyze *ira, IrInstSrcSaveErrRetAddr *instruction) { +static Stage1AirInst *ir_analyze_instruction_save_err_ret_addr(IrAnalyze *ira, Stage1ZirInstSaveErrRetAddr *instruction) { return ir_build_save_err_ret_addr_gen(ira, instruction->base.scope, instruction->base.source_node); } @@ -23660,8 +23660,8 @@ static ErrorMsg *ir_eval_float_op(IrAnalyze *ira, Scope *scope, AstNode *source_ return nullptr; } -static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloatOp *instruction) { - IrInstGen *operand = instruction->operand->child; +static Stage1AirInst *ir_analyze_instruction_float_op(IrAnalyze *ira, Stage1ZirInstFloatOp *instruction) { + Stage1AirInst *operand = instruction->operand->child; ZigType *operand_type = operand->value->type; if (type_is_invalid(operand_type)) return ira->codegen->invalid_inst_gen; @@ -23683,7 +23683,7 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat if (operand_val->special == ConstValSpecialUndef) return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, operand_type); - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, operand_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, operand_type); ZigValue *out_val = result->value; if (operand_type->id == ZigTypeIdVector) { @@ -23722,14 +23722,14 @@ static IrInstGen *ir_analyze_instruction_float_op(IrAnalyze *ira, IrInstSrcFloat return ir_build_float_op_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->fn_id, operand_type); } -static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *instruction) { +static Stage1AirInst *ir_analyze_instruction_bswap(IrAnalyze *ira, Stage1ZirInstBswap *instruction) { Error err; ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child); if (type_is_invalid(int_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *uncasted_op = instruction->op->child; + Stage1AirInst *uncasted_op = instruction->op->child; if (type_is_invalid(uncasted_op->value->type)) return ira->codegen->invalid_inst_gen; @@ -23751,7 +23751,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i bool is_vector = (vector_len != UINT32_MAX); ZigType *op_type = is_vector ? get_vector_type(ira->codegen, vector_len, int_type) : int_type; - IrInstGen *op = ir_implicit_cast(ira, uncasted_op, op_type); + Stage1AirInst *op = ir_implicit_cast(ira, uncasted_op, op_type); if (type_is_invalid(op->value->type)) return ira->codegen->invalid_inst_gen; @@ -23772,7 +23772,7 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i if (val->special == ConstValSpecialUndef) return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, op_type); - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, op_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, op_type); const size_t buf_size = int_type->data.integral.bit_count / 8; uint8_t *buf = heap::c_allocator.allocate_nonzero(buf_size); if (is_vector) { @@ -23808,17 +23808,17 @@ static IrInstGen *ir_analyze_instruction_bswap(IrAnalyze *ira, IrInstSrcBswap *i return ir_build_bswap_gen(ira, instruction->base.scope, instruction->base.source_node, op_type, op); } -static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBitReverse *instruction) { +static Stage1AirInst *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, Stage1ZirInstBitReverse *instruction) { ZigType *int_type = ir_resolve_int_type(ira, instruction->type->child); if (type_is_invalid(int_type)) return ira->codegen->invalid_inst_gen; - IrInstGen *op = ir_implicit_cast(ira, instruction->op->child, int_type); + Stage1AirInst *op = ir_implicit_cast(ira, instruction->op->child, int_type); if (type_is_invalid(op->value->type)) return ira->codegen->invalid_inst_gen; if (int_type->data.integral.bit_count == 0) { - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type); bigint_init_unsigned(&result->value->data.x_bigint, 0); return result; } @@ -23830,7 +23830,7 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi if (val->special == ConstValSpecialUndef) return ir_const_undef(ira, instruction->base.scope, instruction->base.source_node, int_type); - IrInstGen *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type); + Stage1AirInst *result = ir_const(ira, instruction->base.scope, instruction->base.source_node, int_type); size_t num_bits = int_type->data.integral.bit_count; size_t buf_size = (num_bits + 7) / 8; uint8_t *comptime_buf = heap::c_allocator.allocate_nonzero(buf_size); @@ -23863,17 +23863,17 @@ static IrInstGen *ir_analyze_instruction_bit_reverse(IrAnalyze *ira, IrInstSrcBi } -static IrInstGen *ir_analyze_instruction_enum_to_int(IrAnalyze *ira, IrInstSrcEnumToInt *instruction) { - IrInstGen *target = instruction->target->child; +static Stage1AirInst *ir_analyze_instruction_enum_to_int(IrAnalyze *ira, Stage1ZirInstEnumToInt *instruction) { + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_enum_to_int(ira, instruction->base.scope, instruction->base.source_node, target); } -static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIntToEnum *instruction) { +static Stage1AirInst *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, Stage1ZirInstIntToEnum *instruction) { Error err; - IrInstGen *dest_type_value = instruction->dest_type->child; + Stage1AirInst *dest_type_value = instruction->dest_type->child; ZigType *dest_type = ir_resolve_type(ira, dest_type_value); if (type_is_invalid(dest_type)) return ira->codegen->invalid_inst_gen; @@ -23889,24 +23889,24 @@ static IrInstGen *ir_analyze_instruction_int_to_enum(IrAnalyze *ira, IrInstSrcIn ZigType *tag_type = dest_type->data.enumeration.tag_int_type; - IrInstGen *target = instruction->target->child; + Stage1AirInst *target = instruction->target->child; if (type_is_invalid(target->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *casted_target = ir_implicit_cast(ira, target, tag_type); + Stage1AirInst *casted_target = ir_implicit_cast(ira, target, tag_type); if (type_is_invalid(casted_target->value->type)) return ira->codegen->invalid_inst_gen; return ir_analyze_int_to_enum(ira, instruction->base.scope, instruction->base.source_node, casted_target, dest_type); } -static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrInstSrcCheckRuntimeScope *instruction) { - IrInstGen *block_comptime_inst = instruction->scope_is_comptime->child; +static Stage1AirInst *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, Stage1ZirInstCheckRuntimeScope *instruction) { + Stage1AirInst *block_comptime_inst = instruction->scope_is_comptime->child; bool scope_is_comptime; if (!ir_resolve_bool(ira, block_comptime_inst, &scope_is_comptime)) return ira->codegen->invalid_inst_gen; - IrInstGen *is_comptime_inst = instruction->is_comptime->child; + Stage1AirInst *is_comptime_inst = instruction->is_comptime->child; bool is_comptime; if (!ir_resolve_bool(ira, is_comptime_inst, &is_comptime)) return ira->codegen->invalid_inst_gen; @@ -23922,7 +23922,7 @@ static IrInstGen *ir_analyze_instruction_check_runtime_scope(IrAnalyze *ira, IrI return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_has_decl(IrAnalyze *ira, IrInstSrcHasDecl *instruction) { +static Stage1AirInst *ir_analyze_instruction_has_decl(IrAnalyze *ira, Stage1ZirInstHasDecl *instruction) { ZigType *container_type = ir_resolve_type(ira, instruction->container->child); if (type_is_invalid(container_type)) return ira->codegen->invalid_inst_gen; @@ -23965,7 +23965,7 @@ static void populate_invalid_variable_in_scope(CodeGen *g, Scope *scope, AstNode scope_decls->decl_table.put(var_name, &tld_var->base); } -static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInstSrcUndeclaredIdent *instruction) { +static Stage1AirInst *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, Stage1ZirInstUndeclaredIdent *instruction) { // put a variable of same name with invalid type in global scope // so that future references to this same name will find a variable with an invalid type populate_invalid_variable_in_scope(ira->codegen, instruction->base.scope, @@ -23975,13 +23975,13 @@ static IrInstGen *ir_analyze_instruction_undeclared_ident(IrAnalyze *ira, IrInst return ira->codegen->invalid_inst_gen; } -static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndExpr *instruction) { - IrInstGen *value = instruction->value->child; +static Stage1AirInst *ir_analyze_instruction_end_expr(IrAnalyze *ira, Stage1ZirInstEndExpr *instruction) { + Stage1AirInst *value = instruction->value->child; if (type_is_invalid(value->value->type)) return ira->codegen->invalid_inst_gen; bool was_written = instruction->result_loc->written; - IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, + Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, value->value->type, value, false, true); if (result_loc != nullptr) { if (type_is_invalid(result_loc->value->type)) @@ -23990,7 +23990,7 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx return result_loc; if (!was_written || instruction->result_loc->id == ResultLocIdPeer) { - IrInstGen *store_ptr = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, result_loc, value, + Stage1AirInst *store_ptr = ir_analyze_store_ptr(ira, instruction->base.scope, instruction->base.source_node, result_loc, value, instruction->result_loc->allow_write_through_const); if (type_is_invalid(store_ptr->value->type)) { if (instruction->result_loc->id == ResultLocIdReturn && @@ -24018,8 +24018,8 @@ static IrInstGen *ir_analyze_instruction_end_expr(IrAnalyze *ira, IrInstSrcEndEx return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrcImplicitCast *instruction) { - IrInstGen *operand = instruction->operand->child; +static Stage1AirInst *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, Stage1ZirInstImplicitCast *instruction) { + Stage1AirInst *operand = instruction->operand->child; if (type_is_invalid(operand->value->type)) return operand; @@ -24030,12 +24030,12 @@ static IrInstGen *ir_analyze_instruction_implicit_cast(IrAnalyze *ira, IrInstSrc operand, dest_type); } -static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcBitCast *instruction) { - IrInstGen *operand = instruction->operand->child; +static Stage1AirInst *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, Stage1ZirInstBitCast *instruction) { + Stage1AirInst *operand = instruction->operand->child; if (type_is_invalid(operand->value->type)) return operand; - IrInstGen *result_loc = ir_resolve_result(ira, &instruction->base, + Stage1AirInst *result_loc = ir_resolve_result(ira, &instruction->base, &instruction->result_loc_bit_cast->base, operand->value->type, operand, false, true); if (result_loc != nullptr && (type_is_invalid(result_loc->value->type) || result_loc->value->type->id == ZigTypeIdUnreachable)) @@ -24050,8 +24050,8 @@ static IrInstGen *ir_analyze_instruction_bit_cast_src(IrAnalyze *ira, IrInstSrcB return ir_analyze_bit_cast(ira, instruction->base.scope, instruction->base.source_node, operand, dest_type); } -static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira, - IrInstSrcUnionInitNamedField *instruction) +static Stage1AirInst *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira, + Stage1ZirInstUnionInitNamedField *instruction) { ZigType *union_type = ir_resolve_type(ira, instruction->union_type->child); if (type_is_invalid(union_type)) @@ -24067,11 +24067,11 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira, if (field_name == nullptr) return ira->codegen->invalid_inst_gen; - IrInstGen *field_result_loc = instruction->field_result_loc->child; + Stage1AirInst *field_result_loc = instruction->field_result_loc->child; if (type_is_invalid(field_result_loc->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *result_loc = instruction->result_loc->child; + Stage1AirInst *result_loc = instruction->result_loc->child; if (type_is_invalid(result_loc->value->type)) return ira->codegen->invalid_inst_gen; @@ -24079,16 +24079,16 @@ static IrInstGen *ir_analyze_instruction_union_init_named_field(IrAnalyze *ira, union_type, field_name, field_result_loc, result_loc); } -static IrInstGen *ir_analyze_instruction_suspend_begin(IrAnalyze *ira, IrInstSrcSuspendBegin *instruction) { +static Stage1AirInst *ir_analyze_instruction_suspend_begin(IrAnalyze *ira, Stage1ZirInstSuspendBegin *instruction) { return ir_build_suspend_begin_gen(ira, instruction->base.scope, instruction->base.source_node); } -static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSrcSuspendFinish *instruction) { - IrInstGen *begin_base = instruction->begin->base.child; +static Stage1AirInst *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, Stage1ZirInstSuspendFinish *instruction) { + Stage1AirInst *begin_base = instruction->begin->base.child; if (type_is_invalid(begin_base->value->type)) return ira->codegen->invalid_inst_gen; - src_assert(begin_base->id == IrInstGenIdSuspendBegin, instruction->base.source_node); - IrInstGenSuspendBegin *begin = reinterpret_cast(begin_base); + src_assert(begin_base->id == Stage1AirInstIdSuspendBegin, instruction->base.source_node); + Stage1AirInstSuspendBegin *begin = reinterpret_cast(begin_base); ZigFn *fn_entry = ira->fn; src_assert(fn_entry != nullptr, instruction->base.source_node); @@ -24100,8 +24100,8 @@ static IrInstGen *ir_analyze_instruction_suspend_finish(IrAnalyze *ira, IrInstSr return ir_build_suspend_finish_gen(ira, instruction->base.scope, instruction->base.source_node, begin); } -static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, AstNode *source_node, - IrInstGen *frame_ptr, ZigFn **target_fn) +static Stage1AirInst *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, AstNode *source_node, + Stage1AirInst *frame_ptr, ZigFn **target_fn) { if (type_is_invalid(frame_ptr->value->type)) return ira->codegen->invalid_inst_gen; @@ -24109,7 +24109,7 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, *target_fn = nullptr; ZigType *result_type; - IrInstGen *frame; + Stage1AirInst *frame; if (frame_ptr->value->type->id == ZigTypeIdPointer && frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle && frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame) @@ -24139,19 +24139,19 @@ static IrInstGen *analyze_frame_ptr_to_anyframe_T(IrAnalyze *ira, Scope *scope, } ZigType *any_frame_type = get_any_frame_type(ira->codegen, result_type); - IrInstGen *casted_frame = ir_implicit_cast(ira, frame, any_frame_type); + Stage1AirInst *casted_frame = ir_implicit_cast(ira, frame, any_frame_type); if (type_is_invalid(casted_frame->value->type)) return ira->codegen->invalid_inst_gen; return casted_frame; } -static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *instruction) { - IrInstGen *operand = instruction->frame->child; +static Stage1AirInst *ir_analyze_instruction_await(IrAnalyze *ira, Stage1ZirInstAwait *instruction) { + Stage1AirInst *operand = instruction->frame->child; if (type_is_invalid(operand->value->type)) return ira->codegen->invalid_inst_gen; ZigFn *target_fn; - IrInstGen *frame = analyze_frame_ptr_to_anyframe_T(ira, instruction->base.scope, instruction->base.source_node, operand, &target_fn); + Stage1AirInst *frame = analyze_frame_ptr_to_anyframe_T(ira, instruction->base.scope, instruction->base.source_node, operand, &target_fn); if (type_is_invalid(frame->value->type)) return ira->codegen->invalid_inst_gen; @@ -24171,7 +24171,7 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i fn_entry->calls_or_awaits_errorable_fn = true; } - IrInstGen *result_loc; + Stage1AirInst *result_loc; if (type_has_bits(ira->codegen, result_type)) { result_loc = ir_resolve_result(ira, &instruction->base, instruction->result_loc, result_type, nullptr, true, true); @@ -24184,19 +24184,19 @@ static IrInstGen *ir_analyze_instruction_await(IrAnalyze *ira, IrInstSrcAwait *i result_loc = nullptr; } - IrInstGenAwait *result = ir_build_await_gen(ira, instruction->base.scope, instruction->base.source_node, frame, result_type, result_loc, + Stage1AirInstAwait *result = ir_build_await_gen(ira, instruction->base.scope, instruction->base.source_node, frame, result_type, result_loc, instruction->is_nosuspend); result->target_fn = target_fn; fn_entry->await_list.append(result); return ir_finish_anal(ira, &result->base); } -static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume *instruction) { - IrInstGen *frame_ptr = instruction->frame->child; +static Stage1AirInst *ir_analyze_instruction_resume(IrAnalyze *ira, Stage1ZirInstResume *instruction) { + Stage1AirInst *frame_ptr = instruction->frame->child; if (type_is_invalid(frame_ptr->value->type)) return ira->codegen->invalid_inst_gen; - IrInstGen *frame; + Stage1AirInst *frame; if (frame_ptr->value->type->id == ZigTypeIdPointer && frame_ptr->value->type->data.pointer.ptr_len == PtrLenSingle && frame_ptr->value->type->data.pointer.child_type->id == ZigTypeIdFnFrame) @@ -24208,7 +24208,7 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume } ZigType *any_frame_type = get_any_frame_type(ira->codegen, nullptr); - IrInstGen *casted_frame = ir_implicit_cast2(ira, instruction->frame->scope, + Stage1AirInst *casted_frame = ir_implicit_cast2(ira, instruction->frame->scope, instruction->frame->source_node, frame, any_frame_type); if (type_is_invalid(casted_frame->value->type)) return ira->codegen->invalid_inst_gen; @@ -24216,11 +24216,11 @@ static IrInstGen *ir_analyze_instruction_resume(IrAnalyze *ira, IrInstSrcResume return ir_build_resume_gen(ira, instruction->base.scope, instruction->base.source_node, casted_frame); } -static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSpillBegin *instruction) { +static Stage1AirInst *ir_analyze_instruction_spill_begin(IrAnalyze *ira, Stage1ZirInstSpillBegin *instruction) { if (ir_should_inline(ira->zir, instruction->base.scope)) return ir_const_void(ira, instruction->base.scope, instruction->base.source_node); - IrInstGen *operand = instruction->operand->child; + Stage1AirInst *operand = instruction->operand->child; if (type_is_invalid(operand->value->type)) return ira->codegen->invalid_inst_gen; @@ -24238,8 +24238,8 @@ static IrInstGen *ir_analyze_instruction_spill_begin(IrAnalyze *ira, IrInstSrcSp return ir_build_spill_begin_gen(ira, instruction->base.scope, instruction->base.source_node, operand, instruction->spill_id); } -static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpillEnd *instruction) { - IrInstGen *operand = instruction->begin->operand->child; +static Stage1AirInst *ir_analyze_instruction_spill_end(IrAnalyze *ira, Stage1ZirInstSpillEnd *instruction) { + Stage1AirInst *operand = instruction->begin->operand->child; if (type_is_invalid(operand->value->type)) return ira->codegen->invalid_inst_gen; @@ -24250,13 +24250,13 @@ static IrInstGen *ir_analyze_instruction_spill_end(IrAnalyze *ira, IrInstSrcSpil return operand; } - src_assert(instruction->begin->base.child->id == IrInstGenIdSpillBegin, instruction->base.source_node); - IrInstGenSpillBegin *begin = reinterpret_cast(instruction->begin->base.child); + src_assert(instruction->begin->base.child->id == Stage1AirInstIdSpillBegin, instruction->base.source_node); + Stage1AirInstSpillBegin *begin = reinterpret_cast(instruction->begin->base.child); return ir_build_spill_end_gen(ira, instruction->base.scope, instruction->base.source_node, begin, operand->value->type); } -static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instruction) { +static Stage1AirInst *ir_analyze_instruction_src(IrAnalyze *ira, Stage1ZirInstSrc *instruction) { ZigFn *fn_entry = scope_fn_entry(instruction->base.scope); if (fn_entry == nullptr) { ir_add_error_node(ira, instruction->base.source_node, buf_sprintf("@src outside function")); @@ -24318,289 +24318,289 @@ static IrInstGen *ir_analyze_instruction_src(IrAnalyze *ira, IrInstSrcSrc *instr return ir_const_move(ira, instruction->base.scope, instruction->base.source_node, result); } -static IrInstGen *ir_analyze_instruction_base(IrAnalyze *ira, IrInstSrc *instruction) { +static Stage1AirInst *ir_analyze_instruction_base(IrAnalyze *ira, Stage1ZirInst *instruction) { switch (instruction->id) { - case IrInstSrcIdInvalid: + case Stage1ZirInstIdInvalid: zig_unreachable(); - case IrInstSrcIdReturn: - return ir_analyze_instruction_return(ira, (IrInstSrcReturn *)instruction); - case IrInstSrcIdConst: - return ir_analyze_instruction_const(ira, (IrInstSrcConst *)instruction); - case IrInstSrcIdUnOp: - return ir_analyze_instruction_un_op(ira, (IrInstSrcUnOp *)instruction); - case IrInstSrcIdBinOp: - return ir_analyze_instruction_bin_op(ira, (IrInstSrcBinOp *)instruction); - case IrInstSrcIdMergeErrSets: - return ir_analyze_instruction_merge_err_sets(ira, (IrInstSrcMergeErrSets *)instruction); - case IrInstSrcIdDeclVar: - return ir_analyze_instruction_decl_var(ira, (IrInstSrcDeclVar *)instruction); - case IrInstSrcIdLoadPtr: - return ir_analyze_instruction_load_ptr(ira, (IrInstSrcLoadPtr *)instruction); - case IrInstSrcIdStorePtr: - return ir_analyze_instruction_store_ptr(ira, (IrInstSrcStorePtr *)instruction); - case IrInstSrcIdElemPtr: - return ir_analyze_instruction_elem_ptr(ira, (IrInstSrcElemPtr *)instruction); - case IrInstSrcIdVarPtr: - return ir_analyze_instruction_var_ptr(ira, (IrInstSrcVarPtr *)instruction); - case IrInstSrcIdFieldPtr: - return ir_analyze_instruction_field_ptr(ira, (IrInstSrcFieldPtr *)instruction); - case IrInstSrcIdCall: - return ir_analyze_instruction_call(ira, (IrInstSrcCall *)instruction); - case IrInstSrcIdCallArgs: - return ir_analyze_instruction_call_args(ira, (IrInstSrcCallArgs *)instruction); - case IrInstSrcIdCallExtra: - return ir_analyze_instruction_call_extra(ira, (IrInstSrcCallExtra *)instruction); - case IrInstSrcIdAsyncCallExtra: - return ir_analyze_instruction_async_call_extra(ira, (IrInstSrcAsyncCallExtra *)instruction); - case IrInstSrcIdBr: - return ir_analyze_instruction_br(ira, (IrInstSrcBr *)instruction); - case IrInstSrcIdCondBr: - return ir_analyze_instruction_cond_br(ira, (IrInstSrcCondBr *)instruction); - case IrInstSrcIdUnreachable: - return ir_analyze_instruction_unreachable(ira, (IrInstSrcUnreachable *)instruction); - case IrInstSrcIdPhi: - return ir_analyze_instruction_phi(ira, (IrInstSrcPhi *)instruction); - case IrInstSrcIdTypeOf: - return ir_analyze_instruction_typeof(ira, (IrInstSrcTypeOf *)instruction); - case IrInstSrcIdSetCold: - return ir_analyze_instruction_set_cold(ira, (IrInstSrcSetCold *)instruction); - case IrInstSrcIdSetRuntimeSafety: - return ir_analyze_instruction_set_runtime_safety(ira, (IrInstSrcSetRuntimeSafety *)instruction); - case IrInstSrcIdSetFloatMode: - return ir_analyze_instruction_set_float_mode(ira, (IrInstSrcSetFloatMode *)instruction); - case IrInstSrcIdAnyFrameType: - return ir_analyze_instruction_any_frame_type(ira, (IrInstSrcAnyFrameType *)instruction); - case IrInstSrcIdSliceType: - return ir_analyze_instruction_slice_type(ira, (IrInstSrcSliceType *)instruction); - case IrInstSrcIdAsm: - return ir_analyze_instruction_asm(ira, (IrInstSrcAsm *)instruction); - case IrInstSrcIdArrayType: - return ir_analyze_instruction_array_type(ira, (IrInstSrcArrayType *)instruction); - case IrInstSrcIdSizeOf: - return ir_analyze_instruction_size_of(ira, (IrInstSrcSizeOf *)instruction); - case IrInstSrcIdTestNonNull: - return ir_analyze_instruction_test_non_null(ira, (IrInstSrcTestNonNull *)instruction); - case IrInstSrcIdOptionalUnwrapPtr: - return ir_analyze_instruction_optional_unwrap_ptr(ira, (IrInstSrcOptionalUnwrapPtr *)instruction); - case IrInstSrcIdClz: - return ir_analyze_instruction_clz(ira, (IrInstSrcClz *)instruction); - case IrInstSrcIdCtz: - return ir_analyze_instruction_ctz(ira, (IrInstSrcCtz *)instruction); - case IrInstSrcIdPopCount: - return ir_analyze_instruction_pop_count(ira, (IrInstSrcPopCount *)instruction); - case IrInstSrcIdBswap: - return ir_analyze_instruction_bswap(ira, (IrInstSrcBswap *)instruction); - case IrInstSrcIdBitReverse: - return ir_analyze_instruction_bit_reverse(ira, (IrInstSrcBitReverse *)instruction); - case IrInstSrcIdSwitchBr: - return ir_analyze_instruction_switch_br(ira, (IrInstSrcSwitchBr *)instruction); - case IrInstSrcIdSwitchTarget: - return ir_analyze_instruction_switch_target(ira, (IrInstSrcSwitchTarget *)instruction); - case IrInstSrcIdSwitchVar: - return ir_analyze_instruction_switch_var(ira, (IrInstSrcSwitchVar *)instruction); - case IrInstSrcIdSwitchElseVar: - return ir_analyze_instruction_switch_else_var(ira, (IrInstSrcSwitchElseVar *)instruction); - case IrInstSrcIdImport: - return ir_analyze_instruction_import(ira, (IrInstSrcImport *)instruction); - case IrInstSrcIdRef: - return ir_analyze_instruction_ref(ira, (IrInstSrcRef *)instruction); - case IrInstSrcIdContainerInitList: - return ir_analyze_instruction_container_init_list(ira, (IrInstSrcContainerInitList *)instruction); - case IrInstSrcIdContainerInitFields: - return ir_analyze_instruction_container_init_fields(ira, (IrInstSrcContainerInitFields *)instruction); - case IrInstSrcIdCompileErr: - return ir_analyze_instruction_compile_err(ira, (IrInstSrcCompileErr *)instruction); - case IrInstSrcIdCompileLog: - return ir_analyze_instruction_compile_log(ira, (IrInstSrcCompileLog *)instruction); - case IrInstSrcIdErrName: - return ir_analyze_instruction_err_name(ira, (IrInstSrcErrName *)instruction); - case IrInstSrcIdTypeName: - return ir_analyze_instruction_type_name(ira, (IrInstSrcTypeName *)instruction); - case IrInstSrcIdCImport: - return ir_analyze_instruction_c_import(ira, (IrInstSrcCImport *)instruction); - case IrInstSrcIdCInclude: - return ir_analyze_instruction_c_include(ira, (IrInstSrcCInclude *)instruction); - case IrInstSrcIdCDefine: - return ir_analyze_instruction_c_define(ira, (IrInstSrcCDefine *)instruction); - case IrInstSrcIdCUndef: - return ir_analyze_instruction_c_undef(ira, (IrInstSrcCUndef *)instruction); - case IrInstSrcIdEmbedFile: - return ir_analyze_instruction_embed_file(ira, (IrInstSrcEmbedFile *)instruction); - case IrInstSrcIdCmpxchg: - return ir_analyze_instruction_cmpxchg(ira, (IrInstSrcCmpxchg *)instruction); - case IrInstSrcIdFence: - return ir_analyze_instruction_fence(ira, (IrInstSrcFence *)instruction); - case IrInstSrcIdReduce: - return ir_analyze_instruction_reduce(ira, (IrInstSrcReduce *)instruction); - case IrInstSrcIdTruncate: - return ir_analyze_instruction_truncate(ira, (IrInstSrcTruncate *)instruction); - case IrInstSrcIdIntCast: - return ir_analyze_instruction_int_cast(ira, (IrInstSrcIntCast *)instruction); - case IrInstSrcIdFloatCast: - return ir_analyze_instruction_float_cast(ira, (IrInstSrcFloatCast *)instruction); - case IrInstSrcIdErrSetCast: - return ir_analyze_instruction_err_set_cast(ira, (IrInstSrcErrSetCast *)instruction); - case IrInstSrcIdIntToFloat: - return ir_analyze_instruction_int_to_float(ira, (IrInstSrcIntToFloat *)instruction); - case IrInstSrcIdFloatToInt: - return ir_analyze_instruction_float_to_int(ira, (IrInstSrcFloatToInt *)instruction); - case IrInstSrcIdBoolToInt: - return ir_analyze_instruction_bool_to_int(ira, (IrInstSrcBoolToInt *)instruction); - case IrInstSrcIdVectorType: - return ir_analyze_instruction_vector_type(ira, (IrInstSrcVectorType *)instruction); - case IrInstSrcIdShuffleVector: - return ir_analyze_instruction_shuffle_vector(ira, (IrInstSrcShuffleVector *)instruction); - case IrInstSrcIdSplat: - return ir_analyze_instruction_splat(ira, (IrInstSrcSplat *)instruction); - case IrInstSrcIdBoolNot: - return ir_analyze_instruction_bool_not(ira, (IrInstSrcBoolNot *)instruction); - case IrInstSrcIdMemset: - return ir_analyze_instruction_memset(ira, (IrInstSrcMemset *)instruction); - case IrInstSrcIdMemcpy: - return ir_analyze_instruction_memcpy(ira, (IrInstSrcMemcpy *)instruction); - case IrInstSrcIdSlice: - return ir_analyze_instruction_slice(ira, (IrInstSrcSlice *)instruction); - case IrInstSrcIdBreakpoint: - return ir_analyze_instruction_breakpoint(ira, (IrInstSrcBreakpoint *)instruction); - case IrInstSrcIdReturnAddress: - return ir_analyze_instruction_return_address(ira, (IrInstSrcReturnAddress *)instruction); - case IrInstSrcIdFrameAddress: - return ir_analyze_instruction_frame_address(ira, (IrInstSrcFrameAddress *)instruction); - case IrInstSrcIdFrameHandle: - return ir_analyze_instruction_frame_handle(ira, (IrInstSrcFrameHandle *)instruction); - case IrInstSrcIdFrameType: - return ir_analyze_instruction_frame_type(ira, (IrInstSrcFrameType *)instruction); - case IrInstSrcIdFrameSize: - return ir_analyze_instruction_frame_size(ira, (IrInstSrcFrameSize *)instruction); - case IrInstSrcIdAlignOf: - return ir_analyze_instruction_align_of(ira, (IrInstSrcAlignOf *)instruction); - case IrInstSrcIdOverflowOp: - return ir_analyze_instruction_overflow_op(ira, (IrInstSrcOverflowOp *)instruction); - case IrInstSrcIdTestErr: - return ir_analyze_instruction_test_err(ira, (IrInstSrcTestErr *)instruction); - case IrInstSrcIdUnwrapErrCode: - return ir_analyze_instruction_unwrap_err_code(ira, (IrInstSrcUnwrapErrCode *)instruction); - case IrInstSrcIdUnwrapErrPayload: - return ir_analyze_instruction_unwrap_err_payload(ira, (IrInstSrcUnwrapErrPayload *)instruction); - case IrInstSrcIdFnProto: - return ir_analyze_instruction_fn_proto(ira, (IrInstSrcFnProto *)instruction); - case IrInstSrcIdTestComptime: - return ir_analyze_instruction_test_comptime(ira, (IrInstSrcTestComptime *)instruction); - case IrInstSrcIdCheckSwitchProngsUnderNo: - return ir_analyze_instruction_check_switch_prongs(ira, (IrInstSrcCheckSwitchProngs *)instruction, false); - case IrInstSrcIdCheckSwitchProngsUnderYes: - return ir_analyze_instruction_check_switch_prongs(ira, (IrInstSrcCheckSwitchProngs *)instruction, true); - case IrInstSrcIdCheckStatementIsVoid: - return ir_analyze_instruction_check_statement_is_void(ira, (IrInstSrcCheckStatementIsVoid *)instruction); - case IrInstSrcIdDeclRef: - return ir_analyze_instruction_decl_ref(ira, (IrInstSrcDeclRef *)instruction); - case IrInstSrcIdPanic: - return ir_analyze_instruction_panic(ira, (IrInstSrcPanic *)instruction); - case IrInstSrcIdPtrCast: - return ir_analyze_instruction_ptr_cast(ira, (IrInstSrcPtrCast *)instruction); - case IrInstSrcIdIntToPtr: - return ir_analyze_instruction_int_to_ptr(ira, (IrInstSrcIntToPtr *)instruction); - case IrInstSrcIdPtrToInt: - return ir_analyze_instruction_ptr_to_int(ira, (IrInstSrcPtrToInt *)instruction); - case IrInstSrcIdTagName: - return ir_analyze_instruction_enum_tag_name(ira, (IrInstSrcTagName *)instruction); - case IrInstSrcIdFieldParentPtr: - return ir_analyze_instruction_field_parent_ptr(ira, (IrInstSrcFieldParentPtr *)instruction); - case IrInstSrcIdOffsetOf: - return ir_analyze_instruction_offset_of(ira, (IrInstSrcOffsetOf *)instruction); - case IrInstSrcIdBitOffsetOf: - return ir_analyze_instruction_bit_offset_of(ira, (IrInstSrcBitOffsetOf *)instruction); - case IrInstSrcIdTypeInfo: - return ir_analyze_instruction_type_info(ira, (IrInstSrcTypeInfo *) instruction); - case IrInstSrcIdType: - return ir_analyze_instruction_type(ira, (IrInstSrcType *)instruction); - case IrInstSrcIdHasField: - return ir_analyze_instruction_has_field(ira, (IrInstSrcHasField *) instruction); - case IrInstSrcIdSetEvalBranchQuota: - return ir_analyze_instruction_set_eval_branch_quota(ira, (IrInstSrcSetEvalBranchQuota *)instruction); - case IrInstSrcIdPtrType: - return ir_analyze_instruction_ptr_type(ira, (IrInstSrcPtrType *)instruction); - case IrInstSrcIdPtrTypeSimple: - return ir_analyze_instruction_ptr_type_simple(ira, (IrInstSrcPtrTypeSimple *)instruction, false); - case IrInstSrcIdPtrTypeSimpleConst: - return ir_analyze_instruction_ptr_type_simple(ira, (IrInstSrcPtrTypeSimple *)instruction, true); - case IrInstSrcIdAlignCast: - return ir_analyze_instruction_align_cast(ira, (IrInstSrcAlignCast *)instruction); - case IrInstSrcIdImplicitCast: - return ir_analyze_instruction_implicit_cast(ira, (IrInstSrcImplicitCast *)instruction); - case IrInstSrcIdResolveResult: - return ir_analyze_instruction_resolve_result(ira, (IrInstSrcResolveResult *)instruction); - case IrInstSrcIdResetResult: - return ir_analyze_instruction_reset_result(ira, (IrInstSrcResetResult *)instruction); - case IrInstSrcIdSetAlignStack: - return ir_analyze_instruction_set_align_stack(ira, (IrInstSrcSetAlignStack *)instruction); - case IrInstSrcIdArgTypeAllowVarFalse: - return ir_analyze_instruction_arg_type(ira, (IrInstSrcArgType *)instruction, false); - case IrInstSrcIdArgTypeAllowVarTrue: - return ir_analyze_instruction_arg_type(ira, (IrInstSrcArgType *)instruction, true); - case IrInstSrcIdExport: - return ir_analyze_instruction_export(ira, (IrInstSrcExport *)instruction); - case IrInstSrcIdExtern: - return ir_analyze_instruction_extern(ira, (IrInstSrcExtern *)instruction); - case IrInstSrcIdErrorReturnTrace: - return ir_analyze_instruction_error_return_trace(ira, (IrInstSrcErrorReturnTrace *)instruction); - case IrInstSrcIdErrorUnion: - return ir_analyze_instruction_error_union(ira, (IrInstSrcErrorUnion *)instruction); - case IrInstSrcIdAtomicRmw: - return ir_analyze_instruction_atomic_rmw(ira, (IrInstSrcAtomicRmw *)instruction); - case IrInstSrcIdAtomicLoad: - return ir_analyze_instruction_atomic_load(ira, (IrInstSrcAtomicLoad *)instruction); - case IrInstSrcIdAtomicStore: - return ir_analyze_instruction_atomic_store(ira, (IrInstSrcAtomicStore *)instruction); - case IrInstSrcIdSaveErrRetAddr: - return ir_analyze_instruction_save_err_ret_addr(ira, (IrInstSrcSaveErrRetAddr *)instruction); - case IrInstSrcIdAddImplicitReturnType: - return ir_analyze_instruction_add_implicit_return_type(ira, (IrInstSrcAddImplicitReturnType *)instruction); - case IrInstSrcIdFloatOp: - return ir_analyze_instruction_float_op(ira, (IrInstSrcFloatOp *)instruction); - case IrInstSrcIdMulAdd: - return ir_analyze_instruction_mul_add(ira, (IrInstSrcMulAdd *)instruction); - case IrInstSrcIdIntToErr: - return ir_analyze_instruction_int_to_err(ira, (IrInstSrcIntToErr *)instruction); - case IrInstSrcIdErrToInt: - return ir_analyze_instruction_err_to_int(ira, (IrInstSrcErrToInt *)instruction); - case IrInstSrcIdIntToEnum: - return ir_analyze_instruction_int_to_enum(ira, (IrInstSrcIntToEnum *)instruction); - case IrInstSrcIdEnumToInt: - return ir_analyze_instruction_enum_to_int(ira, (IrInstSrcEnumToInt *)instruction); - case IrInstSrcIdCheckRuntimeScope: - return ir_analyze_instruction_check_runtime_scope(ira, (IrInstSrcCheckRuntimeScope *)instruction); - case IrInstSrcIdHasDecl: - return ir_analyze_instruction_has_decl(ira, (IrInstSrcHasDecl *)instruction); - case IrInstSrcIdUndeclaredIdent: - return ir_analyze_instruction_undeclared_ident(ira, (IrInstSrcUndeclaredIdent *)instruction); - case IrInstSrcIdAlloca: + case Stage1ZirInstIdReturn: + return ir_analyze_instruction_return(ira, (Stage1ZirInstReturn *)instruction); + case Stage1ZirInstIdConst: + return ir_analyze_instruction_const(ira, (Stage1ZirInstConst *)instruction); + case Stage1ZirInstIdUnOp: + return ir_analyze_instruction_un_op(ira, (Stage1ZirInstUnOp *)instruction); + case Stage1ZirInstIdBinOp: + return ir_analyze_instruction_bin_op(ira, (Stage1ZirInstBinOp *)instruction); + case Stage1ZirInstIdMergeErrSets: + return ir_analyze_instruction_merge_err_sets(ira, (Stage1ZirInstMergeErrSets *)instruction); + case Stage1ZirInstIdDeclVar: + return ir_analyze_instruction_decl_var(ira, (Stage1ZirInstDeclVar *)instruction); + case Stage1ZirInstIdLoadPtr: + return ir_analyze_instruction_load_ptr(ira, (Stage1ZirInstLoadPtr *)instruction); + case Stage1ZirInstIdStorePtr: + return ir_analyze_instruction_store_ptr(ira, (Stage1ZirInstStorePtr *)instruction); + case Stage1ZirInstIdElemPtr: + return ir_analyze_instruction_elem_ptr(ira, (Stage1ZirInstElemPtr *)instruction); + case Stage1ZirInstIdVarPtr: + return ir_analyze_instruction_var_ptr(ira, (Stage1ZirInstVarPtr *)instruction); + case Stage1ZirInstIdFieldPtr: + return ir_analyze_instruction_field_ptr(ira, (Stage1ZirInstFieldPtr *)instruction); + case Stage1ZirInstIdCall: + return ir_analyze_instruction_call(ira, (Stage1ZirInstCall *)instruction); + case Stage1ZirInstIdCallArgs: + return ir_analyze_instruction_call_args(ira, (Stage1ZirInstCallArgs *)instruction); + case Stage1ZirInstIdCallExtra: + return ir_analyze_instruction_call_extra(ira, (Stage1ZirInstCallExtra *)instruction); + case Stage1ZirInstIdAsyncCallExtra: + return ir_analyze_instruction_async_call_extra(ira, (Stage1ZirInstAsyncCallExtra *)instruction); + case Stage1ZirInstIdBr: + return ir_analyze_instruction_br(ira, (Stage1ZirInstBr *)instruction); + case Stage1ZirInstIdCondBr: + return ir_analyze_instruction_cond_br(ira, (Stage1ZirInstCondBr *)instruction); + case Stage1ZirInstIdUnreachable: + return ir_analyze_instruction_unreachable(ira, (Stage1ZirInstUnreachable *)instruction); + case Stage1ZirInstIdPhi: + return ir_analyze_instruction_phi(ira, (Stage1ZirInstPhi *)instruction); + case Stage1ZirInstIdTypeOf: + return ir_analyze_instruction_typeof(ira, (Stage1ZirInstTypeOf *)instruction); + case Stage1ZirInstIdSetCold: + return ir_analyze_instruction_set_cold(ira, (Stage1ZirInstSetCold *)instruction); + case Stage1ZirInstIdSetRuntimeSafety: + return ir_analyze_instruction_set_runtime_safety(ira, (Stage1ZirInstSetRuntimeSafety *)instruction); + case Stage1ZirInstIdSetFloatMode: + return ir_analyze_instruction_set_float_mode(ira, (Stage1ZirInstSetFloatMode *)instruction); + case Stage1ZirInstIdAnyFrameType: + return ir_analyze_instruction_any_frame_type(ira, (Stage1ZirInstAnyFrameType *)instruction); + case Stage1ZirInstIdSliceType: + return ir_analyze_instruction_slice_type(ira, (Stage1ZirInstSliceType *)instruction); + case Stage1ZirInstIdAsm: + return ir_analyze_instruction_asm(ira, (Stage1ZirInstAsm *)instruction); + case Stage1ZirInstIdArrayType: + return ir_analyze_instruction_array_type(ira, (Stage1ZirInstArrayType *)instruction); + case Stage1ZirInstIdSizeOf: + return ir_analyze_instruction_size_of(ira, (Stage1ZirInstSizeOf *)instruction); + case Stage1ZirInstIdTestNonNull: + return ir_analyze_instruction_test_non_null(ira, (Stage1ZirInstTestNonNull *)instruction); + case Stage1ZirInstIdOptionalUnwrapPtr: + return ir_analyze_instruction_optional_unwrap_ptr(ira, (Stage1ZirInstOptionalUnwrapPtr *)instruction); + case Stage1ZirInstIdClz: + return ir_analyze_instruction_clz(ira, (Stage1ZirInstClz *)instruction); + case Stage1ZirInstIdCtz: + return ir_analyze_instruction_ctz(ira, (Stage1ZirInstCtz *)instruction); + case Stage1ZirInstIdPopCount: + return ir_analyze_instruction_pop_count(ira, (Stage1ZirInstPopCount *)instruction); + case Stage1ZirInstIdBswap: + return ir_analyze_instruction_bswap(ira, (Stage1ZirInstBswap *)instruction); + case Stage1ZirInstIdBitReverse: + return ir_analyze_instruction_bit_reverse(ira, (Stage1ZirInstBitReverse *)instruction); + case Stage1ZirInstIdSwitchBr: + return ir_analyze_instruction_switch_br(ira, (Stage1ZirInstSwitchBr *)instruction); + case Stage1ZirInstIdSwitchTarget: + return ir_analyze_instruction_switch_target(ira, (Stage1ZirInstSwitchTarget *)instruction); + case Stage1ZirInstIdSwitchVar: + return ir_analyze_instruction_switch_var(ira, (Stage1ZirInstSwitchVar *)instruction); + case Stage1ZirInstIdSwitchElseVar: + return ir_analyze_instruction_switch_else_var(ira, (Stage1ZirInstSwitchElseVar *)instruction); + case Stage1ZirInstIdImport: + return ir_analyze_instruction_import(ira, (Stage1ZirInstImport *)instruction); + case Stage1ZirInstIdRef: + return ir_analyze_instruction_ref(ira, (Stage1ZirInstRef *)instruction); + case Stage1ZirInstIdContainerInitList: + return ir_analyze_instruction_container_init_list(ira, (Stage1ZirInstContainerInitList *)instruction); + case Stage1ZirInstIdContainerInitFields: + return ir_analyze_instruction_container_init_fields(ira, (Stage1ZirInstContainerInitFields *)instruction); + case Stage1ZirInstIdCompileErr: + return ir_analyze_instruction_compile_err(ira, (Stage1ZirInstCompileErr *)instruction); + case Stage1ZirInstIdCompileLog: + return ir_analyze_instruction_compile_log(ira, (Stage1ZirInstCompileLog *)instruction); + case Stage1ZirInstIdErrName: + return ir_analyze_instruction_err_name(ira, (Stage1ZirInstErrName *)instruction); + case Stage1ZirInstIdTypeName: + return ir_analyze_instruction_type_name(ira, (Stage1ZirInstTypeName *)instruction); + case Stage1ZirInstIdCImport: + return ir_analyze_instruction_c_import(ira, (Stage1ZirInstCImport *)instruction); + case Stage1ZirInstIdCInclude: + return ir_analyze_instruction_c_include(ira, (Stage1ZirInstCInclude *)instruction); + case Stage1ZirInstIdCDefine: + return ir_analyze_instruction_c_define(ira, (Stage1ZirInstCDefine *)instruction); + case Stage1ZirInstIdCUndef: + return ir_analyze_instruction_c_undef(ira, (Stage1ZirInstCUndef *)instruction); + case Stage1ZirInstIdEmbedFile: + return ir_analyze_instruction_embed_file(ira, (Stage1ZirInstEmbedFile *)instruction); + case Stage1ZirInstIdCmpxchg: + return ir_analyze_instruction_cmpxchg(ira, (Stage1ZirInstCmpxchg *)instruction); + case Stage1ZirInstIdFence: + return ir_analyze_instruction_fence(ira, (Stage1ZirInstFence *)instruction); + case Stage1ZirInstIdReduce: + return ir_analyze_instruction_reduce(ira, (Stage1ZirInstReduce *)instruction); + case Stage1ZirInstIdTruncate: + return ir_analyze_instruction_truncate(ira, (Stage1ZirInstTruncate *)instruction); + case Stage1ZirInstIdIntCast: + return ir_analyze_instruction_int_cast(ira, (Stage1ZirInstIntCast *)instruction); + case Stage1ZirInstIdFloatCast: + return ir_analyze_instruction_float_cast(ira, (Stage1ZirInstFloatCast *)instruction); + case Stage1ZirInstIdErrSetCast: + return ir_analyze_instruction_err_set_cast(ira, (Stage1ZirInstErrSetCast *)instruction); + case Stage1ZirInstIdIntToFloat: + return ir_analyze_instruction_int_to_float(ira, (Stage1ZirInstIntToFloat *)instruction); + case Stage1ZirInstIdFloatToInt: + return ir_analyze_instruction_float_to_int(ira, (Stage1ZirInstFloatToInt *)instruction); + case Stage1ZirInstIdBoolToInt: + return ir_analyze_instruction_bool_to_int(ira, (Stage1ZirInstBoolToInt *)instruction); + case Stage1ZirInstIdVectorType: + return ir_analyze_instruction_vector_type(ira, (Stage1ZirInstVectorType *)instruction); + case Stage1ZirInstIdShuffleVector: + return ir_analyze_instruction_shuffle_vector(ira, (Stage1ZirInstShuffleVector *)instruction); + case Stage1ZirInstIdSplat: + return ir_analyze_instruction_splat(ira, (Stage1ZirInstSplat *)instruction); + case Stage1ZirInstIdBoolNot: + return ir_analyze_instruction_bool_not(ira, (Stage1ZirInstBoolNot *)instruction); + case Stage1ZirInstIdMemset: + return ir_analyze_instruction_memset(ira, (Stage1ZirInstMemset *)instruction); + case Stage1ZirInstIdMemcpy: + return ir_analyze_instruction_memcpy(ira, (Stage1ZirInstMemcpy *)instruction); + case Stage1ZirInstIdSlice: + return ir_analyze_instruction_slice(ira, (Stage1ZirInstSlice *)instruction); + case Stage1ZirInstIdBreakpoint: + return ir_analyze_instruction_breakpoint(ira, (Stage1ZirInstBreakpoint *)instruction); + case Stage1ZirInstIdReturnAddress: + return ir_analyze_instruction_return_address(ira, (Stage1ZirInstReturnAddress *)instruction); + case Stage1ZirInstIdFrameAddress: + return ir_analyze_instruction_frame_address(ira, (Stage1ZirInstFrameAddress *)instruction); + case Stage1ZirInstIdFrameHandle: + return ir_analyze_instruction_frame_handle(ira, (Stage1ZirInstFrameHandle *)instruction); + case Stage1ZirInstIdFrameType: + return ir_analyze_instruction_frame_type(ira, (Stage1ZirInstFrameType *)instruction); + case Stage1ZirInstIdFrameSize: + return ir_analyze_instruction_frame_size(ira, (Stage1ZirInstFrameSize *)instruction); + case Stage1ZirInstIdAlignOf: + return ir_analyze_instruction_align_of(ira, (Stage1ZirInstAlignOf *)instruction); + case Stage1ZirInstIdOverflowOp: + return ir_analyze_instruction_overflow_op(ira, (Stage1ZirInstOverflowOp *)instruction); + case Stage1ZirInstIdTestErr: + return ir_analyze_instruction_test_err(ira, (Stage1ZirInstTestErr *)instruction); + case Stage1ZirInstIdUnwrapErrCode: + return ir_analyze_instruction_unwrap_err_code(ira, (Stage1ZirInstUnwrapErrCode *)instruction); + case Stage1ZirInstIdUnwrapErrPayload: + return ir_analyze_instruction_unwrap_err_payload(ira, (Stage1ZirInstUnwrapErrPayload *)instruction); + case Stage1ZirInstIdFnProto: + return ir_analyze_instruction_fn_proto(ira, (Stage1ZirInstFnProto *)instruction); + case Stage1ZirInstIdTestComptime: + return ir_analyze_instruction_test_comptime(ira, (Stage1ZirInstTestComptime *)instruction); + case Stage1ZirInstIdCheckSwitchProngsUnderNo: + return ir_analyze_instruction_check_switch_prongs(ira, (Stage1ZirInstCheckSwitchProngs *)instruction, false); + case Stage1ZirInstIdCheckSwitchProngsUnderYes: + return ir_analyze_instruction_check_switch_prongs(ira, (Stage1ZirInstCheckSwitchProngs *)instruction, true); + case Stage1ZirInstIdCheckStatementIsVoid: + return ir_analyze_instruction_check_statement_is_void(ira, (Stage1ZirInstCheckStatementIsVoid *)instruction); + case Stage1ZirInstIdDeclRef: + return ir_analyze_instruction_decl_ref(ira, (Stage1ZirInstDeclRef *)instruction); + case Stage1ZirInstIdPanic: + return ir_analyze_instruction_panic(ira, (Stage1ZirInstPanic *)instruction); + case Stage1ZirInstIdPtrCast: + return ir_analyze_instruction_ptr_cast(ira, (Stage1ZirInstPtrCast *)instruction); + case Stage1ZirInstIdIntToPtr: + return ir_analyze_instruction_int_to_ptr(ira, (Stage1ZirInstIntToPtr *)instruction); + case Stage1ZirInstIdPtrToInt: + return ir_analyze_instruction_ptr_to_int(ira, (Stage1ZirInstPtrToInt *)instruction); + case Stage1ZirInstIdTagName: + return ir_analyze_instruction_enum_tag_name(ira, (Stage1ZirInstTagName *)instruction); + case Stage1ZirInstIdFieldParentPtr: + return ir_analyze_instruction_field_parent_ptr(ira, (Stage1ZirInstFieldParentPtr *)instruction); + case Stage1ZirInstIdOffsetOf: + return ir_analyze_instruction_offset_of(ira, (Stage1ZirInstOffsetOf *)instruction); + case Stage1ZirInstIdBitOffsetOf: + return ir_analyze_instruction_bit_offset_of(ira, (Stage1ZirInstBitOffsetOf *)instruction); + case Stage1ZirInstIdTypeInfo: + return ir_analyze_instruction_type_info(ira, (Stage1ZirInstTypeInfo *) instruction); + case Stage1ZirInstIdType: + return ir_analyze_instruction_type(ira, (Stage1ZirInstType *)instruction); + case Stage1ZirInstIdHasField: + return ir_analyze_instruction_has_field(ira, (Stage1ZirInstHasField *) instruction); + case Stage1ZirInstIdSetEvalBranchQuota: + return ir_analyze_instruction_set_eval_branch_quota(ira, (Stage1ZirInstSetEvalBranchQuota *)instruction); + case Stage1ZirInstIdPtrType: + return ir_analyze_instruction_ptr_type(ira, (Stage1ZirInstPtrType *)instruction); + case Stage1ZirInstIdPtrTypeSimple: + return ir_analyze_instruction_ptr_type_simple(ira, (Stage1ZirInstPtrTypeSimple *)instruction, false); + case Stage1ZirInstIdPtrTypeSimpleConst: + return ir_analyze_instruction_ptr_type_simple(ira, (Stage1ZirInstPtrTypeSimple *)instruction, true); + case Stage1ZirInstIdAlignCast: + return ir_analyze_instruction_align_cast(ira, (Stage1ZirInstAlignCast *)instruction); + case Stage1ZirInstIdImplicitCast: + return ir_analyze_instruction_implicit_cast(ira, (Stage1ZirInstImplicitCast *)instruction); + case Stage1ZirInstIdResolveResult: + return ir_analyze_instruction_resolve_result(ira, (Stage1ZirInstResolveResult *)instruction); + case Stage1ZirInstIdResetResult: + return ir_analyze_instruction_reset_result(ira, (Stage1ZirInstResetResult *)instruction); + case Stage1ZirInstIdSetAlignStack: + return ir_analyze_instruction_set_align_stack(ira, (Stage1ZirInstSetAlignStack *)instruction); + case Stage1ZirInstIdArgTypeAllowVarFalse: + return ir_analyze_instruction_arg_type(ira, (Stage1ZirInstArgType *)instruction, false); + case Stage1ZirInstIdArgTypeAllowVarTrue: + return ir_analyze_instruction_arg_type(ira, (Stage1ZirInstArgType *)instruction, true); + case Stage1ZirInstIdExport: + return ir_analyze_instruction_export(ira, (Stage1ZirInstExport *)instruction); + case Stage1ZirInstIdExtern: + return ir_analyze_instruction_extern(ira, (Stage1ZirInstExtern *)instruction); + case Stage1ZirInstIdErrorReturnTrace: + return ir_analyze_instruction_error_return_trace(ira, (Stage1ZirInstErrorReturnTrace *)instruction); + case Stage1ZirInstIdErrorUnion: + return ir_analyze_instruction_error_union(ira, (Stage1ZirInstErrorUnion *)instruction); + case Stage1ZirInstIdAtomicRmw: + return ir_analyze_instruction_atomic_rmw(ira, (Stage1ZirInstAtomicRmw *)instruction); + case Stage1ZirInstIdAtomicLoad: + return ir_analyze_instruction_atomic_load(ira, (Stage1ZirInstAtomicLoad *)instruction); + case Stage1ZirInstIdAtomicStore: + return ir_analyze_instruction_atomic_store(ira, (Stage1ZirInstAtomicStore *)instruction); + case Stage1ZirInstIdSaveErrRetAddr: + return ir_analyze_instruction_save_err_ret_addr(ira, (Stage1ZirInstSaveErrRetAddr *)instruction); + case Stage1ZirInstIdAddImplicitReturnType: + return ir_analyze_instruction_add_implicit_return_type(ira, (Stage1ZirInstAddImplicitReturnType *)instruction); + case Stage1ZirInstIdFloatOp: + return ir_analyze_instruction_float_op(ira, (Stage1ZirInstFloatOp *)instruction); + case Stage1ZirInstIdMulAdd: + return ir_analyze_instruction_mul_add(ira, (Stage1ZirInstMulAdd *)instruction); + case Stage1ZirInstIdIntToErr: + return ir_analyze_instruction_int_to_err(ira, (Stage1ZirInstIntToErr *)instruction); + case Stage1ZirInstIdErrToInt: + return ir_analyze_instruction_err_to_int(ira, (Stage1ZirInstErrToInt *)instruction); + case Stage1ZirInstIdIntToEnum: + return ir_analyze_instruction_int_to_enum(ira, (Stage1ZirInstIntToEnum *)instruction); + case Stage1ZirInstIdEnumToInt: + return ir_analyze_instruction_enum_to_int(ira, (Stage1ZirInstEnumToInt *)instruction); + case Stage1ZirInstIdCheckRuntimeScope: + return ir_analyze_instruction_check_runtime_scope(ira, (Stage1ZirInstCheckRuntimeScope *)instruction); + case Stage1ZirInstIdHasDecl: + return ir_analyze_instruction_has_decl(ira, (Stage1ZirInstHasDecl *)instruction); + case Stage1ZirInstIdUndeclaredIdent: + return ir_analyze_instruction_undeclared_ident(ira, (Stage1ZirInstUndeclaredIdent *)instruction); + case Stage1ZirInstIdAlloca: return nullptr; - case IrInstSrcIdEndExpr: - return ir_analyze_instruction_end_expr(ira, (IrInstSrcEndExpr *)instruction); - case IrInstSrcIdBitCast: - return ir_analyze_instruction_bit_cast_src(ira, (IrInstSrcBitCast *)instruction); - case IrInstSrcIdUnionInitNamedField: - return ir_analyze_instruction_union_init_named_field(ira, (IrInstSrcUnionInitNamedField *)instruction); - case IrInstSrcIdSuspendBegin: - return ir_analyze_instruction_suspend_begin(ira, (IrInstSrcSuspendBegin *)instruction); - case IrInstSrcIdSuspendFinish: - return ir_analyze_instruction_suspend_finish(ira, (IrInstSrcSuspendFinish *)instruction); - case IrInstSrcIdResume: - return ir_analyze_instruction_resume(ira, (IrInstSrcResume *)instruction); - case IrInstSrcIdAwait: - return ir_analyze_instruction_await(ira, (IrInstSrcAwait *)instruction); - case IrInstSrcIdSpillBegin: - return ir_analyze_instruction_spill_begin(ira, (IrInstSrcSpillBegin *)instruction); - case IrInstSrcIdSpillEnd: - return ir_analyze_instruction_spill_end(ira, (IrInstSrcSpillEnd *)instruction); - case IrInstSrcIdWasmMemorySize: - return ir_analyze_instruction_wasm_memory_size(ira, (IrInstSrcWasmMemorySize *)instruction); - case IrInstSrcIdWasmMemoryGrow: - return ir_analyze_instruction_wasm_memory_grow(ira, (IrInstSrcWasmMemoryGrow *)instruction); - case IrInstSrcIdSrc: - return ir_analyze_instruction_src(ira, (IrInstSrcSrc *)instruction); + case Stage1ZirInstIdEndExpr: + return ir_analyze_instruction_end_expr(ira, (Stage1ZirInstEndExpr *)instruction); + case Stage1ZirInstIdBitCast: + return ir_analyze_instruction_bit_cast_src(ira, (Stage1ZirInstBitCast *)instruction); + case Stage1ZirInstIdUnionInitNamedField: + return ir_analyze_instruction_union_init_named_field(ira, (Stage1ZirInstUnionInitNamedField *)instruction); + case Stage1ZirInstIdSuspendBegin: + return ir_analyze_instruction_suspend_begin(ira, (Stage1ZirInstSuspendBegin *)instruction); + case Stage1ZirInstIdSuspendFinish: + return ir_analyze_instruction_suspend_finish(ira, (Stage1ZirInstSuspendFinish *)instruction); + case Stage1ZirInstIdResume: + return ir_analyze_instruction_resume(ira, (Stage1ZirInstResume *)instruction); + case Stage1ZirInstIdAwait: + return ir_analyze_instruction_await(ira, (Stage1ZirInstAwait *)instruction); + case Stage1ZirInstIdSpillBegin: + return ir_analyze_instruction_spill_begin(ira, (Stage1ZirInstSpillBegin *)instruction); + case Stage1ZirInstIdSpillEnd: + return ir_analyze_instruction_spill_end(ira, (Stage1ZirInstSpillEnd *)instruction); + case Stage1ZirInstIdWasmMemorySize: + return ir_analyze_instruction_wasm_memory_size(ira, (Stage1ZirInstWasmMemorySize *)instruction); + case Stage1ZirInstIdWasmMemoryGrow: + return ir_analyze_instruction_wasm_memory_grow(ira, (Stage1ZirInstWasmMemoryGrow *)instruction); + case Stage1ZirInstIdSrc: + return ir_analyze_instruction_src(ira, (Stage1ZirInstSrc *)instruction); } zig_unreachable(); } @@ -24630,7 +24630,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a ira->new_irb.exec = stage1_air; Stage1ZirBasicBlock *old_entry_bb = ira->zir->basic_block_list.at(0); - IrBasicBlockGen *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr); + Stage1AirBasicBlock *new_entry_bb = ir_get_new_bb(ira, old_entry_bb, nullptr); ira->new_irb.current_basic_block = new_entry_bb; ira->old_bb_index = 0; @@ -24638,7 +24638,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a if (result_ptr != nullptr) { assert(result_ptr->type->id == ZigTypeIdPointer); - IrInstGenConst *const_inst = ir_create_inst_noval( + Stage1AirInstConst *const_inst = ir_create_inst_noval( &ira->new_irb, stage1_air->begin_scope, stage1_air->source_node); const_inst->base.value = result_ptr; ira->return_ptr = &const_inst->base; @@ -24650,7 +24650,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a } while (ira->old_bb_index < ira->zir->basic_block_list.length) { - IrInstSrc *old_instruction = ira->zir_current_basic_block->instruction_list.at(ira->instruction_index); + Stage1ZirInst *old_instruction = ira->zir_current_basic_block->instruction_list.at(ira->instruction_index); if (old_instruction->ref_count == 0 && !ir_inst_src_has_side_effects(old_instruction)) { ira->instruction_index += 1; @@ -24664,7 +24664,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a ir_print_inst_src(codegen, stderr, old_instruction, 0); } ira->suspend_source_instr = old_instruction; - IrInstGen *new_instruction = ir_analyze_instruction_base(ira, old_instruction); + Stage1AirInst *new_instruction = ir_analyze_instruction_base(ira, old_instruction); if (new_instruction != nullptr) { src_assert(new_instruction->value->type != nullptr || new_instruction->value->type != nullptr, old_instruction->source_node); old_instruction->child = new_instruction; @@ -24732,283 +24732,283 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a return res_type; } -bool ir_inst_gen_has_side_effects(IrInstGen *instruction) { +bool ir_inst_gen_has_side_effects(Stage1AirInst *instruction) { switch (instruction->id) { - case IrInstGenIdInvalid: + case Stage1AirInstIdInvalid: zig_unreachable(); - case IrInstGenIdBr: - case IrInstGenIdCondBr: - case IrInstGenIdSwitchBr: - case IrInstGenIdDeclVar: - case IrInstGenIdStorePtr: - case IrInstGenIdVectorStoreElem: - case IrInstGenIdCall: - case IrInstGenIdReturn: - case IrInstGenIdUnreachable: - case IrInstGenIdFence: - case IrInstGenIdMemset: - case IrInstGenIdMemcpy: - case IrInstGenIdBreakpoint: - case IrInstGenIdOverflowOp: // TODO when we support multiple returns this can be side effect free - case IrInstGenIdPanic: - case IrInstGenIdSaveErrRetAddr: - case IrInstGenIdAtomicRmw: - case IrInstGenIdAtomicStore: - case IrInstGenIdCmpxchg: - case IrInstGenIdAssertZero: - case IrInstGenIdAssertNonNull: - case IrInstGenIdPtrOfArrayToSlice: - case IrInstGenIdSlice: - case IrInstGenIdOptionalWrap: - case IrInstGenIdVectorToArray: - case IrInstGenIdSuspendBegin: - case IrInstGenIdSuspendFinish: - case IrInstGenIdResume: - case IrInstGenIdAwait: - case IrInstGenIdSpillBegin: - case IrInstGenIdWasmMemoryGrow: - case IrInstGenIdExtern: + case Stage1AirInstIdBr: + case Stage1AirInstIdCondBr: + case Stage1AirInstIdSwitchBr: + case Stage1AirInstIdDeclVar: + case Stage1AirInstIdStorePtr: + case Stage1AirInstIdVectorStoreElem: + case Stage1AirInstIdCall: + case Stage1AirInstIdReturn: + case Stage1AirInstIdUnreachable: + case Stage1AirInstIdFence: + case Stage1AirInstIdMemset: + case Stage1AirInstIdMemcpy: + case Stage1AirInstIdBreakpoint: + case Stage1AirInstIdOverflowOp: // TODO when we support multiple returns this can be side effect free + case Stage1AirInstIdPanic: + case Stage1AirInstIdSaveErrRetAddr: + case Stage1AirInstIdAtomicRmw: + case Stage1AirInstIdAtomicStore: + case Stage1AirInstIdCmpxchg: + case Stage1AirInstIdAssertZero: + case Stage1AirInstIdAssertNonNull: + case Stage1AirInstIdPtrOfArrayToSlice: + case Stage1AirInstIdSlice: + case Stage1AirInstIdOptionalWrap: + case Stage1AirInstIdVectorToArray: + case Stage1AirInstIdSuspendBegin: + case Stage1AirInstIdSuspendFinish: + case Stage1AirInstIdResume: + case Stage1AirInstIdAwait: + case Stage1AirInstIdSpillBegin: + case Stage1AirInstIdWasmMemoryGrow: + case Stage1AirInstIdExtern: return true; - case IrInstGenIdPhi: - case IrInstGenIdBinOp: - case IrInstGenIdConst: - case IrInstGenIdCast: - case IrInstGenIdElemPtr: - case IrInstGenIdVarPtr: - case IrInstGenIdReturnPtr: - case IrInstGenIdStructFieldPtr: - case IrInstGenIdTestNonNull: - case IrInstGenIdClz: - case IrInstGenIdCtz: - case IrInstGenIdPopCount: - case IrInstGenIdBswap: - case IrInstGenIdBitReverse: - case IrInstGenIdUnionTag: - case IrInstGenIdTruncate: - case IrInstGenIdShuffleVector: - case IrInstGenIdSplat: - case IrInstGenIdBoolNot: - case IrInstGenIdReturnAddress: - case IrInstGenIdFrameAddress: - case IrInstGenIdFrameHandle: - case IrInstGenIdFrameSize: - case IrInstGenIdTestErr: - case IrInstGenIdPtrCast: - case IrInstGenIdBitCast: - case IrInstGenIdWidenOrShorten: - case IrInstGenIdPtrToInt: - case IrInstGenIdIntToPtr: - case IrInstGenIdIntToEnum: - case IrInstGenIdIntToErr: - case IrInstGenIdErrToInt: - case IrInstGenIdErrName: - case IrInstGenIdTagName: - case IrInstGenIdFieldParentPtr: - case IrInstGenIdAlignCast: - case IrInstGenIdErrorReturnTrace: - case IrInstGenIdFloatOp: - case IrInstGenIdMulAdd: - case IrInstGenIdAtomicLoad: - case IrInstGenIdArrayToVector: - case IrInstGenIdAlloca: - case IrInstGenIdSpillEnd: - case IrInstGenIdVectorExtractElem: - case IrInstGenIdBinaryNot: - case IrInstGenIdNegation: - case IrInstGenIdWasmMemorySize: - case IrInstGenIdReduce: + case Stage1AirInstIdPhi: + case Stage1AirInstIdBinOp: + case Stage1AirInstIdConst: + case Stage1AirInstIdCast: + case Stage1AirInstIdElemPtr: + case Stage1AirInstIdVarPtr: + case Stage1AirInstIdReturnPtr: + case Stage1AirInstIdStructFieldPtr: + case Stage1AirInstIdTestNonNull: + case Stage1AirInstIdClz: + case Stage1AirInstIdCtz: + case Stage1AirInstIdPopCount: + case Stage1AirInstIdBswap: + case Stage1AirInstIdBitReverse: + case Stage1AirInstIdUnionTag: + case Stage1AirInstIdTruncate: + case Stage1AirInstIdShuffleVector: + case Stage1AirInstIdSplat: + case Stage1AirInstIdBoolNot: + case Stage1AirInstIdReturnAddress: + case Stage1AirInstIdFrameAddress: + case Stage1AirInstIdFrameHandle: + case Stage1AirInstIdFrameSize: + case Stage1AirInstIdTestErr: + case Stage1AirInstIdPtrCast: + case Stage1AirInstIdBitCast: + case Stage1AirInstIdWidenOrShorten: + case Stage1AirInstIdPtrToInt: + case Stage1AirInstIdIntToPtr: + case Stage1AirInstIdIntToEnum: + case Stage1AirInstIdIntToErr: + case Stage1AirInstIdErrToInt: + case Stage1AirInstIdErrName: + case Stage1AirInstIdTagName: + case Stage1AirInstIdFieldParentPtr: + case Stage1AirInstIdAlignCast: + case Stage1AirInstIdErrorReturnTrace: + case Stage1AirInstIdFloatOp: + case Stage1AirInstIdMulAdd: + case Stage1AirInstIdAtomicLoad: + case Stage1AirInstIdArrayToVector: + case Stage1AirInstIdAlloca: + case Stage1AirInstIdSpillEnd: + case Stage1AirInstIdVectorExtractElem: + case Stage1AirInstIdBinaryNot: + case Stage1AirInstIdNegation: + case Stage1AirInstIdWasmMemorySize: + case Stage1AirInstIdReduce: return false; - case IrInstGenIdAsm: + case Stage1AirInstIdAsm: { - IrInstGenAsm *asm_instruction = (IrInstGenAsm *)instruction; + Stage1AirInstAsm *asm_instruction = (Stage1AirInstAsm *)instruction; return asm_instruction->has_side_effects; } - case IrInstGenIdUnwrapErrPayload: + case Stage1AirInstIdUnwrapErrPayload: { - IrInstGenUnwrapErrPayload *unwrap_err_payload_instruction = - (IrInstGenUnwrapErrPayload *)instruction; + Stage1AirInstUnwrapErrPayload *unwrap_err_payload_instruction = + (Stage1AirInstUnwrapErrPayload *)instruction; return unwrap_err_payload_instruction->safety_check_on || unwrap_err_payload_instruction->initializing; } - case IrInstGenIdUnwrapErrCode: - return reinterpret_cast(instruction)->initializing; - case IrInstGenIdUnionFieldPtr: - return reinterpret_cast(instruction)->initializing; - case IrInstGenIdOptionalUnwrapPtr: - return reinterpret_cast(instruction)->initializing; - case IrInstGenIdErrWrapPayload: - return reinterpret_cast(instruction)->result_loc != nullptr; - case IrInstGenIdErrWrapCode: - return reinterpret_cast(instruction)->result_loc != nullptr; - case IrInstGenIdLoadPtr: - return reinterpret_cast(instruction)->result_loc != nullptr; - case IrInstGenIdRef: - return reinterpret_cast(instruction)->result_loc != nullptr; + case Stage1AirInstIdUnwrapErrCode: + return reinterpret_cast(instruction)->initializing; + case Stage1AirInstIdUnionFieldPtr: + return reinterpret_cast(instruction)->initializing; + case Stage1AirInstIdOptionalUnwrapPtr: + return reinterpret_cast(instruction)->initializing; + case Stage1AirInstIdErrWrapPayload: + return reinterpret_cast(instruction)->result_loc != nullptr; + case Stage1AirInstIdErrWrapCode: + return reinterpret_cast(instruction)->result_loc != nullptr; + case Stage1AirInstIdLoadPtr: + return reinterpret_cast(instruction)->result_loc != nullptr; + case Stage1AirInstIdRef: + return reinterpret_cast(instruction)->result_loc != nullptr; } zig_unreachable(); } -bool ir_inst_src_has_side_effects(IrInstSrc *instruction) { +bool ir_inst_src_has_side_effects(Stage1ZirInst *instruction) { switch (instruction->id) { - case IrInstSrcIdInvalid: + case Stage1ZirInstIdInvalid: zig_unreachable(); - case IrInstSrcIdBr: - case IrInstSrcIdCondBr: - case IrInstSrcIdSwitchBr: - case IrInstSrcIdDeclVar: - case IrInstSrcIdStorePtr: - case IrInstSrcIdCallExtra: - case IrInstSrcIdAsyncCallExtra: - case IrInstSrcIdCall: - case IrInstSrcIdCallArgs: - case IrInstSrcIdReturn: - case IrInstSrcIdUnreachable: - case IrInstSrcIdSetCold: - case IrInstSrcIdSetRuntimeSafety: - case IrInstSrcIdSetFloatMode: - case IrInstSrcIdImport: - case IrInstSrcIdCompileErr: - case IrInstSrcIdCompileLog: - case IrInstSrcIdCImport: - case IrInstSrcIdCInclude: - case IrInstSrcIdCDefine: - case IrInstSrcIdCUndef: - case IrInstSrcIdFence: - case IrInstSrcIdMemset: - case IrInstSrcIdMemcpy: - case IrInstSrcIdBreakpoint: - case IrInstSrcIdOverflowOp: // TODO when we support multiple returns this can be side effect free - case IrInstSrcIdCheckSwitchProngsUnderNo: - case IrInstSrcIdCheckSwitchProngsUnderYes: - case IrInstSrcIdCheckStatementIsVoid: - case IrInstSrcIdCheckRuntimeScope: - case IrInstSrcIdPanic: - case IrInstSrcIdSetEvalBranchQuota: - case IrInstSrcIdPtrType: - case IrInstSrcIdPtrTypeSimple: - case IrInstSrcIdPtrTypeSimpleConst: - case IrInstSrcIdSetAlignStack: - case IrInstSrcIdExport: - case IrInstSrcIdExtern: - case IrInstSrcIdSaveErrRetAddr: - case IrInstSrcIdAddImplicitReturnType: - case IrInstSrcIdAtomicRmw: - case IrInstSrcIdAtomicStore: - case IrInstSrcIdCmpxchg: - case IrInstSrcIdUndeclaredIdent: - case IrInstSrcIdEndExpr: - case IrInstSrcIdResetResult: - case IrInstSrcIdSuspendBegin: - case IrInstSrcIdSuspendFinish: - case IrInstSrcIdResume: - case IrInstSrcIdAwait: - case IrInstSrcIdSpillBegin: - case IrInstSrcIdWasmMemoryGrow: + case Stage1ZirInstIdBr: + case Stage1ZirInstIdCondBr: + case Stage1ZirInstIdSwitchBr: + case Stage1ZirInstIdDeclVar: + case Stage1ZirInstIdStorePtr: + case Stage1ZirInstIdCallExtra: + case Stage1ZirInstIdAsyncCallExtra: + case Stage1ZirInstIdCall: + case Stage1ZirInstIdCallArgs: + case Stage1ZirInstIdReturn: + case Stage1ZirInstIdUnreachable: + case Stage1ZirInstIdSetCold: + case Stage1ZirInstIdSetRuntimeSafety: + case Stage1ZirInstIdSetFloatMode: + case Stage1ZirInstIdImport: + case Stage1ZirInstIdCompileErr: + case Stage1ZirInstIdCompileLog: + case Stage1ZirInstIdCImport: + case Stage1ZirInstIdCInclude: + case Stage1ZirInstIdCDefine: + case Stage1ZirInstIdCUndef: + case Stage1ZirInstIdFence: + case Stage1ZirInstIdMemset: + case Stage1ZirInstIdMemcpy: + case Stage1ZirInstIdBreakpoint: + case Stage1ZirInstIdOverflowOp: // TODO when we support multiple returns this can be side effect free + case Stage1ZirInstIdCheckSwitchProngsUnderNo: + case Stage1ZirInstIdCheckSwitchProngsUnderYes: + case Stage1ZirInstIdCheckStatementIsVoid: + case Stage1ZirInstIdCheckRuntimeScope: + case Stage1ZirInstIdPanic: + case Stage1ZirInstIdSetEvalBranchQuota: + case Stage1ZirInstIdPtrType: + case Stage1ZirInstIdPtrTypeSimple: + case Stage1ZirInstIdPtrTypeSimpleConst: + case Stage1ZirInstIdSetAlignStack: + case Stage1ZirInstIdExport: + case Stage1ZirInstIdExtern: + case Stage1ZirInstIdSaveErrRetAddr: + case Stage1ZirInstIdAddImplicitReturnType: + case Stage1ZirInstIdAtomicRmw: + case Stage1ZirInstIdAtomicStore: + case Stage1ZirInstIdCmpxchg: + case Stage1ZirInstIdUndeclaredIdent: + case Stage1ZirInstIdEndExpr: + case Stage1ZirInstIdResetResult: + case Stage1ZirInstIdSuspendBegin: + case Stage1ZirInstIdSuspendFinish: + case Stage1ZirInstIdResume: + case Stage1ZirInstIdAwait: + case Stage1ZirInstIdSpillBegin: + case Stage1ZirInstIdWasmMemoryGrow: return true; - case IrInstSrcIdPhi: - case IrInstSrcIdUnOp: - case IrInstSrcIdBinOp: - case IrInstSrcIdMergeErrSets: - case IrInstSrcIdLoadPtr: - case IrInstSrcIdConst: - case IrInstSrcIdContainerInitList: - case IrInstSrcIdContainerInitFields: - case IrInstSrcIdUnionInitNamedField: - case IrInstSrcIdFieldPtr: - case IrInstSrcIdElemPtr: - case IrInstSrcIdVarPtr: - case IrInstSrcIdTypeOf: - case IrInstSrcIdArrayType: - case IrInstSrcIdSliceType: - case IrInstSrcIdAnyFrameType: - case IrInstSrcIdSizeOf: - case IrInstSrcIdTestNonNull: - case IrInstSrcIdOptionalUnwrapPtr: - case IrInstSrcIdClz: - case IrInstSrcIdCtz: - case IrInstSrcIdPopCount: - case IrInstSrcIdBswap: - case IrInstSrcIdBitReverse: - case IrInstSrcIdSwitchVar: - case IrInstSrcIdSwitchElseVar: - case IrInstSrcIdSwitchTarget: - case IrInstSrcIdRef: - case IrInstSrcIdEmbedFile: - case IrInstSrcIdTruncate: - case IrInstSrcIdVectorType: - case IrInstSrcIdShuffleVector: - case IrInstSrcIdSplat: - case IrInstSrcIdBoolNot: - case IrInstSrcIdSlice: - case IrInstSrcIdAlignOf: - case IrInstSrcIdReturnAddress: - case IrInstSrcIdFrameAddress: - case IrInstSrcIdFrameHandle: - case IrInstSrcIdFrameType: - case IrInstSrcIdFrameSize: - case IrInstSrcIdTestErr: - case IrInstSrcIdFnProto: - case IrInstSrcIdTestComptime: - case IrInstSrcIdPtrCast: - case IrInstSrcIdBitCast: - case IrInstSrcIdPtrToInt: - case IrInstSrcIdIntToPtr: - case IrInstSrcIdIntToEnum: - case IrInstSrcIdIntToErr: - case IrInstSrcIdErrToInt: - case IrInstSrcIdDeclRef: - case IrInstSrcIdErrName: - case IrInstSrcIdTypeName: - case IrInstSrcIdTagName: - case IrInstSrcIdFieldParentPtr: - case IrInstSrcIdOffsetOf: - case IrInstSrcIdBitOffsetOf: - case IrInstSrcIdTypeInfo: - case IrInstSrcIdType: - case IrInstSrcIdHasField: - case IrInstSrcIdAlignCast: - case IrInstSrcIdImplicitCast: - case IrInstSrcIdResolveResult: - case IrInstSrcIdArgTypeAllowVarFalse: - case IrInstSrcIdArgTypeAllowVarTrue: - case IrInstSrcIdErrorReturnTrace: - case IrInstSrcIdErrorUnion: - case IrInstSrcIdFloatOp: - case IrInstSrcIdMulAdd: - case IrInstSrcIdAtomicLoad: - case IrInstSrcIdIntCast: - case IrInstSrcIdFloatCast: - case IrInstSrcIdErrSetCast: - case IrInstSrcIdIntToFloat: - case IrInstSrcIdFloatToInt: - case IrInstSrcIdBoolToInt: - case IrInstSrcIdEnumToInt: - case IrInstSrcIdHasDecl: - case IrInstSrcIdAlloca: - case IrInstSrcIdSpillEnd: - case IrInstSrcIdWasmMemorySize: - case IrInstSrcIdSrc: - case IrInstSrcIdReduce: + case Stage1ZirInstIdPhi: + case Stage1ZirInstIdUnOp: + case Stage1ZirInstIdBinOp: + case Stage1ZirInstIdMergeErrSets: + case Stage1ZirInstIdLoadPtr: + case Stage1ZirInstIdConst: + case Stage1ZirInstIdContainerInitList: + case Stage1ZirInstIdContainerInitFields: + case Stage1ZirInstIdUnionInitNamedField: + case Stage1ZirInstIdFieldPtr: + case Stage1ZirInstIdElemPtr: + case Stage1ZirInstIdVarPtr: + case Stage1ZirInstIdTypeOf: + case Stage1ZirInstIdArrayType: + case Stage1ZirInstIdSliceType: + case Stage1ZirInstIdAnyFrameType: + case Stage1ZirInstIdSizeOf: + case Stage1ZirInstIdTestNonNull: + case Stage1ZirInstIdOptionalUnwrapPtr: + case Stage1ZirInstIdClz: + case Stage1ZirInstIdCtz: + case Stage1ZirInstIdPopCount: + case Stage1ZirInstIdBswap: + case Stage1ZirInstIdBitReverse: + case Stage1ZirInstIdSwitchVar: + case Stage1ZirInstIdSwitchElseVar: + case Stage1ZirInstIdSwitchTarget: + case Stage1ZirInstIdRef: + case Stage1ZirInstIdEmbedFile: + case Stage1ZirInstIdTruncate: + case Stage1ZirInstIdVectorType: + case Stage1ZirInstIdShuffleVector: + case Stage1ZirInstIdSplat: + case Stage1ZirInstIdBoolNot: + case Stage1ZirInstIdSlice: + case Stage1ZirInstIdAlignOf: + case Stage1ZirInstIdReturnAddress: + case Stage1ZirInstIdFrameAddress: + case Stage1ZirInstIdFrameHandle: + case Stage1ZirInstIdFrameType: + case Stage1ZirInstIdFrameSize: + case Stage1ZirInstIdTestErr: + case Stage1ZirInstIdFnProto: + case Stage1ZirInstIdTestComptime: + case Stage1ZirInstIdPtrCast: + case Stage1ZirInstIdBitCast: + case Stage1ZirInstIdPtrToInt: + case Stage1ZirInstIdIntToPtr: + case Stage1ZirInstIdIntToEnum: + case Stage1ZirInstIdIntToErr: + case Stage1ZirInstIdErrToInt: + case Stage1ZirInstIdDeclRef: + case Stage1ZirInstIdErrName: + case Stage1ZirInstIdTypeName: + case Stage1ZirInstIdTagName: + case Stage1ZirInstIdFieldParentPtr: + case Stage1ZirInstIdOffsetOf: + case Stage1ZirInstIdBitOffsetOf: + case Stage1ZirInstIdTypeInfo: + case Stage1ZirInstIdType: + case Stage1ZirInstIdHasField: + case Stage1ZirInstIdAlignCast: + case Stage1ZirInstIdImplicitCast: + case Stage1ZirInstIdResolveResult: + case Stage1ZirInstIdArgTypeAllowVarFalse: + case Stage1ZirInstIdArgTypeAllowVarTrue: + case Stage1ZirInstIdErrorReturnTrace: + case Stage1ZirInstIdErrorUnion: + case Stage1ZirInstIdFloatOp: + case Stage1ZirInstIdMulAdd: + case Stage1ZirInstIdAtomicLoad: + case Stage1ZirInstIdIntCast: + case Stage1ZirInstIdFloatCast: + case Stage1ZirInstIdErrSetCast: + case Stage1ZirInstIdIntToFloat: + case Stage1ZirInstIdFloatToInt: + case Stage1ZirInstIdBoolToInt: + case Stage1ZirInstIdEnumToInt: + case Stage1ZirInstIdHasDecl: + case Stage1ZirInstIdAlloca: + case Stage1ZirInstIdSpillEnd: + case Stage1ZirInstIdWasmMemorySize: + case Stage1ZirInstIdSrc: + case Stage1ZirInstIdReduce: return false; - case IrInstSrcIdAsm: + case Stage1ZirInstIdAsm: { - IrInstSrcAsm *asm_instruction = (IrInstSrcAsm *)instruction; + Stage1ZirInstAsm *asm_instruction = (Stage1ZirInstAsm *)instruction; return asm_instruction->has_side_effects; } - case IrInstSrcIdUnwrapErrPayload: + case Stage1ZirInstIdUnwrapErrPayload: { - IrInstSrcUnwrapErrPayload *unwrap_err_payload_instruction = - (IrInstSrcUnwrapErrPayload *)instruction; + Stage1ZirInstUnwrapErrPayload *unwrap_err_payload_instruction = + (Stage1ZirInstUnwrapErrPayload *)instruction; return unwrap_err_payload_instruction->safety_check_on || unwrap_err_payload_instruction->initializing; } - case IrInstSrcIdUnwrapErrCode: - return reinterpret_cast(instruction)->initializing; + case Stage1ZirInstIdUnwrapErrCode: + return reinterpret_cast(instruction)->initializing; } zig_unreachable(); } @@ -25047,7 +25047,7 @@ static ZigType *ir_resolve_lazy_fn_type(IrAnalyze *ira, AstNode *source_node, La param_info->type = nullptr; return get_generic_fn_type(ira->codegen, &fn_type_id); } else { - IrInstGen *param_type_inst = lazy_fn_type->param_types[fn_type_id.next_param_index]; + Stage1AirInst *param_type_inst = lazy_fn_type->param_types[fn_type_id.next_param_index]; ZigType *param_type = ir_resolve_type(ira, param_type_inst); if (type_is_invalid(param_type)) return nullptr; @@ -25257,7 +25257,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) { if (lazy_slice_type->sentinel != nullptr) { if (type_is_invalid(lazy_slice_type->sentinel->value->type)) return ErrorSemanticAnalyzeFail; - IrInstGen *sentinel = ir_implicit_cast(ira, lazy_slice_type->sentinel, elem_type); + Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_slice_type->sentinel, elem_type); if (type_is_invalid(sentinel->value->type)) return ErrorSemanticAnalyzeFail; sentinel_val = ir_resolve_const(ira, sentinel, UndefBad); @@ -25336,7 +25336,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) { if (lazy_ptr_type->sentinel != nullptr) { if (type_is_invalid(lazy_ptr_type->sentinel->value->type)) return ErrorSemanticAnalyzeFail; - IrInstGen *sentinel = ir_implicit_cast(ira, lazy_ptr_type->sentinel, elem_type); + Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_ptr_type->sentinel, elem_type); if (type_is_invalid(sentinel->value->type)) return ErrorSemanticAnalyzeFail; sentinel_val = ir_resolve_const(ira, sentinel, UndefBad); @@ -25500,7 +25500,7 @@ static Error ir_resolve_lazy_raw(AstNode *source_node, ZigValue *val) { if (lazy_array_type->sentinel != nullptr) { if (type_is_invalid(lazy_array_type->sentinel->value->type)) return ErrorSemanticAnalyzeFail; - IrInstGen *sentinel = ir_implicit_cast(ira, lazy_array_type->sentinel, elem_type); + Stage1AirInst *sentinel = ir_implicit_cast(ira, lazy_array_type->sentinel, elem_type); if (type_is_invalid(sentinel->value->type)) return ErrorSemanticAnalyzeFail; sentinel_val = ir_resolve_const(ira, sentinel, UndefBad); @@ -25691,8 +25691,8 @@ Error ir_resolve_lazy(CodeGen *codegen, AstNode *source_node, ZigValue *val) { return ErrorNone; } -void IrInstGen::src() { - IrInstGen *inst = this; +void Stage1AirInst::src() { + Stage1AirInst *inst = this; if (inst->source_node != nullptr) { inst->source_node->src(); } else { @@ -25700,8 +25700,8 @@ void IrInstGen::src() { } } -void IrInstGen::dump() { - IrInstGen *inst = this; +void Stage1AirInst::dump() { + Stage1AirInst *inst = this; inst->src(); if (inst->scope == nullptr) { fprintf(stderr, "(null scope)\n"); diff --git a/src/stage1/ir.hpp b/src/stage1/ir.hpp index 504802aafb..6a998adf40 100644 --- a/src/stage1/ir.hpp +++ b/src/stage1/ir.hpp @@ -10,7 +10,7 @@ #include "all_types.hpp" -IrInstGen *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn, +Stage1AirInst *ir_create_alloca(CodeGen *g, Scope *scope, AstNode *source_node, ZigFn *fn, ZigType *var_type, const char *name_hint); Error ir_eval_const_value(CodeGen *codegen, Scope *scope, AstNode *node, @@ -25,7 +25,7 @@ ZigType *ir_analyze(CodeGen *codegen, Stage1Zir *stage1_zir, Stage1Air *stage1_a ZigType *expected_type, AstNode *expected_type_source_node, ZigValue *result_ptr, ZigFn *fn); -bool ir_inst_gen_has_side_effects(IrInstGen *inst); +bool ir_inst_gen_has_side_effects(Stage1AirInst *inst); struct IrAnalyze; ZigValue *const_ptr_pointee(IrAnalyze *ira, CodeGen *codegen, ZigValue *const_val, diff --git a/src/stage1/ir_print.cpp b/src/stage1/ir_print.cpp index 58c17a9924..bec9521bc2 100644 --- a/src/stage1/ir_print.cpp +++ b/src/stage1/ir_print.cpp @@ -12,26 +12,26 @@ #include "ir_print.hpp" #include "os.hpp" -static uint32_t hash_inst_src_ptr(IrInstSrc* instruction) { +static uint32_t hash_inst_src_ptr(Stage1ZirInst* instruction) { return (uint32_t)(uintptr_t)instruction; } -static uint32_t hash_inst_gen_ptr(IrInstGen* instruction) { +static uint32_t hash_inst_gen_ptr(Stage1AirInst* instruction) { return (uint32_t)(uintptr_t)instruction; } -static bool inst_src_ptr_eql(IrInstSrc* a, IrInstSrc* b) { +static bool inst_src_ptr_eql(Stage1ZirInst* a, Stage1ZirInst* b) { return a == b; } -static bool inst_gen_ptr_eql(IrInstGen* a, IrInstGen* b) { +static bool inst_gen_ptr_eql(Stage1AirInst* a, Stage1AirInst* b) { return a == b; } -using InstSetSrc = HashMap; -using InstSetGen = HashMap; -using InstListSrc = ZigList; -using InstListGen = ZigList; +using InstSetSrc = HashMap; +using InstSetGen = HashMap; +using InstListSrc = ZigList; +using InstListGen = ZigList; struct IrPrintSrc { CodeGen *codegen; @@ -54,8 +54,8 @@ struct IrPrintGen { InstListGen pending; }; -static void ir_print_other_inst_src(IrPrintSrc *irp, IrInstSrc *inst); -static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst); +static void ir_print_other_inst_src(IrPrintSrc *irp, Stage1ZirInst *inst); +static void ir_print_other_inst_gen(IrPrintGen *irp, Stage1AirInst *inst); static void ir_print_call_modifier(FILE *f, CallModifier modifier) { switch (modifier) { @@ -87,473 +87,473 @@ static void ir_print_call_modifier(FILE *f, CallModifier modifier) { } } -const char* ir_inst_src_type_str(IrInstSrcId id) { +const char* ir_inst_src_type_str(Stage1ZirInstId id) { switch (id) { - case IrInstSrcIdInvalid: + case Stage1ZirInstIdInvalid: return "SrcInvalid"; - case IrInstSrcIdShuffleVector: + case Stage1ZirInstIdShuffleVector: return "SrcShuffle"; - case IrInstSrcIdSplat: + case Stage1ZirInstIdSplat: return "SrcSplat"; - case IrInstSrcIdDeclVar: + case Stage1ZirInstIdDeclVar: return "SrcDeclVar"; - case IrInstSrcIdBr: + case Stage1ZirInstIdBr: return "SrcBr"; - case IrInstSrcIdCondBr: + case Stage1ZirInstIdCondBr: return "SrcCondBr"; - case IrInstSrcIdSwitchBr: + case Stage1ZirInstIdSwitchBr: return "SrcSwitchBr"; - case IrInstSrcIdSwitchVar: + case Stage1ZirInstIdSwitchVar: return "SrcSwitchVar"; - case IrInstSrcIdSwitchElseVar: + case Stage1ZirInstIdSwitchElseVar: return "SrcSwitchElseVar"; - case IrInstSrcIdSwitchTarget: + case Stage1ZirInstIdSwitchTarget: return "SrcSwitchTarget"; - case IrInstSrcIdPhi: + case Stage1ZirInstIdPhi: return "SrcPhi"; - case IrInstSrcIdUnOp: + case Stage1ZirInstIdUnOp: return "SrcUnOp"; - case IrInstSrcIdBinOp: + case Stage1ZirInstIdBinOp: return "SrcBinOp"; - case IrInstSrcIdMergeErrSets: + case Stage1ZirInstIdMergeErrSets: return "SrcMergeErrSets"; - case IrInstSrcIdLoadPtr: + case Stage1ZirInstIdLoadPtr: return "SrcLoadPtr"; - case IrInstSrcIdStorePtr: + case Stage1ZirInstIdStorePtr: return "SrcStorePtr"; - case IrInstSrcIdFieldPtr: + case Stage1ZirInstIdFieldPtr: return "SrcFieldPtr"; - case IrInstSrcIdElemPtr: + case Stage1ZirInstIdElemPtr: return "SrcElemPtr"; - case IrInstSrcIdVarPtr: + case Stage1ZirInstIdVarPtr: return "SrcVarPtr"; - case IrInstSrcIdCallExtra: + case Stage1ZirInstIdCallExtra: return "SrcCallExtra"; - case IrInstSrcIdAsyncCallExtra: + case Stage1ZirInstIdAsyncCallExtra: return "SrcAsyncCallExtra"; - case IrInstSrcIdCall: + case Stage1ZirInstIdCall: return "SrcCall"; - case IrInstSrcIdCallArgs: + case Stage1ZirInstIdCallArgs: return "SrcCallArgs"; - case IrInstSrcIdConst: + case Stage1ZirInstIdConst: return "SrcConst"; - case IrInstSrcIdReturn: + case Stage1ZirInstIdReturn: return "SrcReturn"; - case IrInstSrcIdContainerInitList: + case Stage1ZirInstIdContainerInitList: return "SrcContainerInitList"; - case IrInstSrcIdContainerInitFields: + case Stage1ZirInstIdContainerInitFields: return "SrcContainerInitFields"; - case IrInstSrcIdUnreachable: + case Stage1ZirInstIdUnreachable: return "SrcUnreachable"; - case IrInstSrcIdTypeOf: + case Stage1ZirInstIdTypeOf: return "SrcTypeOf"; - case IrInstSrcIdSetCold: + case Stage1ZirInstIdSetCold: return "SrcSetCold"; - case IrInstSrcIdSetRuntimeSafety: + case Stage1ZirInstIdSetRuntimeSafety: return "SrcSetRuntimeSafety"; - case IrInstSrcIdSetFloatMode: + case Stage1ZirInstIdSetFloatMode: return "SrcSetFloatMode"; - case IrInstSrcIdArrayType: + case Stage1ZirInstIdArrayType: return "SrcArrayType"; - case IrInstSrcIdAnyFrameType: + case Stage1ZirInstIdAnyFrameType: return "SrcAnyFrameType"; - case IrInstSrcIdSliceType: + case Stage1ZirInstIdSliceType: return "SrcSliceType"; - case IrInstSrcIdAsm: + case Stage1ZirInstIdAsm: return "SrcAsm"; - case IrInstSrcIdSizeOf: + case Stage1ZirInstIdSizeOf: return "SrcSizeOf"; - case IrInstSrcIdTestNonNull: + case Stage1ZirInstIdTestNonNull: return "SrcTestNonNull"; - case IrInstSrcIdOptionalUnwrapPtr: + case Stage1ZirInstIdOptionalUnwrapPtr: return "SrcOptionalUnwrapPtr"; - case IrInstSrcIdClz: + case Stage1ZirInstIdClz: return "SrcClz"; - case IrInstSrcIdCtz: + case Stage1ZirInstIdCtz: return "SrcCtz"; - case IrInstSrcIdPopCount: + case Stage1ZirInstIdPopCount: return "SrcPopCount"; - case IrInstSrcIdBswap: + case Stage1ZirInstIdBswap: return "SrcBswap"; - case IrInstSrcIdBitReverse: + case Stage1ZirInstIdBitReverse: return "SrcBitReverse"; - case IrInstSrcIdImport: + case Stage1ZirInstIdImport: return "SrcImport"; - case IrInstSrcIdCImport: + case Stage1ZirInstIdCImport: return "SrcCImport"; - case IrInstSrcIdCInclude: + case Stage1ZirInstIdCInclude: return "SrcCInclude"; - case IrInstSrcIdCDefine: + case Stage1ZirInstIdCDefine: return "SrcCDefine"; - case IrInstSrcIdCUndef: + case Stage1ZirInstIdCUndef: return "SrcCUndef"; - case IrInstSrcIdRef: + case Stage1ZirInstIdRef: return "SrcRef"; - case IrInstSrcIdCompileErr: + case Stage1ZirInstIdCompileErr: return "SrcCompileErr"; - case IrInstSrcIdCompileLog: + case Stage1ZirInstIdCompileLog: return "SrcCompileLog"; - case IrInstSrcIdErrName: + case Stage1ZirInstIdErrName: return "SrcErrName"; - case IrInstSrcIdEmbedFile: + case Stage1ZirInstIdEmbedFile: return "SrcEmbedFile"; - case IrInstSrcIdCmpxchg: + case Stage1ZirInstIdCmpxchg: return "SrcCmpxchg"; - case IrInstSrcIdFence: + case Stage1ZirInstIdFence: return "SrcFence"; - case IrInstSrcIdReduce: + case Stage1ZirInstIdReduce: return "SrcReduce"; - case IrInstSrcIdTruncate: + case Stage1ZirInstIdTruncate: return "SrcTruncate"; - case IrInstSrcIdIntCast: + case Stage1ZirInstIdIntCast: return "SrcIntCast"; - case IrInstSrcIdFloatCast: + case Stage1ZirInstIdFloatCast: return "SrcFloatCast"; - case IrInstSrcIdIntToFloat: + case Stage1ZirInstIdIntToFloat: return "SrcIntToFloat"; - case IrInstSrcIdFloatToInt: + case Stage1ZirInstIdFloatToInt: return "SrcFloatToInt"; - case IrInstSrcIdBoolToInt: + case Stage1ZirInstIdBoolToInt: return "SrcBoolToInt"; - case IrInstSrcIdVectorType: + case Stage1ZirInstIdVectorType: return "SrcVectorType"; - case IrInstSrcIdBoolNot: + case Stage1ZirInstIdBoolNot: return "SrcBoolNot"; - case IrInstSrcIdMemset: + case Stage1ZirInstIdMemset: return "SrcMemset"; - case IrInstSrcIdMemcpy: + case Stage1ZirInstIdMemcpy: return "SrcMemcpy"; - case IrInstSrcIdSlice: + case Stage1ZirInstIdSlice: return "SrcSlice"; - case IrInstSrcIdBreakpoint: + case Stage1ZirInstIdBreakpoint: return "SrcBreakpoint"; - case IrInstSrcIdReturnAddress: + case Stage1ZirInstIdReturnAddress: return "SrcReturnAddress"; - case IrInstSrcIdFrameAddress: + case Stage1ZirInstIdFrameAddress: return "SrcFrameAddress"; - case IrInstSrcIdFrameHandle: + case Stage1ZirInstIdFrameHandle: return "SrcFrameHandle"; - case IrInstSrcIdFrameType: + case Stage1ZirInstIdFrameType: return "SrcFrameType"; - case IrInstSrcIdFrameSize: + case Stage1ZirInstIdFrameSize: return "SrcFrameSize"; - case IrInstSrcIdAlignOf: + case Stage1ZirInstIdAlignOf: return "SrcAlignOf"; - case IrInstSrcIdOverflowOp: + case Stage1ZirInstIdOverflowOp: return "SrcOverflowOp"; - case IrInstSrcIdTestErr: + case Stage1ZirInstIdTestErr: return "SrcTestErr"; - case IrInstSrcIdMulAdd: + case Stage1ZirInstIdMulAdd: return "SrcMulAdd"; - case IrInstSrcIdFloatOp: + case Stage1ZirInstIdFloatOp: return "SrcFloatOp"; - case IrInstSrcIdUnwrapErrCode: + case Stage1ZirInstIdUnwrapErrCode: return "SrcUnwrapErrCode"; - case IrInstSrcIdUnwrapErrPayload: + case Stage1ZirInstIdUnwrapErrPayload: return "SrcUnwrapErrPayload"; - case IrInstSrcIdFnProto: + case Stage1ZirInstIdFnProto: return "SrcFnProto"; - case IrInstSrcIdTestComptime: + case Stage1ZirInstIdTestComptime: return "SrcTestComptime"; - case IrInstSrcIdPtrCast: + case Stage1ZirInstIdPtrCast: return "SrcPtrCast"; - case IrInstSrcIdBitCast: + case Stage1ZirInstIdBitCast: return "SrcBitCast"; - case IrInstSrcIdIntToPtr: + case Stage1ZirInstIdIntToPtr: return "SrcIntToPtr"; - case IrInstSrcIdPtrToInt: + case Stage1ZirInstIdPtrToInt: return "SrcPtrToInt"; - case IrInstSrcIdIntToEnum: + case Stage1ZirInstIdIntToEnum: return "SrcIntToEnum"; - case IrInstSrcIdEnumToInt: + case Stage1ZirInstIdEnumToInt: return "SrcEnumToInt"; - case IrInstSrcIdIntToErr: + case Stage1ZirInstIdIntToErr: return "SrcIntToErr"; - case IrInstSrcIdErrToInt: + case Stage1ZirInstIdErrToInt: return "SrcErrToInt"; - case IrInstSrcIdCheckSwitchProngsUnderNo: + case Stage1ZirInstIdCheckSwitchProngsUnderNo: return "SrcCheckSwitchProngsUnderNo"; - case IrInstSrcIdCheckSwitchProngsUnderYes: + case Stage1ZirInstIdCheckSwitchProngsUnderYes: return "SrcCheckSwitchProngsUnderYes"; - case IrInstSrcIdCheckStatementIsVoid: + case Stage1ZirInstIdCheckStatementIsVoid: return "SrcCheckStatementIsVoid"; - case IrInstSrcIdTypeName: + case Stage1ZirInstIdTypeName: return "SrcTypeName"; - case IrInstSrcIdDeclRef: + case Stage1ZirInstIdDeclRef: return "SrcDeclRef"; - case IrInstSrcIdPanic: + case Stage1ZirInstIdPanic: return "SrcPanic"; - case IrInstSrcIdTagName: + case Stage1ZirInstIdTagName: return "SrcTagName"; - case IrInstSrcIdFieldParentPtr: + case Stage1ZirInstIdFieldParentPtr: return "SrcFieldParentPtr"; - case IrInstSrcIdOffsetOf: + case Stage1ZirInstIdOffsetOf: return "SrcOffsetOf"; - case IrInstSrcIdBitOffsetOf: + case Stage1ZirInstIdBitOffsetOf: return "SrcBitOffsetOf"; - case IrInstSrcIdTypeInfo: + case Stage1ZirInstIdTypeInfo: return "SrcTypeInfo"; - case IrInstSrcIdType: + case Stage1ZirInstIdType: return "SrcType"; - case IrInstSrcIdHasField: + case Stage1ZirInstIdHasField: return "SrcHasField"; - case IrInstSrcIdSetEvalBranchQuota: + case Stage1ZirInstIdSetEvalBranchQuota: return "SrcSetEvalBranchQuota"; - case IrInstSrcIdPtrType: + case Stage1ZirInstIdPtrType: return "SrcPtrType"; - case IrInstSrcIdPtrTypeSimple: + case Stage1ZirInstIdPtrTypeSimple: return "SrcPtrTypeSimple"; - case IrInstSrcIdPtrTypeSimpleConst: + case Stage1ZirInstIdPtrTypeSimpleConst: return "SrcPtrTypeSimpleConst"; - case IrInstSrcIdAlignCast: + case Stage1ZirInstIdAlignCast: return "SrcAlignCast"; - case IrInstSrcIdImplicitCast: + case Stage1ZirInstIdImplicitCast: return "SrcImplicitCast"; - case IrInstSrcIdResolveResult: + case Stage1ZirInstIdResolveResult: return "SrcResolveResult"; - case IrInstSrcIdResetResult: + case Stage1ZirInstIdResetResult: return "SrcResetResult"; - case IrInstSrcIdSetAlignStack: + case Stage1ZirInstIdSetAlignStack: return "SrcSetAlignStack"; - case IrInstSrcIdArgTypeAllowVarFalse: + case Stage1ZirInstIdArgTypeAllowVarFalse: return "SrcArgTypeAllowVarFalse"; - case IrInstSrcIdArgTypeAllowVarTrue: + case Stage1ZirInstIdArgTypeAllowVarTrue: return "SrcArgTypeAllowVarTrue"; - case IrInstSrcIdExport: + case Stage1ZirInstIdExport: return "SrcExport"; - case IrInstSrcIdExtern: + case Stage1ZirInstIdExtern: return "SrcExtern"; - case IrInstSrcIdErrorReturnTrace: + case Stage1ZirInstIdErrorReturnTrace: return "SrcErrorReturnTrace"; - case IrInstSrcIdErrorUnion: + case Stage1ZirInstIdErrorUnion: return "SrcErrorUnion"; - case IrInstSrcIdAtomicRmw: + case Stage1ZirInstIdAtomicRmw: return "SrcAtomicRmw"; - case IrInstSrcIdAtomicLoad: + case Stage1ZirInstIdAtomicLoad: return "SrcAtomicLoad"; - case IrInstSrcIdAtomicStore: + case Stage1ZirInstIdAtomicStore: return "SrcAtomicStore"; - case IrInstSrcIdSaveErrRetAddr: + case Stage1ZirInstIdSaveErrRetAddr: return "SrcSaveErrRetAddr"; - case IrInstSrcIdAddImplicitReturnType: + case Stage1ZirInstIdAddImplicitReturnType: return "SrcAddImplicitReturnType"; - case IrInstSrcIdErrSetCast: + case Stage1ZirInstIdErrSetCast: return "SrcErrSetCast"; - case IrInstSrcIdCheckRuntimeScope: + case Stage1ZirInstIdCheckRuntimeScope: return "SrcCheckRuntimeScope"; - case IrInstSrcIdHasDecl: + case Stage1ZirInstIdHasDecl: return "SrcHasDecl"; - case IrInstSrcIdUndeclaredIdent: + case Stage1ZirInstIdUndeclaredIdent: return "SrcUndeclaredIdent"; - case IrInstSrcIdAlloca: + case Stage1ZirInstIdAlloca: return "SrcAlloca"; - case IrInstSrcIdEndExpr: + case Stage1ZirInstIdEndExpr: return "SrcEndExpr"; - case IrInstSrcIdUnionInitNamedField: + case Stage1ZirInstIdUnionInitNamedField: return "SrcUnionInitNamedField"; - case IrInstSrcIdSuspendBegin: + case Stage1ZirInstIdSuspendBegin: return "SrcSuspendBegin"; - case IrInstSrcIdSuspendFinish: + case Stage1ZirInstIdSuspendFinish: return "SrcSuspendFinish"; - case IrInstSrcIdAwait: + case Stage1ZirInstIdAwait: return "SrcAwaitSr"; - case IrInstSrcIdResume: + case Stage1ZirInstIdResume: return "SrcResume"; - case IrInstSrcIdSpillBegin: + case Stage1ZirInstIdSpillBegin: return "SrcSpillBegin"; - case IrInstSrcIdSpillEnd: + case Stage1ZirInstIdSpillEnd: return "SrcSpillEnd"; - case IrInstSrcIdWasmMemorySize: + case Stage1ZirInstIdWasmMemorySize: return "SrcWasmMemorySize"; - case IrInstSrcIdWasmMemoryGrow: + case Stage1ZirInstIdWasmMemoryGrow: return "SrcWasmMemoryGrow"; - case IrInstSrcIdSrc: + case Stage1ZirInstIdSrc: return "SrcSrc"; } zig_unreachable(); } -const char* ir_inst_gen_type_str(IrInstGenId id) { +const char* ir_inst_gen_type_str(Stage1AirInstId id) { switch (id) { - case IrInstGenIdInvalid: + case Stage1AirInstIdInvalid: return "GenInvalid"; - case IrInstGenIdShuffleVector: + case Stage1AirInstIdShuffleVector: return "GenShuffle"; - case IrInstGenIdSplat: + case Stage1AirInstIdSplat: return "GenSplat"; - case IrInstGenIdDeclVar: + case Stage1AirInstIdDeclVar: return "GenDeclVar"; - case IrInstGenIdBr: + case Stage1AirInstIdBr: return "GenBr"; - case IrInstGenIdCondBr: + case Stage1AirInstIdCondBr: return "GenCondBr"; - case IrInstGenIdSwitchBr: + case Stage1AirInstIdSwitchBr: return "GenSwitchBr"; - case IrInstGenIdPhi: + case Stage1AirInstIdPhi: return "GenPhi"; - case IrInstGenIdBinOp: + case Stage1AirInstIdBinOp: return "GenBinOp"; - case IrInstGenIdLoadPtr: + case Stage1AirInstIdLoadPtr: return "GenLoadPtr"; - case IrInstGenIdStorePtr: + case Stage1AirInstIdStorePtr: return "GenStorePtr"; - case IrInstGenIdVectorStoreElem: + case Stage1AirInstIdVectorStoreElem: return "GenVectorStoreElem"; - case IrInstGenIdStructFieldPtr: + case Stage1AirInstIdStructFieldPtr: return "GenStructFieldPtr"; - case IrInstGenIdUnionFieldPtr: + case Stage1AirInstIdUnionFieldPtr: return "GenUnionFieldPtr"; - case IrInstGenIdElemPtr: + case Stage1AirInstIdElemPtr: return "GenElemPtr"; - case IrInstGenIdVarPtr: + case Stage1AirInstIdVarPtr: return "GenVarPtr"; - case IrInstGenIdReturnPtr: + case Stage1AirInstIdReturnPtr: return "GenReturnPtr"; - case IrInstGenIdCall: + case Stage1AirInstIdCall: return "GenCall"; - case IrInstGenIdConst: + case Stage1AirInstIdConst: return "GenConst"; - case IrInstGenIdReturn: + case Stage1AirInstIdReturn: return "GenReturn"; - case IrInstGenIdCast: + case Stage1AirInstIdCast: return "GenCast"; - case IrInstGenIdUnreachable: + case Stage1AirInstIdUnreachable: return "GenUnreachable"; - case IrInstGenIdAsm: + case Stage1AirInstIdAsm: return "GenAsm"; - case IrInstGenIdTestNonNull: + case Stage1AirInstIdTestNonNull: return "GenTestNonNull"; - case IrInstGenIdOptionalUnwrapPtr: + case Stage1AirInstIdOptionalUnwrapPtr: return "GenOptionalUnwrapPtr"; - case IrInstGenIdOptionalWrap: + case Stage1AirInstIdOptionalWrap: return "GenOptionalWrap"; - case IrInstGenIdUnionTag: + case Stage1AirInstIdUnionTag: return "GenUnionTag"; - case IrInstGenIdClz: + case Stage1AirInstIdClz: return "GenClz"; - case IrInstGenIdCtz: + case Stage1AirInstIdCtz: return "GenCtz"; - case IrInstGenIdPopCount: + case Stage1AirInstIdPopCount: return "GenPopCount"; - case IrInstGenIdBswap: + case Stage1AirInstIdBswap: return "GenBswap"; - case IrInstGenIdBitReverse: + case Stage1AirInstIdBitReverse: return "GenBitReverse"; - case IrInstGenIdRef: + case Stage1AirInstIdRef: return "GenRef"; - case IrInstGenIdErrName: + case Stage1AirInstIdErrName: return "GenErrName"; - case IrInstGenIdCmpxchg: + case Stage1AirInstIdCmpxchg: return "GenCmpxchg"; - case IrInstGenIdFence: + case Stage1AirInstIdFence: return "GenFence"; - case IrInstGenIdReduce: + case Stage1AirInstIdReduce: return "GenReduce"; - case IrInstGenIdTruncate: + case Stage1AirInstIdTruncate: return "GenTruncate"; - case IrInstGenIdBoolNot: + case Stage1AirInstIdBoolNot: return "GenBoolNot"; - case IrInstGenIdMemset: + case Stage1AirInstIdMemset: return "GenMemset"; - case IrInstGenIdMemcpy: + case Stage1AirInstIdMemcpy: return "GenMemcpy"; - case IrInstGenIdSlice: + case Stage1AirInstIdSlice: return "GenSlice"; - case IrInstGenIdBreakpoint: + case Stage1AirInstIdBreakpoint: return "GenBreakpoint"; - case IrInstGenIdReturnAddress: + case Stage1AirInstIdReturnAddress: return "GenReturnAddress"; - case IrInstGenIdFrameAddress: + case Stage1AirInstIdFrameAddress: return "GenFrameAddress"; - case IrInstGenIdFrameHandle: + case Stage1AirInstIdFrameHandle: return "GenFrameHandle"; - case IrInstGenIdFrameSize: + case Stage1AirInstIdFrameSize: return "GenFrameSize"; - case IrInstGenIdOverflowOp: + case Stage1AirInstIdOverflowOp: return "GenOverflowOp"; - case IrInstGenIdTestErr: + case Stage1AirInstIdTestErr: return "GenTestErr"; - case IrInstGenIdMulAdd: + case Stage1AirInstIdMulAdd: return "GenMulAdd"; - case IrInstGenIdFloatOp: + case Stage1AirInstIdFloatOp: return "GenFloatOp"; - case IrInstGenIdUnwrapErrCode: + case Stage1AirInstIdUnwrapErrCode: return "GenUnwrapErrCode"; - case IrInstGenIdUnwrapErrPayload: + case Stage1AirInstIdUnwrapErrPayload: return "GenUnwrapErrPayload"; - case IrInstGenIdErrWrapCode: + case Stage1AirInstIdErrWrapCode: return "GenErrWrapCode"; - case IrInstGenIdErrWrapPayload: + case Stage1AirInstIdErrWrapPayload: return "GenErrWrapPayload"; - case IrInstGenIdPtrCast: + case Stage1AirInstIdPtrCast: return "GenPtrCast"; - case IrInstGenIdBitCast: + case Stage1AirInstIdBitCast: return "GenBitCast"; - case IrInstGenIdWidenOrShorten: + case Stage1AirInstIdWidenOrShorten: return "GenWidenOrShorten"; - case IrInstGenIdIntToPtr: + case Stage1AirInstIdIntToPtr: return "GenIntToPtr"; - case IrInstGenIdPtrToInt: + case Stage1AirInstIdPtrToInt: return "GenPtrToInt"; - case IrInstGenIdIntToEnum: + case Stage1AirInstIdIntToEnum: return "GenIntToEnum"; - case IrInstGenIdIntToErr: + case Stage1AirInstIdIntToErr: return "GenIntToErr"; - case IrInstGenIdErrToInt: + case Stage1AirInstIdErrToInt: return "GenErrToInt"; - case IrInstGenIdPanic: + case Stage1AirInstIdPanic: return "GenPanic"; - case IrInstGenIdTagName: + case Stage1AirInstIdTagName: return "GenTagName"; - case IrInstGenIdFieldParentPtr: + case Stage1AirInstIdFieldParentPtr: return "GenFieldParentPtr"; - case IrInstGenIdAlignCast: + case Stage1AirInstIdAlignCast: return "GenAlignCast"; - case IrInstGenIdErrorReturnTrace: + case Stage1AirInstIdErrorReturnTrace: return "GenErrorReturnTrace"; - case IrInstGenIdAtomicRmw: + case Stage1AirInstIdAtomicRmw: return "GenAtomicRmw"; - case IrInstGenIdAtomicLoad: + case Stage1AirInstIdAtomicLoad: return "GenAtomicLoad"; - case IrInstGenIdAtomicStore: + case Stage1AirInstIdAtomicStore: return "GenAtomicStore"; - case IrInstGenIdSaveErrRetAddr: + case Stage1AirInstIdSaveErrRetAddr: return "GenSaveErrRetAddr"; - case IrInstGenIdVectorToArray: + case Stage1AirInstIdVectorToArray: return "GenVectorToArray"; - case IrInstGenIdArrayToVector: + case Stage1AirInstIdArrayToVector: return "GenArrayToVector"; - case IrInstGenIdAssertZero: + case Stage1AirInstIdAssertZero: return "GenAssertZero"; - case IrInstGenIdAssertNonNull: + case Stage1AirInstIdAssertNonNull: return "GenAssertNonNull"; - case IrInstGenIdAlloca: + case Stage1AirInstIdAlloca: return "GenAlloca"; - case IrInstGenIdPtrOfArrayToSlice: + case Stage1AirInstIdPtrOfArrayToSlice: return "GenPtrOfArrayToSlice"; - case IrInstGenIdSuspendBegin: + case Stage1AirInstIdSuspendBegin: return "GenSuspendBegin"; - case IrInstGenIdSuspendFinish: + case Stage1AirInstIdSuspendFinish: return "GenSuspendFinish"; - case IrInstGenIdAwait: + case Stage1AirInstIdAwait: return "GenAwait"; - case IrInstGenIdResume: + case Stage1AirInstIdResume: return "GenResume"; - case IrInstGenIdSpillBegin: + case Stage1AirInstIdSpillBegin: return "GenSpillBegin"; - case IrInstGenIdSpillEnd: + case Stage1AirInstIdSpillEnd: return "GenSpillEnd"; - case IrInstGenIdVectorExtractElem: + case Stage1AirInstIdVectorExtractElem: return "GenVectorExtractElem"; - case IrInstGenIdBinaryNot: + case Stage1AirInstIdBinaryNot: return "GenBinaryNot"; - case IrInstGenIdNegation: + case Stage1AirInstIdNegation: return "GenNegation"; - case IrInstGenIdWasmMemorySize: + case Stage1AirInstIdWasmMemorySize: return "GenWasmMemorySize"; - case IrInstGenIdWasmMemoryGrow: + case Stage1AirInstIdWasmMemoryGrow: return "GenWasmMemoryGrow"; - case IrInstGenIdExtern: + case Stage1AirInstIdExtern: return "GenExtrern"; } zig_unreachable(); @@ -571,12 +571,12 @@ static void ir_print_indent_gen(IrPrintGen *irp) { } } -static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool trailing) { +static void ir_print_prefix_src(IrPrintSrc *irp, Stage1ZirInst *instruction, bool trailing) { ir_print_indent_src(irp); const char mark = trailing ? ':' : '#'; const char *type_name; - if (instruction->id == IrInstSrcIdConst) { - type_name = buf_ptr(&reinterpret_cast(instruction)->value->type->name); + if (instruction->id == Stage1ZirInstIdConst) { + type_name = buf_ptr(&reinterpret_cast(instruction)->value->type->name); } else { type_name = "(unknown)"; } @@ -586,7 +586,7 @@ static void ir_print_prefix_src(IrPrintSrc *irp, IrInstSrc *instruction, bool tr ir_inst_src_type_str(instruction->id), type_name, ref_count); } -static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool trailing) { +static void ir_print_prefix_gen(IrPrintGen *irp, Stage1AirInst *instruction, bool trailing) { ir_print_indent_gen(irp); const char mark = trailing ? ':' : '#'; const char *type_name = instruction->value->type ? buf_ptr(&instruction->value->type->name) : "(unknown)"; @@ -596,11 +596,11 @@ static void ir_print_prefix_gen(IrPrintGen *irp, IrInstGen *instruction, bool tr ir_inst_gen_type_str(instruction->id), type_name, ref_count); } -static void ir_print_var_src(IrPrintSrc *irp, IrInstSrc *inst) { +static void ir_print_var_src(IrPrintSrc *irp, Stage1ZirInst *inst) { fprintf(irp->f, "#%" PRIu32 "", inst->debug_id); } -static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) { +static void ir_print_var_gen(IrPrintGen *irp, Stage1AirInst *inst) { fprintf(irp->f, "#%" PRIu32 "", inst->debug_id); if (irp->printed.maybe_get(inst) == nullptr) { irp->printed.put(inst, 0); @@ -608,7 +608,7 @@ static void ir_print_var_gen(IrPrintGen *irp, IrInstGen *inst) { } } -static void ir_print_other_inst_src(IrPrintSrc *irp, IrInstSrc *inst) { +static void ir_print_other_inst_src(IrPrintSrc *irp, Stage1ZirInst *inst) { if (inst == nullptr) { fprintf(irp->f, "(null)"); return; @@ -623,7 +623,7 @@ static void ir_print_const_value(CodeGen *g, FILE *f, ZigValue *const_val) { fprintf(f, "%s", buf_ptr(&buf)); } -static void ir_print_other_inst_gen(IrPrintGen *irp, IrInstGen *inst) { +static void ir_print_other_inst_gen(IrPrintGen *irp, Stage1AirInst *inst) { if (inst == nullptr) { fprintf(irp->f, "(null)"); } else { @@ -639,7 +639,7 @@ static void ir_print_other_block(IrPrintSrc *irp, Stage1ZirBasicBlock *bb) { } } -static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) { +static void ir_print_other_block_gen(IrPrintGen *irp, Stage1AirBasicBlock *bb) { if (bb == nullptr) { fprintf(irp->f, "(null block)"); } else { @@ -647,21 +647,21 @@ static void ir_print_other_block_gen(IrPrintGen *irp, IrBasicBlockGen *bb) { } } -static void ir_print_return_src(IrPrintSrc *irp, IrInstSrcReturn *inst) { +static void ir_print_return_src(IrPrintSrc *irp, Stage1ZirInstReturn *inst) { fprintf(irp->f, "return "); ir_print_other_inst_src(irp, inst->operand); } -static void ir_print_return_gen(IrPrintGen *irp, IrInstGenReturn *inst) { +static void ir_print_return_gen(IrPrintGen *irp, Stage1AirInstReturn *inst) { fprintf(irp->f, "return "); ir_print_other_inst_gen(irp, inst->operand); } -static void ir_print_const(IrPrintSrc *irp, IrInstSrcConst *const_instruction) { +static void ir_print_const(IrPrintSrc *irp, Stage1ZirInstConst *const_instruction) { ir_print_const_value(irp->codegen, irp->f, const_instruction->value); } -static void ir_print_const(IrPrintGen *irp, IrInstGenConst *const_instruction) { +static void ir_print_const(IrPrintGen *irp, Stage1AirInstConst *const_instruction) { ir_print_const_value(irp->codegen, irp->f, const_instruction->base.value); } @@ -751,12 +751,12 @@ static const char *ir_un_op_id_str(IrUnOp op_id) { zig_unreachable(); } -static void ir_print_un_op(IrPrintSrc *irp, IrInstSrcUnOp *inst) { +static void ir_print_un_op(IrPrintSrc *irp, Stage1ZirInstUnOp *inst) { fprintf(irp->f, "%s ", ir_un_op_id_str(inst->op_id)); ir_print_other_inst_src(irp, inst->value); } -static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction) { +static void ir_print_bin_op(IrPrintSrc *irp, Stage1ZirInstBinOp *bin_op_instruction) { ir_print_other_inst_src(irp, bin_op_instruction->op1); fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id)); ir_print_other_inst_src(irp, bin_op_instruction->op2); @@ -765,7 +765,7 @@ static void ir_print_bin_op(IrPrintSrc *irp, IrInstSrcBinOp *bin_op_instruction) } } -static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction) { +static void ir_print_bin_op(IrPrintGen *irp, Stage1AirInstBinOp *bin_op_instruction) { ir_print_other_inst_gen(irp, bin_op_instruction->op1); fprintf(irp->f, " %s ", ir_bin_op_id_str(bin_op_instruction->op_id)); ir_print_other_inst_gen(irp, bin_op_instruction->op2); @@ -774,7 +774,7 @@ static void ir_print_bin_op(IrPrintGen *irp, IrInstGenBinOp *bin_op_instruction) } } -static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *instruction) { +static void ir_print_merge_err_sets(IrPrintSrc *irp, Stage1ZirInstMergeErrSets *instruction) { ir_print_other_inst_src(irp, instruction->op1); fprintf(irp->f, " || "); ir_print_other_inst_src(irp, instruction->op2); @@ -783,7 +783,7 @@ static void ir_print_merge_err_sets(IrPrintSrc *irp, IrInstSrcMergeErrSets *inst } } -static void ir_print_decl_var_src(IrPrintSrc *irp, IrInstSrcDeclVar *decl_var_instruction) { +static void ir_print_decl_var_src(IrPrintSrc *irp, Stage1ZirInstDeclVar *decl_var_instruction) { const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var"; const char *name = decl_var_instruction->var->name; if (decl_var_instruction->var_type) { @@ -820,7 +820,7 @@ static const char *cast_op_str(CastOp op) { zig_unreachable(); } -static void ir_print_cast(IrPrintGen *irp, IrInstGenCast *cast_instruction) { +static void ir_print_cast(IrPrintGen *irp, Stage1AirInstCast *cast_instruction) { fprintf(irp->f, "%s cast ", cast_op_str(cast_instruction->cast_op)); ir_print_other_inst_gen(irp, cast_instruction->value); } @@ -882,7 +882,7 @@ static void ir_print_result_loc(IrPrintSrc *irp, ResultLoc *result_loc) { zig_unreachable(); } -static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction) { +static void ir_print_call_extra(IrPrintSrc *irp, Stage1ZirInstCallExtra *instruction) { fprintf(irp->f, "opts="); ir_print_other_inst_src(irp, instruction->options); fprintf(irp->f, ", fn="); @@ -893,7 +893,7 @@ static void ir_print_call_extra(IrPrintSrc *irp, IrInstSrcCallExtra *instruction ir_print_result_loc(irp, instruction->result_loc); } -static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra *instruction) { +static void ir_print_async_call_extra(IrPrintSrc *irp, Stage1ZirInstAsyncCallExtra *instruction) { fprintf(irp->f, "modifier="); ir_print_call_modifier(irp->f, instruction->modifier); fprintf(irp->f, ", fn="); @@ -910,14 +910,14 @@ static void ir_print_async_call_extra(IrPrintSrc *irp, IrInstSrcAsyncCallExtra * ir_print_result_loc(irp, instruction->result_loc); } -static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction) { +static void ir_print_call_args(IrPrintSrc *irp, Stage1ZirInstCallArgs *instruction) { fprintf(irp->f, "opts="); ir_print_other_inst_src(irp, instruction->options); fprintf(irp->f, ", fn="); ir_print_other_inst_src(irp, instruction->fn_ref); fprintf(irp->f, ", args=("); for (size_t i = 0; i < instruction->args_len; i += 1) { - IrInstSrc *arg = instruction->args_ptr[i]; + Stage1ZirInst *arg = instruction->args_ptr[i]; if (i != 0) fprintf(irp->f, ", "); ir_print_other_inst_src(irp, arg); @@ -926,7 +926,7 @@ static void ir_print_call_args(IrPrintSrc *irp, IrInstSrcCallArgs *instruction) ir_print_result_loc(irp, instruction->result_loc); } -static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction) { +static void ir_print_call_src(IrPrintSrc *irp, Stage1ZirInstCall *call_instruction) { ir_print_call_modifier(irp->f, call_instruction->modifier); if (call_instruction->fn_entry) { fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name)); @@ -936,7 +936,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction) } fprintf(irp->f, "("); for (size_t i = 0; i < call_instruction->arg_count; i += 1) { - IrInstSrc *arg = call_instruction->args[i]; + Stage1ZirInst *arg = call_instruction->args[i]; if (i != 0) fprintf(irp->f, ", "); ir_print_other_inst_src(irp, arg); @@ -945,7 +945,7 @@ static void ir_print_call_src(IrPrintSrc *irp, IrInstSrcCall *call_instruction) ir_print_result_loc(irp, call_instruction->result_loc); } -static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction) { +static void ir_print_call_gen(IrPrintGen *irp, Stage1AirInstCall *call_instruction) { ir_print_call_modifier(irp->f, call_instruction->modifier); if (call_instruction->fn_entry) { fprintf(irp->f, "%s", buf_ptr(&call_instruction->fn_entry->symbol_name)); @@ -955,7 +955,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction) } fprintf(irp->f, "("); for (size_t i = 0; i < call_instruction->arg_count; i += 1) { - IrInstGen *arg = call_instruction->args[i]; + Stage1AirInst *arg = call_instruction->args[i]; if (i != 0) fprintf(irp->f, ", "); ir_print_other_inst_gen(irp, arg); @@ -964,7 +964,7 @@ static void ir_print_call_gen(IrPrintGen *irp, IrInstGenCall *call_instruction) ir_print_other_inst_gen(irp, call_instruction->result_loc); } -static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) { +static void ir_print_cond_br(IrPrintSrc *irp, Stage1ZirInstCondBr *inst) { fprintf(irp->f, "if ("); ir_print_other_inst_src(irp, inst->condition); fprintf(irp->f, ") "); @@ -977,7 +977,7 @@ static void ir_print_cond_br(IrPrintSrc *irp, IrInstSrcCondBr *inst) { } } -static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) { +static void ir_print_cond_br(IrPrintGen *irp, Stage1AirInstCondBr *inst) { fprintf(irp->f, "if ("); ir_print_other_inst_gen(irp, inst->condition); fprintf(irp->f, ") "); @@ -986,7 +986,7 @@ static void ir_print_cond_br(IrPrintGen *irp, IrInstGenCondBr *inst) { ir_print_other_block_gen(irp, inst->else_block); } -static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) { +static void ir_print_br(IrPrintSrc *irp, Stage1ZirInstBr *br_instruction) { fprintf(irp->f, "goto "); ir_print_other_block(irp, br_instruction->dest_block); if (br_instruction->is_comptime != nullptr) { @@ -995,17 +995,17 @@ static void ir_print_br(IrPrintSrc *irp, IrInstSrcBr *br_instruction) { } } -static void ir_print_br(IrPrintGen *irp, IrInstGenBr *inst) { +static void ir_print_br(IrPrintGen *irp, Stage1AirInstBr *inst) { fprintf(irp->f, "goto "); ir_print_other_block_gen(irp, inst->dest_block); } -static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) { +static void ir_print_phi(IrPrintSrc *irp, Stage1ZirInstPhi *phi_instruction) { assert(phi_instruction->incoming_count != 0); assert(phi_instruction->incoming_count != SIZE_MAX); for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) { Stage1ZirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i]; - IrInstSrc *incoming_value = phi_instruction->incoming_values[i]; + Stage1ZirInst *incoming_value = phi_instruction->incoming_values[i]; if (i != 0) fprintf(irp->f, " "); ir_print_other_block(irp, incoming_block); @@ -1014,12 +1014,12 @@ static void ir_print_phi(IrPrintSrc *irp, IrInstSrcPhi *phi_instruction) { } } -static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) { +static void ir_print_phi(IrPrintGen *irp, Stage1AirInstPhi *phi_instruction) { assert(phi_instruction->incoming_count != 0); assert(phi_instruction->incoming_count != SIZE_MAX); for (size_t i = 0; i < phi_instruction->incoming_count; i += 1) { - IrBasicBlockGen *incoming_block = phi_instruction->incoming_blocks[i]; - IrInstGen *incoming_value = phi_instruction->incoming_values[i]; + Stage1AirBasicBlock *incoming_block = phi_instruction->incoming_blocks[i]; + Stage1AirInst *incoming_value = phi_instruction->incoming_values[i]; if (i != 0) fprintf(irp->f, " "); ir_print_other_block_gen(irp, incoming_block); @@ -1028,13 +1028,13 @@ static void ir_print_phi(IrPrintGen *irp, IrInstGenPhi *phi_instruction) { } } -static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInitList *instruction) { +static void ir_print_container_init_list(IrPrintSrc *irp, Stage1ZirInstContainerInitList *instruction) { fprintf(irp->f, "{"); if (instruction->item_count > 50) { fprintf(irp->f, "...(%" ZIG_PRI_usize " items)...", instruction->item_count); } else { for (size_t i = 0; i < instruction->item_count; i += 1) { - IrInstSrc *result_loc = instruction->elem_result_loc_list[i]; + Stage1ZirInst *result_loc = instruction->elem_result_loc_list[i]; if (i != 0) fprintf(irp->f, ", "); ir_print_other_inst_src(irp, result_loc); @@ -1044,10 +1044,10 @@ static void ir_print_container_init_list(IrPrintSrc *irp, IrInstSrcContainerInit ir_print_other_inst_src(irp, instruction->result_loc); } -static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerInitFields *instruction) { +static void ir_print_container_init_fields(IrPrintSrc *irp, Stage1ZirInstContainerInitFields *instruction) { fprintf(irp->f, "{"); for (size_t i = 0; i < instruction->field_count; i += 1) { - IrInstSrcContainerInitFieldsField *field = &instruction->fields[i]; + Stage1ZirInstContainerInitFieldsField *field = &instruction->fields[i]; const char *comma = (i == 0) ? "" : ", "; fprintf(irp->f, "%s.%s = ", comma, buf_ptr(field->name)); ir_print_other_inst_src(irp, field->result_loc); @@ -1056,15 +1056,15 @@ static void ir_print_container_init_fields(IrPrintSrc *irp, IrInstSrcContainerIn ir_print_other_inst_src(irp, instruction->result_loc); } -static void ir_print_unreachable(IrPrintSrc *irp, IrInstSrcUnreachable *instruction) { +static void ir_print_unreachable(IrPrintSrc *irp, Stage1ZirInstUnreachable *instruction) { fprintf(irp->f, "unreachable"); } -static void ir_print_unreachable(IrPrintGen *irp, IrInstGenUnreachable *instruction) { +static void ir_print_unreachable(IrPrintGen *irp, Stage1AirInstUnreachable *instruction) { fprintf(irp->f, "unreachable"); } -static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) { +static void ir_print_elem_ptr(IrPrintSrc *irp, Stage1ZirInstElemPtr *instruction) { fprintf(irp->f, "&"); ir_print_other_inst_src(irp, instruction->array_ptr); fprintf(irp->f, "["); @@ -1075,7 +1075,7 @@ static void ir_print_elem_ptr(IrPrintSrc *irp, IrInstSrcElemPtr *instruction) { } } -static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) { +static void ir_print_elem_ptr(IrPrintGen *irp, Stage1AirInstElemPtr *instruction) { fprintf(irp->f, "&"); ir_print_other_inst_gen(irp, instruction->array_ptr); fprintf(irp->f, "["); @@ -1086,45 +1086,45 @@ static void ir_print_elem_ptr(IrPrintGen *irp, IrInstGenElemPtr *instruction) { } } -static void ir_print_var_ptr(IrPrintSrc *irp, IrInstSrcVarPtr *instruction) { +static void ir_print_var_ptr(IrPrintSrc *irp, Stage1ZirInstVarPtr *instruction) { fprintf(irp->f, "&%s", instruction->var->name); } -static void ir_print_var_ptr(IrPrintGen *irp, IrInstGenVarPtr *instruction) { +static void ir_print_var_ptr(IrPrintGen *irp, Stage1AirInstVarPtr *instruction) { fprintf(irp->f, "&%s", instruction->var->name); } -static void ir_print_return_ptr(IrPrintGen *irp, IrInstGenReturnPtr *instruction) { +static void ir_print_return_ptr(IrPrintGen *irp, Stage1AirInstReturnPtr *instruction) { fprintf(irp->f, "@ReturnPtr"); } -static void ir_print_load_ptr(IrPrintSrc *irp, IrInstSrcLoadPtr *instruction) { +static void ir_print_load_ptr(IrPrintSrc *irp, Stage1ZirInstLoadPtr *instruction) { ir_print_other_inst_src(irp, instruction->ptr); fprintf(irp->f, ".*"); } -static void ir_print_load_ptr_gen(IrPrintGen *irp, IrInstGenLoadPtr *instruction) { +static void ir_print_load_ptr_gen(IrPrintGen *irp, Stage1AirInstLoadPtr *instruction) { fprintf(irp->f, "loadptr("); ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_store_ptr(IrPrintSrc *irp, IrInstSrcStorePtr *instruction) { +static void ir_print_store_ptr(IrPrintSrc *irp, Stage1ZirInstStorePtr *instruction) { fprintf(irp->f, "*"); ir_print_var_src(irp, instruction->ptr); fprintf(irp->f, " = "); ir_print_other_inst_src(irp, instruction->value); } -static void ir_print_store_ptr(IrPrintGen *irp, IrInstGenStorePtr *instruction) { +static void ir_print_store_ptr(IrPrintGen *irp, Stage1AirInstStorePtr *instruction) { fprintf(irp->f, "*"); ir_print_var_gen(irp, instruction->ptr); fprintf(irp->f, " = "); ir_print_other_inst_gen(irp, instruction->value); } -static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem *instruction) { +static void ir_print_vector_store_elem(IrPrintGen *irp, Stage1AirInstVectorStoreElem *instruction) { fprintf(irp->f, "vector_ptr="); ir_print_var_gen(irp, instruction->vector_ptr); fprintf(irp->f, ",index="); @@ -1133,7 +1133,7 @@ static void ir_print_vector_store_elem(IrPrintGen *irp, IrInstGenVectorStoreElem ir_print_other_inst_gen(irp, instruction->value); } -static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) { +static void ir_print_typeof(IrPrintSrc *irp, Stage1ZirInstTypeOf *instruction) { fprintf(irp->f, "@TypeOf("); if (instruction->value_count == 1) { ir_print_other_inst_src(irp, instruction->value.scalar); @@ -1145,17 +1145,17 @@ static void ir_print_typeof(IrPrintSrc *irp, IrInstSrcTypeOf *instruction) { fprintf(irp->f, ")"); } -static void ir_print_binary_not(IrPrintGen *irp, IrInstGenBinaryNot *instruction) { +static void ir_print_binary_not(IrPrintGen *irp, Stage1AirInstBinaryNot *instruction) { fprintf(irp->f, "~"); ir_print_other_inst_gen(irp, instruction->operand); } -static void ir_print_negation(IrPrintGen *irp, IrInstGenNegation *instruction) { +static void ir_print_negation(IrPrintGen *irp, Stage1AirInstNegation *instruction) { fprintf(irp->f, instruction->wrapping ? "-%%" : "-"); ir_print_other_inst_gen(irp, instruction->operand); } -static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction) { +static void ir_print_field_ptr(IrPrintSrc *irp, Stage1ZirInstFieldPtr *instruction) { if (instruction->field_name_buffer) { fprintf(irp->f, "fieldptr "); ir_print_other_inst_src(irp, instruction->container_ptr); @@ -1170,33 +1170,33 @@ static void ir_print_field_ptr(IrPrintSrc *irp, IrInstSrcFieldPtr *instruction) } } -static void ir_print_struct_field_ptr(IrPrintGen *irp, IrInstGenStructFieldPtr *instruction) { +static void ir_print_struct_field_ptr(IrPrintGen *irp, Stage1AirInstStructFieldPtr *instruction) { fprintf(irp->f, "@StructFieldPtr(&"); ir_print_other_inst_gen(irp, instruction->struct_ptr); fprintf(irp->f, ".%s", buf_ptr(instruction->field->name)); fprintf(irp->f, ")"); } -static void ir_print_union_field_ptr(IrPrintGen *irp, IrInstGenUnionFieldPtr *instruction) { +static void ir_print_union_field_ptr(IrPrintGen *irp, Stage1AirInstUnionFieldPtr *instruction) { fprintf(irp->f, "@UnionFieldPtr(&"); ir_print_other_inst_gen(irp, instruction->union_ptr); fprintf(irp->f, ".%s", buf_ptr(instruction->field->enum_field->name)); fprintf(irp->f, ")"); } -static void ir_print_set_cold(IrPrintSrc *irp, IrInstSrcSetCold *instruction) { +static void ir_print_set_cold(IrPrintSrc *irp, Stage1ZirInstSetCold *instruction) { fprintf(irp->f, "@setCold("); ir_print_other_inst_src(irp, instruction->is_cold); fprintf(irp->f, ")"); } -static void ir_print_set_runtime_safety(IrPrintSrc *irp, IrInstSrcSetRuntimeSafety *instruction) { +static void ir_print_set_runtime_safety(IrPrintSrc *irp, Stage1ZirInstSetRuntimeSafety *instruction) { fprintf(irp->f, "@setRuntimeSafety("); ir_print_other_inst_src(irp, instruction->safety_on); fprintf(irp->f, ")"); } -static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *instruction) { +static void ir_print_set_float_mode(IrPrintSrc *irp, Stage1ZirInstSetFloatMode *instruction) { fprintf(irp->f, "@setFloatMode("); ir_print_other_inst_src(irp, instruction->scope_value); fprintf(irp->f, ", "); @@ -1204,7 +1204,7 @@ static void ir_print_set_float_mode(IrPrintSrc *irp, IrInstSrcSetFloatMode *inst fprintf(irp->f, ")"); } -static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction) { +static void ir_print_array_type(IrPrintSrc *irp, Stage1ZirInstArrayType *instruction) { fprintf(irp->f, "["); ir_print_other_inst_src(irp, instruction->size); if (instruction->sentinel != nullptr) { @@ -1215,13 +1215,13 @@ static void ir_print_array_type(IrPrintSrc *irp, IrInstSrcArrayType *instruction ir_print_other_inst_src(irp, instruction->child_type); } -static void ir_print_slice_type(IrPrintSrc *irp, IrInstSrcSliceType *instruction) { +static void ir_print_slice_type(IrPrintSrc *irp, Stage1ZirInstSliceType *instruction) { const char *const_kw = instruction->is_const ? "const " : ""; fprintf(irp->f, "[]%s", const_kw); ir_print_other_inst_src(irp, instruction->child_type); } -static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *instruction) { +static void ir_print_any_frame_type(IrPrintSrc *irp, Stage1ZirInstAnyFrameType *instruction) { if (instruction->payload_type == nullptr) { fprintf(irp->f, "anyframe"); } else { @@ -1230,7 +1230,7 @@ static void ir_print_any_frame_type(IrPrintSrc *irp, IrInstSrcAnyFrameType *inst } } -static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) { +static void ir_print_asm_src(IrPrintSrc *irp, Stage1ZirInstAsm *instruction) { assert(instruction->base.source_node->type == NodeTypeAsmExpr); AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr; const char *volatile_kw = instruction->has_side_effects ? " volatile" : ""; @@ -1273,7 +1273,7 @@ static void ir_print_asm_src(IrPrintSrc *irp, IrInstSrcAsm *instruction) { fprintf(irp->f, ")"); } -static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) { +static void ir_print_asm_gen(IrPrintGen *irp, Stage1AirInstAsm *instruction) { assert(instruction->base.source_node->type == NodeTypeAsmExpr); AstNodeAsmExpr *asm_expr = &instruction->base.source_node->data.asm_expr; const char *volatile_kw = instruction->has_side_effects ? " volatile" : ""; @@ -1315,7 +1315,7 @@ static void ir_print_asm_gen(IrPrintGen *irp, IrInstGenAsm *instruction) { fprintf(irp->f, ")"); } -static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) { +static void ir_print_size_of(IrPrintSrc *irp, Stage1ZirInstSizeOf *instruction) { if (instruction->bit_size) fprintf(irp->f, "@bitSizeOf("); else @@ -1324,17 +1324,17 @@ static void ir_print_size_of(IrPrintSrc *irp, IrInstSrcSizeOf *instruction) { fprintf(irp->f, ")"); } -static void ir_print_test_non_null(IrPrintSrc *irp, IrInstSrcTestNonNull *instruction) { +static void ir_print_test_non_null(IrPrintSrc *irp, Stage1ZirInstTestNonNull *instruction) { ir_print_other_inst_src(irp, instruction->value); fprintf(irp->f, " != null"); } -static void ir_print_test_non_null(IrPrintGen *irp, IrInstGenTestNonNull *instruction) { +static void ir_print_test_non_null(IrPrintGen *irp, Stage1AirInstTestNonNull *instruction) { ir_print_other_inst_gen(irp, instruction->value); fprintf(irp->f, " != null"); } -static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwrapPtr *instruction) { +static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, Stage1ZirInstOptionalUnwrapPtr *instruction) { fprintf(irp->f, "&"); ir_print_other_inst_src(irp, instruction->base_ptr); fprintf(irp->f, ".*.?"); @@ -1343,7 +1343,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintSrc *irp, IrInstSrcOptionalUnwra } } -static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwrapPtr *instruction) { +static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, Stage1AirInstOptionalUnwrapPtr *instruction) { fprintf(irp->f, "&"); ir_print_other_inst_gen(irp, instruction->base_ptr); fprintf(irp->f, ".*.?"); @@ -1352,7 +1352,7 @@ static void ir_print_optional_unwrap_ptr(IrPrintGen *irp, IrInstGenOptionalUnwra } } -static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) { +static void ir_print_clz(IrPrintSrc *irp, Stage1ZirInstClz *instruction) { fprintf(irp->f, "@clz("); ir_print_other_inst_src(irp, instruction->type); fprintf(irp->f, ","); @@ -1360,13 +1360,13 @@ static void ir_print_clz(IrPrintSrc *irp, IrInstSrcClz *instruction) { fprintf(irp->f, ")"); } -static void ir_print_clz(IrPrintGen *irp, IrInstGenClz *instruction) { +static void ir_print_clz(IrPrintGen *irp, Stage1AirInstClz *instruction) { fprintf(irp->f, "@clz("); ir_print_other_inst_gen(irp, instruction->op); fprintf(irp->f, ")"); } -static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) { +static void ir_print_ctz(IrPrintSrc *irp, Stage1ZirInstCtz *instruction) { fprintf(irp->f, "@ctz("); ir_print_other_inst_src(irp, instruction->type); fprintf(irp->f, ","); @@ -1374,13 +1374,13 @@ static void ir_print_ctz(IrPrintSrc *irp, IrInstSrcCtz *instruction) { fprintf(irp->f, ")"); } -static void ir_print_ctz(IrPrintGen *irp, IrInstGenCtz *instruction) { +static void ir_print_ctz(IrPrintGen *irp, Stage1AirInstCtz *instruction) { fprintf(irp->f, "@ctz("); ir_print_other_inst_gen(irp, instruction->op); fprintf(irp->f, ")"); } -static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction) { +static void ir_print_pop_count(IrPrintSrc *irp, Stage1ZirInstPopCount *instruction) { fprintf(irp->f, "@popCount("); ir_print_other_inst_src(irp, instruction->type); fprintf(irp->f, ","); @@ -1388,13 +1388,13 @@ static void ir_print_pop_count(IrPrintSrc *irp, IrInstSrcPopCount *instruction) fprintf(irp->f, ")"); } -static void ir_print_pop_count(IrPrintGen *irp, IrInstGenPopCount *instruction) { +static void ir_print_pop_count(IrPrintGen *irp, Stage1AirInstPopCount *instruction) { fprintf(irp->f, "@popCount("); ir_print_other_inst_gen(irp, instruction->op); fprintf(irp->f, ")"); } -static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) { +static void ir_print_bswap(IrPrintSrc *irp, Stage1ZirInstBswap *instruction) { fprintf(irp->f, "@byteSwap("); ir_print_other_inst_src(irp, instruction->type); fprintf(irp->f, ","); @@ -1402,13 +1402,13 @@ static void ir_print_bswap(IrPrintSrc *irp, IrInstSrcBswap *instruction) { fprintf(irp->f, ")"); } -static void ir_print_bswap(IrPrintGen *irp, IrInstGenBswap *instruction) { +static void ir_print_bswap(IrPrintGen *irp, Stage1AirInstBswap *instruction) { fprintf(irp->f, "@byteSwap("); ir_print_other_inst_gen(irp, instruction->op); fprintf(irp->f, ")"); } -static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instruction) { +static void ir_print_bit_reverse(IrPrintSrc *irp, Stage1ZirInstBitReverse *instruction) { fprintf(irp->f, "@bitReverse("); ir_print_other_inst_src(irp, instruction->type); fprintf(irp->f, ","); @@ -1416,18 +1416,18 @@ static void ir_print_bit_reverse(IrPrintSrc *irp, IrInstSrcBitReverse *instructi fprintf(irp->f, ")"); } -static void ir_print_bit_reverse(IrPrintGen *irp, IrInstGenBitReverse *instruction) { +static void ir_print_bit_reverse(IrPrintGen *irp, Stage1AirInstBitReverse *instruction) { fprintf(irp->f, "@bitReverse("); ir_print_other_inst_gen(irp, instruction->op); fprintf(irp->f, ")"); } -static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction) { +static void ir_print_switch_br(IrPrintSrc *irp, Stage1ZirInstSwitchBr *instruction) { fprintf(irp->f, "switch ("); ir_print_other_inst_src(irp, instruction->target_value); fprintf(irp->f, ") "); for (size_t i = 0; i < instruction->case_count; i += 1) { - IrInstSrcSwitchBrCase *this_case = &instruction->cases[i]; + Stage1ZirInstSwitchBrCase *this_case = &instruction->cases[i]; ir_print_other_inst_src(irp, this_case->value); fprintf(irp->f, " => "); ir_print_other_block(irp, this_case->block); @@ -1441,12 +1441,12 @@ static void ir_print_switch_br(IrPrintSrc *irp, IrInstSrcSwitchBr *instruction) } } -static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction) { +static void ir_print_switch_br(IrPrintGen *irp, Stage1AirInstSwitchBr *instruction) { fprintf(irp->f, "switch ("); ir_print_other_inst_gen(irp, instruction->target_value); fprintf(irp->f, ") "); for (size_t i = 0; i < instruction->case_count; i += 1) { - IrInstGenSwitchBrCase *this_case = &instruction->cases[i]; + Stage1AirInstSwitchBrCase *this_case = &instruction->cases[i]; ir_print_other_inst_gen(irp, this_case->value); fprintf(irp->f, " => "); ir_print_other_block_gen(irp, this_case->block); @@ -1456,7 +1456,7 @@ static void ir_print_switch_br(IrPrintGen *irp, IrInstGenSwitchBr *instruction) ir_print_other_block_gen(irp, instruction->else_block); } -static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction) { +static void ir_print_switch_var(IrPrintSrc *irp, Stage1ZirInstSwitchVar *instruction) { fprintf(irp->f, "switchvar "); ir_print_other_inst_src(irp, instruction->target_value_ptr); for (size_t i = 0; i < instruction->prongs_len; i += 1) { @@ -1465,79 +1465,79 @@ static void ir_print_switch_var(IrPrintSrc *irp, IrInstSrcSwitchVar *instruction } } -static void ir_print_switch_else_var(IrPrintSrc *irp, IrInstSrcSwitchElseVar *instruction) { +static void ir_print_switch_else_var(IrPrintSrc *irp, Stage1ZirInstSwitchElseVar *instruction) { fprintf(irp->f, "switchelsevar "); ir_print_other_inst_src(irp, &instruction->switch_br->base); } -static void ir_print_switch_target(IrPrintSrc *irp, IrInstSrcSwitchTarget *instruction) { +static void ir_print_switch_target(IrPrintSrc *irp, Stage1ZirInstSwitchTarget *instruction) { fprintf(irp->f, "switchtarget "); ir_print_other_inst_src(irp, instruction->target_value_ptr); } -static void ir_print_union_tag(IrPrintGen *irp, IrInstGenUnionTag *instruction) { +static void ir_print_union_tag(IrPrintGen *irp, Stage1AirInstUnionTag *instruction) { fprintf(irp->f, "uniontag "); ir_print_other_inst_gen(irp, instruction->value); } -static void ir_print_import(IrPrintSrc *irp, IrInstSrcImport *instruction) { +static void ir_print_import(IrPrintSrc *irp, Stage1ZirInstImport *instruction) { fprintf(irp->f, "@import("); ir_print_other_inst_src(irp, instruction->name); fprintf(irp->f, ")"); } -static void ir_print_ref(IrPrintSrc *irp, IrInstSrcRef *instruction) { +static void ir_print_ref(IrPrintSrc *irp, Stage1ZirInstRef *instruction) { fprintf(irp->f, "ref "); ir_print_other_inst_src(irp, instruction->value); } -static void ir_print_ref_gen(IrPrintGen *irp, IrInstGenRef *instruction) { +static void ir_print_ref_gen(IrPrintGen *irp, Stage1AirInstRef *instruction) { fprintf(irp->f, "@ref("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_compile_err(IrPrintSrc *irp, IrInstSrcCompileErr *instruction) { +static void ir_print_compile_err(IrPrintSrc *irp, Stage1ZirInstCompileErr *instruction) { fprintf(irp->f, "@compileError("); ir_print_other_inst_src(irp, instruction->msg); fprintf(irp->f, ")"); } -static void ir_print_compile_log(IrPrintSrc *irp, IrInstSrcCompileLog *instruction) { +static void ir_print_compile_log(IrPrintSrc *irp, Stage1ZirInstCompileLog *instruction) { fprintf(irp->f, "@compileLog("); for (size_t i = 0; i < instruction->msg_count; i += 1) { if (i != 0) fprintf(irp->f, ","); - IrInstSrc *msg = instruction->msg_list[i]; + Stage1ZirInst *msg = instruction->msg_list[i]; ir_print_other_inst_src(irp, msg); } fprintf(irp->f, ")"); } -static void ir_print_err_name(IrPrintSrc *irp, IrInstSrcErrName *instruction) { +static void ir_print_err_name(IrPrintSrc *irp, Stage1ZirInstErrName *instruction) { fprintf(irp->f, "@errorName("); ir_print_other_inst_src(irp, instruction->value); fprintf(irp->f, ")"); } -static void ir_print_err_name(IrPrintGen *irp, IrInstGenErrName *instruction) { +static void ir_print_err_name(IrPrintGen *irp, Stage1AirInstErrName *instruction) { fprintf(irp->f, "@errorName("); ir_print_other_inst_gen(irp, instruction->value); fprintf(irp->f, ")"); } -static void ir_print_c_import(IrPrintSrc *irp, IrInstSrcCImport *instruction) { +static void ir_print_c_import(IrPrintSrc *irp, Stage1ZirInstCImport *instruction) { fprintf(irp->f, "@cImport(...)"); } -static void ir_print_c_include(IrPrintSrc *irp, IrInstSrcCInclude *instruction) { +static void ir_print_c_include(IrPrintSrc *irp, Stage1ZirInstCInclude *instruction) { fprintf(irp->f, "@cInclude("); ir_print_other_inst_src(irp, instruction->name); fprintf(irp->f, ")"); } -static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) { +static void ir_print_c_define(IrPrintSrc *irp, Stage1ZirInstCDefine *instruction) { fprintf(irp->f, "@cDefine("); ir_print_other_inst_src(irp, instruction->name); fprintf(irp->f, ", "); @@ -1545,19 +1545,19 @@ static void ir_print_c_define(IrPrintSrc *irp, IrInstSrcCDefine *instruction) { fprintf(irp->f, ")"); } -static void ir_print_c_undef(IrPrintSrc *irp, IrInstSrcCUndef *instruction) { +static void ir_print_c_undef(IrPrintSrc *irp, Stage1ZirInstCUndef *instruction) { fprintf(irp->f, "@cUndef("); ir_print_other_inst_src(irp, instruction->name); fprintf(irp->f, ")"); } -static void ir_print_embed_file(IrPrintSrc *irp, IrInstSrcEmbedFile *instruction) { +static void ir_print_embed_file(IrPrintSrc *irp, Stage1ZirInstEmbedFile *instruction) { fprintf(irp->f, "@embedFile("); ir_print_other_inst_src(irp, instruction->name); fprintf(irp->f, ")"); } -static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction) { +static void ir_print_cmpxchg_src(IrPrintSrc *irp, Stage1ZirInstCmpxchg *instruction) { fprintf(irp->f, "@cmpxchg("); ir_print_other_inst_src(irp, instruction->ptr); fprintf(irp->f, ", "); @@ -1572,7 +1572,7 @@ static void ir_print_cmpxchg_src(IrPrintSrc *irp, IrInstSrcCmpxchg *instruction) ir_print_result_loc(irp, instruction->result_loc); } -static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction) { +static void ir_print_cmpxchg_gen(IrPrintGen *irp, Stage1AirInstCmpxchg *instruction) { fprintf(irp->f, "@cmpxchg("); ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, ", "); @@ -1583,13 +1583,13 @@ static void ir_print_cmpxchg_gen(IrPrintGen *irp, IrInstGenCmpxchg *instruction) ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_fence(IrPrintSrc *irp, IrInstSrcFence *instruction) { +static void ir_print_fence(IrPrintSrc *irp, Stage1ZirInstFence *instruction) { fprintf(irp->f, "@fence("); ir_print_other_inst_src(irp, instruction->order); fprintf(irp->f, ")"); } -static void ir_print_reduce(IrPrintSrc *irp, IrInstSrcReduce *instruction) { +static void ir_print_reduce(IrPrintSrc *irp, Stage1ZirInstReduce *instruction) { fprintf(irp->f, "@reduce("); ir_print_other_inst_src(irp, instruction->op); fprintf(irp->f, ", "); @@ -1609,7 +1609,7 @@ static const char *atomic_order_str(AtomicOrder order) { zig_unreachable(); } -static void ir_print_fence(IrPrintGen *irp, IrInstGenFence *instruction) { +static void ir_print_fence(IrPrintGen *irp, Stage1AirInstFence *instruction) { fprintf(irp->f, "fence %s", atomic_order_str(instruction->order)); } @@ -1626,13 +1626,13 @@ static const char *reduce_op_str(ReduceOp op) { zig_unreachable(); } -static void ir_print_reduce(IrPrintGen *irp, IrInstGenReduce *instruction) { +static void ir_print_reduce(IrPrintGen *irp, Stage1AirInstReduce *instruction) { fprintf(irp->f, "@reduce(.%s, ", reduce_op_str(instruction->op)); ir_print_other_inst_gen(irp, instruction->value); fprintf(irp->f, ")"); } -static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) { +static void ir_print_truncate(IrPrintSrc *irp, Stage1ZirInstTruncate *instruction) { fprintf(irp->f, "@truncate("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ", "); @@ -1640,13 +1640,13 @@ static void ir_print_truncate(IrPrintSrc *irp, IrInstSrcTruncate *instruction) { fprintf(irp->f, ")"); } -static void ir_print_truncate(IrPrintGen *irp, IrInstGenTruncate *instruction) { +static void ir_print_truncate(IrPrintGen *irp, Stage1AirInstTruncate *instruction) { fprintf(irp->f, "@truncate("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) { +static void ir_print_int_cast(IrPrintSrc *irp, Stage1ZirInstIntCast *instruction) { fprintf(irp->f, "@intCast("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ", "); @@ -1654,7 +1654,7 @@ static void ir_print_int_cast(IrPrintSrc *irp, IrInstSrcIntCast *instruction) { fprintf(irp->f, ")"); } -static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction) { +static void ir_print_float_cast(IrPrintSrc *irp, Stage1ZirInstFloatCast *instruction) { fprintf(irp->f, "@floatCast("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ", "); @@ -1662,7 +1662,7 @@ static void ir_print_float_cast(IrPrintSrc *irp, IrInstSrcFloatCast *instruction fprintf(irp->f, ")"); } -static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruction) { +static void ir_print_err_set_cast(IrPrintSrc *irp, Stage1ZirInstErrSetCast *instruction) { fprintf(irp->f, "@errSetCast("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ", "); @@ -1670,7 +1670,7 @@ static void ir_print_err_set_cast(IrPrintSrc *irp, IrInstSrcErrSetCast *instruct fprintf(irp->f, ")"); } -static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruction) { +static void ir_print_int_to_float(IrPrintSrc *irp, Stage1ZirInstIntToFloat *instruction) { fprintf(irp->f, "@intToFloat("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ", "); @@ -1678,7 +1678,7 @@ static void ir_print_int_to_float(IrPrintSrc *irp, IrInstSrcIntToFloat *instruct fprintf(irp->f, ")"); } -static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruction) { +static void ir_print_float_to_int(IrPrintSrc *irp, Stage1ZirInstFloatToInt *instruction) { fprintf(irp->f, "@floatToInt("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ", "); @@ -1686,13 +1686,13 @@ static void ir_print_float_to_int(IrPrintSrc *irp, IrInstSrcFloatToInt *instruct fprintf(irp->f, ")"); } -static void ir_print_bool_to_int(IrPrintSrc *irp, IrInstSrcBoolToInt *instruction) { +static void ir_print_bool_to_int(IrPrintSrc *irp, Stage1ZirInstBoolToInt *instruction) { fprintf(irp->f, "@boolToInt("); ir_print_other_inst_src(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instruction) { +static void ir_print_vector_type(IrPrintSrc *irp, Stage1ZirInstVectorType *instruction) { fprintf(irp->f, "@Vector("); ir_print_other_inst_src(irp, instruction->len); fprintf(irp->f, ", "); @@ -1700,7 +1700,7 @@ static void ir_print_vector_type(IrPrintSrc *irp, IrInstSrcVectorType *instructi fprintf(irp->f, ")"); } -static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *instruction) { +static void ir_print_shuffle_vector(IrPrintSrc *irp, Stage1ZirInstShuffleVector *instruction) { fprintf(irp->f, "@shuffle("); ir_print_other_inst_src(irp, instruction->scalar_type); fprintf(irp->f, ", "); @@ -1712,7 +1712,7 @@ static void ir_print_shuffle_vector(IrPrintSrc *irp, IrInstSrcShuffleVector *ins fprintf(irp->f, ")"); } -static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *instruction) { +static void ir_print_shuffle_vector(IrPrintGen *irp, Stage1AirInstShuffleVector *instruction) { fprintf(irp->f, "@shuffle("); ir_print_other_inst_gen(irp, instruction->a); fprintf(irp->f, ", "); @@ -1722,7 +1722,7 @@ static void ir_print_shuffle_vector(IrPrintGen *irp, IrInstGenShuffleVector *ins fprintf(irp->f, ")"); } -static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) { +static void ir_print_splat_src(IrPrintSrc *irp, Stage1ZirInstSplat *instruction) { fprintf(irp->f, "@splat("); ir_print_other_inst_src(irp, instruction->len); fprintf(irp->f, ", "); @@ -1730,35 +1730,35 @@ static void ir_print_splat_src(IrPrintSrc *irp, IrInstSrcSplat *instruction) { fprintf(irp->f, ")"); } -static void ir_print_splat_gen(IrPrintGen *irp, IrInstGenSplat *instruction) { +static void ir_print_splat_gen(IrPrintGen *irp, Stage1AirInstSplat *instruction) { fprintf(irp->f, "@splat("); ir_print_other_inst_gen(irp, instruction->scalar); fprintf(irp->f, ")"); } -static void ir_print_bool_not(IrPrintSrc *irp, IrInstSrcBoolNot *instruction) { +static void ir_print_bool_not(IrPrintSrc *irp, Stage1ZirInstBoolNot *instruction) { fprintf(irp->f, "! "); ir_print_other_inst_src(irp, instruction->value); } -static void ir_print_bool_not(IrPrintGen *irp, IrInstGenBoolNot *instruction) { +static void ir_print_bool_not(IrPrintGen *irp, Stage1AirInstBoolNot *instruction) { fprintf(irp->f, "! "); ir_print_other_inst_gen(irp, instruction->value); } -static void ir_print_wasm_memory_size(IrPrintSrc *irp, IrInstSrcWasmMemorySize *instruction) { +static void ir_print_wasm_memory_size(IrPrintSrc *irp, Stage1ZirInstWasmMemorySize *instruction) { fprintf(irp->f, "@wasmMemorySize("); ir_print_other_inst_src(irp, instruction->index); fprintf(irp->f, ")"); } -static void ir_print_wasm_memory_size(IrPrintGen *irp, IrInstGenWasmMemorySize *instruction) { +static void ir_print_wasm_memory_size(IrPrintGen *irp, Stage1AirInstWasmMemorySize *instruction) { fprintf(irp->f, "@wasmMemorySize("); ir_print_other_inst_gen(irp, instruction->index); fprintf(irp->f, ")"); } -static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow *instruction) { +static void ir_print_wasm_memory_grow(IrPrintSrc *irp, Stage1ZirInstWasmMemoryGrow *instruction) { fprintf(irp->f, "@wasmMemoryGrow("); ir_print_other_inst_src(irp, instruction->index); fprintf(irp->f, ", "); @@ -1766,7 +1766,7 @@ static void ir_print_wasm_memory_grow(IrPrintSrc *irp, IrInstSrcWasmMemoryGrow * fprintf(irp->f, ")"); } -static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow *instruction) { +static void ir_print_wasm_memory_grow(IrPrintGen *irp, Stage1AirInstWasmMemoryGrow *instruction) { fprintf(irp->f, "@wasmMemoryGrow("); ir_print_other_inst_gen(irp, instruction->index); fprintf(irp->f, ", "); @@ -1774,11 +1774,11 @@ static void ir_print_wasm_memory_grow(IrPrintGen *irp, IrInstGenWasmMemoryGrow * fprintf(irp->f, ")"); } -static void ir_print_builtin_src(IrPrintSrc *irp, IrInstSrcSrc *instruction) { +static void ir_print_builtin_src(IrPrintSrc *irp, Stage1ZirInstSrc *instruction) { fprintf(irp->f, "@src()"); } -static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) { +static void ir_print_memset(IrPrintSrc *irp, Stage1ZirInstMemset *instruction) { fprintf(irp->f, "@memset("); ir_print_other_inst_src(irp, instruction->dest_ptr); fprintf(irp->f, ", "); @@ -1788,7 +1788,7 @@ static void ir_print_memset(IrPrintSrc *irp, IrInstSrcMemset *instruction) { fprintf(irp->f, ")"); } -static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) { +static void ir_print_memset(IrPrintGen *irp, Stage1AirInstMemset *instruction) { fprintf(irp->f, "@memset("); ir_print_other_inst_gen(irp, instruction->dest_ptr); fprintf(irp->f, ", "); @@ -1798,7 +1798,7 @@ static void ir_print_memset(IrPrintGen *irp, IrInstGenMemset *instruction) { fprintf(irp->f, ")"); } -static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) { +static void ir_print_memcpy(IrPrintSrc *irp, Stage1ZirInstMemcpy *instruction) { fprintf(irp->f, "@memcpy("); ir_print_other_inst_src(irp, instruction->dest_ptr); fprintf(irp->f, ", "); @@ -1808,7 +1808,7 @@ static void ir_print_memcpy(IrPrintSrc *irp, IrInstSrcMemcpy *instruction) { fprintf(irp->f, ")"); } -static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) { +static void ir_print_memcpy(IrPrintGen *irp, Stage1AirInstMemcpy *instruction) { fprintf(irp->f, "@memcpy("); ir_print_other_inst_gen(irp, instruction->dest_ptr); fprintf(irp->f, ", "); @@ -1818,7 +1818,7 @@ static void ir_print_memcpy(IrPrintGen *irp, IrInstGenMemcpy *instruction) { fprintf(irp->f, ")"); } -static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) { +static void ir_print_slice_src(IrPrintSrc *irp, Stage1ZirInstSlice *instruction) { ir_print_other_inst_src(irp, instruction->ptr); fprintf(irp->f, "["); ir_print_other_inst_src(irp, instruction->start); @@ -1829,7 +1829,7 @@ static void ir_print_slice_src(IrPrintSrc *irp, IrInstSrcSlice *instruction) { ir_print_result_loc(irp, instruction->result_loc); } -static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) { +static void ir_print_slice_gen(IrPrintGen *irp, Stage1AirInstSlice *instruction) { ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, "["); ir_print_other_inst_gen(irp, instruction->start); @@ -1840,63 +1840,63 @@ static void ir_print_slice_gen(IrPrintGen *irp, IrInstGenSlice *instruction) { ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_breakpoint(IrPrintSrc *irp, IrInstSrcBreakpoint *instruction) { +static void ir_print_breakpoint(IrPrintSrc *irp, Stage1ZirInstBreakpoint *instruction) { fprintf(irp->f, "@breakpoint()"); } -static void ir_print_breakpoint(IrPrintGen *irp, IrInstGenBreakpoint *instruction) { +static void ir_print_breakpoint(IrPrintGen *irp, Stage1AirInstBreakpoint *instruction) { fprintf(irp->f, "@breakpoint()"); } -static void ir_print_frame_address(IrPrintSrc *irp, IrInstSrcFrameAddress *instruction) { +static void ir_print_frame_address(IrPrintSrc *irp, Stage1ZirInstFrameAddress *instruction) { fprintf(irp->f, "@frameAddress()"); } -static void ir_print_frame_address(IrPrintGen *irp, IrInstGenFrameAddress *instruction) { +static void ir_print_frame_address(IrPrintGen *irp, Stage1AirInstFrameAddress *instruction) { fprintf(irp->f, "@frameAddress()"); } -static void ir_print_handle(IrPrintSrc *irp, IrInstSrcFrameHandle *instruction) { +static void ir_print_handle(IrPrintSrc *irp, Stage1ZirInstFrameHandle *instruction) { fprintf(irp->f, "@frame()"); } -static void ir_print_handle(IrPrintGen *irp, IrInstGenFrameHandle *instruction) { +static void ir_print_handle(IrPrintGen *irp, Stage1AirInstFrameHandle *instruction) { fprintf(irp->f, "@frame()"); } -static void ir_print_frame_type(IrPrintSrc *irp, IrInstSrcFrameType *instruction) { +static void ir_print_frame_type(IrPrintSrc *irp, Stage1ZirInstFrameType *instruction) { fprintf(irp->f, "@Frame("); ir_print_other_inst_src(irp, instruction->fn); fprintf(irp->f, ")"); } -static void ir_print_frame_size_src(IrPrintSrc *irp, IrInstSrcFrameSize *instruction) { +static void ir_print_frame_size_src(IrPrintSrc *irp, Stage1ZirInstFrameSize *instruction) { fprintf(irp->f, "@frameSize("); ir_print_other_inst_src(irp, instruction->fn); fprintf(irp->f, ")"); } -static void ir_print_frame_size_gen(IrPrintGen *irp, IrInstGenFrameSize *instruction) { +static void ir_print_frame_size_gen(IrPrintGen *irp, Stage1AirInstFrameSize *instruction) { fprintf(irp->f, "@frameSize("); ir_print_other_inst_gen(irp, instruction->fn); fprintf(irp->f, ")"); } -static void ir_print_return_address(IrPrintSrc *irp, IrInstSrcReturnAddress *instruction) { +static void ir_print_return_address(IrPrintSrc *irp, Stage1ZirInstReturnAddress *instruction) { fprintf(irp->f, "@returnAddress()"); } -static void ir_print_return_address(IrPrintGen *irp, IrInstGenReturnAddress *instruction) { +static void ir_print_return_address(IrPrintGen *irp, Stage1AirInstReturnAddress *instruction) { fprintf(irp->f, "@returnAddress()"); } -static void ir_print_align_of(IrPrintSrc *irp, IrInstSrcAlignOf *instruction) { +static void ir_print_align_of(IrPrintSrc *irp, Stage1ZirInstAlignOf *instruction) { fprintf(irp->f, "@alignOf("); ir_print_other_inst_src(irp, instruction->type_value); fprintf(irp->f, ")"); } -static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instruction) { +static void ir_print_overflow_op(IrPrintSrc *irp, Stage1ZirInstOverflowOp *instruction) { switch (instruction->op) { case IrOverflowOpAdd: fprintf(irp->f, "@addWithOverflow("); @@ -1921,7 +1921,7 @@ static void ir_print_overflow_op(IrPrintSrc *irp, IrInstSrcOverflowOp *instructi fprintf(irp->f, ")"); } -static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instruction) { +static void ir_print_overflow_op(IrPrintGen *irp, Stage1AirInstOverflowOp *instruction) { switch (instruction->op) { case IrOverflowOpAdd: fprintf(irp->f, "@addWithOverflow("); @@ -1944,64 +1944,64 @@ static void ir_print_overflow_op(IrPrintGen *irp, IrInstGenOverflowOp *instructi fprintf(irp->f, ")"); } -static void ir_print_test_err_src(IrPrintSrc *irp, IrInstSrcTestErr *instruction) { +static void ir_print_test_err_src(IrPrintSrc *irp, Stage1ZirInstTestErr *instruction) { fprintf(irp->f, "@testError("); ir_print_other_inst_src(irp, instruction->base_ptr); fprintf(irp->f, ")"); } -static void ir_print_test_err_gen(IrPrintGen *irp, IrInstGenTestErr *instruction) { +static void ir_print_test_err_gen(IrPrintGen *irp, Stage1AirInstTestErr *instruction) { fprintf(irp->f, "@testError("); ir_print_other_inst_gen(irp, instruction->err_union); fprintf(irp->f, ")"); } -static void ir_print_unwrap_err_code(IrPrintSrc *irp, IrInstSrcUnwrapErrCode *instruction) { +static void ir_print_unwrap_err_code(IrPrintSrc *irp, Stage1ZirInstUnwrapErrCode *instruction) { fprintf(irp->f, "UnwrapErrorCode("); ir_print_other_inst_src(irp, instruction->err_union_ptr); fprintf(irp->f, ")"); } -static void ir_print_unwrap_err_code(IrPrintGen *irp, IrInstGenUnwrapErrCode *instruction) { +static void ir_print_unwrap_err_code(IrPrintGen *irp, Stage1AirInstUnwrapErrCode *instruction) { fprintf(irp->f, "UnwrapErrorCode("); ir_print_other_inst_gen(irp, instruction->err_union_ptr); fprintf(irp->f, ")"); } -static void ir_print_unwrap_err_payload(IrPrintSrc *irp, IrInstSrcUnwrapErrPayload *instruction) { +static void ir_print_unwrap_err_payload(IrPrintSrc *irp, Stage1ZirInstUnwrapErrPayload *instruction) { fprintf(irp->f, "ErrorUnionFieldPayload("); ir_print_other_inst_src(irp, instruction->value); fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing); } -static void ir_print_unwrap_err_payload(IrPrintGen *irp, IrInstGenUnwrapErrPayload *instruction) { +static void ir_print_unwrap_err_payload(IrPrintGen *irp, Stage1AirInstUnwrapErrPayload *instruction) { fprintf(irp->f, "ErrorUnionFieldPayload("); ir_print_other_inst_gen(irp, instruction->value); fprintf(irp->f, ")safety=%d,init=%d",instruction->safety_check_on, instruction->initializing); } -static void ir_print_optional_wrap(IrPrintGen *irp, IrInstGenOptionalWrap *instruction) { +static void ir_print_optional_wrap(IrPrintGen *irp, Stage1AirInstOptionalWrap *instruction) { fprintf(irp->f, "@optionalWrap("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_err_wrap_code(IrPrintGen *irp, IrInstGenErrWrapCode *instruction) { +static void ir_print_err_wrap_code(IrPrintGen *irp, Stage1AirInstErrWrapCode *instruction) { fprintf(irp->f, "@errWrapCode("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_err_wrap_payload(IrPrintGen *irp, IrInstGenErrWrapPayload *instruction) { +static void ir_print_err_wrap_payload(IrPrintGen *irp, Stage1AirInstErrWrapPayload *instruction) { fprintf(irp->f, "@errWrapPayload("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) { +static void ir_print_fn_proto(IrPrintSrc *irp, Stage1ZirInstFnProto *instruction) { fprintf(irp->f, "fn("); for (size_t i = 0; i < instruction->base.source_node->data.fn_proto.params.length; i += 1) { if (i != 0) @@ -2022,13 +2022,13 @@ static void ir_print_fn_proto(IrPrintSrc *irp, IrInstSrcFnProto *instruction) { ir_print_other_inst_src(irp, instruction->return_type); } -static void ir_print_test_comptime(IrPrintSrc *irp, IrInstSrcTestComptime *instruction) { +static void ir_print_test_comptime(IrPrintSrc *irp, Stage1ZirInstTestComptime *instruction) { fprintf(irp->f, "@testComptime("); ir_print_other_inst_src(irp, instruction->value); fprintf(irp->f, ")"); } -static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction) { +static void ir_print_ptr_cast_src(IrPrintSrc *irp, Stage1ZirInstPtrCast *instruction) { fprintf(irp->f, "@ptrCast("); if (instruction->dest_type) { ir_print_other_inst_src(irp, instruction->dest_type); @@ -2038,51 +2038,51 @@ static void ir_print_ptr_cast_src(IrPrintSrc *irp, IrInstSrcPtrCast *instruction fprintf(irp->f, ")"); } -static void ir_print_ptr_cast_gen(IrPrintGen *irp, IrInstGenPtrCast *instruction) { +static void ir_print_ptr_cast_gen(IrPrintGen *irp, Stage1AirInstPtrCast *instruction) { fprintf(irp->f, "@ptrCast("); ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, ")"); } -static void ir_print_implicit_cast(IrPrintSrc *irp, IrInstSrcImplicitCast *instruction) { +static void ir_print_implicit_cast(IrPrintSrc *irp, Stage1ZirInstImplicitCast *instruction) { fprintf(irp->f, "@implicitCast("); ir_print_other_inst_src(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_result_loc(irp, &instruction->result_loc_cast->base); } -static void ir_print_bit_cast_src(IrPrintSrc *irp, IrInstSrcBitCast *instruction) { +static void ir_print_bit_cast_src(IrPrintSrc *irp, Stage1ZirInstBitCast *instruction) { fprintf(irp->f, "@bitCast("); ir_print_other_inst_src(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_result_loc(irp, &instruction->result_loc_bit_cast->base); } -static void ir_print_bit_cast_gen(IrPrintGen *irp, IrInstGenBitCast *instruction) { +static void ir_print_bit_cast_gen(IrPrintGen *irp, Stage1AirInstBitCast *instruction) { fprintf(irp->f, "@bitCast("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")"); } -static void ir_print_widen_or_shorten(IrPrintGen *irp, IrInstGenWidenOrShorten *instruction) { +static void ir_print_widen_or_shorten(IrPrintGen *irp, Stage1AirInstWidenOrShorten *instruction) { fprintf(irp->f, "WidenOrShorten("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_ptr_to_int(IrPrintSrc *irp, IrInstSrcPtrToInt *instruction) { +static void ir_print_ptr_to_int(IrPrintSrc *irp, Stage1ZirInstPtrToInt *instruction) { fprintf(irp->f, "@ptrToInt("); ir_print_other_inst_src(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_ptr_to_int(IrPrintGen *irp, IrInstGenPtrToInt *instruction) { +static void ir_print_ptr_to_int(IrPrintGen *irp, Stage1AirInstPtrToInt *instruction) { fprintf(irp->f, "@ptrToInt("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction) { +static void ir_print_int_to_ptr(IrPrintSrc *irp, Stage1ZirInstIntToPtr *instruction) { fprintf(irp->f, "@intToPtr("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ","); @@ -2090,13 +2090,13 @@ static void ir_print_int_to_ptr(IrPrintSrc *irp, IrInstSrcIntToPtr *instruction) fprintf(irp->f, ")"); } -static void ir_print_int_to_ptr(IrPrintGen *irp, IrInstGenIntToPtr *instruction) { +static void ir_print_int_to_ptr(IrPrintGen *irp, Stage1AirInstIntToPtr *instruction) { fprintf(irp->f, "@intToPtr("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instruction) { +static void ir_print_int_to_enum(IrPrintSrc *irp, Stage1ZirInstIntToEnum *instruction) { fprintf(irp->f, "@intToEnum("); ir_print_other_inst_src(irp, instruction->dest_type); fprintf(irp->f, ","); @@ -2104,19 +2104,19 @@ static void ir_print_int_to_enum(IrPrintSrc *irp, IrInstSrcIntToEnum *instructio fprintf(irp->f, ")"); } -static void ir_print_int_to_enum(IrPrintGen *irp, IrInstGenIntToEnum *instruction) { +static void ir_print_int_to_enum(IrPrintGen *irp, Stage1AirInstIntToEnum *instruction) { fprintf(irp->f, "@intToEnum("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_enum_to_int(IrPrintSrc *irp, IrInstSrcEnumToInt *instruction) { +static void ir_print_enum_to_int(IrPrintSrc *irp, Stage1ZirInstEnumToInt *instruction) { fprintf(irp->f, "@enumToInt("); ir_print_other_inst_src(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeScope *instruction) { +static void ir_print_check_runtime_scope(IrPrintSrc *irp, Stage1ZirInstCheckRuntimeScope *instruction) { fprintf(irp->f, "@checkRuntimeScope("); ir_print_other_inst_src(irp, instruction->scope_is_comptime); fprintf(irp->f, ","); @@ -2124,49 +2124,49 @@ static void ir_print_check_runtime_scope(IrPrintSrc *irp, IrInstSrcCheckRuntimeS fprintf(irp->f, ")"); } -static void ir_print_array_to_vector(IrPrintGen *irp, IrInstGenArrayToVector *instruction) { +static void ir_print_array_to_vector(IrPrintGen *irp, Stage1AirInstArrayToVector *instruction) { fprintf(irp->f, "ArrayToVector("); ir_print_other_inst_gen(irp, instruction->array); fprintf(irp->f, ")"); } -static void ir_print_vector_to_array(IrPrintGen *irp, IrInstGenVectorToArray *instruction) { +static void ir_print_vector_to_array(IrPrintGen *irp, Stage1AirInstVectorToArray *instruction) { fprintf(irp->f, "VectorToArray("); ir_print_other_inst_gen(irp, instruction->vector); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_ptr_of_array_to_slice(IrPrintGen *irp, IrInstGenPtrOfArrayToSlice *instruction) { +static void ir_print_ptr_of_array_to_slice(IrPrintGen *irp, Stage1AirInstPtrOfArrayToSlice *instruction) { fprintf(irp->f, "PtrOfArrayToSlice("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")result="); ir_print_other_inst_gen(irp, instruction->result_loc); } -static void ir_print_assert_zero(IrPrintGen *irp, IrInstGenAssertZero *instruction) { +static void ir_print_assert_zero(IrPrintGen *irp, Stage1AirInstAssertZero *instruction) { fprintf(irp->f, "AssertZero("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_assert_non_null(IrPrintGen *irp, IrInstGenAssertNonNull *instruction) { +static void ir_print_assert_non_null(IrPrintGen *irp, Stage1AirInstAssertNonNull *instruction) { fprintf(irp->f, "AssertNonNull("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_alloca_src(IrPrintSrc *irp, IrInstSrcAlloca *instruction) { +static void ir_print_alloca_src(IrPrintSrc *irp, Stage1ZirInstAlloca *instruction) { fprintf(irp->f, "Alloca(align="); ir_print_other_inst_src(irp, instruction->align); fprintf(irp->f, ",name=%s)", instruction->name_hint); } -static void ir_print_alloca_gen(IrPrintGen *irp, IrInstGenAlloca *instruction) { +static void ir_print_alloca_gen(IrPrintGen *irp, Stage1AirInstAlloca *instruction) { fprintf(irp->f, "Alloca(align=%" PRIu32 ",name=%s)", instruction->align, instruction->name_hint); } -static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) { +static void ir_print_end_expr(IrPrintSrc *irp, Stage1ZirInstEndExpr *instruction) { fprintf(irp->f, "EndExpr(result="); ir_print_result_loc(irp, instruction->result_loc); fprintf(irp->f, ",value="); @@ -2174,27 +2174,27 @@ static void ir_print_end_expr(IrPrintSrc *irp, IrInstSrcEndExpr *instruction) { fprintf(irp->f, ")"); } -static void ir_print_int_to_err(IrPrintSrc *irp, IrInstSrcIntToErr *instruction) { +static void ir_print_int_to_err(IrPrintSrc *irp, Stage1ZirInstIntToErr *instruction) { fprintf(irp->f, "inttoerr "); ir_print_other_inst_src(irp, instruction->target); } -static void ir_print_int_to_err(IrPrintGen *irp, IrInstGenIntToErr *instruction) { +static void ir_print_int_to_err(IrPrintGen *irp, Stage1AirInstIntToErr *instruction) { fprintf(irp->f, "inttoerr "); ir_print_other_inst_gen(irp, instruction->target); } -static void ir_print_err_to_int(IrPrintSrc *irp, IrInstSrcErrToInt *instruction) { +static void ir_print_err_to_int(IrPrintSrc *irp, Stage1ZirInstErrToInt *instruction) { fprintf(irp->f, "errtoint "); ir_print_other_inst_src(irp, instruction->target); } -static void ir_print_err_to_int(IrPrintGen *irp, IrInstGenErrToInt *instruction) { +static void ir_print_err_to_int(IrPrintGen *irp, Stage1AirInstErrToInt *instruction) { fprintf(irp->f, "errtoint "); ir_print_other_inst_gen(irp, instruction->target); } -static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchProngs *instruction, +static void ir_print_check_switch_prongs(IrPrintSrc *irp, Stage1ZirInstCheckSwitchProngs *instruction, bool have_underscore_prong) { fprintf(irp->f, "@checkSwitchProngs("); @@ -2213,28 +2213,28 @@ static void ir_print_check_switch_prongs(IrPrintSrc *irp, IrInstSrcCheckSwitchPr fprintf(irp->f, " _:%s", have_under_str); } -static void ir_print_check_statement_is_void(IrPrintSrc *irp, IrInstSrcCheckStatementIsVoid *instruction) { +static void ir_print_check_statement_is_void(IrPrintSrc *irp, Stage1ZirInstCheckStatementIsVoid *instruction) { fprintf(irp->f, "@checkStatementIsVoid("); ir_print_other_inst_src(irp, instruction->statement_value); fprintf(irp->f, ")"); } -static void ir_print_type_name(IrPrintSrc *irp, IrInstSrcTypeName *instruction) { +static void ir_print_type_name(IrPrintSrc *irp, Stage1ZirInstTypeName *instruction) { fprintf(irp->f, "typename "); ir_print_other_inst_src(irp, instruction->type_value); } -static void ir_print_tag_name(IrPrintSrc *irp, IrInstSrcTagName *instruction) { +static void ir_print_tag_name(IrPrintSrc *irp, Stage1ZirInstTagName *instruction) { fprintf(irp->f, "tagname "); ir_print_other_inst_src(irp, instruction->target); } -static void ir_print_tag_name(IrPrintGen *irp, IrInstGenTagName *instruction) { +static void ir_print_tag_name(IrPrintGen *irp, Stage1AirInstTagName *instruction) { fprintf(irp->f, "tagname "); ir_print_other_inst_gen(irp, instruction->target); } -static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) { +static void ir_print_ptr_type(IrPrintSrc *irp, Stage1ZirInstPtrType *instruction) { fprintf(irp->f, "&"); if (instruction->align_value != nullptr) { fprintf(irp->f, "align("); @@ -2248,7 +2248,7 @@ static void ir_print_ptr_type(IrPrintSrc *irp, IrInstSrcPtrType *instruction) { ir_print_other_inst_src(irp, instruction->child_type); } -static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *instruction, +static void ir_print_ptr_type_simple(IrPrintSrc *irp, Stage1ZirInstPtrTypeSimple *instruction, bool is_const) { fprintf(irp->f, "&"); @@ -2257,24 +2257,24 @@ static void ir_print_ptr_type_simple(IrPrintSrc *irp, IrInstSrcPtrTypeSimple *in ir_print_other_inst_src(irp, instruction->child_type); } -static void ir_print_decl_ref(IrPrintSrc *irp, IrInstSrcDeclRef *instruction) { +static void ir_print_decl_ref(IrPrintSrc *irp, Stage1ZirInstDeclRef *instruction) { const char *ptr_str = (instruction->lval != LValNone) ? "ptr " : ""; fprintf(irp->f, "declref %s%s", ptr_str, buf_ptr(instruction->tld->name)); } -static void ir_print_panic(IrPrintSrc *irp, IrInstSrcPanic *instruction) { +static void ir_print_panic(IrPrintSrc *irp, Stage1ZirInstPanic *instruction) { fprintf(irp->f, "@panic("); ir_print_other_inst_src(irp, instruction->msg); fprintf(irp->f, ")"); } -static void ir_print_panic(IrPrintGen *irp, IrInstGenPanic *instruction) { +static void ir_print_panic(IrPrintGen *irp, Stage1AirInstPanic *instruction) { fprintf(irp->f, "@panic("); ir_print_other_inst_gen(irp, instruction->msg); fprintf(irp->f, ")"); } -static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr *instruction) { +static void ir_print_field_parent_ptr(IrPrintSrc *irp, Stage1ZirInstFieldParentPtr *instruction) { fprintf(irp->f, "@fieldParentPtr("); ir_print_other_inst_src(irp, instruction->type_value); fprintf(irp->f, ","); @@ -2284,13 +2284,13 @@ static void ir_print_field_parent_ptr(IrPrintSrc *irp, IrInstSrcFieldParentPtr * fprintf(irp->f, ")"); } -static void ir_print_field_parent_ptr(IrPrintGen *irp, IrInstGenFieldParentPtr *instruction) { +static void ir_print_field_parent_ptr(IrPrintGen *irp, Stage1AirInstFieldParentPtr *instruction) { fprintf(irp->f, "@fieldParentPtr(%s,", buf_ptr(instruction->field->name)); ir_print_other_inst_gen(irp, instruction->field_ptr); fprintf(irp->f, ")"); } -static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction) { +static void ir_print_offset_of(IrPrintSrc *irp, Stage1ZirInstOffsetOf *instruction) { fprintf(irp->f, "@offset_of("); ir_print_other_inst_src(irp, instruction->type_value); fprintf(irp->f, ","); @@ -2298,7 +2298,7 @@ static void ir_print_offset_of(IrPrintSrc *irp, IrInstSrcOffsetOf *instruction) fprintf(irp->f, ")"); } -static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instruction) { +static void ir_print_bit_offset_of(IrPrintSrc *irp, Stage1ZirInstBitOffsetOf *instruction) { fprintf(irp->f, "@bit_offset_of("); ir_print_other_inst_src(irp, instruction->type_value); fprintf(irp->f, ","); @@ -2306,19 +2306,19 @@ static void ir_print_bit_offset_of(IrPrintSrc *irp, IrInstSrcBitOffsetOf *instru fprintf(irp->f, ")"); } -static void ir_print_type_info(IrPrintSrc *irp, IrInstSrcTypeInfo *instruction) { +static void ir_print_type_info(IrPrintSrc *irp, Stage1ZirInstTypeInfo *instruction) { fprintf(irp->f, "@typeInfo("); ir_print_other_inst_src(irp, instruction->type_value); fprintf(irp->f, ")"); } -static void ir_print_type(IrPrintSrc *irp, IrInstSrcType *instruction) { +static void ir_print_type(IrPrintSrc *irp, Stage1ZirInstType *instruction) { fprintf(irp->f, "@Type("); ir_print_other_inst_src(irp, instruction->type_info); fprintf(irp->f, ")"); } -static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction) { +static void ir_print_has_field(IrPrintSrc *irp, Stage1ZirInstHasField *instruction) { fprintf(irp->f, "@hasField("); ir_print_other_inst_src(irp, instruction->container_type); fprintf(irp->f, ","); @@ -2326,13 +2326,13 @@ static void ir_print_has_field(IrPrintSrc *irp, IrInstSrcHasField *instruction) fprintf(irp->f, ")"); } -static void ir_print_set_eval_branch_quota(IrPrintSrc *irp, IrInstSrcSetEvalBranchQuota *instruction) { +static void ir_print_set_eval_branch_quota(IrPrintSrc *irp, Stage1ZirInstSetEvalBranchQuota *instruction) { fprintf(irp->f, "@setEvalBranchQuota("); ir_print_other_inst_src(irp, instruction->new_quota); fprintf(irp->f, ")"); } -static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction) { +static void ir_print_align_cast(IrPrintSrc *irp, Stage1ZirInstAlignCast *instruction) { fprintf(irp->f, "@alignCast("); ir_print_other_inst_src(irp, instruction->align_bytes); fprintf(irp->f, ","); @@ -2340,31 +2340,31 @@ static void ir_print_align_cast(IrPrintSrc *irp, IrInstSrcAlignCast *instruction fprintf(irp->f, ")"); } -static void ir_print_align_cast(IrPrintGen *irp, IrInstGenAlignCast *instruction) { +static void ir_print_align_cast(IrPrintGen *irp, Stage1AirInstAlignCast *instruction) { fprintf(irp->f, "@alignCast("); ir_print_other_inst_gen(irp, instruction->target); fprintf(irp->f, ")"); } -static void ir_print_resolve_result(IrPrintSrc *irp, IrInstSrcResolveResult *instruction) { +static void ir_print_resolve_result(IrPrintSrc *irp, Stage1ZirInstResolveResult *instruction) { fprintf(irp->f, "ResolveResult("); ir_print_result_loc(irp, instruction->result_loc); fprintf(irp->f, ")"); } -static void ir_print_reset_result(IrPrintSrc *irp, IrInstSrcResetResult *instruction) { +static void ir_print_reset_result(IrPrintSrc *irp, Stage1ZirInstResetResult *instruction) { fprintf(irp->f, "ResetResult("); ir_print_result_loc(irp, instruction->result_loc); fprintf(irp->f, ")"); } -static void ir_print_set_align_stack(IrPrintSrc *irp, IrInstSrcSetAlignStack *instruction) { +static void ir_print_set_align_stack(IrPrintSrc *irp, Stage1ZirInstSetAlignStack *instruction) { fprintf(irp->f, "@setAlignStack("); ir_print_other_inst_src(irp, instruction->align_bytes); fprintf(irp->f, ")"); } -static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bool allow_var) { +static void ir_print_arg_type(IrPrintSrc *irp, Stage1ZirInstArgType *instruction, bool allow_var) { fprintf(irp->f, "@ArgType("); ir_print_other_inst_src(irp, instruction->fn_type); fprintf(irp->f, ","); @@ -2378,7 +2378,7 @@ static void ir_print_arg_type(IrPrintSrc *irp, IrInstSrcArgType *instruction, bo fprintf(irp->f, ")"); } -static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) { +static void ir_print_export(IrPrintSrc *irp, Stage1ZirInstExport *instruction) { fprintf(irp->f, "@export("); ir_print_other_inst_src(irp, instruction->target); fprintf(irp->f, ","); @@ -2386,11 +2386,11 @@ static void ir_print_export(IrPrintSrc *irp, IrInstSrcExport *instruction) { fprintf(irp->f, ")"); } -static void ir_print_extern(IrPrintGen *irp, IrInstGenExtern *instruction) { +static void ir_print_extern(IrPrintGen *irp, Stage1AirInstExtern *instruction) { fprintf(irp->f, "@extern(...)"); } -static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) { +static void ir_print_extern(IrPrintSrc *irp, Stage1ZirInstExtern *instruction) { fprintf(irp->f, "@extern("); ir_print_other_inst_src(irp, instruction->type); fprintf(irp->f, ","); @@ -2398,7 +2398,7 @@ static void ir_print_extern(IrPrintSrc *irp, IrInstSrcExtern *instruction) { fprintf(irp->f, ")"); } -static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTrace *instruction) { +static void ir_print_error_return_trace(IrPrintSrc *irp, Stage1ZirInstErrorReturnTrace *instruction) { fprintf(irp->f, "@errorReturnTrace("); switch (instruction->optional) { case IrInstErrorReturnTraceNull: @@ -2411,7 +2411,7 @@ static void ir_print_error_return_trace(IrPrintSrc *irp, IrInstSrcErrorReturnTra fprintf(irp->f, ")"); } -static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTrace *instruction) { +static void ir_print_error_return_trace(IrPrintGen *irp, Stage1AirInstErrorReturnTrace *instruction) { fprintf(irp->f, "@errorReturnTrace("); switch (instruction->optional) { case IrInstErrorReturnTraceNull: @@ -2424,13 +2424,13 @@ static void ir_print_error_return_trace(IrPrintGen *irp, IrInstGenErrorReturnTra fprintf(irp->f, ")"); } -static void ir_print_error_union(IrPrintSrc *irp, IrInstSrcErrorUnion *instruction) { +static void ir_print_error_union(IrPrintSrc *irp, Stage1ZirInstErrorUnion *instruction) { ir_print_other_inst_src(irp, instruction->err_set); fprintf(irp->f, "!"); ir_print_other_inst_src(irp, instruction->payload); } -static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction) { +static void ir_print_atomic_rmw(IrPrintSrc *irp, Stage1ZirInstAtomicRmw *instruction) { fprintf(irp->f, "@atomicRmw("); ir_print_other_inst_src(irp, instruction->operand_type); fprintf(irp->f, ","); @@ -2444,7 +2444,7 @@ static void ir_print_atomic_rmw(IrPrintSrc *irp, IrInstSrcAtomicRmw *instruction fprintf(irp->f, ")"); } -static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction) { +static void ir_print_atomic_rmw(IrPrintGen *irp, Stage1AirInstAtomicRmw *instruction) { fprintf(irp->f, "@atomicRmw("); ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, ",[TODO print op],"); @@ -2452,7 +2452,7 @@ static void ir_print_atomic_rmw(IrPrintGen *irp, IrInstGenAtomicRmw *instruction fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering)); } -static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instruction) { +static void ir_print_atomic_load(IrPrintSrc *irp, Stage1ZirInstAtomicLoad *instruction) { fprintf(irp->f, "@atomicLoad("); ir_print_other_inst_src(irp, instruction->operand_type); fprintf(irp->f, ","); @@ -2462,13 +2462,13 @@ static void ir_print_atomic_load(IrPrintSrc *irp, IrInstSrcAtomicLoad *instructi fprintf(irp->f, ")"); } -static void ir_print_atomic_load(IrPrintGen *irp, IrInstGenAtomicLoad *instruction) { +static void ir_print_atomic_load(IrPrintGen *irp, Stage1AirInstAtomicLoad *instruction) { fprintf(irp->f, "@atomicLoad("); ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, ",%s)", atomic_order_str(instruction->ordering)); } -static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruction) { +static void ir_print_atomic_store(IrPrintSrc *irp, Stage1ZirInstAtomicStore *instruction) { fprintf(irp->f, "@atomicStore("); ir_print_other_inst_src(irp, instruction->operand_type); fprintf(irp->f, ","); @@ -2480,7 +2480,7 @@ static void ir_print_atomic_store(IrPrintSrc *irp, IrInstSrcAtomicStore *instruc fprintf(irp->f, ")"); } -static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruction) { +static void ir_print_atomic_store(IrPrintGen *irp, Stage1AirInstAtomicStore *instruction) { fprintf(irp->f, "@atomicStore("); ir_print_other_inst_gen(irp, instruction->ptr); fprintf(irp->f, ","); @@ -2489,33 +2489,33 @@ static void ir_print_atomic_store(IrPrintGen *irp, IrInstGenAtomicStore *instruc } -static void ir_print_save_err_ret_addr(IrPrintSrc *irp, IrInstSrcSaveErrRetAddr *instruction) { +static void ir_print_save_err_ret_addr(IrPrintSrc *irp, Stage1ZirInstSaveErrRetAddr *instruction) { fprintf(irp->f, "@saveErrRetAddr()"); } -static void ir_print_save_err_ret_addr(IrPrintGen *irp, IrInstGenSaveErrRetAddr *instruction) { +static void ir_print_save_err_ret_addr(IrPrintGen *irp, Stage1AirInstSaveErrRetAddr *instruction) { fprintf(irp->f, "@saveErrRetAddr()"); } -static void ir_print_add_implicit_return_type(IrPrintSrc *irp, IrInstSrcAddImplicitReturnType *instruction) { +static void ir_print_add_implicit_return_type(IrPrintSrc *irp, Stage1ZirInstAddImplicitReturnType *instruction) { fprintf(irp->f, "@addImplicitReturnType("); ir_print_other_inst_src(irp, instruction->value); fprintf(irp->f, ")"); } -static void ir_print_float_op(IrPrintSrc *irp, IrInstSrcFloatOp *instruction) { +static void ir_print_float_op(IrPrintSrc *irp, Stage1ZirInstFloatOp *instruction) { fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id)); ir_print_other_inst_src(irp, instruction->operand); fprintf(irp->f, ")"); } -static void ir_print_float_op(IrPrintGen *irp, IrInstGenFloatOp *instruction) { +static void ir_print_float_op(IrPrintGen *irp, Stage1AirInstFloatOp *instruction) { fprintf(irp->f, "@%s(", float_op_to_name(instruction->fn_id)); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")"); } -static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) { +static void ir_print_mul_add(IrPrintSrc *irp, Stage1ZirInstMulAdd *instruction) { fprintf(irp->f, "@mulAdd("); ir_print_other_inst_src(irp, instruction->type_value); fprintf(irp->f, ","); @@ -2527,7 +2527,7 @@ static void ir_print_mul_add(IrPrintSrc *irp, IrInstSrcMulAdd *instruction) { fprintf(irp->f, ")"); } -static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) { +static void ir_print_mul_add(IrPrintGen *irp, Stage1AirInstMulAdd *instruction) { fprintf(irp->f, "@mulAdd("); ir_print_other_inst_gen(irp, instruction->op1); fprintf(irp->f, ","); @@ -2537,7 +2537,7 @@ static void ir_print_mul_add(IrPrintGen *irp, IrInstGenMulAdd *instruction) { fprintf(irp->f, ")"); } -static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_instruction) { +static void ir_print_decl_var_gen(IrPrintGen *irp, Stage1AirInstDeclVar *decl_var_instruction) { ZigVar *var = decl_var_instruction->var; const char *var_or_const = decl_var_instruction->var->gen_is_const ? "const" : "var"; const char *name = decl_var_instruction->var->name; @@ -2547,7 +2547,7 @@ static void ir_print_decl_var_gen(IrPrintGen *irp, IrInstGenDeclVar *decl_var_in ir_print_other_inst_gen(irp, decl_var_instruction->var_ptr); } -static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) { +static void ir_print_has_decl(IrPrintSrc *irp, Stage1ZirInstHasDecl *instruction) { fprintf(irp->f, "@hasDecl("); ir_print_other_inst_src(irp, instruction->container); fprintf(irp->f, ","); @@ -2555,11 +2555,11 @@ static void ir_print_has_decl(IrPrintSrc *irp, IrInstSrcHasDecl *instruction) { fprintf(irp->f, ")"); } -static void ir_print_undeclared_ident(IrPrintSrc *irp, IrInstSrcUndeclaredIdent *instruction) { +static void ir_print_undeclared_ident(IrPrintSrc *irp, Stage1ZirInstUndeclaredIdent *instruction) { fprintf(irp->f, "@undeclaredIdent(%s)", buf_ptr(instruction->name)); } -static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitNamedField *instruction) { +static void ir_print_union_init_named_field(IrPrintSrc *irp, Stage1ZirInstUnionInitNamedField *instruction) { fprintf(irp->f, "@unionInit("); ir_print_other_inst_src(irp, instruction->union_type); fprintf(irp->f, ", "); @@ -2571,33 +2571,33 @@ static void ir_print_union_init_named_field(IrPrintSrc *irp, IrInstSrcUnionInitN fprintf(irp->f, ")"); } -static void ir_print_suspend_begin(IrPrintSrc *irp, IrInstSrcSuspendBegin *instruction) { +static void ir_print_suspend_begin(IrPrintSrc *irp, Stage1ZirInstSuspendBegin *instruction) { fprintf(irp->f, "@suspendBegin()"); } -static void ir_print_suspend_begin(IrPrintGen *irp, IrInstGenSuspendBegin *instruction) { +static void ir_print_suspend_begin(IrPrintGen *irp, Stage1AirInstSuspendBegin *instruction) { fprintf(irp->f, "@suspendBegin()"); } -static void ir_print_suspend_finish(IrPrintSrc *irp, IrInstSrcSuspendFinish *instruction) { +static void ir_print_suspend_finish(IrPrintSrc *irp, Stage1ZirInstSuspendFinish *instruction) { fprintf(irp->f, "@suspendFinish()"); } -static void ir_print_suspend_finish(IrPrintGen *irp, IrInstGenSuspendFinish *instruction) { +static void ir_print_suspend_finish(IrPrintGen *irp, Stage1AirInstSuspendFinish *instruction) { fprintf(irp->f, "@suspendFinish()"); } -static void ir_print_resume(IrPrintSrc *irp, IrInstSrcResume *instruction) { +static void ir_print_resume(IrPrintSrc *irp, Stage1ZirInstResume *instruction) { fprintf(irp->f, "resume "); ir_print_other_inst_src(irp, instruction->frame); } -static void ir_print_resume(IrPrintGen *irp, IrInstGenResume *instruction) { +static void ir_print_resume(IrPrintGen *irp, Stage1AirInstResume *instruction) { fprintf(irp->f, "resume "); ir_print_other_inst_gen(irp, instruction->frame); } -static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) { +static void ir_print_await_src(IrPrintSrc *irp, Stage1ZirInstAwait *instruction) { fprintf(irp->f, "@await("); ir_print_other_inst_src(irp, instruction->frame); fprintf(irp->f, ","); @@ -2605,7 +2605,7 @@ static void ir_print_await_src(IrPrintSrc *irp, IrInstSrcAwait *instruction) { fprintf(irp->f, ")"); } -static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) { +static void ir_print_await_gen(IrPrintGen *irp, Stage1AirInstAwait *instruction) { fprintf(irp->f, "@await("); ir_print_other_inst_gen(irp, instruction->frame); fprintf(irp->f, ","); @@ -2613,31 +2613,31 @@ static void ir_print_await_gen(IrPrintGen *irp, IrInstGenAwait *instruction) { fprintf(irp->f, ")"); } -static void ir_print_spill_begin(IrPrintSrc *irp, IrInstSrcSpillBegin *instruction) { +static void ir_print_spill_begin(IrPrintSrc *irp, Stage1ZirInstSpillBegin *instruction) { fprintf(irp->f, "@spillBegin("); ir_print_other_inst_src(irp, instruction->operand); fprintf(irp->f, ")"); } -static void ir_print_spill_begin(IrPrintGen *irp, IrInstGenSpillBegin *instruction) { +static void ir_print_spill_begin(IrPrintGen *irp, Stage1AirInstSpillBegin *instruction) { fprintf(irp->f, "@spillBegin("); ir_print_other_inst_gen(irp, instruction->operand); fprintf(irp->f, ")"); } -static void ir_print_spill_end(IrPrintSrc *irp, IrInstSrcSpillEnd *instruction) { +static void ir_print_spill_end(IrPrintSrc *irp, Stage1ZirInstSpillEnd *instruction) { fprintf(irp->f, "@spillEnd("); ir_print_other_inst_src(irp, &instruction->begin->base); fprintf(irp->f, ")"); } -static void ir_print_spill_end(IrPrintGen *irp, IrInstGenSpillEnd *instruction) { +static void ir_print_spill_end(IrPrintGen *irp, Stage1AirInstSpillEnd *instruction) { fprintf(irp->f, "@spillEnd("); ir_print_other_inst_gen(irp, &instruction->begin->base); fprintf(irp->f, ")"); } -static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtractElem *instruction) { +static void ir_print_vector_extract_elem(IrPrintGen *irp, Stage1AirInstVectorExtractElem *instruction) { fprintf(irp->f, "@vectorExtractElem("); ir_print_other_inst_gen(irp, instruction->vector); fprintf(irp->f, ","); @@ -2645,703 +2645,703 @@ static void ir_print_vector_extract_elem(IrPrintGen *irp, IrInstGenVectorExtract fprintf(irp->f, ")"); } -static void ir_print_inst_src(IrPrintSrc *irp, IrInstSrc *instruction, bool trailing) { +static void ir_print_inst_src(IrPrintSrc *irp, Stage1ZirInst *instruction, bool trailing) { ir_print_prefix_src(irp, instruction, trailing); switch (instruction->id) { - case IrInstSrcIdInvalid: + case Stage1ZirInstIdInvalid: zig_unreachable(); - case IrInstSrcIdReturn: - ir_print_return_src(irp, (IrInstSrcReturn *)instruction); + case Stage1ZirInstIdReturn: + ir_print_return_src(irp, (Stage1ZirInstReturn *)instruction); break; - case IrInstSrcIdConst: - ir_print_const(irp, (IrInstSrcConst *)instruction); + case Stage1ZirInstIdConst: + ir_print_const(irp, (Stage1ZirInstConst *)instruction); break; - case IrInstSrcIdBinOp: - ir_print_bin_op(irp, (IrInstSrcBinOp *)instruction); + case Stage1ZirInstIdBinOp: + ir_print_bin_op(irp, (Stage1ZirInstBinOp *)instruction); break; - case IrInstSrcIdMergeErrSets: - ir_print_merge_err_sets(irp, (IrInstSrcMergeErrSets *)instruction); + case Stage1ZirInstIdMergeErrSets: + ir_print_merge_err_sets(irp, (Stage1ZirInstMergeErrSets *)instruction); break; - case IrInstSrcIdDeclVar: - ir_print_decl_var_src(irp, (IrInstSrcDeclVar *)instruction); + case Stage1ZirInstIdDeclVar: + ir_print_decl_var_src(irp, (Stage1ZirInstDeclVar *)instruction); break; - case IrInstSrcIdCallExtra: - ir_print_call_extra(irp, (IrInstSrcCallExtra *)instruction); + case Stage1ZirInstIdCallExtra: + ir_print_call_extra(irp, (Stage1ZirInstCallExtra *)instruction); break; - case IrInstSrcIdAsyncCallExtra: - ir_print_async_call_extra(irp, (IrInstSrcAsyncCallExtra *)instruction); + case Stage1ZirInstIdAsyncCallExtra: + ir_print_async_call_extra(irp, (Stage1ZirInstAsyncCallExtra *)instruction); break; - case IrInstSrcIdCall: - ir_print_call_src(irp, (IrInstSrcCall *)instruction); + case Stage1ZirInstIdCall: + ir_print_call_src(irp, (Stage1ZirInstCall *)instruction); break; - case IrInstSrcIdCallArgs: - ir_print_call_args(irp, (IrInstSrcCallArgs *)instruction); + case Stage1ZirInstIdCallArgs: + ir_print_call_args(irp, (Stage1ZirInstCallArgs *)instruction); break; - case IrInstSrcIdUnOp: - ir_print_un_op(irp, (IrInstSrcUnOp *)instruction); + case Stage1ZirInstIdUnOp: + ir_print_un_op(irp, (Stage1ZirInstUnOp *)instruction); break; - case IrInstSrcIdCondBr: - ir_print_cond_br(irp, (IrInstSrcCondBr *)instruction); + case Stage1ZirInstIdCondBr: + ir_print_cond_br(irp, (Stage1ZirInstCondBr *)instruction); break; - case IrInstSrcIdBr: - ir_print_br(irp, (IrInstSrcBr *)instruction); + case Stage1ZirInstIdBr: + ir_print_br(irp, (Stage1ZirInstBr *)instruction); break; - case IrInstSrcIdPhi: - ir_print_phi(irp, (IrInstSrcPhi *)instruction); + case Stage1ZirInstIdPhi: + ir_print_phi(irp, (Stage1ZirInstPhi *)instruction); break; - case IrInstSrcIdContainerInitList: - ir_print_container_init_list(irp, (IrInstSrcContainerInitList *)instruction); + case Stage1ZirInstIdContainerInitList: + ir_print_container_init_list(irp, (Stage1ZirInstContainerInitList *)instruction); break; - case IrInstSrcIdContainerInitFields: - ir_print_container_init_fields(irp, (IrInstSrcContainerInitFields *)instruction); + case Stage1ZirInstIdContainerInitFields: + ir_print_container_init_fields(irp, (Stage1ZirInstContainerInitFields *)instruction); break; - case IrInstSrcIdUnreachable: - ir_print_unreachable(irp, (IrInstSrcUnreachable *)instruction); + case Stage1ZirInstIdUnreachable: + ir_print_unreachable(irp, (Stage1ZirInstUnreachable *)instruction); break; - case IrInstSrcIdElemPtr: - ir_print_elem_ptr(irp, (IrInstSrcElemPtr *)instruction); + case Stage1ZirInstIdElemPtr: + ir_print_elem_ptr(irp, (Stage1ZirInstElemPtr *)instruction); break; - case IrInstSrcIdVarPtr: - ir_print_var_ptr(irp, (IrInstSrcVarPtr *)instruction); + case Stage1ZirInstIdVarPtr: + ir_print_var_ptr(irp, (Stage1ZirInstVarPtr *)instruction); break; - case IrInstSrcIdLoadPtr: - ir_print_load_ptr(irp, (IrInstSrcLoadPtr *)instruction); + case Stage1ZirInstIdLoadPtr: + ir_print_load_ptr(irp, (Stage1ZirInstLoadPtr *)instruction); break; - case IrInstSrcIdStorePtr: - ir_print_store_ptr(irp, (IrInstSrcStorePtr *)instruction); + case Stage1ZirInstIdStorePtr: + ir_print_store_ptr(irp, (Stage1ZirInstStorePtr *)instruction); break; - case IrInstSrcIdTypeOf: - ir_print_typeof(irp, (IrInstSrcTypeOf *)instruction); + case Stage1ZirInstIdTypeOf: + ir_print_typeof(irp, (Stage1ZirInstTypeOf *)instruction); break; - case IrInstSrcIdFieldPtr: - ir_print_field_ptr(irp, (IrInstSrcFieldPtr *)instruction); + case Stage1ZirInstIdFieldPtr: + ir_print_field_ptr(irp, (Stage1ZirInstFieldPtr *)instruction); break; - case IrInstSrcIdSetCold: - ir_print_set_cold(irp, (IrInstSrcSetCold *)instruction); + case Stage1ZirInstIdSetCold: + ir_print_set_cold(irp, (Stage1ZirInstSetCold *)instruction); break; - case IrInstSrcIdSetRuntimeSafety: - ir_print_set_runtime_safety(irp, (IrInstSrcSetRuntimeSafety *)instruction); + case Stage1ZirInstIdSetRuntimeSafety: + ir_print_set_runtime_safety(irp, (Stage1ZirInstSetRuntimeSafety *)instruction); break; - case IrInstSrcIdSetFloatMode: - ir_print_set_float_mode(irp, (IrInstSrcSetFloatMode *)instruction); + case Stage1ZirInstIdSetFloatMode: + ir_print_set_float_mode(irp, (Stage1ZirInstSetFloatMode *)instruction); break; - case IrInstSrcIdArrayType: - ir_print_array_type(irp, (IrInstSrcArrayType *)instruction); + case Stage1ZirInstIdArrayType: + ir_print_array_type(irp, (Stage1ZirInstArrayType *)instruction); break; - case IrInstSrcIdSliceType: - ir_print_slice_type(irp, (IrInstSrcSliceType *)instruction); + case Stage1ZirInstIdSliceType: + ir_print_slice_type(irp, (Stage1ZirInstSliceType *)instruction); break; - case IrInstSrcIdAnyFrameType: - ir_print_any_frame_type(irp, (IrInstSrcAnyFrameType *)instruction); + case Stage1ZirInstIdAnyFrameType: + ir_print_any_frame_type(irp, (Stage1ZirInstAnyFrameType *)instruction); break; - case IrInstSrcIdAsm: - ir_print_asm_src(irp, (IrInstSrcAsm *)instruction); + case Stage1ZirInstIdAsm: + ir_print_asm_src(irp, (Stage1ZirInstAsm *)instruction); break; - case IrInstSrcIdSizeOf: - ir_print_size_of(irp, (IrInstSrcSizeOf *)instruction); + case Stage1ZirInstIdSizeOf: + ir_print_size_of(irp, (Stage1ZirInstSizeOf *)instruction); break; - case IrInstSrcIdTestNonNull: - ir_print_test_non_null(irp, (IrInstSrcTestNonNull *)instruction); + case Stage1ZirInstIdTestNonNull: + ir_print_test_non_null(irp, (Stage1ZirInstTestNonNull *)instruction); break; - case IrInstSrcIdOptionalUnwrapPtr: - ir_print_optional_unwrap_ptr(irp, (IrInstSrcOptionalUnwrapPtr *)instruction); + case Stage1ZirInstIdOptionalUnwrapPtr: + ir_print_optional_unwrap_ptr(irp, (Stage1ZirInstOptionalUnwrapPtr *)instruction); break; - case IrInstSrcIdPopCount: - ir_print_pop_count(irp, (IrInstSrcPopCount *)instruction); + case Stage1ZirInstIdPopCount: + ir_print_pop_count(irp, (Stage1ZirInstPopCount *)instruction); break; - case IrInstSrcIdCtz: - ir_print_ctz(irp, (IrInstSrcCtz *)instruction); + case Stage1ZirInstIdCtz: + ir_print_ctz(irp, (Stage1ZirInstCtz *)instruction); break; - case IrInstSrcIdBswap: - ir_print_bswap(irp, (IrInstSrcBswap *)instruction); + case Stage1ZirInstIdBswap: + ir_print_bswap(irp, (Stage1ZirInstBswap *)instruction); break; - case IrInstSrcIdBitReverse: - ir_print_bit_reverse(irp, (IrInstSrcBitReverse *)instruction); + case Stage1ZirInstIdBitReverse: + ir_print_bit_reverse(irp, (Stage1ZirInstBitReverse *)instruction); break; - case IrInstSrcIdSwitchBr: - ir_print_switch_br(irp, (IrInstSrcSwitchBr *)instruction); + case Stage1ZirInstIdSwitchBr: + ir_print_switch_br(irp, (Stage1ZirInstSwitchBr *)instruction); break; - case IrInstSrcIdSwitchVar: - ir_print_switch_var(irp, (IrInstSrcSwitchVar *)instruction); + case Stage1ZirInstIdSwitchVar: + ir_print_switch_var(irp, (Stage1ZirInstSwitchVar *)instruction); break; - case IrInstSrcIdSwitchElseVar: - ir_print_switch_else_var(irp, (IrInstSrcSwitchElseVar *)instruction); + case Stage1ZirInstIdSwitchElseVar: + ir_print_switch_else_var(irp, (Stage1ZirInstSwitchElseVar *)instruction); break; - case IrInstSrcIdSwitchTarget: - ir_print_switch_target(irp, (IrInstSrcSwitchTarget *)instruction); + case Stage1ZirInstIdSwitchTarget: + ir_print_switch_target(irp, (Stage1ZirInstSwitchTarget *)instruction); break; - case IrInstSrcIdImport: - ir_print_import(irp, (IrInstSrcImport *)instruction); + case Stage1ZirInstIdImport: + ir_print_import(irp, (Stage1ZirInstImport *)instruction); break; - case IrInstSrcIdRef: - ir_print_ref(irp, (IrInstSrcRef *)instruction); + case Stage1ZirInstIdRef: + ir_print_ref(irp, (Stage1ZirInstRef *)instruction); break; - case IrInstSrcIdCompileErr: - ir_print_compile_err(irp, (IrInstSrcCompileErr *)instruction); + case Stage1ZirInstIdCompileErr: + ir_print_compile_err(irp, (Stage1ZirInstCompileErr *)instruction); break; - case IrInstSrcIdCompileLog: - ir_print_compile_log(irp, (IrInstSrcCompileLog *)instruction); + case Stage1ZirInstIdCompileLog: + ir_print_compile_log(irp, (Stage1ZirInstCompileLog *)instruction); break; - case IrInstSrcIdErrName: - ir_print_err_name(irp, (IrInstSrcErrName *)instruction); + case Stage1ZirInstIdErrName: + ir_print_err_name(irp, (Stage1ZirInstErrName *)instruction); break; - case IrInstSrcIdCImport: - ir_print_c_import(irp, (IrInstSrcCImport *)instruction); + case Stage1ZirInstIdCImport: + ir_print_c_import(irp, (Stage1ZirInstCImport *)instruction); break; - case IrInstSrcIdCInclude: - ir_print_c_include(irp, (IrInstSrcCInclude *)instruction); + case Stage1ZirInstIdCInclude: + ir_print_c_include(irp, (Stage1ZirInstCInclude *)instruction); break; - case IrInstSrcIdCDefine: - ir_print_c_define(irp, (IrInstSrcCDefine *)instruction); + case Stage1ZirInstIdCDefine: + ir_print_c_define(irp, (Stage1ZirInstCDefine *)instruction); break; - case IrInstSrcIdCUndef: - ir_print_c_undef(irp, (IrInstSrcCUndef *)instruction); + case Stage1ZirInstIdCUndef: + ir_print_c_undef(irp, (Stage1ZirInstCUndef *)instruction); break; - case IrInstSrcIdEmbedFile: - ir_print_embed_file(irp, (IrInstSrcEmbedFile *)instruction); + case Stage1ZirInstIdEmbedFile: + ir_print_embed_file(irp, (Stage1ZirInstEmbedFile *)instruction); break; - case IrInstSrcIdCmpxchg: - ir_print_cmpxchg_src(irp, (IrInstSrcCmpxchg *)instruction); + case Stage1ZirInstIdCmpxchg: + ir_print_cmpxchg_src(irp, (Stage1ZirInstCmpxchg *)instruction); break; - case IrInstSrcIdFence: - ir_print_fence(irp, (IrInstSrcFence *)instruction); + case Stage1ZirInstIdFence: + ir_print_fence(irp, (Stage1ZirInstFence *)instruction); break; - case IrInstSrcIdReduce: - ir_print_reduce(irp, (IrInstSrcReduce *)instruction); + case Stage1ZirInstIdReduce: + ir_print_reduce(irp, (Stage1ZirInstReduce *)instruction); break; - case IrInstSrcIdTruncate: - ir_print_truncate(irp, (IrInstSrcTruncate *)instruction); + case Stage1ZirInstIdTruncate: + ir_print_truncate(irp, (Stage1ZirInstTruncate *)instruction); break; - case IrInstSrcIdIntCast: - ir_print_int_cast(irp, (IrInstSrcIntCast *)instruction); + case Stage1ZirInstIdIntCast: + ir_print_int_cast(irp, (Stage1ZirInstIntCast *)instruction); break; - case IrInstSrcIdFloatCast: - ir_print_float_cast(irp, (IrInstSrcFloatCast *)instruction); + case Stage1ZirInstIdFloatCast: + ir_print_float_cast(irp, (Stage1ZirInstFloatCast *)instruction); break; - case IrInstSrcIdErrSetCast: - ir_print_err_set_cast(irp, (IrInstSrcErrSetCast *)instruction); + case Stage1ZirInstIdErrSetCast: + ir_print_err_set_cast(irp, (Stage1ZirInstErrSetCast *)instruction); break; - case IrInstSrcIdIntToFloat: - ir_print_int_to_float(irp, (IrInstSrcIntToFloat *)instruction); + case Stage1ZirInstIdIntToFloat: + ir_print_int_to_float(irp, (Stage1ZirInstIntToFloat *)instruction); break; - case IrInstSrcIdFloatToInt: - ir_print_float_to_int(irp, (IrInstSrcFloatToInt *)instruction); + case Stage1ZirInstIdFloatToInt: + ir_print_float_to_int(irp, (Stage1ZirInstFloatToInt *)instruction); break; - case IrInstSrcIdBoolToInt: - ir_print_bool_to_int(irp, (IrInstSrcBoolToInt *)instruction); + case Stage1ZirInstIdBoolToInt: + ir_print_bool_to_int(irp, (Stage1ZirInstBoolToInt *)instruction); break; - case IrInstSrcIdVectorType: - ir_print_vector_type(irp, (IrInstSrcVectorType *)instruction); + case Stage1ZirInstIdVectorType: + ir_print_vector_type(irp, (Stage1ZirInstVectorType *)instruction); break; - case IrInstSrcIdShuffleVector: - ir_print_shuffle_vector(irp, (IrInstSrcShuffleVector *)instruction); + case Stage1ZirInstIdShuffleVector: + ir_print_shuffle_vector(irp, (Stage1ZirInstShuffleVector *)instruction); break; - case IrInstSrcIdSplat: - ir_print_splat_src(irp, (IrInstSrcSplat *)instruction); + case Stage1ZirInstIdSplat: + ir_print_splat_src(irp, (Stage1ZirInstSplat *)instruction); break; - case IrInstSrcIdBoolNot: - ir_print_bool_not(irp, (IrInstSrcBoolNot *)instruction); + case Stage1ZirInstIdBoolNot: + ir_print_bool_not(irp, (Stage1ZirInstBoolNot *)instruction); break; - case IrInstSrcIdMemset: - ir_print_memset(irp, (IrInstSrcMemset *)instruction); + case Stage1ZirInstIdMemset: + ir_print_memset(irp, (Stage1ZirInstMemset *)instruction); break; - case IrInstSrcIdMemcpy: - ir_print_memcpy(irp, (IrInstSrcMemcpy *)instruction); + case Stage1ZirInstIdMemcpy: + ir_print_memcpy(irp, (Stage1ZirInstMemcpy *)instruction); break; - case IrInstSrcIdSlice: - ir_print_slice_src(irp, (IrInstSrcSlice *)instruction); + case Stage1ZirInstIdSlice: + ir_print_slice_src(irp, (Stage1ZirInstSlice *)instruction); break; - case IrInstSrcIdBreakpoint: - ir_print_breakpoint(irp, (IrInstSrcBreakpoint *)instruction); + case Stage1ZirInstIdBreakpoint: + ir_print_breakpoint(irp, (Stage1ZirInstBreakpoint *)instruction); break; - case IrInstSrcIdReturnAddress: - ir_print_return_address(irp, (IrInstSrcReturnAddress *)instruction); + case Stage1ZirInstIdReturnAddress: + ir_print_return_address(irp, (Stage1ZirInstReturnAddress *)instruction); break; - case IrInstSrcIdFrameAddress: - ir_print_frame_address(irp, (IrInstSrcFrameAddress *)instruction); + case Stage1ZirInstIdFrameAddress: + ir_print_frame_address(irp, (Stage1ZirInstFrameAddress *)instruction); break; - case IrInstSrcIdFrameHandle: - ir_print_handle(irp, (IrInstSrcFrameHandle *)instruction); + case Stage1ZirInstIdFrameHandle: + ir_print_handle(irp, (Stage1ZirInstFrameHandle *)instruction); break; - case IrInstSrcIdFrameType: - ir_print_frame_type(irp, (IrInstSrcFrameType *)instruction); + case Stage1ZirInstIdFrameType: + ir_print_frame_type(irp, (Stage1ZirInstFrameType *)instruction); break; - case IrInstSrcIdFrameSize: - ir_print_frame_size_src(irp, (IrInstSrcFrameSize *)instruction); + case Stage1ZirInstIdFrameSize: + ir_print_frame_size_src(irp, (Stage1ZirInstFrameSize *)instruction); break; - case IrInstSrcIdAlignOf: - ir_print_align_of(irp, (IrInstSrcAlignOf *)instruction); + case Stage1ZirInstIdAlignOf: + ir_print_align_of(irp, (Stage1ZirInstAlignOf *)instruction); break; - case IrInstSrcIdOverflowOp: - ir_print_overflow_op(irp, (IrInstSrcOverflowOp *)instruction); + case Stage1ZirInstIdOverflowOp: + ir_print_overflow_op(irp, (Stage1ZirInstOverflowOp *)instruction); break; - case IrInstSrcIdTestErr: - ir_print_test_err_src(irp, (IrInstSrcTestErr *)instruction); + case Stage1ZirInstIdTestErr: + ir_print_test_err_src(irp, (Stage1ZirInstTestErr *)instruction); break; - case IrInstSrcIdUnwrapErrCode: - ir_print_unwrap_err_code(irp, (IrInstSrcUnwrapErrCode *)instruction); + case Stage1ZirInstIdUnwrapErrCode: + ir_print_unwrap_err_code(irp, (Stage1ZirInstUnwrapErrCode *)instruction); break; - case IrInstSrcIdUnwrapErrPayload: - ir_print_unwrap_err_payload(irp, (IrInstSrcUnwrapErrPayload *)instruction); + case Stage1ZirInstIdUnwrapErrPayload: + ir_print_unwrap_err_payload(irp, (Stage1ZirInstUnwrapErrPayload *)instruction); break; - case IrInstSrcIdFnProto: - ir_print_fn_proto(irp, (IrInstSrcFnProto *)instruction); + case Stage1ZirInstIdFnProto: + ir_print_fn_proto(irp, (Stage1ZirInstFnProto *)instruction); break; - case IrInstSrcIdTestComptime: - ir_print_test_comptime(irp, (IrInstSrcTestComptime *)instruction); + case Stage1ZirInstIdTestComptime: + ir_print_test_comptime(irp, (Stage1ZirInstTestComptime *)instruction); break; - case IrInstSrcIdPtrCast: - ir_print_ptr_cast_src(irp, (IrInstSrcPtrCast *)instruction); + case Stage1ZirInstIdPtrCast: + ir_print_ptr_cast_src(irp, (Stage1ZirInstPtrCast *)instruction); break; - case IrInstSrcIdBitCast: - ir_print_bit_cast_src(irp, (IrInstSrcBitCast *)instruction); + case Stage1ZirInstIdBitCast: + ir_print_bit_cast_src(irp, (Stage1ZirInstBitCast *)instruction); break; - case IrInstSrcIdPtrToInt: - ir_print_ptr_to_int(irp, (IrInstSrcPtrToInt *)instruction); + case Stage1ZirInstIdPtrToInt: + ir_print_ptr_to_int(irp, (Stage1ZirInstPtrToInt *)instruction); break; - case IrInstSrcIdIntToPtr: - ir_print_int_to_ptr(irp, (IrInstSrcIntToPtr *)instruction); + case Stage1ZirInstIdIntToPtr: + ir_print_int_to_ptr(irp, (Stage1ZirInstIntToPtr *)instruction); break; - case IrInstSrcIdIntToEnum: - ir_print_int_to_enum(irp, (IrInstSrcIntToEnum *)instruction); + case Stage1ZirInstIdIntToEnum: + ir_print_int_to_enum(irp, (Stage1ZirInstIntToEnum *)instruction); break; - case IrInstSrcIdIntToErr: - ir_print_int_to_err(irp, (IrInstSrcIntToErr *)instruction); + case Stage1ZirInstIdIntToErr: + ir_print_int_to_err(irp, (Stage1ZirInstIntToErr *)instruction); break; - case IrInstSrcIdErrToInt: - ir_print_err_to_int(irp, (IrInstSrcErrToInt *)instruction); + case Stage1ZirInstIdErrToInt: + ir_print_err_to_int(irp, (Stage1ZirInstErrToInt *)instruction); break; - case IrInstSrcIdCheckSwitchProngsUnderNo: - ir_print_check_switch_prongs(irp, (IrInstSrcCheckSwitchProngs *)instruction, false); + case Stage1ZirInstIdCheckSwitchProngsUnderNo: + ir_print_check_switch_prongs(irp, (Stage1ZirInstCheckSwitchProngs *)instruction, false); break; - case IrInstSrcIdCheckSwitchProngsUnderYes: - ir_print_check_switch_prongs(irp, (IrInstSrcCheckSwitchProngs *)instruction, true); + case Stage1ZirInstIdCheckSwitchProngsUnderYes: + ir_print_check_switch_prongs(irp, (Stage1ZirInstCheckSwitchProngs *)instruction, true); break; - case IrInstSrcIdCheckStatementIsVoid: - ir_print_check_statement_is_void(irp, (IrInstSrcCheckStatementIsVoid *)instruction); + case Stage1ZirInstIdCheckStatementIsVoid: + ir_print_check_statement_is_void(irp, (Stage1ZirInstCheckStatementIsVoid *)instruction); break; - case IrInstSrcIdTypeName: - ir_print_type_name(irp, (IrInstSrcTypeName *)instruction); + case Stage1ZirInstIdTypeName: + ir_print_type_name(irp, (Stage1ZirInstTypeName *)instruction); break; - case IrInstSrcIdTagName: - ir_print_tag_name(irp, (IrInstSrcTagName *)instruction); + case Stage1ZirInstIdTagName: + ir_print_tag_name(irp, (Stage1ZirInstTagName *)instruction); break; - case IrInstSrcIdPtrType: - ir_print_ptr_type(irp, (IrInstSrcPtrType *)instruction); + case Stage1ZirInstIdPtrType: + ir_print_ptr_type(irp, (Stage1ZirInstPtrType *)instruction); break; - case IrInstSrcIdPtrTypeSimple: - ir_print_ptr_type_simple(irp, (IrInstSrcPtrTypeSimple *)instruction, false); + case Stage1ZirInstIdPtrTypeSimple: + ir_print_ptr_type_simple(irp, (Stage1ZirInstPtrTypeSimple *)instruction, false); break; - case IrInstSrcIdPtrTypeSimpleConst: - ir_print_ptr_type_simple(irp, (IrInstSrcPtrTypeSimple *)instruction, true); + case Stage1ZirInstIdPtrTypeSimpleConst: + ir_print_ptr_type_simple(irp, (Stage1ZirInstPtrTypeSimple *)instruction, true); break; - case IrInstSrcIdDeclRef: - ir_print_decl_ref(irp, (IrInstSrcDeclRef *)instruction); + case Stage1ZirInstIdDeclRef: + ir_print_decl_ref(irp, (Stage1ZirInstDeclRef *)instruction); break; - case IrInstSrcIdPanic: - ir_print_panic(irp, (IrInstSrcPanic *)instruction); + case Stage1ZirInstIdPanic: + ir_print_panic(irp, (Stage1ZirInstPanic *)instruction); break; - case IrInstSrcIdFieldParentPtr: - ir_print_field_parent_ptr(irp, (IrInstSrcFieldParentPtr *)instruction); + case Stage1ZirInstIdFieldParentPtr: + ir_print_field_parent_ptr(irp, (Stage1ZirInstFieldParentPtr *)instruction); break; - case IrInstSrcIdOffsetOf: - ir_print_offset_of(irp, (IrInstSrcOffsetOf *)instruction); + case Stage1ZirInstIdOffsetOf: + ir_print_offset_of(irp, (Stage1ZirInstOffsetOf *)instruction); break; - case IrInstSrcIdBitOffsetOf: - ir_print_bit_offset_of(irp, (IrInstSrcBitOffsetOf *)instruction); + case Stage1ZirInstIdBitOffsetOf: + ir_print_bit_offset_of(irp, (Stage1ZirInstBitOffsetOf *)instruction); break; - case IrInstSrcIdTypeInfo: - ir_print_type_info(irp, (IrInstSrcTypeInfo *)instruction); + case Stage1ZirInstIdTypeInfo: + ir_print_type_info(irp, (Stage1ZirInstTypeInfo *)instruction); break; - case IrInstSrcIdType: - ir_print_type(irp, (IrInstSrcType *)instruction); + case Stage1ZirInstIdType: + ir_print_type(irp, (Stage1ZirInstType *)instruction); break; - case IrInstSrcIdHasField: - ir_print_has_field(irp, (IrInstSrcHasField *)instruction); + case Stage1ZirInstIdHasField: + ir_print_has_field(irp, (Stage1ZirInstHasField *)instruction); break; - case IrInstSrcIdSetEvalBranchQuota: - ir_print_set_eval_branch_quota(irp, (IrInstSrcSetEvalBranchQuota *)instruction); + case Stage1ZirInstIdSetEvalBranchQuota: + ir_print_set_eval_branch_quota(irp, (Stage1ZirInstSetEvalBranchQuota *)instruction); break; - case IrInstSrcIdAlignCast: - ir_print_align_cast(irp, (IrInstSrcAlignCast *)instruction); + case Stage1ZirInstIdAlignCast: + ir_print_align_cast(irp, (Stage1ZirInstAlignCast *)instruction); break; - case IrInstSrcIdImplicitCast: - ir_print_implicit_cast(irp, (IrInstSrcImplicitCast *)instruction); + case Stage1ZirInstIdImplicitCast: + ir_print_implicit_cast(irp, (Stage1ZirInstImplicitCast *)instruction); break; - case IrInstSrcIdResolveResult: - ir_print_resolve_result(irp, (IrInstSrcResolveResult *)instruction); + case Stage1ZirInstIdResolveResult: + ir_print_resolve_result(irp, (Stage1ZirInstResolveResult *)instruction); break; - case IrInstSrcIdResetResult: - ir_print_reset_result(irp, (IrInstSrcResetResult *)instruction); + case Stage1ZirInstIdResetResult: + ir_print_reset_result(irp, (Stage1ZirInstResetResult *)instruction); break; - case IrInstSrcIdSetAlignStack: - ir_print_set_align_stack(irp, (IrInstSrcSetAlignStack *)instruction); + case Stage1ZirInstIdSetAlignStack: + ir_print_set_align_stack(irp, (Stage1ZirInstSetAlignStack *)instruction); break; - case IrInstSrcIdArgTypeAllowVarFalse: - ir_print_arg_type(irp, (IrInstSrcArgType *)instruction, false); + case Stage1ZirInstIdArgTypeAllowVarFalse: + ir_print_arg_type(irp, (Stage1ZirInstArgType *)instruction, false); break; - case IrInstSrcIdArgTypeAllowVarTrue: - ir_print_arg_type(irp, (IrInstSrcArgType *)instruction, true); + case Stage1ZirInstIdArgTypeAllowVarTrue: + ir_print_arg_type(irp, (Stage1ZirInstArgType *)instruction, true); break; - case IrInstSrcIdExport: - ir_print_export(irp, (IrInstSrcExport *)instruction); + case Stage1ZirInstIdExport: + ir_print_export(irp, (Stage1ZirInstExport *)instruction); break; - case IrInstSrcIdExtern: - ir_print_extern(irp, (IrInstSrcExtern*)instruction); + case Stage1ZirInstIdExtern: + ir_print_extern(irp, (Stage1ZirInstExtern*)instruction); break; - case IrInstSrcIdErrorReturnTrace: - ir_print_error_return_trace(irp, (IrInstSrcErrorReturnTrace *)instruction); + case Stage1ZirInstIdErrorReturnTrace: + ir_print_error_return_trace(irp, (Stage1ZirInstErrorReturnTrace *)instruction); break; - case IrInstSrcIdErrorUnion: - ir_print_error_union(irp, (IrInstSrcErrorUnion *)instruction); + case Stage1ZirInstIdErrorUnion: + ir_print_error_union(irp, (Stage1ZirInstErrorUnion *)instruction); break; - case IrInstSrcIdAtomicRmw: - ir_print_atomic_rmw(irp, (IrInstSrcAtomicRmw *)instruction); + case Stage1ZirInstIdAtomicRmw: + ir_print_atomic_rmw(irp, (Stage1ZirInstAtomicRmw *)instruction); break; - case IrInstSrcIdSaveErrRetAddr: - ir_print_save_err_ret_addr(irp, (IrInstSrcSaveErrRetAddr *)instruction); + case Stage1ZirInstIdSaveErrRetAddr: + ir_print_save_err_ret_addr(irp, (Stage1ZirInstSaveErrRetAddr *)instruction); break; - case IrInstSrcIdAddImplicitReturnType: - ir_print_add_implicit_return_type(irp, (IrInstSrcAddImplicitReturnType *)instruction); + case Stage1ZirInstIdAddImplicitReturnType: + ir_print_add_implicit_return_type(irp, (Stage1ZirInstAddImplicitReturnType *)instruction); break; - case IrInstSrcIdFloatOp: - ir_print_float_op(irp, (IrInstSrcFloatOp *)instruction); + case Stage1ZirInstIdFloatOp: + ir_print_float_op(irp, (Stage1ZirInstFloatOp *)instruction); break; - case IrInstSrcIdMulAdd: - ir_print_mul_add(irp, (IrInstSrcMulAdd *)instruction); + case Stage1ZirInstIdMulAdd: + ir_print_mul_add(irp, (Stage1ZirInstMulAdd *)instruction); break; - case IrInstSrcIdAtomicLoad: - ir_print_atomic_load(irp, (IrInstSrcAtomicLoad *)instruction); + case Stage1ZirInstIdAtomicLoad: + ir_print_atomic_load(irp, (Stage1ZirInstAtomicLoad *)instruction); break; - case IrInstSrcIdAtomicStore: - ir_print_atomic_store(irp, (IrInstSrcAtomicStore *)instruction); + case Stage1ZirInstIdAtomicStore: + ir_print_atomic_store(irp, (Stage1ZirInstAtomicStore *)instruction); break; - case IrInstSrcIdEnumToInt: - ir_print_enum_to_int(irp, (IrInstSrcEnumToInt *)instruction); + case Stage1ZirInstIdEnumToInt: + ir_print_enum_to_int(irp, (Stage1ZirInstEnumToInt *)instruction); break; - case IrInstSrcIdCheckRuntimeScope: - ir_print_check_runtime_scope(irp, (IrInstSrcCheckRuntimeScope *)instruction); + case Stage1ZirInstIdCheckRuntimeScope: + ir_print_check_runtime_scope(irp, (Stage1ZirInstCheckRuntimeScope *)instruction); break; - case IrInstSrcIdHasDecl: - ir_print_has_decl(irp, (IrInstSrcHasDecl *)instruction); + case Stage1ZirInstIdHasDecl: + ir_print_has_decl(irp, (Stage1ZirInstHasDecl *)instruction); break; - case IrInstSrcIdUndeclaredIdent: - ir_print_undeclared_ident(irp, (IrInstSrcUndeclaredIdent *)instruction); + case Stage1ZirInstIdUndeclaredIdent: + ir_print_undeclared_ident(irp, (Stage1ZirInstUndeclaredIdent *)instruction); break; - case IrInstSrcIdAlloca: - ir_print_alloca_src(irp, (IrInstSrcAlloca *)instruction); + case Stage1ZirInstIdAlloca: + ir_print_alloca_src(irp, (Stage1ZirInstAlloca *)instruction); break; - case IrInstSrcIdEndExpr: - ir_print_end_expr(irp, (IrInstSrcEndExpr *)instruction); + case Stage1ZirInstIdEndExpr: + ir_print_end_expr(irp, (Stage1ZirInstEndExpr *)instruction); break; - case IrInstSrcIdUnionInitNamedField: - ir_print_union_init_named_field(irp, (IrInstSrcUnionInitNamedField *)instruction); + case Stage1ZirInstIdUnionInitNamedField: + ir_print_union_init_named_field(irp, (Stage1ZirInstUnionInitNamedField *)instruction); break; - case IrInstSrcIdSuspendBegin: - ir_print_suspend_begin(irp, (IrInstSrcSuspendBegin *)instruction); + case Stage1ZirInstIdSuspendBegin: + ir_print_suspend_begin(irp, (Stage1ZirInstSuspendBegin *)instruction); break; - case IrInstSrcIdSuspendFinish: - ir_print_suspend_finish(irp, (IrInstSrcSuspendFinish *)instruction); + case Stage1ZirInstIdSuspendFinish: + ir_print_suspend_finish(irp, (Stage1ZirInstSuspendFinish *)instruction); break; - case IrInstSrcIdResume: - ir_print_resume(irp, (IrInstSrcResume *)instruction); + case Stage1ZirInstIdResume: + ir_print_resume(irp, (Stage1ZirInstResume *)instruction); break; - case IrInstSrcIdAwait: - ir_print_await_src(irp, (IrInstSrcAwait *)instruction); + case Stage1ZirInstIdAwait: + ir_print_await_src(irp, (Stage1ZirInstAwait *)instruction); break; - case IrInstSrcIdSpillBegin: - ir_print_spill_begin(irp, (IrInstSrcSpillBegin *)instruction); + case Stage1ZirInstIdSpillBegin: + ir_print_spill_begin(irp, (Stage1ZirInstSpillBegin *)instruction); break; - case IrInstSrcIdSpillEnd: - ir_print_spill_end(irp, (IrInstSrcSpillEnd *)instruction); + case Stage1ZirInstIdSpillEnd: + ir_print_spill_end(irp, (Stage1ZirInstSpillEnd *)instruction); break; - case IrInstSrcIdClz: - ir_print_clz(irp, (IrInstSrcClz *)instruction); + case Stage1ZirInstIdClz: + ir_print_clz(irp, (Stage1ZirInstClz *)instruction); break; - case IrInstSrcIdWasmMemorySize: - ir_print_wasm_memory_size(irp, (IrInstSrcWasmMemorySize *)instruction); + case Stage1ZirInstIdWasmMemorySize: + ir_print_wasm_memory_size(irp, (Stage1ZirInstWasmMemorySize *)instruction); break; - case IrInstSrcIdWasmMemoryGrow: - ir_print_wasm_memory_grow(irp, (IrInstSrcWasmMemoryGrow *)instruction); + case Stage1ZirInstIdWasmMemoryGrow: + ir_print_wasm_memory_grow(irp, (Stage1ZirInstWasmMemoryGrow *)instruction); break; - case IrInstSrcIdSrc: - ir_print_builtin_src(irp, (IrInstSrcSrc *)instruction); + case Stage1ZirInstIdSrc: + ir_print_builtin_src(irp, (Stage1ZirInstSrc *)instruction); break; } fprintf(irp->f, "\n"); } -static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trailing) { +static void ir_print_inst_gen(IrPrintGen *irp, Stage1AirInst *instruction, bool trailing) { ir_print_prefix_gen(irp, instruction, trailing); switch (instruction->id) { - case IrInstGenIdInvalid: + case Stage1AirInstIdInvalid: zig_unreachable(); - case IrInstGenIdReturn: - ir_print_return_gen(irp, (IrInstGenReturn *)instruction); + case Stage1AirInstIdReturn: + ir_print_return_gen(irp, (Stage1AirInstReturn *)instruction); break; - case IrInstGenIdConst: - ir_print_const(irp, (IrInstGenConst *)instruction); + case Stage1AirInstIdConst: + ir_print_const(irp, (Stage1AirInstConst *)instruction); break; - case IrInstGenIdBinOp: - ir_print_bin_op(irp, (IrInstGenBinOp *)instruction); + case Stage1AirInstIdBinOp: + ir_print_bin_op(irp, (Stage1AirInstBinOp *)instruction); break; - case IrInstGenIdDeclVar: - ir_print_decl_var_gen(irp, (IrInstGenDeclVar *)instruction); + case Stage1AirInstIdDeclVar: + ir_print_decl_var_gen(irp, (Stage1AirInstDeclVar *)instruction); break; - case IrInstGenIdCast: - ir_print_cast(irp, (IrInstGenCast *)instruction); + case Stage1AirInstIdCast: + ir_print_cast(irp, (Stage1AirInstCast *)instruction); break; - case IrInstGenIdCall: - ir_print_call_gen(irp, (IrInstGenCall *)instruction); + case Stage1AirInstIdCall: + ir_print_call_gen(irp, (Stage1AirInstCall *)instruction); break; - case IrInstGenIdCondBr: - ir_print_cond_br(irp, (IrInstGenCondBr *)instruction); + case Stage1AirInstIdCondBr: + ir_print_cond_br(irp, (Stage1AirInstCondBr *)instruction); break; - case IrInstGenIdBr: - ir_print_br(irp, (IrInstGenBr *)instruction); + case Stage1AirInstIdBr: + ir_print_br(irp, (Stage1AirInstBr *)instruction); break; - case IrInstGenIdPhi: - ir_print_phi(irp, (IrInstGenPhi *)instruction); + case Stage1AirInstIdPhi: + ir_print_phi(irp, (Stage1AirInstPhi *)instruction); break; - case IrInstGenIdUnreachable: - ir_print_unreachable(irp, (IrInstGenUnreachable *)instruction); + case Stage1AirInstIdUnreachable: + ir_print_unreachable(irp, (Stage1AirInstUnreachable *)instruction); break; - case IrInstGenIdElemPtr: - ir_print_elem_ptr(irp, (IrInstGenElemPtr *)instruction); + case Stage1AirInstIdElemPtr: + ir_print_elem_ptr(irp, (Stage1AirInstElemPtr *)instruction); break; - case IrInstGenIdVarPtr: - ir_print_var_ptr(irp, (IrInstGenVarPtr *)instruction); + case Stage1AirInstIdVarPtr: + ir_print_var_ptr(irp, (Stage1AirInstVarPtr *)instruction); break; - case IrInstGenIdReturnPtr: - ir_print_return_ptr(irp, (IrInstGenReturnPtr *)instruction); + case Stage1AirInstIdReturnPtr: + ir_print_return_ptr(irp, (Stage1AirInstReturnPtr *)instruction); break; - case IrInstGenIdLoadPtr: - ir_print_load_ptr_gen(irp, (IrInstGenLoadPtr *)instruction); + case Stage1AirInstIdLoadPtr: + ir_print_load_ptr_gen(irp, (Stage1AirInstLoadPtr *)instruction); break; - case IrInstGenIdStorePtr: - ir_print_store_ptr(irp, (IrInstGenStorePtr *)instruction); + case Stage1AirInstIdStorePtr: + ir_print_store_ptr(irp, (Stage1AirInstStorePtr *)instruction); break; - case IrInstGenIdStructFieldPtr: - ir_print_struct_field_ptr(irp, (IrInstGenStructFieldPtr *)instruction); + case Stage1AirInstIdStructFieldPtr: + ir_print_struct_field_ptr(irp, (Stage1AirInstStructFieldPtr *)instruction); break; - case IrInstGenIdUnionFieldPtr: - ir_print_union_field_ptr(irp, (IrInstGenUnionFieldPtr *)instruction); + case Stage1AirInstIdUnionFieldPtr: + ir_print_union_field_ptr(irp, (Stage1AirInstUnionFieldPtr *)instruction); break; - case IrInstGenIdAsm: - ir_print_asm_gen(irp, (IrInstGenAsm *)instruction); + case Stage1AirInstIdAsm: + ir_print_asm_gen(irp, (Stage1AirInstAsm *)instruction); break; - case IrInstGenIdTestNonNull: - ir_print_test_non_null(irp, (IrInstGenTestNonNull *)instruction); + case Stage1AirInstIdTestNonNull: + ir_print_test_non_null(irp, (Stage1AirInstTestNonNull *)instruction); break; - case IrInstGenIdOptionalUnwrapPtr: - ir_print_optional_unwrap_ptr(irp, (IrInstGenOptionalUnwrapPtr *)instruction); + case Stage1AirInstIdOptionalUnwrapPtr: + ir_print_optional_unwrap_ptr(irp, (Stage1AirInstOptionalUnwrapPtr *)instruction); break; - case IrInstGenIdPopCount: - ir_print_pop_count(irp, (IrInstGenPopCount *)instruction); + case Stage1AirInstIdPopCount: + ir_print_pop_count(irp, (Stage1AirInstPopCount *)instruction); break; - case IrInstGenIdClz: - ir_print_clz(irp, (IrInstGenClz *)instruction); + case Stage1AirInstIdClz: + ir_print_clz(irp, (Stage1AirInstClz *)instruction); break; - case IrInstGenIdCtz: - ir_print_ctz(irp, (IrInstGenCtz *)instruction); + case Stage1AirInstIdCtz: + ir_print_ctz(irp, (Stage1AirInstCtz *)instruction); break; - case IrInstGenIdBswap: - ir_print_bswap(irp, (IrInstGenBswap *)instruction); + case Stage1AirInstIdBswap: + ir_print_bswap(irp, (Stage1AirInstBswap *)instruction); break; - case IrInstGenIdBitReverse: - ir_print_bit_reverse(irp, (IrInstGenBitReverse *)instruction); + case Stage1AirInstIdBitReverse: + ir_print_bit_reverse(irp, (Stage1AirInstBitReverse *)instruction); break; - case IrInstGenIdSwitchBr: - ir_print_switch_br(irp, (IrInstGenSwitchBr *)instruction); + case Stage1AirInstIdSwitchBr: + ir_print_switch_br(irp, (Stage1AirInstSwitchBr *)instruction); break; - case IrInstGenIdUnionTag: - ir_print_union_tag(irp, (IrInstGenUnionTag *)instruction); + case Stage1AirInstIdUnionTag: + ir_print_union_tag(irp, (Stage1AirInstUnionTag *)instruction); break; - case IrInstGenIdRef: - ir_print_ref_gen(irp, (IrInstGenRef *)instruction); + case Stage1AirInstIdRef: + ir_print_ref_gen(irp, (Stage1AirInstRef *)instruction); break; - case IrInstGenIdErrName: - ir_print_err_name(irp, (IrInstGenErrName *)instruction); + case Stage1AirInstIdErrName: + ir_print_err_name(irp, (Stage1AirInstErrName *)instruction); break; - case IrInstGenIdCmpxchg: - ir_print_cmpxchg_gen(irp, (IrInstGenCmpxchg *)instruction); + case Stage1AirInstIdCmpxchg: + ir_print_cmpxchg_gen(irp, (Stage1AirInstCmpxchg *)instruction); break; - case IrInstGenIdFence: - ir_print_fence(irp, (IrInstGenFence *)instruction); + case Stage1AirInstIdFence: + ir_print_fence(irp, (Stage1AirInstFence *)instruction); break; - case IrInstGenIdReduce: - ir_print_reduce(irp, (IrInstGenReduce *)instruction); + case Stage1AirInstIdReduce: + ir_print_reduce(irp, (Stage1AirInstReduce *)instruction); break; - case IrInstGenIdTruncate: - ir_print_truncate(irp, (IrInstGenTruncate *)instruction); + case Stage1AirInstIdTruncate: + ir_print_truncate(irp, (Stage1AirInstTruncate *)instruction); break; - case IrInstGenIdShuffleVector: - ir_print_shuffle_vector(irp, (IrInstGenShuffleVector *)instruction); + case Stage1AirInstIdShuffleVector: + ir_print_shuffle_vector(irp, (Stage1AirInstShuffleVector *)instruction); break; - case IrInstGenIdSplat: - ir_print_splat_gen(irp, (IrInstGenSplat *)instruction); + case Stage1AirInstIdSplat: + ir_print_splat_gen(irp, (Stage1AirInstSplat *)instruction); break; - case IrInstGenIdBoolNot: - ir_print_bool_not(irp, (IrInstGenBoolNot *)instruction); + case Stage1AirInstIdBoolNot: + ir_print_bool_not(irp, (Stage1AirInstBoolNot *)instruction); break; - case IrInstGenIdMemset: - ir_print_memset(irp, (IrInstGenMemset *)instruction); + case Stage1AirInstIdMemset: + ir_print_memset(irp, (Stage1AirInstMemset *)instruction); break; - case IrInstGenIdMemcpy: - ir_print_memcpy(irp, (IrInstGenMemcpy *)instruction); + case Stage1AirInstIdMemcpy: + ir_print_memcpy(irp, (Stage1AirInstMemcpy *)instruction); break; - case IrInstGenIdSlice: - ir_print_slice_gen(irp, (IrInstGenSlice *)instruction); + case Stage1AirInstIdSlice: + ir_print_slice_gen(irp, (Stage1AirInstSlice *)instruction); break; - case IrInstGenIdBreakpoint: - ir_print_breakpoint(irp, (IrInstGenBreakpoint *)instruction); + case Stage1AirInstIdBreakpoint: + ir_print_breakpoint(irp, (Stage1AirInstBreakpoint *)instruction); break; - case IrInstGenIdReturnAddress: - ir_print_return_address(irp, (IrInstGenReturnAddress *)instruction); + case Stage1AirInstIdReturnAddress: + ir_print_return_address(irp, (Stage1AirInstReturnAddress *)instruction); break; - case IrInstGenIdFrameAddress: - ir_print_frame_address(irp, (IrInstGenFrameAddress *)instruction); + case Stage1AirInstIdFrameAddress: + ir_print_frame_address(irp, (Stage1AirInstFrameAddress *)instruction); break; - case IrInstGenIdFrameHandle: - ir_print_handle(irp, (IrInstGenFrameHandle *)instruction); + case Stage1AirInstIdFrameHandle: + ir_print_handle(irp, (Stage1AirInstFrameHandle *)instruction); break; - case IrInstGenIdFrameSize: - ir_print_frame_size_gen(irp, (IrInstGenFrameSize *)instruction); + case Stage1AirInstIdFrameSize: + ir_print_frame_size_gen(irp, (Stage1AirInstFrameSize *)instruction); break; - case IrInstGenIdOverflowOp: - ir_print_overflow_op(irp, (IrInstGenOverflowOp *)instruction); + case Stage1AirInstIdOverflowOp: + ir_print_overflow_op(irp, (Stage1AirInstOverflowOp *)instruction); break; - case IrInstGenIdTestErr: - ir_print_test_err_gen(irp, (IrInstGenTestErr *)instruction); + case Stage1AirInstIdTestErr: + ir_print_test_err_gen(irp, (Stage1AirInstTestErr *)instruction); break; - case IrInstGenIdUnwrapErrCode: - ir_print_unwrap_err_code(irp, (IrInstGenUnwrapErrCode *)instruction); + case Stage1AirInstIdUnwrapErrCode: + ir_print_unwrap_err_code(irp, (Stage1AirInstUnwrapErrCode *)instruction); break; - case IrInstGenIdUnwrapErrPayload: - ir_print_unwrap_err_payload(irp, (IrInstGenUnwrapErrPayload *)instruction); + case Stage1AirInstIdUnwrapErrPayload: + ir_print_unwrap_err_payload(irp, (Stage1AirInstUnwrapErrPayload *)instruction); break; - case IrInstGenIdOptionalWrap: - ir_print_optional_wrap(irp, (IrInstGenOptionalWrap *)instruction); + case Stage1AirInstIdOptionalWrap: + ir_print_optional_wrap(irp, (Stage1AirInstOptionalWrap *)instruction); break; - case IrInstGenIdErrWrapCode: - ir_print_err_wrap_code(irp, (IrInstGenErrWrapCode *)instruction); + case Stage1AirInstIdErrWrapCode: + ir_print_err_wrap_code(irp, (Stage1AirInstErrWrapCode *)instruction); break; - case IrInstGenIdErrWrapPayload: - ir_print_err_wrap_payload(irp, (IrInstGenErrWrapPayload *)instruction); + case Stage1AirInstIdErrWrapPayload: + ir_print_err_wrap_payload(irp, (Stage1AirInstErrWrapPayload *)instruction); break; - case IrInstGenIdPtrCast: - ir_print_ptr_cast_gen(irp, (IrInstGenPtrCast *)instruction); + case Stage1AirInstIdPtrCast: + ir_print_ptr_cast_gen(irp, (Stage1AirInstPtrCast *)instruction); break; - case IrInstGenIdBitCast: - ir_print_bit_cast_gen(irp, (IrInstGenBitCast *)instruction); + case Stage1AirInstIdBitCast: + ir_print_bit_cast_gen(irp, (Stage1AirInstBitCast *)instruction); break; - case IrInstGenIdWidenOrShorten: - ir_print_widen_or_shorten(irp, (IrInstGenWidenOrShorten *)instruction); + case Stage1AirInstIdWidenOrShorten: + ir_print_widen_or_shorten(irp, (Stage1AirInstWidenOrShorten *)instruction); break; - case IrInstGenIdPtrToInt: - ir_print_ptr_to_int(irp, (IrInstGenPtrToInt *)instruction); + case Stage1AirInstIdPtrToInt: + ir_print_ptr_to_int(irp, (Stage1AirInstPtrToInt *)instruction); break; - case IrInstGenIdIntToPtr: - ir_print_int_to_ptr(irp, (IrInstGenIntToPtr *)instruction); + case Stage1AirInstIdIntToPtr: + ir_print_int_to_ptr(irp, (Stage1AirInstIntToPtr *)instruction); break; - case IrInstGenIdIntToEnum: - ir_print_int_to_enum(irp, (IrInstGenIntToEnum *)instruction); + case Stage1AirInstIdIntToEnum: + ir_print_int_to_enum(irp, (Stage1AirInstIntToEnum *)instruction); break; - case IrInstGenIdIntToErr: - ir_print_int_to_err(irp, (IrInstGenIntToErr *)instruction); + case Stage1AirInstIdIntToErr: + ir_print_int_to_err(irp, (Stage1AirInstIntToErr *)instruction); break; - case IrInstGenIdErrToInt: - ir_print_err_to_int(irp, (IrInstGenErrToInt *)instruction); + case Stage1AirInstIdErrToInt: + ir_print_err_to_int(irp, (Stage1AirInstErrToInt *)instruction); break; - case IrInstGenIdTagName: - ir_print_tag_name(irp, (IrInstGenTagName *)instruction); + case Stage1AirInstIdTagName: + ir_print_tag_name(irp, (Stage1AirInstTagName *)instruction); break; - case IrInstGenIdPanic: - ir_print_panic(irp, (IrInstGenPanic *)instruction); + case Stage1AirInstIdPanic: + ir_print_panic(irp, (Stage1AirInstPanic *)instruction); break; - case IrInstGenIdFieldParentPtr: - ir_print_field_parent_ptr(irp, (IrInstGenFieldParentPtr *)instruction); + case Stage1AirInstIdFieldParentPtr: + ir_print_field_parent_ptr(irp, (Stage1AirInstFieldParentPtr *)instruction); break; - case IrInstGenIdAlignCast: - ir_print_align_cast(irp, (IrInstGenAlignCast *)instruction); + case Stage1AirInstIdAlignCast: + ir_print_align_cast(irp, (Stage1AirInstAlignCast *)instruction); break; - case IrInstGenIdErrorReturnTrace: - ir_print_error_return_trace(irp, (IrInstGenErrorReturnTrace *)instruction); + case Stage1AirInstIdErrorReturnTrace: + ir_print_error_return_trace(irp, (Stage1AirInstErrorReturnTrace *)instruction); break; - case IrInstGenIdAtomicRmw: - ir_print_atomic_rmw(irp, (IrInstGenAtomicRmw *)instruction); + case Stage1AirInstIdAtomicRmw: + ir_print_atomic_rmw(irp, (Stage1AirInstAtomicRmw *)instruction); break; - case IrInstGenIdSaveErrRetAddr: - ir_print_save_err_ret_addr(irp, (IrInstGenSaveErrRetAddr *)instruction); + case Stage1AirInstIdSaveErrRetAddr: + ir_print_save_err_ret_addr(irp, (Stage1AirInstSaveErrRetAddr *)instruction); break; - case IrInstGenIdFloatOp: - ir_print_float_op(irp, (IrInstGenFloatOp *)instruction); + case Stage1AirInstIdFloatOp: + ir_print_float_op(irp, (Stage1AirInstFloatOp *)instruction); break; - case IrInstGenIdMulAdd: - ir_print_mul_add(irp, (IrInstGenMulAdd *)instruction); + case Stage1AirInstIdMulAdd: + ir_print_mul_add(irp, (Stage1AirInstMulAdd *)instruction); break; - case IrInstGenIdAtomicLoad: - ir_print_atomic_load(irp, (IrInstGenAtomicLoad *)instruction); + case Stage1AirInstIdAtomicLoad: + ir_print_atomic_load(irp, (Stage1AirInstAtomicLoad *)instruction); break; - case IrInstGenIdAtomicStore: - ir_print_atomic_store(irp, (IrInstGenAtomicStore *)instruction); + case Stage1AirInstIdAtomicStore: + ir_print_atomic_store(irp, (Stage1AirInstAtomicStore *)instruction); break; - case IrInstGenIdArrayToVector: - ir_print_array_to_vector(irp, (IrInstGenArrayToVector *)instruction); + case Stage1AirInstIdArrayToVector: + ir_print_array_to_vector(irp, (Stage1AirInstArrayToVector *)instruction); break; - case IrInstGenIdVectorToArray: - ir_print_vector_to_array(irp, (IrInstGenVectorToArray *)instruction); + case Stage1AirInstIdVectorToArray: + ir_print_vector_to_array(irp, (Stage1AirInstVectorToArray *)instruction); break; - case IrInstGenIdPtrOfArrayToSlice: - ir_print_ptr_of_array_to_slice(irp, (IrInstGenPtrOfArrayToSlice *)instruction); + case Stage1AirInstIdPtrOfArrayToSlice: + ir_print_ptr_of_array_to_slice(irp, (Stage1AirInstPtrOfArrayToSlice *)instruction); break; - case IrInstGenIdAssertZero: - ir_print_assert_zero(irp, (IrInstGenAssertZero *)instruction); + case Stage1AirInstIdAssertZero: + ir_print_assert_zero(irp, (Stage1AirInstAssertZero *)instruction); break; - case IrInstGenIdAssertNonNull: - ir_print_assert_non_null(irp, (IrInstGenAssertNonNull *)instruction); + case Stage1AirInstIdAssertNonNull: + ir_print_assert_non_null(irp, (Stage1AirInstAssertNonNull *)instruction); break; - case IrInstGenIdAlloca: - ir_print_alloca_gen(irp, (IrInstGenAlloca *)instruction); + case Stage1AirInstIdAlloca: + ir_print_alloca_gen(irp, (Stage1AirInstAlloca *)instruction); break; - case IrInstGenIdSuspendBegin: - ir_print_suspend_begin(irp, (IrInstGenSuspendBegin *)instruction); + case Stage1AirInstIdSuspendBegin: + ir_print_suspend_begin(irp, (Stage1AirInstSuspendBegin *)instruction); break; - case IrInstGenIdSuspendFinish: - ir_print_suspend_finish(irp, (IrInstGenSuspendFinish *)instruction); + case Stage1AirInstIdSuspendFinish: + ir_print_suspend_finish(irp, (Stage1AirInstSuspendFinish *)instruction); break; - case IrInstGenIdResume: - ir_print_resume(irp, (IrInstGenResume *)instruction); + case Stage1AirInstIdResume: + ir_print_resume(irp, (Stage1AirInstResume *)instruction); break; - case IrInstGenIdAwait: - ir_print_await_gen(irp, (IrInstGenAwait *)instruction); + case Stage1AirInstIdAwait: + ir_print_await_gen(irp, (Stage1AirInstAwait *)instruction); break; - case IrInstGenIdSpillBegin: - ir_print_spill_begin(irp, (IrInstGenSpillBegin *)instruction); + case Stage1AirInstIdSpillBegin: + ir_print_spill_begin(irp, (Stage1AirInstSpillBegin *)instruction); break; - case IrInstGenIdSpillEnd: - ir_print_spill_end(irp, (IrInstGenSpillEnd *)instruction); + case Stage1AirInstIdSpillEnd: + ir_print_spill_end(irp, (Stage1AirInstSpillEnd *)instruction); break; - case IrInstGenIdVectorExtractElem: - ir_print_vector_extract_elem(irp, (IrInstGenVectorExtractElem *)instruction); + case Stage1AirInstIdVectorExtractElem: + ir_print_vector_extract_elem(irp, (Stage1AirInstVectorExtractElem *)instruction); break; - case IrInstGenIdVectorStoreElem: - ir_print_vector_store_elem(irp, (IrInstGenVectorStoreElem *)instruction); + case Stage1AirInstIdVectorStoreElem: + ir_print_vector_store_elem(irp, (Stage1AirInstVectorStoreElem *)instruction); break; - case IrInstGenIdBinaryNot: - ir_print_binary_not(irp, (IrInstGenBinaryNot *)instruction); + case Stage1AirInstIdBinaryNot: + ir_print_binary_not(irp, (Stage1AirInstBinaryNot *)instruction); break; - case IrInstGenIdNegation: - ir_print_negation(irp, (IrInstGenNegation *)instruction); + case Stage1AirInstIdNegation: + ir_print_negation(irp, (Stage1AirInstNegation *)instruction); break; - case IrInstGenIdWasmMemorySize: - ir_print_wasm_memory_size(irp, (IrInstGenWasmMemorySize *)instruction); + case Stage1AirInstIdWasmMemorySize: + ir_print_wasm_memory_size(irp, (Stage1AirInstWasmMemorySize *)instruction); break; - case IrInstGenIdWasmMemoryGrow: - ir_print_wasm_memory_grow(irp, (IrInstGenWasmMemoryGrow *)instruction); + case Stage1AirInstIdWasmMemoryGrow: + ir_print_wasm_memory_grow(irp, (Stage1AirInstWasmMemoryGrow *)instruction); break; - case IrInstGenIdExtern: - ir_print_extern(irp, (IrInstGenExtern *)instruction); + case Stage1AirInstIdExtern: + ir_print_extern(irp, (Stage1AirInstExtern *)instruction); break; } @@ -3351,15 +3351,15 @@ static void ir_print_inst_gen(IrPrintGen *irp, IrInstGen *instruction, bool trai static void irp_print_basic_block_src(IrPrintSrc *irp, Stage1ZirBasicBlock *current_block) { fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id); for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) { - IrInstSrc *instruction = current_block->instruction_list.at(instr_i); + Stage1ZirInst *instruction = current_block->instruction_list.at(instr_i); ir_print_inst_src(irp, instruction, false); } } -static void irp_print_basic_block_gen(IrPrintGen *irp, IrBasicBlockGen *current_block) { +static void irp_print_basic_block_gen(IrPrintGen *irp, Stage1AirBasicBlock *current_block) { fprintf(irp->f, "%s_%" PRIu32 ":\n", current_block->name_hint, current_block->debug_id); for (size_t instr_i = 0; instr_i < current_block->instruction_list.length; instr_i += 1) { - IrInstGen *instruction = current_block->instruction_list.at(instr_i); + Stage1AirInst *instruction = current_block->instruction_list.at(instr_i); irp->printed.put(instruction, 0); irp->pending.clear(); ir_print_inst_gen(irp, instruction, false); @@ -3378,7 +3378,7 @@ void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb irp_print_basic_block_src(&ir_print, bb); } -void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size) { +void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, Stage1AirBasicBlock *bb, int indent_size) { IrPrintGen ir_print = {}; ir_print.codegen = codegen; ir_print.f = f; @@ -3426,7 +3426,7 @@ void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_s irp->printed.deinit(); } -void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int indent_size) { +void ir_print_inst_src(CodeGen *codegen, FILE *f, Stage1ZirInst *instruction, int indent_size) { IrPrintSrc ir_print = {}; IrPrintSrc *irp = &ir_print; irp->codegen = codegen; @@ -3437,7 +3437,7 @@ void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *instruction, int in ir_print_inst_src(irp, instruction, false); } -void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int indent_size) { +void ir_print_inst_gen(CodeGen *codegen, FILE *f, Stage1AirInst *instruction, int indent_size) { IrPrintGen ir_print = {}; IrPrintGen *irp = &ir_print; irp->codegen = codegen; @@ -3451,8 +3451,8 @@ void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *instruction, int in ir_print_inst_gen(irp, instruction, false); } -void IrInstSrc::dump() { - IrInstSrc *inst = this; +void Stage1ZirInst::dump() { + Stage1ZirInst *inst = this; inst->src(); if (inst->scope == nullptr) { fprintf(stderr, "(null scope)\n"); diff --git a/src/stage1/ir_print.hpp b/src/stage1/ir_print.hpp index ec325adfa6..1baddc5bd9 100644 --- a/src/stage1/ir_print.hpp +++ b/src/stage1/ir_print.hpp @@ -14,12 +14,12 @@ void ir_print_src(CodeGen *codegen, FILE *f, Stage1Zir *executable, int indent_size); void ir_print_gen(CodeGen *codegen, FILE *f, Stage1Air *executable, int indent_size); -void ir_print_inst_src(CodeGen *codegen, FILE *f, IrInstSrc *inst, int indent_size); -void ir_print_inst_gen(CodeGen *codegen, FILE *f, IrInstGen *inst, int indent_size); +void ir_print_inst_src(CodeGen *codegen, FILE *f, Stage1ZirInst *inst, int indent_size); +void ir_print_inst_gen(CodeGen *codegen, FILE *f, Stage1AirInst *inst, int indent_size); void ir_print_basic_block_src(CodeGen *codegen, FILE *f, Stage1ZirBasicBlock *bb, int indent_size); -void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, IrBasicBlockGen *bb, int indent_size); +void ir_print_basic_block_gen(CodeGen *codegen, FILE *f, Stage1AirBasicBlock *bb, int indent_size); -const char* ir_inst_src_type_str(IrInstSrcId id); -const char* ir_inst_gen_type_str(IrInstGenId id); +const char* ir_inst_src_type_str(Stage1ZirInstId id); +const char* ir_inst_gen_type_str(Stage1AirInstId id); #endif