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x86_64: 2 means better
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@ -353,6 +353,7 @@ pub const Mnemonic = enum {
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pmovsxbd, pmovsxbq, pmovsxbw, pmovsxdq, pmovsxwd, pmovsxwq,
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pmovsxbd, pmovsxbq, pmovsxbw, pmovsxdq, pmovsxwd, pmovsxwq,
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pmovzxbd, pmovzxbq, pmovzxbw, pmovzxdq, pmovzxwd, pmovzxwq,
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pmovzxbd, pmovzxbq, pmovzxbw, pmovzxdq, pmovzxwd, pmovzxwq,
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pmulld,
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pmulld,
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ptest,
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roundpd, roundps, roundsd, roundss,
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roundpd, roundps, roundsd, roundss,
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// SSE4.2
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// SSE4.2
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pcmpgtq,
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pcmpgtq,
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@ -413,6 +414,7 @@ pub const Mnemonic = enum {
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vpsrad, vpsraq, vpsraw,
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vpsrad, vpsraq, vpsraw,
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vpsrld, vpsrldq, vpsrlq, vpsrlw,
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vpsrld, vpsrldq, vpsrlq, vpsrlw,
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vpsubb, vpsubd, vpsubq, vpsubsb, vpsubsw, vpsubusb, vpsubusw, vpsubw,
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vpsubb, vpsubd, vpsubq, vpsubsb, vpsubsw, vpsubusb, vpsubusw, vpsubw,
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vptest,
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vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
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vpunpckhbw, vpunpckhdq, vpunpckhqdq, vpunpckhwd,
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vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
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vpunpcklbw, vpunpckldq, vpunpcklqdq, vpunpcklwd,
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vpxor,
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vpxor,
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@ -421,6 +423,7 @@ pub const Mnemonic = enum {
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vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,
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vsqrtpd, vsqrtps, vsqrtsd, vsqrtss,
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vstmxcsr,
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vstmxcsr,
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vsubpd, vsubps, vsubsd, vsubss,
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vsubpd, vsubps, vsubsd, vsubss,
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vtestpd, vtestps,
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vxorpd, vxorps,
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vxorpd, vxorps,
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// F16C
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// F16C
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vcvtph2ps, vcvtps2ph,
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vcvtph2ps, vcvtps2ph,
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@ -150,6 +150,31 @@ pub const Condition = enum(u5) {
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.nz_or_p => .z_and_np,
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.nz_or_p => .z_and_np,
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};
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};
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}
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}
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/// Returns the equivalent condition when the operands are swapped.
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pub fn commute(cond: Condition) Condition {
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return switch (cond) {
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else => cond,
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.a => .b,
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.ae => .be,
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.b => .a,
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.be => .ae,
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.c => .a,
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.g => .l,
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.ge => .le,
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.l => .g,
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.le => .ge,
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.na => .nb,
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.nae => .nbe,
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.nb => .na,
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.nbe => .nae,
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.nc => .na,
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.ng => .nl,
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.nge => .nle,
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.nl => .ng,
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.nle => .nge,
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};
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}
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};
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};
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pub const Register = enum(u7) {
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pub const Register = enum(u7) {
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@ -1251,6 +1251,8 @@ pub const table = [_]Entry{
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.{ .pmulld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x40 }, 0, .none, .sse4_1 },
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.{ .pmulld, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x40 }, 0, .none, .sse4_1 },
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.{ .ptest, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x17 }, 0, .none, .sse4_1 },
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.{ .roundpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .none, .sse4_1 },
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.{ .roundpd, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x09 }, 0, .none, .sse4_1 },
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.{ .roundps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x08 }, 0, .none, .sse4_1 },
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.{ .roundps, .rmi, &.{ .xmm, .xmm_m128, .imm8 }, &.{ 0x66, 0x0f, 0x3a, 0x08 }, 0, .none, .sse4_1 },
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@ -1676,6 +1678,9 @@ pub const table = [_]Entry{
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.{ .vpsubusb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd8 }, 0, .vex_128_wig, .avx },
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.{ .vpsubusb, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd8 }, 0, .vex_128_wig, .avx },
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.{ .vpsubusw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd9 }, 0, .vex_128_wig, .avx },
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.{ .vpsubusw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0xd9 }, 0, .vex_128_wig, .avx },
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.{ .vptest, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x17 }, 0, .vex_128_wig, .avx },
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.{ .vptest, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x17 }, 0, .vex_256_wig, .avx },
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.{ .vpunpckhbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_128_wig, .avx },
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.{ .vpunpckhbw, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x68 }, 0, .vex_128_wig, .avx },
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.{ .vpunpckhwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_128_wig, .avx },
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.{ .vpunpckhwd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x69 }, 0, .vex_128_wig, .avx },
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.{ .vpunpckhdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_128_wig, .avx },
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.{ .vpunpckhdq, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x6a }, 0, .vex_128_wig, .avx },
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@ -1726,6 +1731,11 @@ pub const table = [_]Entry{
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.{ .vsubss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .vex_lig_wig, .avx },
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.{ .vsubss, .rvm, &.{ .xmm, .xmm, .xmm_m32 }, &.{ 0xf3, 0x0f, 0x5c }, 0, .vex_lig_wig, .avx },
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.{ .vtestps, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x0e }, 0, .vex_128_w0, .avx },
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.{ .vtestps, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x0e }, 0, .vex_256_w0, .avx },
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.{ .vtestpd, .rm, &.{ .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x38, 0x0f }, 0, .vex_128_w0, .avx },
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.{ .vtestpd, .rm, &.{ .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x38, 0x0f }, 0, .vex_256_w0, .avx },
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.{ .vxorpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_128_wig, .avx },
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.{ .vxorpd, .rvm, &.{ .xmm, .xmm, .xmm_m128 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_128_wig, .avx },
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.{ .vxorpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_256_wig, .avx },
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.{ .vxorpd, .rvm, &.{ .ymm, .ymm, .ymm_m256 }, &.{ 0x66, 0x0f, 0x57 }, 0, .vex_256_wig, .avx },
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@ -263,6 +263,12 @@ fn testBinary(comptime op: anytype) !void {
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0xbfd88aee1d82ed32, 0x20e91c15b701059a,
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0xbfd88aee1d82ed32, 0x20e91c15b701059a,
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0xed533d18f8657f3f, 0x1ddd7cd7f6bab957,
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0xed533d18f8657f3f, 0x1ddd7cd7f6bab957,
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});
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});
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if (false) try testType(@Vector(1, u128), .{
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0x5f11e16b0ca3392f907a857881455d2e,
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}, .{
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0xf9142d73b408fd6955922f9fc147f7d7,
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});
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}
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}
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inline fn bitAnd(comptime Type: type, lhs: Type, rhs: Type) @TypeOf(lhs & rhs) {
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inline fn bitAnd(comptime Type: type, lhs: Type, rhs: Type) @TypeOf(lhs & rhs) {
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