From 70c92331c79018f8c5cc845f1015af7fa941f3a4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Wed, 28 Aug 2024 21:32:06 +0200
Subject: [PATCH] llvm: Limit f16/f128 lowering on arm to fp_armv8 and soft
 float.

---
 src/codegen/llvm.zig | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index d7d1be6a50..5ba80e3c4e 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -12423,6 +12423,11 @@ fn backendSupportsF16(target: std.Target) bool {
         .mips64el,
         .s390x,
         => false,
+        .arm,
+        .armeb,
+        .thumb,
+        .thumbeb,
+        => target.floatAbi() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8),
         .aarch64,
         .aarch64_be,
         => std.Target.aarch64.featureSetHas(target.cpu.features, .fp_armv8),
@@ -12445,6 +12450,11 @@ fn backendSupportsF128(target: std.Target) bool {
         .powerpc64,
         .powerpc64le,
         => target.os.tag != .aix,
+        .arm,
+        .armeb,
+        .thumb,
+        .thumbeb,
+        => target.floatAbi() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8),
         .aarch64,
         .aarch64_be,
         => std.Target.aarch64.featureSetHas(target.cpu.features, .fp_armv8),