From 67a052df81dbd40a49ce07b58e854d56b1def03a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:07:35 +0200 Subject: [PATCH] std.Target: Remove `amdil`/`amdil64` arch tags. This is really obscure and no one is 100% sure what it is. It seems to be old and unused. My suspicion is that it's just an old term for "AMDGPU" before it was upstreamed to LLVM. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project+amdil&type=code --- lib/compiler/aro/aro/target.zig | 6 ------ lib/std/Target.zig | 16 ---------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 34 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 7c6c879683..8d51fbabfd 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .x86, .xcore, .nvptx, - .amdil, .hsail, .spir, .kalimba, @@ -496,7 +495,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .aarch64 => copy.cpu.arch = .arm, .aarch64_be => copy.cpu.arch = .armeb, - .amdil64 => copy.cpu.arch = .amdil, .nvptx64 => copy.cpu.arch = .nvptx, .wasm64 => copy.cpu.arch = .wasm32, .hsail64 => copy.cpu.arch = .hsail, @@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .amdgcn, .bpfeb, .bpfel, - .amdil64, .nvptx64, .wasm64, .hsail64, @@ -559,7 +556,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { => {}, // Already 64 bit .aarch64_32 => copy.cpu.arch = .aarch64, - .amdil => copy.cpu.arch = .amdil64, .arm => copy.cpu.arch = .aarch64, .armeb => copy.cpu.arch = .aarch64_be, .hsail => copy.cpu.arch = .hsail64, @@ -631,8 +627,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .amdil => "amdil", - .amdil64 => "amdil64", .hsail => "hsail", .hsail64 => "hsail64", .spir => "spir", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index d281bcf6db..fedd339b3d 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1011,8 +1011,6 @@ pub const Cpu = struct { xtensa, nvptx, nvptx64, - amdil, - amdil64, hsail, hsail64, spir, @@ -1156,7 +1154,6 @@ pub const Cpu = struct { .xcore => .XCORE, .xtensa => .XTENSA, .nvptx => .NONE, - .amdil => .NONE, .hsail => .NONE, .spir => .NONE, .kalimba => .CSR_KALIMBA, @@ -1173,7 +1170,6 @@ pub const Cpu = struct { .riscv64 => .RISCV, .x86_64 => .X86_64, .nvptx64 => .NONE, - .amdil64 => .NONE, .hsail64 => .NONE, .spir64 => .NONE, .wasm64 => .NONE, @@ -1217,7 +1213,6 @@ pub const Cpu = struct { .xcore => .Unknown, .xtensa => .Unknown, .nvptx => .Unknown, - .amdil => .Unknown, .hsail => .Unknown, .spir => .Unknown, .kalimba => .Unknown, @@ -1234,7 +1229,6 @@ pub const Cpu = struct { .riscv64 => .RISCV64, .x86_64 => .X64, .nvptx64 => .Unknown, - .amdil64 => .Unknown, .hsail64 => .Unknown, .spir64 => .Unknown, .wasm64 => .Unknown, @@ -1261,8 +1255,6 @@ pub const Cpu = struct { .aarch64_32, .aarch64, .amdgcn, - .amdil, - .amdil64, .bpfel, .csky, .xtensa, @@ -1772,8 +1764,6 @@ pub const DynamicLinker = struct { .tce, .tcele, .xcore, - .amdil, - .amdil64, .hsail, .hsail64, .spir, @@ -1878,7 +1868,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .x86, .xcore, .nvptx, - .amdil, .hsail, .spir, .kalimba, @@ -1901,7 +1890,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .riscv64, .x86_64, .nvptx64, - .amdil64, .hsail64, .spir64, .wasm64, @@ -2402,7 +2390,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .amdil, .hsail, .spir, .spirv32, @@ -2415,7 +2402,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .aarch64_32, .amdgcn, - .amdil64, .bpfel, .bpfeb, .hexagon, @@ -2518,7 +2504,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .amdil, .hsail, .spir, .spirv32, @@ -2537,7 +2522,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .thumbeb, .aarch64_32, .amdgcn, - .amdil64, .bpfel, .bpfeb, .hexagon, diff --git a/src/Type.zig b/src/Type.zig index bfe9a94d33..093bd2cbbe 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1650,14 +1650,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .m68k, .tce, .tcele, - .amdil, .hsail, .spir, .kalimba, .spirv, .spirv32, .shave, - .amdil64, .hsail64, .spir64, .ve, diff --git a/src/Zcu.zig b/src/Zcu.zig index dbece763ec..b3b93507f4 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment( .thumbeb, .x86, .xcore, - .amdil, .hsail, .spir, .kalimba, @@ -3280,7 +3279,6 @@ pub fn atomicPtrAlignment( .riscv64, .sparc64, .s390x, - .amdil64, .hsail64, .spir64, .wasm64, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index b56ca01484..a4c417c6e6 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .amdil => "amdil", - .amdil64 => "amdil64", .hsail => "hsail", .hsail64 => "hsail64", .spir => "spir", @@ -303,8 +301,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .xtensa => .xtensa, .nvptx => .nvptx, .nvptx64 => .nvptx64, - .amdil => .amdil, - .amdil64 => .amdil64, .hsail => .hsail, .hsail64 => .hsail64, .spir => .spir, @@ -12088,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { // LLVM backends that have no initialization functions. .tce, .tcele, - .amdil, - .amdil64, .hsail, .hsail64, .shave, diff --git a/src/target.zig b/src/target.zig index 19b8320cd8..3e213df4f6 100644 --- a/src/target.zig +++ b/src/target.zig @@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .xtensa, .nvptx, .nvptx64, - .amdil, - .amdil64, .hsail, .hsail64, .spir,