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stage2: sparc64: Implement SPARCv9 and

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This commit is contained in:
Koakuma 2022-06-15 23:29:19 +07:00
parent 6218d70d09
commit 672cd2f02f
2 changed files with 11 additions and 1 deletions
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4
src/arch/sparc64/Emit.zig
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@ -93,7 +93,7 @@ pub fn emitMir(
.lduw => try emit.mirArithmetic3Op(inst),
.ldx => try emit.mirArithmetic3Op(inst),
.@"and" => @panic("TODO implement sparc64 and"),
.@"and" => try emit.mirArithmetic3Op(inst),
.@"or" => try emit.mirArithmetic3Op(inst),
.xor => try emit.mirArithmetic3Op(inst),
.xnor => try emit.mirArithmetic3Op(inst),
@ -227,6 +227,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
.lduh => try emit.writeInstruction(Instruction.lduh(i13, rs1, imm, rd)),
.lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)),
.ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)),
.@"and" => try emit.writeInstruction(Instruction.@"and"(i13, rs1, imm, rd)),
.@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)),
.xor => try emit.writeInstruction(Instruction.xor(i13, rs1, imm, rd)),
.xnor => try emit.writeInstruction(Instruction.xnor(i13, rs1, imm, rd)),
@ -251,6 +252,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
.lduh => try emit.writeInstruction(Instruction.lduh(Register, rs1, rs2, rd)),
.lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)),
.ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)),
.@"and" => try emit.writeInstruction(Instruction.@"and"(Register, rs1, rs2, rd)),
.@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)),
.xor => try emit.writeInstruction(Instruction.xor(Register, rs1, rs2, rd)),
.xnor => try emit.writeInstruction(Instruction.xnor(Register, rs1, rs2, rd)),

8
src/arch/sparc64/bits.zig
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@ -1229,6 +1229,14 @@ pub const Instruction = union(enum) {
};
}
pub fn @"and"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
return switch (s2) {
Register => format3a(0b10, 0b00_0001, rs1, rs2, rd),
i13 => format3b(0b10, 0b00_0001, rs1, rs2, rd),
else => unreachable,
};
}
pub fn @"or"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
return switch (s2) {
Register => format3a(0b10, 0b00_0010, rs1, rs2, rd),