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stage2 ARM: implement airCmp with binOp lowering mechanism
This commit is contained in:
joachimschmidt557
parent
c29bf2f51a
commit
669603029e
@ -1783,17 +1783,20 @@ fn binOpRegister(
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};
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defer self.register_manager.unfreezeRegs(&.{rhs_reg});
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const dest_reg = switch (tag) {
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.cmp_eq => .r0, // cmp has no destination regardless
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null);
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if (lhs_is_register and self.reuseOperand(inst, bin_op.lhs, 0, lhs)) {
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break :blk lhs_reg;
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} else if (rhs_is_register and self.reuseOperand(inst, bin_op.rhs, 1, rhs)) {
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break :blk rhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null),
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};
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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if (!rhs_is_register) try self.genSetReg(rhs_ty, rhs_reg, rhs);
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@ -1801,6 +1804,7 @@ fn binOpRegister(
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add, .ptr_add => .add,
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.sub, .ptr_sub => .sub,
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.cmp_eq => .cmp,
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.mul => .mul,
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.bit_and,
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.bool_and,
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@ -1823,6 +1827,7 @@ fn binOpRegister(
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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.cmp_eq,
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.bit_and,
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.bool_and,
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.bit_or,
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@ -1904,26 +1909,30 @@ fn binOpImmediate(
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};
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defer self.register_manager.unfreezeRegs(&.{lhs_reg});
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const dest_reg = if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const dest_reg = switch (tag) {
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.cmp_eq => .r0, // cmp has no destination reg
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else => if (maybe_inst) |inst| blk: {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (lhs_is_register and self.reuseOperand(
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inst,
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if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
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if (lhs_and_rhs_swapped) 1 else 0,
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lhs,
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)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null);
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if (lhs_is_register and self.reuseOperand(
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inst,
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if (lhs_and_rhs_swapped) bin_op.rhs else bin_op.lhs,
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if (lhs_and_rhs_swapped) 1 else 0,
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lhs,
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)) {
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break :blk lhs_reg;
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} else {
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break :blk try self.register_manager.allocReg(inst);
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}
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} else try self.register_manager.allocReg(null),
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};
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if (!lhs_is_register) try self.genSetReg(lhs_ty, lhs_reg, lhs);
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const mir_tag: Mir.Inst.Tag = switch (tag) {
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.add => .add,
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.sub => .sub,
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.cmp_eq => .cmp,
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.bit_and,
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.bool_and,
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=> .@"and",
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@ -1945,6 +1954,7 @@ fn binOpImmediate(
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const mir_data: Mir.Inst.Data = switch (tag) {
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.add,
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.sub,
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.cmp_eq,
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.bit_and,
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.bool_and,
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.bit_or,
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@ -1999,6 +2009,7 @@ fn binOp(
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switch (tag) {
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.add,
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.sub,
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.cmp_eq,
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=> {
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switch (lhs_ty.zigTypeTag()) {
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.Float => return self.fail("TODO ARM binary operations on floats", .{}),
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@ -2012,12 +2023,15 @@ fn binOp(
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// operands
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const lhs_immediate_ok = switch (tag) {
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.add => lhs == .immediate and Instruction.Operand.fromU32(lhs.immediate) != null,
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.sub => false,
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.sub,
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.cmp_eq,
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=> false,
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else => unreachable,
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};
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const rhs_immediate_ok = switch (tag) {
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.add,
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.sub,
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.cmp_eq,
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=> rhs == .immediate and Instruction.Operand.fromU32(rhs.immediate) != null,
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else => unreachable,
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};
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@ -2150,31 +2164,6 @@ fn binOp(
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}
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}
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fn armOperandShouldBeRegister(self: *Self, mcv: MCValue) !bool {
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return switch (mcv) {
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.none => unreachable,
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.undef => unreachable,
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.dead, .unreach => unreachable,
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.compare_flags_unsigned => unreachable,
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.compare_flags_signed => unreachable,
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.ptr_stack_offset => unreachable,
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.ptr_embedded_in_code => unreachable,
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.immediate => |imm| blk: {
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if (imm > std.math.maxInt(u32)) return self.fail("TODO ARM binary arithmetic immediate larger than u32", .{});
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// Load immediate into register if it doesn't fit
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// in an operand
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break :blk Instruction.Operand.fromU32(@intCast(u32, imm)) == null;
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},
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.register => true,
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.stack_offset,
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.stack_argument_offset,
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.embedded_in_code,
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.memory,
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=> true,
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};
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}
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fn genLdrRegister(self: *Self, dest_reg: Register, addr_reg: Register, abi_size: u32) !void {
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switch (abi_size) {
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1, 3, 4 => {
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@ -2548,84 +2537,38 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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const rhs = try self.resolveInst(bin_op.rhs);
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const lhs_ty = self.air.typeOf(bin_op.lhs);
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if (lhs_ty.abiSize(self.target.*) > 4) {
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return self.fail("TODO cmp for types with size > 4", .{});
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}
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const signedness: std.builtin.Signedness = blk: {
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// by default we tell the operand type is unsigned (i.e. bools and enum values)
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if (lhs_ty.zigTypeTag() != .Int) break :blk .unsigned;
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// incase of an actual integer, we emit the correct signedness
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break :blk lhs_ty.intInfo(self.target.*).signedness;
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};
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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// lhs should always be a register
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const rhs_should_be_register = try self.armOperandShouldBeRegister(rhs);
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if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
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defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
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if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
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defer if (rhs_is_register) self.register_manager.unfreezeRegs(&.{rhs.register});
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var lhs_mcv = lhs;
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var rhs_mcv = rhs;
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// Allocate registers
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if (rhs_should_be_register) {
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if (!lhs_is_register and !rhs_is_register) {
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const regs = try self.register_manager.allocRegs(2, .{
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Air.refToIndex(bin_op.lhs).?, Air.refToIndex(bin_op.rhs).?,
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});
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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} else if (!rhs_is_register) {
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const track_inst = if (self.liveness.operandDies(inst, 1)) null else Air.refToIndex(bin_op.rhs).?;
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rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(track_inst) };
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} else if (!lhs_is_register) {
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const track_inst = if (self.liveness.operandDies(inst, 0)) null else Air.refToIndex(bin_op.lhs).?;
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lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(track_inst) };
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}
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} else {
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if (!lhs_is_register) {
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const track_inst = if (self.liveness.operandDies(inst, 0)) null else Air.refToIndex(bin_op.lhs).?;
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lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(track_inst) };
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}
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}
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// Move the operands to the newly allocated registers
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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if (lhs_mcv == .register and !lhs_is_register) {
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try self.genSetReg(lhs_ty, lhs_mcv.register, lhs);
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branch.inst_table.putAssumeCapacity(Air.refToIndex(bin_op.lhs).?, lhs);
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}
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if (rhs_mcv == .register and !rhs_is_register) {
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try self.genSetReg(lhs_ty, rhs_mcv.register, rhs);
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branch.inst_table.putAssumeCapacity(Air.refToIndex(bin_op.rhs).?, rhs);
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}
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_ = try self.addInst(.{
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.tag = .cmp,
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.data = .{ .rr_op = .{
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.rd = undefined,
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.rn = lhs_mcv.register,
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.op = switch (rhs_mcv) {
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.immediate => |imm| Instruction.Operand.fromU32(@intCast(u32, imm)).?,
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.register => |reg| Instruction.Operand.reg(reg, Instruction.Operand.Shift.none),
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switch (lhs_ty.zigTypeTag()) {
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.Vector => return self.fail("TODO ARM cmp vectors", .{}),
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.Optional => return self.fail("TODO ARM cmp optionals", .{}),
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.Float => return self.fail("TODO ARM cmp floats", .{}),
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.Int, .Bool, .Pointer, .ErrorSet, .Enum => {
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var int_buffer: Type.Payload.Bits = undefined;
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const int_ty = switch (lhs_ty.zigTypeTag()) {
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.Enum => lhs_ty.intTagType(&int_buffer),
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.Int => lhs_ty,
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.Bool => Type.initTag(.u1),
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.Pointer => Type.usize,
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.ErrorSet => Type.initTag(.u16),
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else => unreachable,
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},
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} },
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});
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};
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break :result switch (signedness) {
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.signed => MCValue{ .compare_flags_signed = op },
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.unsigned => MCValue{ .compare_flags_unsigned = op },
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};
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const int_info = int_ty.intInfo(self.target.*);
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if (int_info.bits <= 32) {
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try self.spillCompareFlagsIfOccupied();
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self.compare_flags_inst = inst;
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_ = try self.binOp(.cmp_eq, inst, lhs, rhs, int_ty, int_ty);
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break :result switch (int_info.signedness) {
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.signed => MCValue{ .compare_flags_signed = op },
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.unsigned => MCValue{ .compare_flags_unsigned = op },
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};
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} else {
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return self.fail("TODO ARM cmp for ints > 32 bits", .{});
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}
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},
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else => unreachable,
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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