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x86_64: implement some binary ops for large values
This commit is contained in:
Jacob Young
parent
3a516433b0
commit
65838fcabe
@ -4010,9 +4010,6 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue
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.register_overflow => unreachable,
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.register => |dst_reg| try self.asmRegister(mir_tag, registerAlias(dst_reg, abi_size)),
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.ptr_stack_offset, .stack_offset => |off| {
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if (off > math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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if (abi_size > 8) {
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return self.fail("TODO implement {} for stack dst with large ABI", .{mir_tag});
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}
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@ -4454,9 +4451,6 @@ fn genBinOp(
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if (lhs_ty.zigTypeTag() == .Vector) {
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return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmt(self.bin_file.options.module.?)});
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}
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if (lhs_ty.abiSize(self.target.*) > 8) {
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return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmt(self.bin_file.options.module.?)});
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}
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switch (lhs) {
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.immediate => |imm| switch (imm) {
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@ -4686,7 +4680,6 @@ fn genBinOp(
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const addr_reg = (try self.register_manager.allocReg(null, gp)).to64();
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const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
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defer self.register_manager.unlockReg(addr_reg_lock);
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try self.loadMemPtrIntoRegister(addr_reg, Type.usize, mat_src_mcv);
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// To get the actual address of the value we want to modify we
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@ -4801,9 +4794,6 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
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return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = reg });
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},
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.stack_offset => |off| {
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if (off > math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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try self.asmRegisterMemory(
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mir_tag,
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registerAlias(dst_reg, abi_size),
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@ -4812,78 +4802,155 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
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},
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}
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},
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.ptr_stack_offset, .stack_offset => |off| {
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if (off > math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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if (abi_size > 8) {
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return self.fail("TODO implement {} for stack dst with large ABI", .{mir_tag});
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}
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.ptr_stack_offset, .stack_offset => |dst_off| {
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const src: ?struct {
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limb_reg: Register,
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limb_lock: RegisterLock,
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addr_reg: Register,
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addr_lock: RegisterLock,
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} = switch (src_mcv) {
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else => null,
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.memory, .linker_load => addr: {
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const src_limb_reg = try self.register_manager.allocReg(null, gp);
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const src_limb_lock = self.register_manager.lockRegAssumeUnused(src_limb_reg);
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errdefer self.register_manager.unlockReg(src_limb_lock);
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switch (src_mcv) {
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.none => unreachable,
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.undef => unreachable,
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.dead, .unreach => unreachable,
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.register_overflow => unreachable,
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.register => |src_reg| {
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try self.asmMemoryRegister(mir_tag, Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .rbp,
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.disp = -off,
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}), registerAlias(src_reg, abi_size));
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const src_addr_reg = try self.register_manager.allocReg(null, gp);
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const src_addr_lock = self.register_manager.lockRegAssumeUnused(src_addr_reg);
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errdefer self.register_manager.unlockReg(src_addr_lock);
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try self.loadMemPtrIntoRegister(src_addr_reg, Type.usize, src_mcv);
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// To get the actual address of the value we want to modify we
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// we have to go through the GOT
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try self.asmRegisterMemory(
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.mov,
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src_addr_reg,
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Memory.sib(.qword, .{ .base = src_addr_reg }),
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);
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break :addr .{
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.addr_reg = src_addr_reg,
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.addr_lock = src_addr_lock,
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.limb_reg = src_limb_reg,
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.limb_lock = src_limb_lock,
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};
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},
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.immediate => |imm| {
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switch (self.regBitSize(ty)) {
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8, 16, 32 => {
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try self.asmMemoryImmediate(
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mir_tag,
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .rbp,
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.disp = -off,
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}),
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if (math.cast(i32, @bitCast(i64, imm))) |small|
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Immediate.s(small)
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else
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Immediate.u(@intCast(u32, imm)),
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);
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},
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64 => {
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if (math.cast(i32, @bitCast(i64, imm))) |small| {
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};
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defer if (src) |locks| {
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self.register_manager.unlockReg(locks.limb_lock);
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self.register_manager.unlockReg(locks.addr_lock);
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};
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const ty_signedness =
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if (ty.isAbiInt()) ty.intInfo(self.target.*).signedness else .unsigned;
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const limb_ty = if (abi_size <= 8) ty else switch (ty_signedness) {
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.signed => Type.usize,
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.unsigned => Type.isize,
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};
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const limb_abi_size = @min(abi_size, 8);
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var off: i32 = 0;
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while (off < abi_size) : (off += 8) {
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const mir_limb_tag = switch (off) {
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0 => mir_tag,
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else => switch (mir_tag) {
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.add => .adc,
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.sub => .sbb,
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.@"or", .@"and", .xor => mir_tag,
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else => return self.fail("TODO genBinOpMir implement large ABI for {s}", .{
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@tagName(mir_tag),
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}),
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},
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};
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const dst_limb_mem = Memory.sib(
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Memory.PtrSize.fromSize(limb_abi_size),
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.{ .base = .rbp, .disp = off - dst_off },
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);
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switch (src_mcv) {
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.none => unreachable,
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.undef => unreachable,
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.dead, .unreach => unreachable,
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.register_overflow => unreachable,
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.register => |src_reg| {
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assert(off == 0);
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try self.asmMemoryRegister(
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mir_limb_tag,
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dst_limb_mem,
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registerAlias(src_reg, limb_abi_size),
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);
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},
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.immediate => |src_imm| {
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const imm = if (off == 0) src_imm else switch (ty_signedness) {
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.signed => @bitCast(u64, @bitCast(i64, src_imm) >> 63),
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.unsigned => 0,
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};
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switch (self.regBitSize(limb_ty)) {
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8, 16, 32 => {
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try self.asmMemoryImmediate(
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mir_tag,
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .rbp,
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.disp = -off,
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}),
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Immediate.s(small),
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mir_limb_tag,
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dst_limb_mem,
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if (math.cast(i32, @bitCast(i64, imm))) |small|
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Immediate.s(small)
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else
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Immediate.u(@intCast(u32, imm)),
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);
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} else {
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try self.asmMemoryRegister(
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mir_tag,
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Memory.sib(Memory.PtrSize.fromSize(abi_size), .{
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.base = .rbp,
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.disp = -off,
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}),
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registerAlias(try self.copyToTmpRegister(ty, src_mcv), abi_size),
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);
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}
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},
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else => return self.fail("TODO genBinOpMir implement large immediate ABI", .{}),
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}
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},
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.memory,
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.linker_load,
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.stack_offset,
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.ptr_stack_offset,
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.eflags,
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=> {
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assert(abi_size <= 8);
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},
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64 => {
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if (math.cast(i32, @bitCast(i64, imm))) |small| {
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try self.asmMemoryImmediate(
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mir_limb_tag,
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dst_limb_mem,
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Immediate.s(small),
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);
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} else {
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try self.asmMemoryRegister(
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mir_limb_tag,
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dst_limb_mem,
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registerAlias(
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try self.copyToTmpRegister(limb_ty, .{ .immediate = imm }),
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limb_abi_size,
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),
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);
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}
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},
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else => unreachable,
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}
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},
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.memory, .linker_load => {
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try self.asmRegisterMemory(
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.mov,
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registerAlias(src.?.limb_reg, limb_abi_size),
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Memory.sib(
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Memory.PtrSize.fromSize(limb_abi_size),
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.{ .base = src.?.addr_reg, .disp = off },
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),
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);
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try self.asmMemoryRegister(
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mir_limb_tag,
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dst_limb_mem,
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registerAlias(src.?.limb_reg, limb_abi_size),
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);
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},
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.stack_offset, .ptr_stack_offset, .eflags => {
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const src_limb_reg = try self.copyToTmpRegister(limb_ty, switch (src_mcv) {
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.stack_offset => |src_off| .{ .stack_offset = src_off - off },
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.ptr_stack_offset,
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.eflags,
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=> off: {
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assert(off == 0);
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break :off src_mcv;
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},
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else => unreachable,
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});
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const src_limb_lock = self.register_manager.lockReg(src_limb_reg);
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defer if (src_limb_lock) |lock| self.register_manager.unlockReg(lock);
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const tmp_reg = try self.copyToTmpRegister(ty, src_mcv);
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const tmp_lock = self.register_manager.lockReg(tmp_reg);
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defer if (tmp_lock) |lock| self.register_manager.unlockReg(lock);
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return self.genBinOpMir(mir_tag, ty, dst_mcv, .{ .register = tmp_reg });
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},
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try self.asmMemoryRegister(
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mir_limb_tag,
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dst_limb_mem,
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registerAlias(src_limb_reg, limb_abi_size),
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);
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},
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}
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}
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},
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.memory => {
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@ -6735,10 +6802,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
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}
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},
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.register => |reg| {
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if (stack_offset > math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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const base_reg = opts.dest_stack_base orelse .rbp;
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switch (ty.zigTypeTag()) {
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@ -6973,13 +7036,11 @@ fn genInlineMemset(
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fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void {
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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if (abi_size > 8) return self.fail("genSetReg called with a value larger than one register", .{});
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switch (mcv) {
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.dead => unreachable,
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.register_overflow => unreachable,
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.ptr_stack_offset => |off| {
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if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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try self.asmRegisterMemory(
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.lea,
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registerAlias(reg, abi_size),
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@ -7158,10 +7219,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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},
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},
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.stack_offset => |off| {
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if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
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return self.fail("stack offset too large", .{});
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}
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switch (ty.zigTypeTag()) {
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.Int => switch (ty.intInfo(self.target.*).signedness) {
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.signed => {
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