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x86_64: implement 128-bit integer comparisons
This commit is contained in:
Jacob Young
parent
2a5335d7b6
commit
644d943861
@ -7962,10 +7962,10 @@ fn genBinOpMir(
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.air_ref,
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=> unreachable,
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.immediate,
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.eflags,
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.register,
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.register_pair,
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.register_offset,
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.eflags,
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.indirect,
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.lea_direct,
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.lea_got,
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@ -8750,33 +8750,122 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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.lt, .gte => {},
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.lte, .gt => unreachable,
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.eq, .neq => {
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const dst_addr_mcv: MCValue = switch (dst_mcv) {
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.memory, .indirect, .load_frame => dst_mcv.address(),
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else => .{ .register = try self.copyToTmpRegister(
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Type.usize,
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dst_mcv.address(),
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) },
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};
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const dst_addr_lock = if (dst_addr_mcv.getReg()) |reg|
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self.register_manager.lockReg(reg)
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else
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null;
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defer if (dst_addr_lock) |lock| self.register_manager.unlockReg(lock);
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const OpInfo = ?struct { addr_reg: Register, addr_lock: RegisterLock };
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const src_addr_mcv: MCValue = switch (src_mcv) {
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.memory, .indirect, .load_frame => src_mcv.address(),
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else => .{ .register = try self.copyToTmpRegister(
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Type.usize,
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src_mcv.address(),
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) },
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const resolved_dst_mcv = switch (dst_mcv) {
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else => dst_mcv,
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.air_ref => |dst_ref| try self.resolveInst(dst_ref),
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};
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const src_addr_lock = if (src_addr_mcv.getReg()) |reg|
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self.register_manager.lockReg(reg)
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else
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null;
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defer if (src_addr_lock) |lock| self.register_manager.unlockReg(lock);
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const dst_info: OpInfo = switch (resolved_dst_mcv) {
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.none,
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.unreach,
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.dead,
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.undef,
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.immediate,
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.eflags,
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.register,
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.register_offset,
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.register_overflow,
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.indirect,
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.lea_direct,
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.lea_got,
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.lea_tlv,
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.lea_frame,
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.reserved_frame,
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.air_ref,
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=> unreachable,
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.register_pair, .load_frame => null,
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.memory, .load_got, .load_direct, .load_tlv => dst: {
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switch (resolved_dst_mcv) {
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.memory => |addr| if (math.cast(
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i32,
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@as(i64, @bitCast(addr)),
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) != null and math.cast(
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i32,
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@as(i64, @bitCast(addr)) + abi_size - 8,
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) != null) break :dst null,
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.load_got, .load_direct, .load_tlv => {},
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else => unreachable,
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}
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const regs = try self.register_manager.allocRegs(2, .{ null, null }, gp);
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const dst_addr_reg =
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(try self.register_manager.allocReg(null, gp)).to64();
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const dst_addr_lock =
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self.register_manager.lockRegAssumeUnused(dst_addr_reg);
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errdefer self.register_manager.unlockReg(dst_addr_lock);
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try self.genSetReg(
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dst_addr_reg,
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Type.usize,
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resolved_dst_mcv.address(),
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);
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break :dst .{
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.addr_reg = dst_addr_reg,
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.addr_lock = dst_addr_lock,
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};
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},
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};
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defer if (dst_info) |info|
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self.register_manager.unlockReg(info.addr_lock);
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const resolved_src_mcv = switch (src_mcv) {
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else => src_mcv,
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.air_ref => |src_ref| try self.resolveInst(src_ref),
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};
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const src_info: OpInfo = switch (resolved_src_mcv) {
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.none,
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.unreach,
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.dead,
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.undef,
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.immediate,
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.eflags,
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.register,
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.register_offset,
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.register_overflow,
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.indirect,
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.lea_direct,
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.lea_got,
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.lea_tlv,
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.lea_frame,
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.reserved_frame,
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.air_ref,
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=> unreachable,
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.register_pair, .load_frame => null,
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.memory, .load_got, .load_direct, .load_tlv => src: {
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switch (resolved_src_mcv) {
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.memory => |addr| if (math.cast(
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i32,
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@as(i64, @bitCast(addr)),
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) != null and math.cast(
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i32,
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@as(i64, @bitCast(addr)) + abi_size - 8,
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) != null) break :src null,
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.load_got, .load_direct, .load_tlv => {},
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else => unreachable,
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}
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const src_addr_reg =
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(try self.register_manager.allocReg(null, gp)).to64();
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const src_addr_lock =
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self.register_manager.lockRegAssumeUnused(src_addr_reg);
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errdefer self.register_manager.unlockReg(src_addr_lock);
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try self.genSetReg(
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src_addr_reg,
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Type.usize,
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resolved_src_mcv.address(),
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);
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break :src .{
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.addr_reg = src_addr_reg,
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.addr_lock = src_addr_lock,
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};
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},
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};
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defer if (src_info) |info|
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self.register_manager.unlockReg(info.addr_lock);
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const regs =
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try self.register_manager.allocRegs(2, .{ null, null }, gp);
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const acc_reg = regs[0].to64();
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const locks = self.register_manager.lockRegsAssumeUnused(2, regs);
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defer for (locks) |lock| self.register_manager.unlockReg(lock);
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@ -8784,18 +8873,52 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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const limbs_len = std.math.divCeil(u16, abi_size, 8) catch unreachable;
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var limb_i: u16 = 0;
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while (limb_i < limbs_len) : (limb_i += 1) {
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const off = limb_i * 8;
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const tmp_reg = regs[@min(limb_i, 1)].to64();
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try self.genSetReg(
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tmp_reg,
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Type.usize,
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dst_addr_mcv.offset(limb_i * 8).deref(),
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);
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try self.genSetReg(tmp_reg, Type.usize, if (dst_info) |info| .{
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.indirect = .{ .reg = info.addr_reg, .off = off },
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} else switch (resolved_dst_mcv) {
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.register_pair => |dst_regs| .{ .register = dst_regs[limb_i] },
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.memory => |dst_addr| .{
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.memory = @bitCast(@as(i64, @bitCast(dst_addr)) + off),
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},
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.indirect => |reg_off| .{ .indirect = .{
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.reg = reg_off.reg,
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.off = reg_off.off + off,
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} },
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.load_frame => |frame_addr| .{ .load_frame = .{
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.index = frame_addr.index,
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.off = frame_addr.off + off,
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} },
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else => unreachable,
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});
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try self.genBinOpMir(
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.{ ._, .xor },
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Type.usize,
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.{ .register = tmp_reg },
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src_addr_mcv.offset(limb_i * 8).deref(),
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if (src_info) |info| .{
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.indirect = .{ .reg = info.addr_reg, .off = off },
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} else switch (resolved_src_mcv) {
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.register_pair => |src_regs| .{
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.register = src_regs[limb_i],
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},
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.memory => |src_addr| .{
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.memory = @bitCast(@as(i64, @bitCast(src_addr)) + off),
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},
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.indirect => |reg_off| .{ .indirect = .{
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.reg = reg_off.reg,
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.off = reg_off.off + off,
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} },
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.load_frame => |frame_addr| .{ .load_frame = .{
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.index = frame_addr.index,
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.off = frame_addr.off + off,
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} },
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else => unreachable,
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},
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);
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if (limb_i > 0) try self.asmRegisterRegister(
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.{ ._, .@"or" },
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acc_reg,
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@ -258,7 +258,6 @@ test "nested packed struct unaligned" {
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (native_endian != .Little) return error.SkipZigTest; // Byte aligned packed struct field pointers have not been implemented yet
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const S1 = packed struct {
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