Merge pull request #25600 from alexrp/std-debug-more-arches

`std.debug`: add CPU contexts and DWARF mappings for more architectures
This commit is contained in:
Alex Rønne Petersen 2025-10-18 11:12:56 +02:00 committed by GitHub
commit 631915ad96
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4 changed files with 677 additions and 296 deletions

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@ -872,10 +872,14 @@ const StackIterator = union(enum) {
};
const fp_usability: FpUsability = switch (builtin.target.cpu.arch) {
.avr,
.csky,
.mips,
.mipsel,
.mips64,
.mips64el,
.msp430,
.xcore,
=> .useless,
.hexagon,
// The PowerPC ABIs don't actually strictly require a backchain pointer; they allow omitting

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@ -1430,14 +1430,20 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
return switch (arch) {
.aarch64, .aarch64_be => 32,
.arc => 160,
.arm, .armeb, .thumb, .thumbeb => 15,
.csky => 64,
.hexagon => 76,
.lanai => 2,
.loongarch32, .loongarch64 => 64,
.m68k => 26,
.mips, .mipsel, .mips64, .mips64el => 66,
.or1k => 35,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
.riscv32, .riscv32be, .riscv64, .riscv64be => 65,
.s390x => 65,
.sparc, .sparc64 => 32,
.ve => 144,
.x86 => 8,
.x86_64 => 16,
else => null,
@ -1447,14 +1453,20 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
return switch (arch) {
.aarch64, .aarch64_be => 29,
.arc => 27,
.arm, .armeb, .thumb, .thumbeb => 11,
.csky => 14,
.hexagon => 30,
.lanai => 5,
.loongarch32, .loongarch64 => 22,
.m68k => 14,
.mips, .mipsel, .mips64, .mips64el => 30,
.or1k => 2,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
.riscv32, .riscv32be, .riscv64, .riscv64be => 8,
.s390x => 11,
.sparc, .sparc64 => 30,
.ve => 9,
.x86 => 5,
.x86_64 => 6,
else => unreachable,
@ -1464,14 +1476,20 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
return switch (arch) {
.aarch64, .aarch64_be => 31,
.arc => 28,
.arm, .armeb, .thumb, .thumbeb => 13,
.csky => 14,
.hexagon => 29,
.lanai => 4,
.loongarch32, .loongarch64 => 3,
.m68k => 15,
.mips, .mipsel, .mips64, .mips64el => 29,
.or1k => 1,
.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
.riscv32, .riscv32be, .riscv64, .riscv64be => 2,
.s390x => 15,
.sparc, .sparc64 => 14,
.ve => 11,
.x86 => 4,
.x86_64 => 7,
else => unreachable,

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@ -94,22 +94,27 @@ pub const can_unwind: bool = s: {
// Notably, we are yet to support unwinding on ARM. There, unwinding is not done through
// `.eh_frame`, but instead with the `.ARM.exidx` section, which has a different format.
const archs: []const std.Target.Cpu.Arch = switch (builtin.target.os.tag) {
// Not supported yet: arm, m68k
// Not supported yet: arm
.haiku => &.{
.aarch64,
.m68k,
.riscv64,
.x86,
.x86_64,
},
// Not supported yet: arc, arm/armeb/thumb/thumbeb, csky, m68k, or1k, xtensa
// Not supported yet: arm/armeb/thumb/thumbeb, xtensa
.linux => &.{
.aarch64,
.aarch64_be,
.arc,
.csky,
.loongarch64,
.m68k,
.mips,
.mipsel,
.mips64,
.mips64el,
.or1k,
.riscv32,
.riscv64,
.s390x,
@ -131,10 +136,11 @@ pub const can_unwind: bool = s: {
.riscv64,
.x86_64,
},
// Not supported yet: arm/armeb, m68k, mips64/mips64el
// Not supported yet: arm/armeb, mips64/mips64el
.netbsd => &.{
.aarch64,
.aarch64_be,
.m68k,
.mips,
.mipsel,
.x86,

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