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Merge pull request #25600 from alexrp/std-debug-more-arches
`std.debug`: add CPU contexts and DWARF mappings for more architectures
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commit
631915ad96
@ -872,10 +872,14 @@ const StackIterator = union(enum) {
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};
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const fp_usability: FpUsability = switch (builtin.target.cpu.arch) {
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.avr,
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.csky,
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.msp430,
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.xcore,
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=> .useless,
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.hexagon,
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// The PowerPC ABIs don't actually strictly require a backchain pointer; they allow omitting
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@ -1430,14 +1430,20 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
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pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
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return switch (arch) {
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.aarch64, .aarch64_be => 32,
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.arc => 160,
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.arm, .armeb, .thumb, .thumbeb => 15,
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.csky => 64,
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.hexagon => 76,
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.lanai => 2,
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.loongarch32, .loongarch64 => 64,
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.m68k => 26,
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.mips, .mipsel, .mips64, .mips64el => 66,
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.or1k => 35,
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
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.riscv32, .riscv32be, .riscv64, .riscv64be => 65,
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.s390x => 65,
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.sparc, .sparc64 => 32,
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.ve => 144,
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.x86 => 8,
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.x86_64 => 16,
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else => null,
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@ -1447,14 +1453,20 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
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pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
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return switch (arch) {
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.aarch64, .aarch64_be => 29,
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.arc => 27,
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.arm, .armeb, .thumb, .thumbeb => 11,
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.csky => 14,
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.hexagon => 30,
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.lanai => 5,
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.loongarch32, .loongarch64 => 22,
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.m68k => 14,
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.mips, .mipsel, .mips64, .mips64el => 30,
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.or1k => 2,
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
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.riscv32, .riscv32be, .riscv64, .riscv64be => 8,
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.s390x => 11,
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.sparc, .sparc64 => 30,
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.ve => 9,
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.x86 => 5,
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.x86_64 => 6,
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else => unreachable,
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@ -1464,14 +1476,20 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
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pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
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return switch (arch) {
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.aarch64, .aarch64_be => 31,
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.arc => 28,
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.arm, .armeb, .thumb, .thumbeb => 13,
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.csky => 14,
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.hexagon => 29,
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.lanai => 4,
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.loongarch32, .loongarch64 => 3,
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.m68k => 15,
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.mips, .mipsel, .mips64, .mips64el => 29,
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.or1k => 1,
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
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.riscv32, .riscv32be, .riscv64, .riscv64be => 2,
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.s390x => 15,
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.sparc, .sparc64 => 14,
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.ve => 11,
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.x86 => 4,
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.x86_64 => 7,
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else => unreachable,
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@ -94,22 +94,27 @@ pub const can_unwind: bool = s: {
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// Notably, we are yet to support unwinding on ARM. There, unwinding is not done through
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// `.eh_frame`, but instead with the `.ARM.exidx` section, which has a different format.
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const archs: []const std.Target.Cpu.Arch = switch (builtin.target.os.tag) {
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// Not supported yet: arm, m68k
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// Not supported yet: arm
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.haiku => &.{
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.aarch64,
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.m68k,
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.riscv64,
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.x86,
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.x86_64,
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},
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// Not supported yet: arc, arm/armeb/thumb/thumbeb, csky, m68k, or1k, xtensa
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// Not supported yet: arm/armeb/thumb/thumbeb, xtensa
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.linux => &.{
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.aarch64,
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.aarch64_be,
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.arc,
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.csky,
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.loongarch64,
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.m68k,
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.mips,
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.mipsel,
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.mips64,
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.mips64el,
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.or1k,
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.riscv32,
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.riscv64,
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.s390x,
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@ -131,10 +136,11 @@ pub const can_unwind: bool = s: {
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.riscv64,
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.x86_64,
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},
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// Not supported yet: arm/armeb, m68k, mips64/mips64el
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// Not supported yet: arm/armeb, mips64/mips64el
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.netbsd => &.{
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.aarch64,
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.aarch64_be,
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.m68k,
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.mips,
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.mipsel,
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.x86,
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