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windows: add zig impl of IsProcessorFeaturePresent syscall
This commit is contained in:
Jakub Konka
parent
1eac3c57ec
commit
625415d738
@ -2103,6 +2103,7 @@ pub const USHORT = u16;
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pub const SHORT = i16;
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pub const ULONG = u32;
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pub const LONG = i32;
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pub const ULONG64 = u64;
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pub const ULONGLONG = u64;
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pub const LONGLONG = i64;
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pub const HLOCAL = HANDLE;
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@ -3715,106 +3716,281 @@ pub const CTRL_SHUTDOWN_EVENT: DWORD = 6;
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pub const HANDLER_ROUTINE = std.meta.FnPtr(fn (dwCtrlType: DWORD) callconv(WINAPI) BOOL);
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/// The 64-bit load/store atomic instructions are available.
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pub const PF_ARM_64BIT_LOADSTORE_ATOMIC = 25;
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/// Processor feature enumeration.
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pub const PF = enum(DWORD) {
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/// On a Pentium, a floating-point precision error can occur in rare circumstances.
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FLOATING_POINT_PRECISION_ERRATA = 0,
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/// The divide instruction_available.
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pub const PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE = 24;
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/// Floating-point operations are emulated using software emulator.
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/// This function returns a nonzero value if floating-point operations are emulated; otherwise, it returns zero.
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FLOATING_POINT_EMULATED = 1,
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/// The external cache is available.
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pub const PF_ARM_EXTERNAL_CACHE_AVAILABLE = 26;
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/// The atomic compare and exchange operation (cmpxchg) is available.
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COMPARE_EXCHANGE_DOUBLE = 2,
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/// The floating-point multiply-accumulate instruction is available.
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pub const PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE = 27;
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/// The MMX instruction set is available.
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MMX_INSTRUCTIONS_AVAILABLE = 3,
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/// The VFP/Neon: 32 x 64bit register bank is present.
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/// This flag has the same meaning as PF_ARM_VFP_EXTENDED_REGISTERS.
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pub const PF_ARM_VFP_32_REGISTERS_AVAILABLE = 18;
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/// The SSE instruction set is available.
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XMMI_INSTRUCTIONS_AVAILABLE = 6,
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/// The 3D-Now instruction is available.
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pub const PF_3DNOW_INSTRUCTIONS_AVAILABLE = 7;
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/// The 3D-Now instruction is available.
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@"3DNOW_INSTRUCTIONS_AVAILABLE" = 7,
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/// The processor channels are enabled.
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pub const PF_CHANNELS_ENABLED = 16;
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/// The RDTSC instruction is available.
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RDTSC_INSTRUCTION_AVAILABLE = 8,
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/// The atomic compare and exchange operation (cmpxchg) is available.
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pub const PF_COMPARE_EXCHANGE_DOUBLE = 2;
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/// The processor is PAE-enabled.
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PAE_ENABLED = 9,
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/// The atomic compare and exchange 128-bit operation (cmpxchg16b) is available.
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pub const PF_COMPARE_EXCHANGE128 = 14;
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/// The SSE2 instruction set is available.
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XMMI64_INSTRUCTIONS_AVAILABLE = 10,
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/// The atomic compare 64 and exchange 128-bit operation (cmp8xchg16) is available.
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pub const PF_COMPARE64_EXCHANGE128 = 15;
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/// Data execution prevention is enabled.
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NX_ENABLED = 12,
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/// _fastfail() is available.
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pub const PF_FASTFAIL_AVAILABLE = 23;
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/// The SSE3 instruction set is available.
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SSE3_INSTRUCTIONS_AVAILABLE = 13,
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/// Floating-point operations are emulated using software emulator.
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/// This function returns a nonzero value if floating-point operations are emulated; otherwise, it returns zero.
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pub const PF_FLOATING_POINT_EMULATED = 1;
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/// The atomic compare and exchange 128-bit operation (cmpxchg16b) is available.
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COMPARE_EXCHANGE128 = 14,
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/// On a Pentium, a floating-point precision error can occur in rare circumstances.
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pub const PF_FLOATING_POINT_PRECISION_ERRATA = 0;
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/// The atomic compare 64 and exchange 128-bit operation (cmp8xchg16) is available.
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COMPARE64_EXCHANGE128 = 15,
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/// The MMX instruction set is available.
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pub const PF_MMX_INSTRUCTIONS_AVAILABLE = 3;
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/// The processor channels are enabled.
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CHANNELS_ENABLED = 16,
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/// Data execution prevention is enabled.
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pub const PF_NX_ENABLED = 12;
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/// The processor implements the XSAVI and XRSTOR instructions.
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XSAVE_ENABLED = 17,
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/// The processor is PAE-enabled.
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pub const PF_PAE_ENABLED = 9;
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/// The VFP/Neon: 32 x 64bit register bank is present.
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/// This flag has the same meaning as PF_ARM_VFP_EXTENDED_REGISTERS.
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ARM_VFP_32_REGISTERS_AVAILABLE = 18,
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/// The RDTSC instruction is available.
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pub const PF_RDTSC_INSTRUCTION_AVAILABLE = 8;
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/// Second Level Address Translation is supported by the hardware.
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SECOND_LEVEL_ADDRESS_TRANSLATION = 20,
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/// RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions are available.
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pub const PF_RDWRFSGBASE_AVAILABLE = 22;
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/// Virtualization is enabled in the firmware and made available by the operating system.
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VIRT_FIRMWARE_ENABLED = 21,
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/// Second Level Address Translation is supported by the hardware.
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pub const PF_SECOND_LEVEL_ADDRESS_TRANSLATION = 20;
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/// RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions are available.
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RDWRFSGBASE_AVAILABLE = 22,
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/// The SSE3 instruction set is available.
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pub const PF_SSE3_INSTRUCTIONS_AVAILABLE = 13;
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/// _fastfail() is available.
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FASTFAIL_AVAILABLE = 23,
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/// The SSSE3 instruction set is available.
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pub const PF_SSSE3_INSTRUCTIONS_AVAILABLE = 36;
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/// The divide instruction_available.
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ARM_DIVIDE_INSTRUCTION_AVAILABLE = 24,
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/// The SSE4_1 instruction set is available.
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pub const PF_SSE4_1_INSTRUCTIONS_AVAILABLE = 37;
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/// The 64-bit load/store atomic instructions are available.
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ARM_64BIT_LOADSTORE_ATOMIC = 25,
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/// The SSE4_2 instruction set is available.
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pub const PF_SSE4_2_INSTRUCTIONS_AVAILABLE = 38;
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/// The external cache is available.
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ARM_EXTERNAL_CACHE_AVAILABLE = 26,
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/// The AVX instruction set is available.
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pub const PF_AVX_INSTRUCTIONS_AVAILABLE = 39;
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/// The floating-point multiply-accumulate instruction is available.
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ARM_FMAC_INSTRUCTIONS_AVAILABLE = 27,
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/// The AVX2 instruction set is available.
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pub const PF_AVX2_INSTRUCTIONS_AVAILABLE = 40;
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/// This ARM processor implements the ARM v8 instructions set.
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ARM_V8_INSTRUCTIONS_AVAILABLE = 29,
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/// The AVX512F instruction set is available.
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pub const PF_AVX512F_INSTRUCTIONS_AVAILABLE = 41;
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/// This ARM processor implements the ARM v8 extra cryptographic instructions (i.e., AES, SHA1 and SHA2).
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ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE = 30,
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/// Virtualization is enabled in the firmware and made available by the operating system.
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pub const PF_VIRT_FIRMWARE_ENABLED = 21;
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/// This ARM processor implements the ARM v8 extra CRC32 instructions.
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ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE = 31,
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/// The SSE instruction set is available.
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pub const PF_XMMI_INSTRUCTIONS_AVAILABLE = 6;
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/// This ARM processor implements the ARM v8.1 atomic instructions (e.g., CAS, SWP).
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ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE = 34,
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/// The SSE2 instruction set is available.
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pub const PF_XMMI64_INSTRUCTIONS_AVAILABLE = 10;
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/// The SSSE3 instruction set is available.
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SSSE3_INSTRUCTIONS_AVAILABLE = 36,
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/// The processor implements the XSAVI and XRSTOR instructions.
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pub const PF_XSAVE_ENABLED = 17;
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/// The SSE4_1 instruction set is available.
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SSE4_1_INSTRUCTIONS_AVAILABLE = 37,
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/// This ARM processor implements the ARM v8 instructions set.
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pub const PF_ARM_V8_INSTRUCTIONS_AVAILABLE = 29;
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/// The SSE4_2 instruction set is available.
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SSE4_2_INSTRUCTIONS_AVAILABLE = 38,
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/// This ARM processor implements the ARM v8 extra cryptographic instructions (i.e., AES, SHA1 and SHA2).
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pub const PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE = 30;
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/// The AVX instruction set is available.
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AVX_INSTRUCTIONS_AVAILABLE = 39,
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/// This ARM processor implements the ARM v8 extra CRC32 instructions.
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pub const PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE = 31;
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/// The AVX2 instruction set is available.
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AVX2_INSTRUCTIONS_AVAILABLE = 40,
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/// This ARM processor implements the ARM v8.1 atomic instructions (e.g., CAS, SWP).
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pub const PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE = 34;
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/// The AVX512F instruction set is available.
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AVX512F_INSTRUCTIONS_AVAILABLE = 41,
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};
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pub const MAX_WOW64_SHARED_ENTRIES = 16;
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pub const PROCESSOR_FEATURE_MAX = 64;
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pub const MAXIMUM_XSTATE_FEATURES = 64;
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pub const KSYSTEM_TIME = extern struct {
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LowPart: ULONG,
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High1Time: LONG,
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High2Time: LONG,
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};
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pub const NT_PRODUCT_TYPE = enum(INT) {
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NtProductWinNt = 1,
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NtProductLanManNt,
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NtProductServer,
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};
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pub const ALTERNATIVE_ARCHITECTURE_TYPE = enum(INT) {
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StandardDesign,
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NEC98x86,
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EndAlternatives,
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};
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pub const XSTATE_FEATURE = extern struct {
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Offset: ULONG,
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Size: ULONG,
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};
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pub const XSTATE_CONFIGURATION = extern struct {
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EnabledFeatures: ULONG64,
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Size: ULONG,
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OptimizedSave: ULONG,
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Features: [MAXIMUM_XSTATE_FEATURES]XSTATE_FEATURE,
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};
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/// Shared Kernel User Data
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pub const KUSER_SHARED_DATA = extern struct {
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TickCountLowDeprecated: ULONG,
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TickCountMultiplier: ULONG,
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InterruptTime: KSYSTEM_TIME,
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SystemTime: KSYSTEM_TIME,
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TimeZoneBias: KSYSTEM_TIME,
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ImageNumberLow: USHORT,
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ImageNumberHigh: USHORT,
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NtSystemRoot: [260]WCHAR,
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MaxStackTraceDepth: ULONG,
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CryptoExponent: ULONG,
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TimeZoneId: ULONG,
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LargePageMinimum: ULONG,
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AitSamplingValue: ULONG,
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AppCompatFlag: ULONG,
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RNGSeedVersion: ULONGLONG,
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GlobalValidationRunlevel: ULONG,
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TimeZoneBiasStamp: LONG,
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NtBuildNumber: ULONG,
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NtProductType: NT_PRODUCT_TYPE,
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ProductTypeIsValid: BOOLEAN,
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Reserved0: [1]BOOLEAN,
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NativeProcessorArchitecture: USHORT,
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NtMajorVersion: ULONG,
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NtMinorVersion: ULONG,
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ProcessorFeatures: [PROCESSOR_FEATURE_MAX]BOOLEAN,
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Reserved1: ULONG,
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Reserved3: ULONG,
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TimeSlip: ULONG,
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AlternativeArchitecture: ALTERNATIVE_ARCHITECTURE_TYPE,
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BootId: ULONG,
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SystemExpirationDate: LARGE_INTEGER,
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SuiteMaskY: ULONG,
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KdDebuggerEnabled: BOOLEAN,
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DummyUnion1: extern union {
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MitigationPolicies: UCHAR,
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Alt: packed struct {
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NXSupportPolicy: u2,
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SEHValidationPolicy: u2,
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CurDirDevicesSkippedForDlls: u2,
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Reserved: u2,
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},
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},
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CyclesPerYield: USHORT,
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ActiveConsoleId: ULONG,
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DismountCount: ULONG,
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ComPlusPackage: ULONG,
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LastSystemRITEventTickCount: ULONG,
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NumberOfPhysicalPages: ULONG,
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SafeBootMode: BOOLEAN,
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DummyUnion2: extern union {
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VirtualizationFlags: UCHAR,
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Alt: packed struct {
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ArchStartedInEl2: u1,
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QcSlIsSupported: u1,
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SpareBits: u6,
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},
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},
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Reserved12: [2]UCHAR,
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DummyUnion3: extern union {
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SharedDataFlags: ULONG,
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Alt: packed struct {
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DbgErrorPortPresent: u1,
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DbgElevationEnabled: u1,
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DbgVirtEnabled: u1,
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DbgInstallerDetectEnabled: u1,
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DbgLkgEnabled: u1,
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DbgDynProcessorEnabled: u1,
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DbgConsoleBrokerEnabled: u1,
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DbgSecureBootEnabled: u1,
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DbgMultiSessionSku: u1,
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DbgMultiUsersInSessionSku: u1,
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DbgStateSeparationEnabled: u1,
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SpareBits: u21,
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},
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},
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DataFlagsPad: [1]ULONG,
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TestRetInstruction: ULONGLONG,
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QpcFrequency: LONGLONG,
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SystemCall: ULONG,
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Reserved2: ULONG,
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SystemCallPad: [2]ULONGLONG,
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DummyUnion4: extern union {
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TickCount: KSYSTEM_TIME,
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TickCountQuad: ULONG64,
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Alt: extern struct {
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ReservedTickCountOverlay: [3]ULONG,
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TickCountPad: [1]ULONG,
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},
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},
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Cookie: ULONG,
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CookiePad: [1]ULONG,
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ConsoleSessionForegroundProcessId: LONGLONG,
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TimeUpdateLock: ULONGLONG,
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BaselineSystemTimeQpc: ULONGLONG,
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BaselineInterruptTimeQpc: ULONGLONG,
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QpcSystemTimeIncrement: ULONGLONG,
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QpcInterruptTimeIncrement: ULONGLONG,
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QpcSystemTimeIncrementShift: UCHAR,
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QpcInterruptTimeIncrementShift: UCHAR,
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UnparkedProcessorCount: USHORT,
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EnclaveFeatureMask: [4]ULONG,
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TelemetryCoverageRound: ULONG,
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UserModeGlobalLogger: [16]USHORT,
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ImageFileExecutionOptions: ULONG,
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LangGenerationCount: ULONG,
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Reserved4: ULONGLONG,
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InterruptTimeBias: ULONGLONG,
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QpcBias: ULONGLONG,
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ActiveProcessorCount: ULONG,
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ActiveGroupCount: UCHAR,
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Reserved9: UCHAR,
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DummyUnion5: extern union {
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QpcData: USHORT,
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Alt: extern struct {
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QpcBypassEnabled: UCHAR,
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QpcShift: UCHAR,
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},
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},
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TimeZoneBiasEffectiveStart: LARGE_INTEGER,
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TimeZoneBiasEffectiveEnd: LARGE_INTEGER,
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XState: XSTATE_CONFIGURATION,
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FeatureConfigurationChangeStamp: KSYSTEM_TIME,
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Spare: ULONG,
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UserPointerAuthMask: ULONG64,
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};
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/// Read-only user-mode address for the shared data.
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/// https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/api/ntexapi_x/kuser_shared_data/index.htm
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/// https://msrc-blog.microsoft.com/2022/04/05/randomizing-the-kuser_shared_data-structure-on-windows/
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pub const SharedUserData: *const KUSER_SHARED_DATA = @intToPtr(*const KUSER_SHARED_DATA, 0x7FFE0000);
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pub fn IsProcessorFeaturePresent(feature: PF) bool {
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if (@enumToInt(feature) >= PROCESSOR_FEATURE_MAX) return false;
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return SharedUserData.ProcessorFeatures[@enumToInt(feature)] == 1;
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}
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