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Merge pull request #20985 from alexrp/gpu-nonsense

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Follow-up on `std.Target` GPU changes in #20960
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Andrew Kelley 2024-08-11 20:23:28 -07:00 committed by GitHub
commit 61dac74128
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2 changed files with 24 additions and 14 deletions
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27
lib/std/Target.zig
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@ -1898,12 +1898,12 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.sparc,
.spirv32,
.loongarch32,
.dxil,
.xtensa,
=> 32,
.aarch64,
.aarch64_be,
.dxil,
.mips64,
.mips64el,
.powerpc64,
@ -2302,15 +2302,18 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.short, .ushort => return 16,
.int, .uint, .float => return 32,
.long, .ulong, .longlong, .ulonglong, .double => return 64,
.longdouble => return 64,
.longdouble => return 128,
},
.opencl, .vulkan => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .float => return 32,
.long, .ulong, .longlong, .ulonglong, .double => return 64,
.longdouble => return 64,
.long, .ulong, .double => return 64,
.longlong, .ulonglong => return 128,
// Note: The OpenCL specification does not guarantee a particular size for long double,
// but clang uses 128 bits.
.longdouble => return 128,
},
.ps4, .ps5 => switch (c_type) {
@ -2385,6 +2388,7 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.csky,
.x86,
.xcore,
.dxil,
.loongarch32,
.kalimba,
.spu_2,
@ -2394,7 +2398,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.amdgcn,
.bpfel,
.bpfeb,
.dxil,
.hexagon,
.m68k,
.mips,
@ -2404,9 +2407,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.nvptx,
.nvptx64,
.s390x,
.spirv,
.spirv32,
.spirv64,
=> 8,
.aarch64,
@ -2421,6 +2421,9 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.riscv32,
.riscv64,
.sparc64,
.spirv,
.spirv32,
.spirv64,
.x86_64,
.ve,
.wasm32,
@ -2489,6 +2492,7 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.csky,
.xcore,
.dxil,
.loongarch32,
.kalimba,
.spu_2,
@ -2504,7 +2508,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.amdgcn,
.bpfel,
.bpfeb,
.dxil,
.hexagon,
.x86,
.m68k,
@ -2515,9 +2518,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.nvptx,
.nvptx64,
.s390x,
.spirv,
.spirv32,
.spirv64,
=> 8,
.aarch64,
@ -2532,6 +2532,9 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.riscv32,
.riscv64,
.sparc64,
.spirv,
.spirv32,
.spirv64,
.x86_64,
.ve,
.wasm32,

11
src/codegen/llvm.zig
View File

@ -91,7 +91,14 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
=> unreachable, // Gated by hasLlvmSupport().
};
try llvm_triple.appendSlice(llvm_arch);
try llvm_triple.appendSlice("-unknown-");
// Unlike CPU backends, GPU backends actually care about the vendor tag.
try llvm_triple.appendSlice(switch (target.cpu.arch) {
.amdgcn => if (target.os.tag == .mesa3d) "-mesa-" else "-amd-",
.nvptx, .nvptx64 => "-nvidia-",
.spirv64 => if (target.os.tag == .amdhsa) "-amd-" else "-unknown-",
else => "-unknown-",
});
const llvm_os = switch (target.os.tag) {
.freestanding => "unknown",
@ -111,6 +118,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.cuda => "cuda",
.nvcl => "nvcl",
.amdhsa => "amdhsa",
.opencl => "unknown", // https://llvm.org/docs/SPIRVUsage.html#target-triples
.ps4 => "ps4",
.ps5 => "ps5",
.elfiamcu => "elfiamcu",
@ -132,7 +140,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.serenity => "serenity",
.vulkan => "vulkan",
.opencl,
.glsl450,
.plan9,
.minix,