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riscv64: Add missing fence for seq_cst atomic_store.

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Alex Rønne Petersen 2024-11-01 04:04:31 +01:00
parent e40de86082
commit 61ae9a2f45
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1 changed files with 12 additions and 1 deletions
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13
src/arch/riscv64/CodeGen.zig
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@ -7729,7 +7729,7 @@ fn airAtomicLoad(func: *Func, inst: Air.Inst.Index) !void {
const ptr_mcv = try func.resolveInst(atomic_load.ptr);
const bit_size = elem_ty.bitSize(zcu);
if (bit_size > 64) return func.fail("TODO: airAtomicStore > 64 bits", .{});
if (bit_size > 64) return func.fail("TODO: airAtomicLoad > 64 bits", .{});
const result_mcv = try func.allocRegOrMem(elem_ty, inst, true);
assert(result_mcv == .register); // should be less than 8 bytes
@ -7793,6 +7793,17 @@ fn airAtomicStore(func: *Func, inst: Air.Inst.Index, order: std.builtin.AtomicOr
}
try func.store(ptr_mcv, val_mcv, ptr_ty);
if (order == .seq_cst) {
_ = try func.addInst(.{
.tag = .fence,
.data = .{ .fence = .{
.pred = .rw,
.succ = .rw,
} },
});
}
return func.finishAir(inst, .unreach, .{ bin_op.lhs, bin_op.rhs, .none });
}