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x86_64: fix packed store crash

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This commit is contained in:
Jacob Young 2023-06-24 22:51:29 -04:00
parent d98147414d
commit 614c807702
3 changed files with 5 additions and 6 deletions
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9
src/arch/x86_64/CodeGen.zig
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@ -5404,6 +5404,7 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In
const limb_abi_size: u16 = @min(ptr_info.packed_offset.host_size, 8); const limb_abi_size: u16 = @min(ptr_info.packed_offset.host_size, 8);
const limb_abi_bits = limb_abi_size * 8; const limb_abi_bits = limb_abi_size * 8;
const limb_ty = try mod.intType(.unsigned, limb_abi_bits);
const src_bit_size = src_ty.bitSize(mod); const src_bit_size = src_ty.bitSize(mod);
const src_byte_off = @as(i32, @intCast(ptr_info.packed_offset.bit_offset / limb_abi_bits * limb_abi_size)); const src_byte_off = @as(i32, @intCast(ptr_info.packed_offset.bit_offset / limb_abi_bits * limb_abi_size));
@ -5443,23 +5444,23 @@ fn packedStore(self: *Self, ptr_ty: Type, ptr_mcv: MCValue, src_mcv: MCValue) In
const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
defer self.register_manager.unlockReg(tmp_lock); defer self.register_manager.unlockReg(tmp_lock);
try self.genSetReg(tmp_reg, src_ty, src_mcv); try self.genSetReg(tmp_reg, limb_ty, src_mcv);
switch (limb_i) { switch (limb_i) {
0 => try self.genShiftBinOpMir( 0 => try self.genShiftBinOpMir(
.{ ._l, .sh }, .{ ._l, .sh },
src_ty, limb_ty,
tmp_mcv, tmp_mcv,
.{ .immediate = src_bit_off }, .{ .immediate = src_bit_off },
), ),
1 => try self.genShiftBinOpMir( 1 => try self.genShiftBinOpMir(
.{ ._r, .sh }, .{ ._r, .sh },
src_ty, limb_ty,
tmp_mcv, tmp_mcv,
.{ .immediate = limb_abi_bits - src_bit_off }, .{ .immediate = limb_abi_bits - src_bit_off },
), ),
else => unreachable, else => unreachable,
} }
try self.genBinOpMir(.{ ._, .@"and" }, src_ty, tmp_mcv, .{ .immediate = part_mask }); try self.genBinOpMir(.{ ._, .@"and" }, limb_ty, tmp_mcv, .{ .immediate = part_mask });
try self.asmMemoryRegister( try self.asmMemoryRegister(
.{ ._, .@"or" }, .{ ._, .@"or" },
limb_mem, limb_mem,

1
test/behavior/bugs/13664.zig
View File

@ -13,7 +13,6 @@ fn value() i64 {
return 1341; return 1341;
} }
test { test {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO

1
test/behavior/struct.zig
View File

@ -530,7 +530,6 @@ test "packed struct fields are ordered from LSB to MSB" {
test "implicit cast packed struct field to const ptr" { test "implicit cast packed struct field to const ptr" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;