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stage2: sparc64: Implement airBinop for bool_and/or

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Koakuma 2022-07-08 20:42:40 +07:00 committed by Andrew Kelley
parent 4fc6df9f62
commit 61265fba04
1 changed files with 22 additions and 2 deletions
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24
src/arch/sparc64/CodeGen.zig
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@ -548,8 +548,8 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
.cmp_vector => @panic("TODO try self.airCmpVector(inst)"),
.cmp_lt_errors_len => try self.airCmpLtErrorsLen(inst),
.bool_and => @panic("TODO try self.airBoolOp(inst)"),
.bool_or => @panic("TODO try self.airBoolOp(inst)"),
.bool_and => try self.airBinOp(inst, .bool_and),
.bool_or => try self.airBinOp(inst, .bool_or),
.bit_and => try self.airBinOp(inst, .bit_and),
.bit_or => try self.airBinOp(inst, .bit_or),
.xor => try self.airBinOp(inst, .xor),
@ -2525,6 +2525,26 @@ fn binOp(
}
},
.bool_and,
.bool_or,
=> {
switch (lhs_ty.zigTypeTag()) {
.Bool => {
assert(lhs != .immediate); // should have been handled by Sema
assert(rhs != .immediate); // should have been handled by Sema
const mir_tag: Mir.Inst.Tag = switch (tag) {
.bool_and => .@"and",
.bool_or => .@"or",
else => unreachable,
};
return try self.binOpRegister(mir_tag, lhs, rhs, lhs_ty, rhs_ty, metadata);
},
else => unreachable,
}
},
.shl => {
const base_tag: Air.Inst.Tag = switch (tag) {
.shl => .shl_exact,