From 5f97652da8881773b823a0730e5791816668528a Mon Sep 17 00:00:00 2001 From: Jakub Konka Date: Sun, 15 May 2022 09:44:05 +0200 Subject: [PATCH] x64: remove verbose_mir functionality Originally I thought interleaving AIR with MIR will be useful, however as it stands, I have used it very sporadically, and recently, not at all, and I do not think anyone else is actually using it. If there is a simple error such as a wrong instruction emitted, `objdump` is perfectly capable of narrowing it down, while if there's something more subtle happening, regardless of having `--verbose-mir` functionality or not, you still gotta go via the debugger which offers a better view at interleaved source program with the emitted machine code. Finally, I believe `-femit-asm` when we add it will offer a more generic substitute. --- src/Compilation.zig | 3 - src/arch/x86_64/CodeGen.zig | 12 - src/arch/x86_64/PrintMir.zig | 478 ----------------------------------- src/main.zig | 4 - 4 files changed, 497 deletions(-) delete mode 100644 src/arch/x86_64/PrintMir.zig diff --git a/src/Compilation.zig b/src/Compilation.zig index 2091502da2..407c753193 100644 --- a/src/Compilation.zig +++ b/src/Compilation.zig @@ -82,7 +82,6 @@ clang_preprocessor_mode: ClangPreprocessorMode, /// Whether to print clang argvs to stdout. verbose_cc: bool, verbose_air: bool, -verbose_mir: bool, verbose_llvm_ir: bool, verbose_cimport: bool, verbose_llvm_cpu_features: bool, @@ -775,7 +774,6 @@ pub const InitOptions = struct { verbose_cc: bool = false, verbose_link: bool = false, verbose_air: bool = false, - verbose_mir: bool = false, verbose_llvm_ir: bool = false, verbose_cimport: bool = false, verbose_llvm_cpu_features: bool = false, @@ -1683,7 +1681,6 @@ pub fn create(gpa: Allocator, options: InitOptions) !*Compilation { .clang_preprocessor_mode = options.clang_preprocessor_mode, .verbose_cc = options.verbose_cc, .verbose_air = options.verbose_air, - .verbose_mir = options.verbose_mir, .verbose_llvm_ir = options.verbose_llvm_ir, .verbose_cimport = options.verbose_cimport, .verbose_llvm_cpu_features = options.verbose_llvm_cpu_features, diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig index be053f310c..80a9bbbd78 100644 --- a/src/arch/x86_64/CodeGen.zig +++ b/src/arch/x86_64/CodeGen.zig @@ -348,18 +348,6 @@ pub fn generate( else => |e| return e, }; - if (builtin.mode == .Debug and bin_file.options.module.?.comp.verbose_mir) { - const w = std.io.getStdErr().writer(); - w.print("# Begin Function MIR: {s}:\n", .{fn_owner_decl.name}) catch {}; - const PrintMir = @import("PrintMir.zig"); - const print = PrintMir{ - .mir = mir, - .bin_file = bin_file, - }; - print.printMir(w, function.mir_to_air_map, air) catch {}; // we don't care if the debug printing fails - w.print("# End Function MIR: {s}\n\n", .{fn_owner_decl.name}) catch {}; - } - if (function.err_msg) |em| { return FnResult{ .fail = em }; } else { diff --git a/src/arch/x86_64/PrintMir.zig b/src/arch/x86_64/PrintMir.zig deleted file mode 100644 index e457d859ea..0000000000 --- a/src/arch/x86_64/PrintMir.zig +++ /dev/null @@ -1,478 +0,0 @@ -//! This file contains the functionality for print x86_64 MIR in a debug way, interleaved with AIR - -const Print = @This(); - -const std = @import("std"); -const assert = std.debug.assert; -const bits = @import("bits.zig"); -const abi = @import("abi.zig"); -const leb128 = std.leb; -const link = @import("../../link.zig"); -const log = std.log.scoped(.codegen); -const math = std.math; -const mem = std.mem; - -const Air = @import("../../Air.zig"); -const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput; -const DW = std.dwarf; -const Encoder = bits.Encoder; -const ErrorMsg = Module.ErrorMsg; -const MCValue = @import("CodeGen.zig").MCValue; -const Mir = @import("Mir.zig"); -const Module = @import("../../Module.zig"); -const Instruction = bits.Instruction; -const Register = bits.Register; -const Type = @import("../../type.zig").Type; -const fmtIntSizeBin = std.fmt.fmtIntSizeBin; - -mir: Mir, -bin_file: *link.File, - -pub fn printMir(print: *const Print, w: anytype, mir_to_air_map: std.AutoHashMap(Mir.Inst.Index, Air.Inst.Index), air: Air) !void { - const instruction_bytes = print.mir.instructions.len * - // Here we don't use @sizeOf(Mir.Inst.Data) because it would include - // the debug safety tag but we want to measure release size. - (@sizeOf(Mir.Inst.Tag) + 2 + 8); - const extra_bytes = print.mir.extra.len * @sizeOf(u32); - const total_bytes = @sizeOf(Mir) + instruction_bytes + extra_bytes; - - // zig fmt: off - std.debug.print( - \\# Total MIR bytes: {} - \\# MIR Instructions: {d} ({}) - \\# MIR Extra Data: {d} ({}) - \\ - , .{ - fmtIntSizeBin(total_bytes), - print.mir.instructions.len, fmtIntSizeBin(instruction_bytes), - print.mir.extra.len, fmtIntSizeBin(extra_bytes), - }); - // zig fmt: on - const mir_tags = print.mir.instructions.items(.tag); - - for (mir_tags) |tag, index| { - const inst = @intCast(u32, index); - if (mir_to_air_map.get(inst)) |air_index| { - try w.print("air index %{} ({}) for following mir inst(s)\n", .{ air_index, air.instructions.items(.tag)[air_index] }); - } - try w.writeAll(" "); - switch (tag) { - .adc => try print.mirArith(.adc, inst, w), - .add => try print.mirArith(.add, inst, w), - .sub => try print.mirArith(.sub, inst, w), - .xor => try print.mirArith(.xor, inst, w), - .@"and" => try print.mirArith(.@"and", inst, w), - .@"or" => try print.mirArith(.@"or", inst, w), - .sbb => try print.mirArith(.sbb, inst, w), - .cmp => try print.mirArith(.cmp, inst, w), - .mov => try print.mirArith(.mov, inst, w), - - .adc_mem_imm => try print.mirArithMemImm(.adc, inst, w), - .add_mem_imm => try print.mirArithMemImm(.add, inst, w), - .sub_mem_imm => try print.mirArithMemImm(.sub, inst, w), - .xor_mem_imm => try print.mirArithMemImm(.xor, inst, w), - .and_mem_imm => try print.mirArithMemImm(.@"and", inst, w), - .or_mem_imm => try print.mirArithMemImm(.@"or", inst, w), - .sbb_mem_imm => try print.mirArithMemImm(.sbb, inst, w), - .cmp_mem_imm => try print.mirArithMemImm(.cmp, inst, w), - .mov_mem_imm => try print.mirArithMemImm(.mov, inst, w), - - .adc_scale_src => try print.mirArithScaleSrc(.adc, inst, w), - .add_scale_src => try print.mirArithScaleSrc(.add, inst, w), - .sub_scale_src => try print.mirArithScaleSrc(.sub, inst, w), - .xor_scale_src => try print.mirArithScaleSrc(.xor, inst, w), - .and_scale_src => try print.mirArithScaleSrc(.@"and", inst, w), - .or_scale_src => try print.mirArithScaleSrc(.@"or", inst, w), - .sbb_scale_src => try print.mirArithScaleSrc(.sbb, inst, w), - .cmp_scale_src => try print.mirArithScaleSrc(.cmp, inst, w), - .mov_scale_src => try print.mirArithScaleSrc(.mov, inst, w), - - .adc_scale_dst => try print.mirArithScaleDst(.adc, inst, w), - .add_scale_dst => try print.mirArithScaleDst(.add, inst, w), - .sub_scale_dst => try print.mirArithScaleDst(.sub, inst, w), - .xor_scale_dst => try print.mirArithScaleDst(.xor, inst, w), - .and_scale_dst => try print.mirArithScaleDst(.@"and", inst, w), - .or_scale_dst => try print.mirArithScaleDst(.@"or", inst, w), - .sbb_scale_dst => try print.mirArithScaleDst(.sbb, inst, w), - .cmp_scale_dst => try print.mirArithScaleDst(.cmp, inst, w), - .mov_scale_dst => try print.mirArithScaleDst(.mov, inst, w), - - .adc_scale_imm => try print.mirArithScaleImm(.adc, inst, w), - .add_scale_imm => try print.mirArithScaleImm(.add, inst, w), - .sub_scale_imm => try print.mirArithScaleImm(.sub, inst, w), - .xor_scale_imm => try print.mirArithScaleImm(.xor, inst, w), - .and_scale_imm => try print.mirArithScaleImm(.@"and", inst, w), - .or_scale_imm => try print.mirArithScaleImm(.@"or", inst, w), - .sbb_scale_imm => try print.mirArithScaleImm(.sbb, inst, w), - .cmp_scale_imm => try print.mirArithScaleImm(.cmp, inst, w), - .mov_scale_imm => try print.mirArithScaleImm(.mov, inst, w), - - .adc_mem_index_imm => try print.mirArithMemIndexImm(.adc, inst, w), - .add_mem_index_imm => try print.mirArithMemIndexImm(.add, inst, w), - .sub_mem_index_imm => try print.mirArithMemIndexImm(.sub, inst, w), - .xor_mem_index_imm => try print.mirArithMemIndexImm(.xor, inst, w), - .and_mem_index_imm => try print.mirArithMemIndexImm(.@"and", inst, w), - .or_mem_index_imm => try print.mirArithMemIndexImm(.@"or", inst, w), - .sbb_mem_index_imm => try print.mirArithMemIndexImm(.sbb, inst, w), - .cmp_mem_index_imm => try print.mirArithMemIndexImm(.cmp, inst, w), - .mov_mem_index_imm => try print.mirArithMemIndexImm(.mov, inst, w), - - .movabs => try print.mirMovabs(inst, w), - - .lea => try print.mirLea(inst, w), - .lea_pie => try print.mirLeaPie(inst, w), - - .imul_complex => try print.mirIMulComplex(inst, w), - - .push => try print.mirPushPop(.push, inst, w), - .pop => try print.mirPushPop(.pop, inst, w), - - .jmp => try print.mirJmpCall(.jmp, inst, w), - .call => try print.mirJmpCall(.call, inst, w), - - .cond_jmp_greater_less => try print.mirCondJmp(.cond_jmp_greater_less, inst, w), - .cond_jmp_above_below => try print.mirCondJmp(.cond_jmp_above_below, inst, w), - .cond_jmp_eq_ne => try print.mirCondJmp(.cond_jmp_eq_ne, inst, w), - - .cond_set_byte_greater_less => try print.mirCondSetByte(.cond_set_byte_greater_less, inst, w), - .cond_set_byte_above_below => try print.mirCondSetByte(.cond_set_byte_above_below, inst, w), - .cond_set_byte_eq_ne => try print.mirCondSetByte(.cond_set_byte_eq_ne, inst, w), - - .@"test" => try print.mirTest(inst, w), - - .brk => try w.writeAll("brk\n"), - .ret => try w.writeAll("ret\n"), - .nop => try w.writeAll("nop\n"), - .syscall => try w.writeAll("syscall\n"), - - .call_extern => try print.mirCallExtern(inst, w), - - .dbg_line, .dbg_prologue_end, .dbg_epilogue_begin => try w.print("{s}\n", .{@tagName(tag)}), - - .push_regs_from_callee_preserved_regs => try print.mirPushPopRegsFromCalleePreservedRegs(.push, inst, w), - .pop_regs_from_callee_preserved_regs => try print.mirPushPopRegsFromCalleePreservedRegs(.pop, inst, w), - - else => { - try w.print("TODO emit asm for {s}\n", .{@tagName(tag)}); - }, - } - } -} - -fn mirPushPop(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - switch (ops.flags) { - 0b00 => { - // PUSH/POP reg - try w.print("{s} {s}", .{ @tagName(tag), @tagName(ops.reg1) }); - }, - 0b01 => { - // PUSH/POP r/m64 - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("{s} [{s} + {d}]", .{ @tagName(tag), @tagName(ops.reg1), imm }); - }, - 0b10 => { - const imm = print.mir.instructions.items(.data)[inst].imm; - // PUSH imm32 - assert(tag == .push); - try w.print("{s} {d}", .{ @tagName(tag), imm }); - }, - 0b11 => unreachable, - } - try w.writeByte('\n'); -} -fn mirPushPopRegsFromCalleePreservedRegs(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const payload = print.mir.instructions.items(.data)[inst].payload; - const data = print.mir.extraData(Mir.RegsToPushOrPop, payload).data; - const regs = data.regs; - var disp: u32 = data.disp + 8; - if (regs == 0) return w.writeAll("no regs from callee_preserved_regs\n"); - var printed_first_reg = false; - for (abi.callee_preserved_regs) |reg, i| { - if ((regs >> @intCast(u5, i)) & 1 == 0) continue; - if (printed_first_reg) try w.writeAll(" "); - printed_first_reg = true; - if (tag == .push) { - try w.print("mov qword ptr [{s} + {d}], {s}", .{ - @tagName(ops.reg1), - @bitCast(u32, -@intCast(i32, disp)), - @tagName(reg.to64()), - }); - } else { - try w.print("mov {s}, qword ptr [{s} + {d}]", .{ - @tagName(reg.to64()), - @tagName(ops.reg1), - @bitCast(u32, -@intCast(i32, disp)), - }); - } - disp += 8; - try w.writeByte('\n'); - } -} - -fn mirJmpCall(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - try w.print("{s} ", .{@tagName(tag)}); - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const flag = @truncate(u1, ops.flags); - if (flag == 0) { - return w.writeAll("TODO target\n"); - } - if (ops.reg1 == .none) { - // JMP/CALL [imm] - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("[{x}]\n", .{imm}); - return; - } - // JMP/CALL reg - try w.print("{s}\n", .{@tagName(ops.reg1)}); -} - -fn mirCondJmp(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - _ = print; - _ = tag; - _ = inst; - try w.writeAll("TODO print mirCondJmp\n"); -} - -fn mirCondSetByte(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - _ = tag; - _ = inst; - _ = print; - try w.writeAll("TODO print mirCondSetByte\n"); -} - -fn mirTest(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void { - _ = print; - _ = inst; - try w.writeAll("TODO print mirTest\n"); -} - -fn mirArith(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - try w.writeAll(@tagName(tag)); - try w.writeByte(' '); - switch (ops.flags) { - 0b00 => { - if (ops.reg2 == .none) { - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("{s}, {d}", .{ @tagName(ops.reg1), imm }); - } else try w.print("{s}, {s}", .{ @tagName(ops.reg1), @tagName(ops.reg2) }); - }, - 0b01 => { - const imm = print.mir.instructions.items(.data)[inst].imm; - if (ops.reg2 == .none) { - try w.print("{s}, ", .{@tagName(ops.reg1)}); - switch (ops.reg1.size()) { - 8 => try w.print("byte ptr ", .{}), - 16 => try w.print("word ptr ", .{}), - 32 => try w.print("dword ptr ", .{}), - 64 => try w.print("qword ptr ", .{}), - else => unreachable, - } - try w.print("[ds:{d}]", .{imm}); - } else { - try w.print("{s}, ", .{@tagName(ops.reg1)}); - switch (ops.reg1.size()) { - 8 => try w.print("byte ptr ", .{}), - 16 => try w.print("word ptr ", .{}), - 32 => try w.print("dword ptr ", .{}), - 64 => try w.print("qword ptr ", .{}), - else => unreachable, - } - try w.print("[{s} + {d}]", .{ @tagName(ops.reg2), imm }); - } - }, - 0b10 => { - const imm = print.mir.instructions.items(.data)[inst].imm; - if (ops.reg2 == .none) { - try w.writeAll("unused variant"); - } else { - switch (ops.reg2.size()) { - 8 => try w.print("byte ptr ", .{}), - 16 => try w.print("word ptr ", .{}), - 32 => try w.print("dword ptr ", .{}), - 64 => try w.print("qword ptr ", .{}), - else => unreachable, - } - try w.print("[{s} + {d}], {s}", .{ @tagName(ops.reg1), imm, @tagName(ops.reg2) }); - } - }, - 0b11 => { - try w.writeAll("unused variant"); - }, - } - try w.writeByte('\n'); -} - -fn mirArithMemImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const payload = print.mir.instructions.items(.data)[inst].payload; - const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data; - try w.print("{s} ", .{@tagName(tag)}); - switch (ops.flags) { - 0b00 => try w.print("byte ptr ", .{}), - 0b01 => try w.print("word ptr ", .{}), - 0b10 => try w.print("dword ptr ", .{}), - 0b11 => try w.print("qword ptr ", .{}), - } - try w.print("[{s} + {d}], {d}\n", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand }); -} - -fn mirArithScaleSrc(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const scale = ops.flags; - // OP reg1, [reg2 + scale*rcx + imm32] - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("{s} {s}, [{s} + {d}*rcx + {d}]\n", .{ @tagName(tag), @tagName(ops.reg1), @tagName(ops.reg2), scale, imm }); -} - -fn mirArithScaleDst(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const scale = ops.flags; - const imm = print.mir.instructions.items(.data)[inst].imm; - - if (ops.reg2 == .none) { - // OP [reg1 + scale*rax + 0], imm32 - try w.print("{s} [{s} + {d}*rax + 0], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm }); - } - - // OP [reg1 + scale*rax + imm32], reg2 - try w.print("{s} [{s} + {d}*rax + {d}], {s}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm, @tagName(ops.reg2) }); -} - -fn mirArithScaleImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const scale = ops.flags; - const payload = print.mir.instructions.items(.data)[inst].payload; - const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data; - try w.print("{s} [{s} + {d}*rax + {d}], {d}\n", .{ @tagName(tag), @tagName(ops.reg1), scale, imm_pair.dest_off, imm_pair.operand }); -} - -fn mirArithMemIndexImm(print: *const Print, tag: Mir.Inst.Tag, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const payload = print.mir.instructions.items(.data)[inst].payload; - const imm_pair = print.mir.extraData(Mir.ImmPair, payload).data; - try w.print("{s} ", .{@tagName(tag)}); - switch (ops.flags) { - 0b00 => try w.print("byte ptr ", .{}), - 0b01 => try w.print("word ptr ", .{}), - 0b10 => try w.print("dword ptr ", .{}), - 0b11 => try w.print("qword ptr ", .{}), - } - try w.print("[{s} + 1*rax + {d}], {d}\n", .{ @tagName(ops.reg1), imm_pair.dest_off, imm_pair.operand }); -} - -fn mirMovabs(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void { - const tag = print.mir.instructions.items(.tag)[inst]; - assert(tag == .movabs); - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - - const is_64 = ops.reg1.size() == 64; - const imm: i128 = if (is_64) blk: { - const payload = print.mir.instructions.items(.data)[inst].payload; - const imm64 = print.mir.extraData(Mir.Imm64, payload).data; - break :blk imm64.decode(); - } else print.mir.instructions.items(.data)[inst].imm; - if (ops.flags == 0b00) { - // movabs reg, imm64 - try w.print("movabs {s}, {d}\n", .{ @tagName(ops.reg1), imm }); - } - if (ops.reg1 == .none) { - try w.writeAll("movabs moffs64, rax\n"); - } else { - // movabs rax, moffs64 - try w.writeAll("movabs rax, moffs64\n"); - } -} - -fn mirIMulComplex(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void { - const tag = print.mir.instructions.items(.tag)[inst]; - assert(tag == .imul_complex); - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - switch (ops.flags) { - 0b00 => { - try w.print("imul {s}, {s}\n", .{ @tagName(ops.reg1), @tagName(ops.reg2) }); - }, - 0b10 => { - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("imul {s}, {s}, {d}\n", .{ @tagName(ops.reg1), @tagName(ops.reg2), imm }); - }, - else => return w.writeAll("TODO implement imul\n"), - } -} - -fn mirLea(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - try w.writeAll("lea "); - switch (ops.flags) { - 0b00 => { - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("{s} [", .{@tagName(ops.reg1)}); - if (ops.reg2 != .none) { - try w.print("{s} + ", .{@tagName(ops.reg2)}); - } else { - try w.print("ds:", .{}); - } - try w.print("{d}]", .{imm}); - }, - 0b01 => { - try w.print("{s}, ", .{@tagName(ops.reg1)}); - switch (ops.reg1.size()) { - 8 => try w.print("byte ptr ", .{}), - 16 => try w.print("word ptr ", .{}), - 32 => try w.print("dword ptr ", .{}), - 64 => try w.print("qword ptr ", .{}), - else => unreachable, - } - try w.print("[rip + 0x0] ", .{}); - const payload = print.mir.instructions.items(.data)[inst].payload; - const imm = print.mir.extraData(Mir.Imm64, payload).data.decode(); - try w.print("target@{x}", .{imm}); - }, - 0b10 => { - const imm = print.mir.instructions.items(.data)[inst].imm; - try w.print("{s}, ", .{@tagName(ops.reg1)}); - switch (ops.reg1.size()) { - 8 => try w.print("byte ptr ", .{}), - 16 => try w.print("word ptr ", .{}), - 32 => try w.print("dword ptr ", .{}), - 64 => try w.print("qword ptr ", .{}), - else => unreachable, - } - try w.print("[rbp + rcx + {d}]", .{imm}); - }, - 0b11 => { - try w.writeAll("unused variant"); - }, - } - try w.writeAll("\n"); -} - -fn mirLeaPie(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void { - const ops = Mir.Ops.decode(print.mir.instructions.items(.ops)[inst]); - const load_reloc = print.mir.instructions.items(.data)[inst].load_reloc; - try w.print("lea {s}, ", .{@tagName(ops.reg1)}); - switch (ops.reg1.size()) { - 8 => try w.print("byte ptr ", .{}), - 16 => try w.print("word ptr ", .{}), - 32 => try w.print("dword ptr ", .{}), - 64 => try w.print("qword ptr ", .{}), - else => unreachable, - } - try w.print("[rip + 0x0] ", .{}); - if (print.bin_file.cast(link.File.MachO)) |macho_file| { - const target = macho_file.locals.items[load_reloc.sym_index]; - const target_name = macho_file.getString(target.n_strx); - try w.print("target@{s}", .{target_name}); - } else { - try w.print("TODO lea PIE for other backends", .{}); - } - return w.writeByte('\n'); -} - -fn mirCallExtern(print: *const Print, inst: Mir.Inst.Index, w: anytype) !void { - _ = print; - _ = inst; - return w.writeAll("TODO call_extern"); -} diff --git a/src/main.zig b/src/main.zig index 246eacfe7a..bd923ed85f 100644 --- a/src/main.zig +++ b/src/main.zig @@ -594,7 +594,6 @@ fn buildOutputType( var verbose_link = std.process.hasEnvVarConstant("ZIG_VERBOSE_LINK"); var verbose_cc = std.process.hasEnvVarConstant("ZIG_VERBOSE_CC"); var verbose_air = false; - var verbose_mir = false; var verbose_llvm_ir = false; var verbose_cimport = false; var verbose_llvm_cpu_features = false; @@ -1233,8 +1232,6 @@ fn buildOutputType( verbose_cc = true; } else if (mem.eql(u8, arg, "--verbose-air")) { verbose_air = true; - } else if (mem.eql(u8, arg, "--verbose-mir")) { - verbose_mir = true; } else if (mem.eql(u8, arg, "--verbose-llvm-ir")) { verbose_llvm_ir = true; } else if (mem.eql(u8, arg, "--verbose-cimport")) { @@ -2720,7 +2717,6 @@ fn buildOutputType( .verbose_cc = verbose_cc, .verbose_link = verbose_link, .verbose_air = verbose_air, - .verbose_mir = verbose_mir, .verbose_llvm_ir = verbose_llvm_ir, .verbose_cimport = verbose_cimport, .verbose_llvm_cpu_features = verbose_llvm_cpu_features,