mirror/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2025-12-10 08:13:07 +00:00
Code Issues Packages Projects Releases Wiki Activity

compiler_rt: atomics: Add Leon CAS instruction check for SPARC atomics

Browse Source
This commit is contained in:
Koakuma 2022-04-15 19:40:36 +07:00
parent 6aa89115f9
commit 5b283fba77
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/std/special/compiler_rt/atomics.zig
View File

@ -1,6 +1,7 @@
const std = @import("std"); const std = @import("std");
const builtin = @import("builtin"); const builtin = @import("builtin");
const arch = builtin.cpu.arch; const cpu = builtin.cpu;
const arch = cpu.arch;
const linkage: std.builtin.GlobalLinkage = if (builtin.is_test) .Internal else .Weak; const linkage: std.builtin.GlobalLinkage = if (builtin.is_test) .Internal else .Weak;
@ -27,9 +28,7 @@ const largest_atomic_size = switch (arch) {
// On SPARC systems that lacks CAS and/or swap instructions, the only // On SPARC systems that lacks CAS and/or swap instructions, the only
// available atomic operation is a test-and-set (`ldstub`), so we force // available atomic operation is a test-and-set (`ldstub`), so we force
// every atomic memory access to go through the lock. // every atomic memory access to go through the lock.
// XXX: Check the presence of CAS/swap instructions and set this parameter .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
// accordingly.
.sparc, .sparcel, .sparcv9 => 0,
// XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
// and set this parameter accordingly. // and set this parameter accordingly.