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stage1: make f80 always size 16, align 16
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@ -46,8 +46,10 @@ pub const f128_toint = 1.0 / f128_epsilon;
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pub const F80Repr = if (@import("builtin").cpu.arch.endian() == .Little) extern struct {
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fraction: u64,
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exp: u16,
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_pad: u32 = undefined,
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} else extern struct {
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exp: u16,
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_pad: u32 = undefined, // TODO verify compatibility with hardware
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fraction: u64,
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};
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@ -8197,6 +8197,7 @@ static LLVMValueRef gen_const_val(CodeGen *g, ZigValue *const_val, const char *n
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buf[1] = tmp;
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#endif
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LLVMValueRef as_i128 = LLVMConstIntOfArbitraryPrecision(LLVMInt128Type(), 2, buf);
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if (!target_has_f80(g->zig_target)) return as_i128;
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LLVMValueRef as_int = LLVMConstTrunc(as_i128, LLVMIntType(80));
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return LLVMConstBitCast(as_int, get_llvm_type(g, type_entry));
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}
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@ -9420,13 +9421,15 @@ static void define_builtin_types(CodeGen *g) {
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add_fp_entry(g, "f64", 64, LLVMDoubleType(), &g->builtin_types.entry_f64);
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add_fp_entry(g, "f128", 128, LLVMFP128Type(), &g->builtin_types.entry_f128);
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if (target_has_f80(g->zig_target)) {
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add_fp_entry(g, "f80", 80, LLVMX86FP80Type(), &g->builtin_types.entry_f80);
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} else {
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{
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ZigType *entry = new_type_table_entry(ZigTypeIdFloat);
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entry->llvm_type = get_int_type(g, false, 128)->llvm_type;
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entry->size_in_bits = 8 * LLVMStoreSizeOfType(g->target_data_ref, entry->llvm_type);
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entry->abi_size = LLVMABISizeOfType(g->target_data_ref, entry->llvm_type);
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if (target_has_f80(g->zig_target)) {
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entry->llvm_type = LLVMX86FP80Type();
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} else {
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entry->llvm_type = get_int_type(g, false, 128)->llvm_type;
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}
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entry->size_in_bits = 8 * 16;
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entry->abi_size = 16;
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entry->abi_align = 16;
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buf_init_from_str(&entry->name, "f80");
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entry->data.floating.bit_count = 80;
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