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std: Add Wasm SIMD opcodes and value type

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This adds the opcodes for both the simd128 and relaxed-simd features.
Those instructions are required by the self-hosted WebAssembly
backend. Additionally, this also adds the new `v128` Valtype which
is required to represent a 128bit simd value. SIMD values that do
not have exactly 128 bits will be represented differently.
This commit is contained in:
Luuk de Gram 2022-12-05 21:25:32 +01:00
parent 4832677c3b
commit 5a6b6992d8
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1 changed files with 272 additions and 0 deletions
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lib/std/wasm.zig
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@ -237,6 +237,277 @@ pub const PrefixedOpcode = enum(u8) {
_,
};
/// Simd opcodes that require a prefix `0xFD`.
/// Each opcode represents a varuint32, meaning
/// they are encoded as leb128 in binary.
pub const SimdOpcode = enum(u32) {
v128_load = 0x00,
v128_load8x8_s = 0x01,
v128_load8x8_u = 0x02,
v128_load16x4_s = 0x03,
v128_load16x4_u = 0x04,
v128_load32x2_s = 0x05,
v128_load32x2_u = 0x06,
v128_load8_splat = 0x07,
v128_load16_splat = 0x08,
v128_load32_splat = 0x09,
v128_load64_splat = 0x0A,
v128_store = 0x0B,
v128_const = 0x0C,
i8x16_shuffle = 0x0D,
i8x16_swizzle = 0x0E,
@"8x16_splat" = 0x0F,
i16x8_splat = 0x10,
i32x4_splat = 0x11,
i64x2_splat = 0x12,
f32x4_splat = 0x13,
f64x2_splat = 0x14,
@"8x16_extract_lane_s" = 0x15,
i8x16_extract_lane_u = 0x16,
i8x16_replace_lane = 0x17,
i16x8_extract_lane_s = 0x18,
i16x8_extract_lane_u = 0x19,
i16x8_replace_lane = 0x1A,
i32x4_extract_lane = 0x1B,
i32x4_replace_lane = 0x1C,
i64x2_extract_lane = 0x1D,
i64x2_replace_lane = 0x1E,
f32x4_extract_lane = 0x1F,
f32x4_replace_lane = 0x20,
f64x2_extract_lane = 0x21,
f64x2_replace_lane = 0x22,
i8x16_eq = 0x23,
i16x8_eq = 0x2D,
i32x4_eq = 0x37,
i8x16_ne = 0x24,
i16x8_ne = 0x2E,
i32x4_ne = 0x38,
i8x16_lt_s = 0x25,
i16x8_lt_s = 0x2F,
i32x4_lt_s = 0x39,
i8x16_lt_u = 0x26,
i16x8_lt_u = 0x30,
i32x4_lt_u = 0x3A,
i8x16_gt_s = 0x27,
i16x8_gt_s = 0x31,
i32x4_gt_s = 0x3B,
i8x16_gt_u = 0x28,
i16x8_gt_u = 0x32,
i32x4_gt_u = 0x3C,
i8x16_le_s = 0x29,
i16x8_le_s = 0x33,
i32x4_le_s = 0x3D,
i8x16_le_u = 0x2A,
i16x8_le_u = 0x34,
i32x4_le_u = 0x3E,
i8x16_ge_s = 0x2B,
i16x8_ge_s = 0x35,
i32x4_ge_s = 0x3F,
i8x16_ge_u = 0x2C,
i16x8_ge_u = 0x36,
i32x4_ge_u = 0x40,
f32x4_eq = 0x41,
f64x2_eq = 0x47,
f32x4_ne = 0x42,
f64x2_ne = 0x48,
f32x4_lt = 0x43,
f64x2_lt = 0x49,
f32x4_gt = 0x44,
f64x2_gt = 0x4A,
f32x4_le = 0x45,
f64x2_le = 0x4B,
f32x4_ge = 0x46,
f64x2_ge = 0x4C,
v128_not = 0x4D,
v128_and = 0x4E,
v128_andnot = 0x4F,
v128_or = 0x50,
v128_xor = 0x51,
v128_bitselect = 0x52,
v128_any_true = 0x53,
v128_load8_lane = 0x54,
v128_load16_lane = 0x55,
v128_load32_lane = 0x56,
v128_load64_lane = 0x57,
v128_store8_lane = 0x58,
v128_store16_lane = 0x59,
v128_store32_lane = 0x5A,
v128_store64_lane = 0x5B,
v128_load32_zero = 0x5C,
v128_load64_zero = 0x5D,
f32x4_demote_f64x2_zero = 0x5E,
f64x2_promote_low_f32x4 = 0x5F,
i8x16_abs = 0x60,
i16x8_abs = 0x80,
i32x4_abs = 0xA0,
i64x2_abs = 0xC0,
i8x16_neg = 0x61,
i16x8_neg = 0x81,
i32x4_neg = 0xA1,
i64x2_neg = 0xC1,
i8x16_popcnt = 0x62,
i16x8_q15mulr_sat_s = 0x82,
i8x16_all_true = 0x63,
i16x8_all_true = 0x83,
i32x4_all_true = 0xA3,
i64x2_all_true = 0xC3,
i8x16_bitmask = 0x64,
i16x8_bitmask = 0x84,
i32x4_bitmask = 0xA4,
i64x2_bitmask = 0xC4,
i8x16_narrow_i16x8_s = 0x65,
i16x8_narrow_i32x4_s = 0x85,
i8x16_narrow_i16x8_u = 0x66,
i16x8_narrow_i32x4_u = 0x86,
f32x4_ceil = 0x67,
i16x8_extend_low_i8x16_s = 0x87,
i32x4_extend_low_i16x8_s = 0xA7,
i64x2_extend_low_i32x4_s = 0xC7,
f32x4_floor = 0x68,
i16x8_extend_high_i8x16_s = 0x88,
i32x4_extend_high_i16x8_s = 0xA8,
i64x2_extend_high_i32x4_s = 0xC8,
f32x4_trunc = 0x69,
i16x8_extend_low_i8x16_u = 0x89,
i32x4_extend_low_i16x8_u = 0xA9,
i64x2_extend_low_i32x4_u = 0xC9,
f32x4_nearest = 0x6A,
i16x8_extend_high_i8x16_u = 0x8A,
i32x4_extend_high_i16x8_u = 0xAA,
i64x2_extend_high_i32x4_u = 0xCA,
i8x16_shl = 0x6B,
i16x8_shl = 0x8B,
i32x4_shl = 0xAB,
i64x2_shl = 0xCB,
i8x16_shr_s = 0x6C,
i16x8_shr_s = 0x8C,
i32x4_shr_s = 0xAC,
i64x2_shr_s = 0xCC,
i8x16_shr_u = 0x6D,
i16x8_shr_u = 0x8D,
i32x4_shr_u = 0xAD,
i64x2_shr_u = 0xCD,
i8x16_add = 0x6E,
i16x8_add = 0x8E,
i32x4_add = 0xAE,
i64x2_add = 0xCE,
i8x16_add_sat_s = 0x6F,
i16x8_add_sat_s = 0x8F,
i8x16_add_sat_u = 0x70,
i16x8_add_sat_u = 0x90,
i8x16_sub = 0x71,
i16x8_sub = 0x91,
i32x4_sub = 0xB1,
i64x2_sub = 0xD1,
i8x16_sub_sat_s = 0x72,
i16x8_sub_sat_s = 0x92,
i8x16_sub_sat_u = 0x73,
i16x8_sub_sat_u = 0x93,
f64x2_ceil = 0x74,
f64x2_nearest = 0x94,
f64x2_floor = 0x75,
i16x8_mul = 0x95,
i32x4_mul = 0xB5,
i64x2_mul = 0xD5,
i8x16_min_s = 0x76,
i16x8_min_s = 0x96,
i32x4_min_s = 0xB6,
i64x2_eq = 0xD6,
i8x16_min_u = 0x77,
i16x8_min_u = 0x97,
i32x4_min_u = 0xB7,
i64x2_ne = 0xD7,
i8x16_max_s = 0x78,
i16x8_max_s = 0x98,
i32x4_max_s = 0xB8,
i64x2_lt_s = 0xD8,
i8x16_max_u = 0x79,
i16x8_max_u = 0x99,
i32x4_max_u = 0xB9,
i64x2_gt_s = 0xD9,
f64x2_trunc = 0x7A,
i32x4_dot_i16x8_s = 0xBA,
i64x2_le_s = 0xDA,
i8x16_avgr_u = 0x7B,
i16x8_avgr_u = 0x9B,
i64x2_ge_s = 0xDB,
i16x8_extadd_pairwise_i8x16_s = 0x7C,
i16x8_extmul_low_i8x16_s = 0x9C,
i32x4_extmul_low_i16x8_s = 0xBC,
i64x2_extmul_low_i32x4_s = 0xDC,
i16x8_extadd_pairwise_i8x16_u = 0x7D,
i16x8_extmul_high_i8x16_s = 0x9D,
i32x4_extmul_high_i16x8_s = 0xBD,
i64x2_extmul_high_i32x4_s = 0xDD,
i32x4_extadd_pairwise_i16x8_s = 0x7E,
i16x8_extmul_low_i8x16_u = 0x9E,
i32x4_extmul_low_i16x8_u = 0xBE,
i64x2_extmul_low_i32x4_u = 0xDE,
i32x4_extadd_pairwise_i16x8_u = 0x7F,
i16x8_extmul_high_i8x16_u = 0x9F,
i32x4_extmul_high_i16x8_u = 0xBF,
i64x2_extmul_high_i32x4_u = 0xDF,
f32x4_abs = 0xE0,
f64x2_abs = 0xEC,
f32x4_neg = 0xE1,
f64x2_neg = 0xED,
f32x4_sqrt = 0xE3,
f64x2_sqrt = 0xEF,
f32x4_add = 0xE4,
f64x2_add = 0xF0,
f32x4_sub = 0xE5,
f64x2_sub = 0xF1,
f32x4_mul = 0xE6,
f64x2_mul = 0xF2,
f32x4_div = 0xE7,
f64x2_div = 0xF3,
f32x4_min = 0xE8,
f64x2_min = 0xF4,
f32x4_max = 0xE9,
f64x2_max = 0xF5,
f32x4_pmin = 0xEA,
f64x2_pmin = 0xF6,
f32x4_pmax = 0xEB,
f64x2_pmax = 0xF7,
i32x4_trunc_sat_f32x4_s = 0xF8,
i32x4_trunc_sat_f32x4_u = 0xF9,
f32x4_convert_i32x4_s = 0xFA,
f32x4_convert_i32x4_u = 0xFB,
i32x4_trunc_sat_f64x2_s_zero = 0xFC,
i32x4_trunc_sat_f64x2_u_zero = 0xFD,
f64x2_convert_low_i32x4_s = 0xFE,
f64x2_convert_low_i32x4_u = 0xFF,
// relaxed-simd opcodes
i8x16_relaxed_swizzle = 0x100,
i32x4_relaxed_trunc_f32x4_s = 0x101,
i32x4_relaxed_trunc_f32x4_u = 0x102,
i32x4_relaxed_trunc_f64x2_s_zero = 0x103,
i32x4_relaxed_trunc_f64x2_u_zero = 0x104,
f32x4_relaxed_madd = 0x105,
f32x4_relaxed_nmadd = 0x106,
f64x2_relaxed_madd = 0x107,
f64x2_relaxed_nmadd = 0x108,
i8x16_relaxed_laneselect = 0x109,
i16x8_relaxed_laneselect = 0x10a,
i32x4_relaxed_laneselect = 0x10b,
i64x2_relaxed_laneselect = 0x10c,
f32x4_relaxed_min = 0x10d,
f32x4_relaxed_max = 0x10e,
f64x2_relaxed_min = 0x10f,
f64x2_relaxed_max = 0x110,
i16x8_relaxed_q15mulr_s = 0x111,
i16x8_relaxed_dot_i8x16_i7x16_s = 0x112,
i32x4_relaxed_dot_i8x16_i7x16_add_s = 0x113,
f32x4_relaxed_dot_bf16x8_add_f32x4 = 0x114,
};
/// Returns the integer value of an `SimdOpcode`. Used by the Zig compiler
/// to write instructions to the wasm binary file
pub fn simdOpcode(op: SimdOpcode) u32 {
return @enumToInt(op);
}
/// Enum representing all Wasm value types as per spec:
/// https://webassembly.github.io/spec/core/binary/types.html
pub const Valtype = enum(u8) {
@ -244,6 +515,7 @@ pub const Valtype = enum(u8) {
i64 = 0x7E,
f32 = 0x7D,
f64 = 0x7C,
v128 = 0x7B,
};
/// Returns the integer value of a `Valtype`