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std.Target: update CPU features to LLVM 21

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Alex Rønne Petersen 2025-07-16 06:33:25 +02:00
parent 94f95fefe3
commit 587eddda28
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13 changed files with 2227 additions and 212 deletions
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397
lib/std/Target/aarch64.zig
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@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model; const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum { pub const Feature = enum {
a320,
addr_lsl_slow_14, addr_lsl_slow_14,
aes, aes,
aggressive_fma, aggressive_fma,
@ -44,6 +45,7 @@ pub const Feature = enum {
crypto, crypto,
cssc, cssc,
d128, d128,
disable_fast_inc_vl,
disable_latency_sched_heuristic, disable_latency_sched_heuristic,
disable_ldp, disable_ldp,
disable_stp, disable_stp,
@ -54,6 +56,7 @@ pub const Feature = enum {
el3, el3,
enable_select_opt, enable_select_opt,
ete, ete,
execute_only,
exynos_cheap_as_move, exynos_cheap_as_move,
f32mm, f32mm,
f64mm, f64mm,
@ -114,6 +117,7 @@ pub const Feature = enum {
no_zcz_fp, no_zcz_fp,
nv, nv,
occmo, occmo,
olympus,
outline_atomics, outline_atomics,
pan, pan,
pan_rwv, pan_rwv,
@ -187,6 +191,7 @@ pub const Feature = enum {
ssbs, ssbs,
ssve_aes, ssve_aes,
ssve_bitperm, ssve_bitperm,
ssve_fexpa,
ssve_fp8dot2, ssve_fp8dot2,
ssve_fp8dot4, ssve_fp8dot4,
ssve_fp8fma, ssve_fp8fma,
@ -207,6 +212,8 @@ pub const Feature = enum {
sve_bfscale, sve_bfscale,
sve_bitperm, sve_bitperm,
sve_f16f32mm, sve_f16f32mm,
sve_sha3,
sve_sm4,
tagged_globals, tagged_globals,
the, the,
tlb_rmi, tlb_rmi,
@ -244,7 +251,10 @@ pub const Feature = enum {
vh, vh,
wfxt, wfxt,
xs, xs,
zcm, zcm_fpr32,
zcm_fpr64,
zcm_gpr32,
zcm_gpr64,
zcz, zcz,
zcz_fp_workaround, zcz_fp_workaround,
zcz_gp, zcz_gp,
@ -260,6 +270,15 @@ pub const all_features = blk: {
const len = @typeInfo(Feature).@"enum".fields.len; const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count); std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined; var result: [len]CpuFeature = undefined;
result[@intFromEnum(Feature.a320)] = .{
.llvm_name = "a320",
.description = "Cortex-A320 ARM processors",
.dependencies = featureSet(&[_]Feature{
.fuse_adrp_add,
.fuse_aes,
.use_postra_scheduler,
}),
};
result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{ result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{
.llvm_name = "addr-lsl-slow-14", .llvm_name = "addr-lsl-slow-14",
.description = "Address operands with shift amount of 1 or 4 are slow", .description = "Address operands with shift amount of 1 or 4 are slow",
@ -472,6 +491,11 @@ pub const all_features = blk: {
.lse128, .lse128,
}), }),
}; };
result[@intFromEnum(Feature.disable_fast_inc_vl)] = .{
.llvm_name = "disable-fast-inc-vl",
.description = "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.disable_latency_sched_heuristic)] = .{ result[@intFromEnum(Feature.disable_latency_sched_heuristic)] = .{
.llvm_name = "disable-latency-sched-heuristic", .llvm_name = "disable-latency-sched-heuristic",
.description = "Disable latency scheduling heuristic", .description = "Disable latency scheduling heuristic",
@ -526,6 +550,11 @@ pub const all_features = blk: {
.trbe, .trbe,
}), }),
}; };
result[@intFromEnum(Feature.execute_only)] = .{
.llvm_name = "execute-only",
.description = "Enable the generation of execute only code.",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.exynos_cheap_as_move)] = .{ result[@intFromEnum(Feature.exynos_cheap_as_move)] = .{
.llvm_name = "exynos-cheap-as-move", .llvm_name = "exynos-cheap-as-move",
.description = "Use Exynos specific handling of cheap instructions", .description = "Use Exynos specific handling of cheap instructions",
@ -876,6 +905,20 @@ pub const all_features = blk: {
.description = "Enable Armv9.6-A Outer cacheable cache maintenance operations", .description = "Enable Armv9.6-A Outer cacheable cache maintenance operations",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.olympus)] = .{
.llvm_name = "olympus",
.description = "NVIDIA Olympus processors",
.dependencies = featureSet(&[_]Feature{
.alu_lsl_fast,
.cmp_bcc_fusion,
.enable_select_opt,
.fuse_adrp_add,
.fuse_aes,
.predictable_select_expensive,
.use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler,
}),
};
result[@intFromEnum(Feature.outline_atomics)] = .{ result[@intFromEnum(Feature.outline_atomics)] = .{
.llvm_name = "outline-atomics", .llvm_name = "outline-atomics",
.description = "Enable out of line atomics to support LSE instructions", .description = "Enable out of line atomics to support LSE instructions",
@ -1298,6 +1341,13 @@ pub const all_features = blk: {
.sve_bitperm, .sve_bitperm,
}), }),
}; };
result[@intFromEnum(Feature.ssve_fexpa)] = .{
.llvm_name = "ssve-fexpa",
.description = "Enable SVE FEXPA instruction in Streaming SVE mode",
.dependencies = featureSet(&[_]Feature{
.sme2,
}),
};
result[@intFromEnum(Feature.ssve_fp8dot2)] = .{ result[@intFromEnum(Feature.ssve_fp8dot2)] = .{
.llvm_name = "ssve-fp8dot2", .llvm_name = "ssve-fp8dot2",
.description = "Enable SVE2 FP8 2-way dot product instructions", .description = "Enable SVE2 FP8 2-way dot product instructions",
@ -1369,18 +1419,18 @@ pub const all_features = blk: {
}; };
result[@intFromEnum(Feature.sve2_sha3)] = .{ result[@intFromEnum(Feature.sve2_sha3)] = .{
.llvm_name = "sve2-sha3", .llvm_name = "sve2-sha3",
.description = "Enable SHA3 SVE2 instructions", .description = "Shorthand for +sve2+sve-sha3",
.dependencies = featureSet(&[_]Feature{ .dependencies = featureSet(&[_]Feature{
.sha3,
.sve2, .sve2,
.sve_sha3,
}), }),
}; };
result[@intFromEnum(Feature.sve2_sm4)] = .{ result[@intFromEnum(Feature.sve2_sm4)] = .{
.llvm_name = "sve2-sm4", .llvm_name = "sve2-sm4",
.description = "Enable SM4 SVE2 instructions", .description = "Shorthand for +sve2+sve-sm4",
.dependencies = featureSet(&[_]Feature{ .dependencies = featureSet(&[_]Feature{
.sm4,
.sve2, .sve2,
.sve_sm4,
}), }),
}; };
result[@intFromEnum(Feature.sve2p1)] = .{ result[@intFromEnum(Feature.sve2p1)] = .{
@ -1431,6 +1481,20 @@ pub const all_features = blk: {
.sve, .sve,
}), }),
}; };
result[@intFromEnum(Feature.sve_sha3)] = .{
.llvm_name = "sve-sha3",
.description = "Enable SVE SHA3 instructions",
.dependencies = featureSet(&[_]Feature{
.sha3,
}),
};
result[@intFromEnum(Feature.sve_sm4)] = .{
.llvm_name = "sve-sm4",
.description = "Enable SVE SM4 instructions",
.dependencies = featureSet(&[_]Feature{
.sm4,
}),
};
result[@intFromEnum(Feature.tagged_globals)] = .{ result[@intFromEnum(Feature.tagged_globals)] = .{
.llvm_name = "tagged-globals", .llvm_name = "tagged-globals",
.description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
@ -1746,9 +1810,24 @@ pub const all_features = blk: {
.description = "Enable Armv8.7-A limited-TLB-maintenance instruction", .description = "Enable Armv8.7-A limited-TLB-maintenance instruction",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.zcm)] = .{ result[@intFromEnum(Feature.zcm_fpr32)] = .{
.llvm_name = "zcm", .llvm_name = "zcm-fpr32",
.description = "Has zero-cycle register moves", .description = "Has zero-cycle register moves for FPR32 registers",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.zcm_fpr64)] = .{
.llvm_name = "zcm-fpr64",
.description = "Has zero-cycle register moves for FPR64 registers",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.zcm_gpr32)] = .{
.llvm_name = "zcm-gpr32",
.description = "Has zero-cycle register moves for GPR32 registers",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.zcm_gpr64)] = .{
.llvm_name = "zcm-gpr64",
.description = "Has zero-cycle register moves for GPR64 registers",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.zcz)] = .{ result[@intFromEnum(Feature.zcz)] = .{
@ -1894,7 +1973,8 @@ pub const cpu = struct {
.store_pair_suppress, .store_pair_suppress,
.v8a, .v8a,
.vh, .vh,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -1914,7 +1994,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8_2a, .v8_2a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -1934,7 +2015,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8_3a, .v8_3a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -1954,7 +2036,8 @@ pub const cpu = struct {
.sha3, .sha3,
.store_pair_suppress, .store_pair_suppress,
.v8_4a, .v8_4a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -1986,7 +2069,8 @@ pub const cpu = struct {
.ssbs, .ssbs,
.store_pair_suppress, .store_pair_suppress,
.v8_4a, .v8_4a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2012,7 +2096,8 @@ pub const cpu = struct {
.sha3, .sha3,
.store_pair_suppress, .store_pair_suppress,
.v8_6a, .v8_6a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2039,7 +2124,8 @@ pub const cpu = struct {
.sha3, .sha3,
.store_pair_suppress, .store_pair_suppress,
.v8_6a, .v8_6a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2066,7 +2152,37 @@ pub const cpu = struct {
.sha3, .sha3,
.store_pair_suppress, .store_pair_suppress,
.v8_6a, .v8_6a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz,
}),
};
pub const apple_a18: CpuModel = .{
.name = "apple_a18",
.llvm_name = "apple-a18",
.features = featureSet(&[_]Feature{
.aes,
.alternate_sextload_cvt_f32_pattern,
.arith_bcc_fusion,
.arith_cbz_fusion,
.disable_latency_sched_heuristic,
.fp16fml,
.fpac,
.fuse_address,
.fuse_adrp_add,
.fuse_aes,
.fuse_arith_logic,
.fuse_crypto_eor,
.fuse_csel,
.fuse_literals,
.perfmon,
.sha3,
.sme2,
.sme_f64f64,
.sme_i16i64,
.v8_7a,
.zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2085,7 +2201,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8a, .v8a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
.zcz_fp_workaround, .zcz_fp_workaround,
}), }),
@ -2105,7 +2222,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8a, .v8a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
.zcz_fp_workaround, .zcz_fp_workaround,
}), }),
@ -2125,7 +2243,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8a, .v8a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
.zcz_fp_workaround, .zcz_fp_workaround,
}), }),
@ -2158,7 +2277,8 @@ pub const cpu = struct {
.ssbs, .ssbs,
.store_pair_suppress, .store_pair_suppress,
.v8_4a, .v8_4a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2184,7 +2304,8 @@ pub const cpu = struct {
.sha3, .sha3,
.store_pair_suppress, .store_pair_suppress,
.v8_6a, .v8_6a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2211,7 +2332,8 @@ pub const cpu = struct {
.sha3, .sha3,
.store_pair_suppress, .store_pair_suppress,
.v8_6a, .v8_6a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2239,7 +2361,36 @@ pub const cpu = struct {
.sme_f64f64, .sme_f64f64,
.sme_i16i64, .sme_i16i64,
.v8_7a, .v8_7a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz,
}),
};
pub const apple_s10: CpuModel = .{
.name = "apple_s10",
.llvm_name = "apple-s10",
.features = featureSet(&[_]Feature{
.aes,
.alternate_sextload_cvt_f32_pattern,
.arith_bcc_fusion,
.arith_cbz_fusion,
.disable_latency_sched_heuristic,
.fp16fml,
.fpac,
.fuse_address,
.fuse_adrp_add,
.fuse_aes,
.fuse_arith_logic,
.fuse_crypto_eor,
.fuse_csel,
.fuse_literals,
.hcx,
.perfmon,
.sha3,
.store_pair_suppress,
.v8_6a,
.zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2259,7 +2410,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8_3a, .v8_3a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2279,7 +2431,99 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8_3a, .v8_3a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz,
}),
};
pub const apple_s6: CpuModel = .{
.name = "apple_s6",
.llvm_name = "apple-s6",
.features = featureSet(&[_]Feature{
.aes,
.alternate_sextload_cvt_f32_pattern,
.arith_bcc_fusion,
.arith_cbz_fusion,
.disable_latency_sched_heuristic,
.fp16fml,
.fuse_aes,
.fuse_crypto_eor,
.perfmon,
.sha3,
.store_pair_suppress,
.v8_4a,
.zcm_fpr64,
.zcm_gpr64,
.zcz,
}),
};
pub const apple_s7: CpuModel = .{
.name = "apple_s7",
.llvm_name = "apple-s7",
.features = featureSet(&[_]Feature{
.aes,
.alternate_sextload_cvt_f32_pattern,
.arith_bcc_fusion,
.arith_cbz_fusion,
.disable_latency_sched_heuristic,
.fp16fml,
.fuse_aes,
.fuse_crypto_eor,
.perfmon,
.sha3,
.store_pair_suppress,
.v8_4a,
.zcm_fpr64,
.zcm_gpr64,
.zcz,
}),
};
pub const apple_s8: CpuModel = .{
.name = "apple_s8",
.llvm_name = "apple-s8",
.features = featureSet(&[_]Feature{
.aes,
.alternate_sextload_cvt_f32_pattern,
.arith_bcc_fusion,
.arith_cbz_fusion,
.disable_latency_sched_heuristic,
.fp16fml,
.fuse_aes,
.fuse_crypto_eor,
.perfmon,
.sha3,
.store_pair_suppress,
.v8_4a,
.zcm_fpr64,
.zcm_gpr64,
.zcz,
}),
};
pub const apple_s9: CpuModel = .{
.name = "apple_s9",
.llvm_name = "apple-s9",
.features = featureSet(&[_]Feature{
.aes,
.alternate_sextload_cvt_f32_pattern,
.arith_bcc_fusion,
.arith_cbz_fusion,
.disable_latency_sched_heuristic,
.fp16fml,
.fpac,
.fuse_address,
.fuse_adrp_add,
.fuse_aes,
.fuse_arith_logic,
.fuse_crypto_eor,
.fuse_csel,
.fuse_literals,
.hcx,
.perfmon,
.sha3,
.store_pair_suppress,
.v8_6a,
.zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
}), }),
}; };
@ -2302,6 +2546,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -2313,6 +2558,19 @@ pub const cpu = struct {
.v9a, .v9a,
}), }),
}; };
pub const cortex_a320: CpuModel = .{
.name = "cortex_a320",
.llvm_name = "cortex-a320",
.features = featureSet(&[_]Feature{
.a320,
.ete,
.fp16fml,
.mte,
.perfmon,
.sve_bitperm,
.v9_2a,
}),
};
pub const cortex_a34: CpuModel = .{ pub const cortex_a34: CpuModel = .{
.name = "cortex_a34", .name = "cortex_a34",
.llvm_name = "cortex-a34", .llvm_name = "cortex-a34",
@ -2342,12 +2600,14 @@ pub const cpu = struct {
.bf16, .bf16,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
.mte, .mte,
.perfmon, .perfmon,
.sve_bitperm, .sve_bitperm,
.use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler, .use_postra_scheduler,
.v9a, .v9a,
}), }),
@ -2358,11 +2618,13 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
.perfmon, .perfmon,
.sve_bitperm, .sve_bitperm,
.use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler, .use_postra_scheduler,
.v9_2a, .v9_2a,
}), }),
@ -2373,6 +2635,7 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -2483,6 +2746,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -2504,6 +2768,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -2542,6 +2807,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -2562,6 +2828,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -2582,6 +2849,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -2764,6 +3032,7 @@ pub const cpu = struct {
.llvm_name = "cortex-r82", .llvm_name = "cortex-r82",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.ccdp, .ccdp,
.fpac,
.perfmon, .perfmon,
.predres, .predres,
.use_postra_scheduler, .use_postra_scheduler,
@ -2775,6 +3044,7 @@ pub const cpu = struct {
.llvm_name = "cortex-r82ae", .llvm_name = "cortex-r82ae",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.ccdp, .ccdp,
.fpac,
.perfmon, .perfmon,
.predres, .predres,
.use_postra_scheduler, .use_postra_scheduler,
@ -2840,6 +3110,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -2862,6 +3133,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -2884,6 +3156,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -2905,6 +3178,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -2932,7 +3206,8 @@ pub const cpu = struct {
.sha2, .sha2,
.store_pair_suppress, .store_pair_suppress,
.v8a, .v8a,
.zcm, .zcm_fpr64,
.zcm_gpr64,
.zcz, .zcz,
.zcz_fp_workaround, .zcz_fp_workaround,
}), }),
@ -3081,6 +3356,8 @@ pub const cpu = struct {
.faminmax, .faminmax,
.fp16fml, .fp16fml,
.fp8dot2, .fp8dot2,
.fp8dot4,
.fp8fma,
.fpac, .fpac,
.fujitsu_monaka, .fujitsu_monaka,
.ls64, .ls64,
@ -3088,13 +3365,38 @@ pub const cpu = struct {
.perfmon, .perfmon,
.rand, .rand,
.specres2, .specres2,
.sve2_sha3,
.sve2_sm4,
.sve_aes, .sve_aes,
.sve_bitperm, .sve_bitperm,
.sve_sha3,
.sve_sm4,
.v9_3a, .v9_3a,
}), }),
}; };
pub const gb10: CpuModel = .{
.name = "gb10",
.llvm_name = "gb10",
.features = featureSet(&[_]Feature{
.alu_lsl_fast,
.avoid_ldapur,
.enable_select_opt,
.ete,
.fp16fml,
.fpac,
.fuse_adrp_add,
.fuse_aes,
.mte,
.perfmon,
.predictable_select_expensive,
.spe,
.sve_aes,
.sve_bitperm,
.sve_sha3,
.sve_sm4,
.use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler,
.v9_2a,
}),
};
pub const generic: CpuModel = .{ pub const generic: CpuModel = .{
.name = "generic", .name = "generic",
.llvm_name = "generic", .llvm_name = "generic",
@ -3115,9 +3417,11 @@ pub const cpu = struct {
.avoid_ldapur, .avoid_ldapur,
.bf16, .bf16,
.cmp_bcc_fusion, .cmp_bcc_fusion,
.disable_latency_sched_heuristic,
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -3126,7 +3430,10 @@ pub const cpu = struct {
.predictable_select_expensive, .predictable_select_expensive,
.rand, .rand,
.spe, .spe,
.sve_aes,
.sve_bitperm, .sve_bitperm,
.sve_sha3,
.sve_sm4,
.use_fixed_over_scalable_if_equal_cost, .use_fixed_over_scalable_if_equal_cost,
.use_postra_scheduler, .use_postra_scheduler,
.v9a, .v9a,
@ -3158,6 +3465,7 @@ pub const cpu = struct {
.ccdp, .ccdp,
.enable_select_opt, .enable_select_opt,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -3221,6 +3529,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -3240,6 +3549,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.mte, .mte,
@ -3287,9 +3597,11 @@ pub const cpu = struct {
.avoid_ldapur, .avoid_ldapur,
.bf16, .bf16,
.cmp_bcc_fusion, .cmp_bcc_fusion,
.disable_latency_sched_heuristic,
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.i8mm, .i8mm,
@ -3314,6 +3626,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.ls64, .ls64,
@ -3337,6 +3650,7 @@ pub const cpu = struct {
.enable_select_opt, .enable_select_opt,
.ete, .ete,
.fp16fml, .fp16fml,
.fpac,
.fuse_adrp_add, .fuse_adrp_add,
.fuse_aes, .fuse_aes,
.ls64, .ls64,
@ -3350,6 +3664,33 @@ pub const cpu = struct {
.v9_2a, .v9_2a,
}), }),
}; };
pub const olympus: CpuModel = .{
.name = "olympus",
.llvm_name = "olympus",
.features = featureSet(&[_]Feature{
.brbe,
.chk,
.ete,
.faminmax,
.fp16fml,
.fp8dot2,
.fp8dot4,
.fp8fma,
.fpac,
.ls64,
.lut,
.mte,
.olympus,
.perfmon,
.rand,
.spe,
.sve_aes,
.sve_bitperm,
.sve_sha3,
.sve_sm4,
.v9_2a,
}),
};
pub const oryon_1: CpuModel = .{ pub const oryon_1: CpuModel = .{
.name = "oryon_1", .name = "oryon_1",
.llvm_name = "oryon-1", .llvm_name = "oryon-1",

291
lib/std/Target/amdgcn.zig
View File

@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum { pub const Feature = enum {
@"16_bit_insts", @"16_bit_insts",
@"64_bit_literals",
a16, a16,
add_no_carry_insts, add_no_carry_insts,
addressablelocalmemorysize163840, addressablelocalmemorysize163840,
@ -33,8 +34,11 @@ pub const Feature = enum {
auto_waitcnt_before_barrier, auto_waitcnt_before_barrier,
back_off_barrier, back_off_barrier,
bf16_cvt_insts, bf16_cvt_insts,
bf16_trans_insts,
bf8_cvt_scale_insts, bf8_cvt_scale_insts,
bitop3_insts, bitop3_insts,
block_vgpr_csr,
bvh_dual_bvh_8_insts,
ci_insts, ci_insts,
cumode, cumode,
cvt_fp8_vop1_bug, cvt_fp8_vop1_bug,
@ -61,6 +65,8 @@ pub const Feature = enum {
dpp_src1_sgpr, dpp_src1_sgpr,
ds128, ds128,
ds_src2_insts, ds_src2_insts,
dynamic_vgpr,
dynamic_vgpr_block_size_32,
extended_image_insts, extended_image_insts,
f16bf16_to_fp6bf6_cvt_scale_insts, f16bf16_to_fp6bf6_cvt_scale_insts,
f32_to_f16bf16_cvt_sr_insts, f32_to_f16bf16_cvt_sr_insts,
@ -78,13 +84,13 @@ pub const Feature = enum {
fma_mix_insts, fma_mix_insts,
fmacf64_inst, fmacf64_inst,
fmaf, fmaf,
force_store_sc0_sc1,
fp4_cvt_scale_insts, fp4_cvt_scale_insts,
fp64, fp64,
fp6bf6_cvt_scale_insts, fp6bf6_cvt_scale_insts,
fp8_conversion_insts, fp8_conversion_insts,
fp8_cvt_scale_insts, fp8_cvt_scale_insts,
fp8_insts, fp8_insts,
fp8e5m3_insts,
full_rate_64_ops, full_rate_64_ops,
g16, g16,
gcn3_encoding, gcn3_encoding,
@ -98,6 +104,7 @@ pub const Feature = enum {
gfx11, gfx11,
gfx11_insts, gfx11_insts,
gfx12, gfx12,
gfx1250_insts,
gfx12_insts, gfx12_insts,
gfx7_gfx8_gfx9_insts, gfx7_gfx8_gfx9_insts,
gfx8_insts, gfx8_insts,
@ -108,6 +115,7 @@ pub const Feature = enum {
gfx9_insts, gfx9_insts,
gws, gws,
half_rate_64_ops, half_rate_64_ops,
ieee_minimum_maximum_insts,
image_gather4_d16_bug, image_gather4_d16_bug,
image_insts, image_insts,
image_store_d16_bug, image_store_d16_bug,
@ -115,11 +123,13 @@ pub const Feature = enum {
int_clamp_insts, int_clamp_insts,
inv_2pi_inline_imm, inv_2pi_inline_imm,
kernarg_preload, kernarg_preload,
lds_barrier_arrive_atomic,
lds_branch_vmem_war_hazard, lds_branch_vmem_war_hazard,
lds_misaligned_bug, lds_misaligned_bug,
ldsbankcount16, ldsbankcount16,
ldsbankcount32, ldsbankcount32,
load_store_opt, load_store_opt,
lshl_add_u64_inst,
mad_intra_fwd_bug, mad_intra_fwd_bug,
mad_mac_f32_insts, mad_mac_f32_insts,
mad_mix_insts, mad_mix_insts,
@ -151,6 +161,7 @@ pub const Feature = enum {
permlane16_swap, permlane16_swap,
permlane32_swap, permlane32_swap,
pk_fmac_f16_inst, pk_fmac_f16_inst,
point_sample_accel,
precise_memory, precise_memory,
priv_enabled_trap2_nop_bug, priv_enabled_trap2_nop_bug,
prng_inst, prng_inst,
@ -159,11 +170,13 @@ pub const Feature = enum {
pseudo_scalar_trans, pseudo_scalar_trans,
r128_a16, r128_a16,
real_true16, real_true16,
relaxed_buffer_oob_mode,
required_export_priority, required_export_priority,
requires_cov6, requires_cov6,
restricted_soffset, restricted_soffset,
s_memrealtime, s_memrealtime,
s_memtime_inst, s_memtime_inst,
safe_smem_prefetch,
salu_float, salu_float,
scalar_atomics, scalar_atomics,
scalar_dwordx3_loads, scalar_dwordx3_loads,
@ -176,6 +189,7 @@ pub const Feature = enum {
sdwa_scalar, sdwa_scalar,
sdwa_sdst, sdwa_sdst,
sea_islands, sea_islands,
setprio_inc_wg_inst,
sgpr_init_bug, sgpr_init_bug,
shader_cycles_hi_lo_registers, shader_cycles_hi_lo_registers,
shader_cycles_register, shader_cycles_register,
@ -185,6 +199,7 @@ pub const Feature = enum {
sramecc, sramecc,
sramecc_support, sramecc_support,
tgsplit, tgsplit,
transpose_load_f4f6_insts,
trap_handler, trap_handler,
trig_reduced_range, trig_reduced_range,
true16, true16,
@ -199,6 +214,7 @@ pub const Feature = enum {
vcmpx_exec_war_hazard, vcmpx_exec_war_hazard,
vcmpx_permlane_hazard, vcmpx_permlane_hazard,
vgpr_index_mode, vgpr_index_mode,
vmem_to_lds_load_insts,
vmem_to_scalar_write_hazard, vmem_to_scalar_write_hazard,
vmem_write_vgpr_in_order, vmem_write_vgpr_in_order,
volcanic_islands, volcanic_islands,
@ -206,6 +222,7 @@ pub const Feature = enum {
vop3p, vop3p,
vopd, vopd,
vscnt, vscnt,
wait_xcnt,
wavefrontsize16, wavefrontsize16,
wavefrontsize32, wavefrontsize32,
wavefrontsize64, wavefrontsize64,
@ -220,6 +237,7 @@ pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
pub const all_features = blk: { pub const all_features = blk: {
@setEvalBranchQuota(2000);
const len = @typeInfo(Feature).@"enum".fields.len; const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count); std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined; var result: [len]CpuFeature = undefined;
@ -228,6 +246,11 @@ pub const all_features = blk: {
.description = "Has i16/f16 instructions", .description = "Has i16/f16 instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.@"64_bit_literals")] = .{
.llvm_name = "64-bit-literals",
.description = "Can use 64-bit literals with single DWORD instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.a16)] = .{ result[@intFromEnum(Feature.a16)] = .{
.llvm_name = "a16", .llvm_name = "a16",
.description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands", .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
@ -373,6 +396,11 @@ pub const all_features = blk: {
.description = "Has bf16 conversion instructions", .description = "Has bf16 conversion instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.bf16_trans_insts)] = .{
.llvm_name = "bf16-trans-insts",
.description = "Has bf16 transcendental instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.bf8_cvt_scale_insts)] = .{ result[@intFromEnum(Feature.bf8_cvt_scale_insts)] = .{
.llvm_name = "bf8-cvt-scale-insts", .llvm_name = "bf8-cvt-scale-insts",
.description = "Has bf8 conversion scale instructions", .description = "Has bf8 conversion scale instructions",
@ -383,6 +411,16 @@ pub const all_features = blk: {
.description = "Has v_bitop3_b32/v_bitop3_b16 instructions", .description = "Has v_bitop3_b32/v_bitop3_b16 instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.block_vgpr_csr)] = .{
.llvm_name = "block-vgpr-csr",
.description = "Use block load/store for VGPR callee saved registers",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.bvh_dual_bvh_8_insts)] = .{
.llvm_name = "bvh-dual-bvh-8-insts",
.description = "Has image_bvh_dual_intersect_ray and image_bvh8_intersect_ray instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.ci_insts)] = .{ result[@intFromEnum(Feature.ci_insts)] = .{
.llvm_name = "ci-insts", .llvm_name = "ci-insts",
.description = "Additional instructions for CI+", .description = "Additional instructions for CI+",
@ -515,6 +553,16 @@ pub const all_features = blk: {
.description = "Has ds_*_src2 instructions", .description = "Has ds_*_src2 instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.dynamic_vgpr)] = .{
.llvm_name = "dynamic-vgpr",
.description = "Enable dynamic VGPR mode",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.dynamic_vgpr_block_size_32)] = .{
.llvm_name = "dynamic-vgpr-block-size-32",
.description = "Use a block size of 32 for dynamic VGPR allocation (default is 16)",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.extended_image_insts)] = .{ result[@intFromEnum(Feature.extended_image_insts)] = .{
.llvm_name = "extended-image-insts", .llvm_name = "extended-image-insts",
.description = "Support mips != 0, lod != 0, gather4, and get_lod", .description = "Support mips != 0, lod != 0, gather4, and get_lod",
@ -600,11 +648,6 @@ pub const all_features = blk: {
.description = "Enable single precision FMA (not as fast as mul+add, but fused)", .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{
.llvm_name = "force-store-sc0-sc1",
.description = "Has SC0 and SC1 on stores",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.fp4_cvt_scale_insts)] = .{ result[@intFromEnum(Feature.fp4_cvt_scale_insts)] = .{
.llvm_name = "fp4-cvt-scale-insts", .llvm_name = "fp4-cvt-scale-insts",
.description = "Has fp4 conversion scale instructions", .description = "Has fp4 conversion scale instructions",
@ -635,6 +678,11 @@ pub const all_features = blk: {
.description = "Has fp8 and bf8 instructions", .description = "Has fp8 and bf8 instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.fp8e5m3_insts)] = .{
.llvm_name = "fp8e5m3-insts",
.description = "Has fp8 e5m3 format support",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.full_rate_64_ops)] = .{ result[@intFromEnum(Feature.full_rate_64_ops)] = .{
.llvm_name = "full-rate-64-ops", .llvm_name = "full-rate-64-ops",
.description = "Most fp64 instructions are full rate", .description = "Most fp64 instructions are full rate",
@ -710,6 +758,7 @@ pub const all_features = blk: {
.unaligned_buffer_access, .unaligned_buffer_access,
.unaligned_ds_access, .unaligned_ds_access,
.unaligned_scratch_access, .unaligned_scratch_access,
.vmem_to_lds_load_insts,
.vmem_write_vgpr_in_order, .vmem_write_vgpr_in_order,
.vop3_literal, .vop3_literal,
.vop3p, .vop3p,
@ -827,6 +876,7 @@ pub const all_features = blk: {
.gfx12_insts, .gfx12_insts,
.gfx8_insts, .gfx8_insts,
.gfx9_insts, .gfx9_insts,
.ieee_minimum_maximum_insts,
.int_clamp_insts, .int_clamp_insts,
.inv_2pi_inline_imm, .inv_2pi_inline_imm,
.max_hard_clause_length_32, .max_hard_clause_length_32,
@ -847,6 +897,11 @@ pub const all_features = blk: {
.vscnt, .vscnt,
}), }),
}; };
result[@intFromEnum(Feature.gfx1250_insts)] = .{
.llvm_name = "gfx1250-insts",
.description = "Additional instructions for GFX1250+",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.gfx12_insts)] = .{ result[@intFromEnum(Feature.gfx12_insts)] = .{
.llvm_name = "gfx12-insts", .llvm_name = "gfx12-insts",
.description = "Additional instructions for GFX12+", .description = "Additional instructions for GFX12+",
@ -902,6 +957,7 @@ pub const all_features = blk: {
.unaligned_ds_access, .unaligned_ds_access,
.unaligned_scratch_access, .unaligned_scratch_access,
.vgpr_index_mode, .vgpr_index_mode,
.vmem_to_lds_load_insts,
.vmem_write_vgpr_in_order, .vmem_write_vgpr_in_order,
.vop3p, .vop3p,
.wavefrontsize64, .wavefrontsize64,
@ -951,6 +1007,11 @@ pub const all_features = blk: {
.description = "Most fp64 instructions are half rate instead of quarter", .description = "Most fp64 instructions are half rate instead of quarter",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.ieee_minimum_maximum_insts)] = .{
.llvm_name = "ieee-minimum-maximum-insts",
.description = "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32 and v_pk_minimum/maximum_f16 instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.image_gather4_d16_bug)] = .{ result[@intFromEnum(Feature.image_gather4_d16_bug)] = .{
.llvm_name = "image-gather4-d16-bug", .llvm_name = "image-gather4-d16-bug",
.description = "Image Gather4 D16 hardware bug", .description = "Image Gather4 D16 hardware bug",
@ -986,6 +1047,11 @@ pub const all_features = blk: {
.description = "Hardware supports preloading of kernel arguments in user SGPRs.", .description = "Hardware supports preloading of kernel arguments in user SGPRs.",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.lds_barrier_arrive_atomic)] = .{
.llvm_name = "lds-barrier-arrive-atomic",
.description = "Has LDS barrier-arrive atomic instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.lds_branch_vmem_war_hazard)] = .{ result[@intFromEnum(Feature.lds_branch_vmem_war_hazard)] = .{
.llvm_name = "lds-branch-vmem-war-hazard", .llvm_name = "lds-branch-vmem-war-hazard",
.description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", .description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
@ -1011,6 +1077,11 @@ pub const all_features = blk: {
.description = "Enable SI load/store optimizer pass", .description = "Enable SI load/store optimizer pass",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.lshl_add_u64_inst)] = .{
.llvm_name = "lshl-add-u64-inst",
.description = "Has v_lshl_add_u64 instruction",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.mad_intra_fwd_bug)] = .{ result[@intFromEnum(Feature.mad_intra_fwd_bug)] = .{
.llvm_name = "mad-intra-fwd-bug", .llvm_name = "mad-intra-fwd-bug",
.description = "MAD_U64/I64 intra instruction forwarding bug", .description = "MAD_U64/I64 intra instruction forwarding bug",
@ -1166,6 +1237,11 @@ pub const all_features = blk: {
.description = "Has v_pk_fmac_f16 instruction", .description = "Has v_pk_fmac_f16 instruction",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.point_sample_accel)] = .{
.llvm_name = "point-sample-accel",
.description = "Has point sample acceleration feature",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.precise_memory)] = .{ result[@intFromEnum(Feature.precise_memory)] = .{
.llvm_name = "precise-memory", .llvm_name = "precise-memory",
.description = "Enable precise memory mode", .description = "Enable precise memory mode",
@ -1206,6 +1282,11 @@ pub const all_features = blk: {
.description = "Use true 16-bit registers", .description = "Use true 16-bit registers",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.relaxed_buffer_oob_mode)] = .{
.llvm_name = "relaxed-buffer-oob-mode",
.description = "Disable strict out-of-bounds buffer guarantees. An OOB access may potentially cause an adjacent access to be treated as if it were also OOB",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.required_export_priority)] = .{ result[@intFromEnum(Feature.required_export_priority)] = .{
.llvm_name = "required-export-priority", .llvm_name = "required-export-priority",
.description = "Export priority must be explicitly manipulated on GFX11.5", .description = "Export priority must be explicitly manipulated on GFX11.5",
@ -1231,6 +1312,11 @@ pub const all_features = blk: {
.description = "Has s_memtime instruction", .description = "Has s_memtime instruction",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.safe_smem_prefetch)] = .{
.llvm_name = "safe-smem-prefetch",
.description = "SMEM prefetches do not fail on illegal address",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.salu_float)] = .{ result[@intFromEnum(Feature.salu_float)] = .{
.llvm_name = "salu-float", .llvm_name = "salu-float",
.description = "Has SALU floating point instructions", .description = "Has SALU floating point instructions",
@ -1315,6 +1401,11 @@ pub const all_features = blk: {
.wavefrontsize64, .wavefrontsize64,
}), }),
}; };
result[@intFromEnum(Feature.setprio_inc_wg_inst)] = .{
.llvm_name = "setprio-inc-wg-inst",
.description = "Has s_setprio_inc_wg instruction.",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sgpr_init_bug)] = .{ result[@intFromEnum(Feature.sgpr_init_bug)] = .{
.llvm_name = "sgpr-init-bug", .llvm_name = "sgpr-init-bug",
.description = "VI SGPR initialization bug requiring a fixed SGPR allocation size", .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
@ -1379,6 +1470,11 @@ pub const all_features = blk: {
.description = "Enable threadgroup split execution", .description = "Enable threadgroup split execution",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.transpose_load_f4f6_insts)] = .{
.llvm_name = "transpose-load-f4f6-insts",
.description = "Has ds_load_tr4/tr6 and global_load_tr4/tr6 instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.trap_handler)] = .{ result[@intFromEnum(Feature.trap_handler)] = .{
.llvm_name = "trap-handler", .llvm_name = "trap-handler",
.description = "Trap handler support", .description = "Trap handler support",
@ -1449,6 +1545,11 @@ pub const all_features = blk: {
.description = "Has VGPR mode register indexing", .description = "Has VGPR mode register indexing",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.vmem_to_lds_load_insts)] = .{
.llvm_name = "vmem-to-lds-load-insts",
.description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_load w/lds bit set or global_load_lds. This does not include scratch_load_lds.",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.vmem_to_scalar_write_hazard)] = .{ result[@intFromEnum(Feature.vmem_to_scalar_write_hazard)] = .{
.llvm_name = "vmem-to-scalar-write-hazard", .llvm_name = "vmem-to-scalar-write-hazard",
.description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
@ -1517,6 +1618,11 @@ pub const all_features = blk: {
.description = "Has separate store vscnt counter", .description = "Has separate store vscnt counter",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.wait_xcnt)] = .{
.llvm_name = "wait-xcnt",
.description = "Has s_wait_xcnt instruction",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.wavefrontsize16)] = .{ result[@intFromEnum(Feature.wavefrontsize16)] = .{
.llvm_name = "wavefrontsize16", .llvm_name = "wavefrontsize16",
.description = "The number of threads per wavefront", .description = "The number of threads per wavefront",
@ -1588,18 +1694,13 @@ pub const cpu = struct {
pub const generic: CpuModel = .{ pub const generic: CpuModel = .{
.name = "generic", .name = "generic",
.llvm_name = "generic", .llvm_name = "generic",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{}),
.gds,
.gws,
}),
}; };
pub const generic_hsa: CpuModel = .{ pub const generic_hsa: CpuModel = .{
.name = "generic_hsa", .name = "generic_hsa",
.llvm_name = "generic-hsa", .llvm_name = "generic-hsa",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.flat_address_space, .flat_address_space,
.gds,
.gws,
}), }),
}; };
pub const gfx1010: CpuModel = .{ pub const gfx1010: CpuModel = .{
@ -1961,6 +2062,7 @@ pub const cpu = struct {
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.priv_enabled_trap2_nop_bug, .priv_enabled_trap2_nop_bug,
.real_true16,
.shader_cycles_register, .shader_cycles_register,
.user_sgpr_init16_bug, .user_sgpr_init16_bug,
.valu_trans_use_hazard, .valu_trans_use_hazard,
@ -1993,6 +2095,7 @@ pub const cpu = struct {
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.priv_enabled_trap2_nop_bug, .priv_enabled_trap2_nop_bug,
.real_true16,
.shader_cycles_register, .shader_cycles_register,
.valu_trans_use_hazard, .valu_trans_use_hazard,
.vcmpx_permlane_hazard, .vcmpx_permlane_hazard,
@ -2023,6 +2126,7 @@ pub const cpu = struct {
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.priv_enabled_trap2_nop_bug, .priv_enabled_trap2_nop_bug,
.real_true16,
.shader_cycles_register, .shader_cycles_register,
.user_sgpr_init16_bug, .user_sgpr_init16_bug,
.valu_trans_use_hazard, .valu_trans_use_hazard,
@ -2054,6 +2158,7 @@ pub const cpu = struct {
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.priv_enabled_trap2_nop_bug, .priv_enabled_trap2_nop_bug,
.real_true16,
.shader_cycles_register, .shader_cycles_register,
.valu_trans_use_hazard, .valu_trans_use_hazard,
.vcmpx_permlane_hazard, .vcmpx_permlane_hazard,
@ -2082,6 +2187,7 @@ pub const cpu = struct {
.nsa_encoding, .nsa_encoding,
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.point_sample_accel,
.required_export_priority, .required_export_priority,
.salu_float, .salu_float,
.shader_cycles_register, .shader_cycles_register,
@ -2112,6 +2218,7 @@ pub const cpu = struct {
.nsa_encoding, .nsa_encoding,
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.point_sample_accel,
.required_export_priority, .required_export_priority,
.salu_float, .salu_float,
.shader_cycles_register, .shader_cycles_register,
@ -2141,6 +2248,7 @@ pub const cpu = struct {
.nsa_encoding, .nsa_encoding,
.packed_tid, .packed_tid,
.partial_nsa_encoding, .partial_nsa_encoding,
.point_sample_accel,
.required_export_priority, .required_export_priority,
.salu_float, .salu_float,
.shader_cycles_register, .shader_cycles_register,
@ -2223,6 +2331,7 @@ pub const cpu = struct {
.atomic_fadd_rtn_insts, .atomic_fadd_rtn_insts,
.atomic_flat_pk_add_16_insts, .atomic_flat_pk_add_16_insts,
.atomic_global_pk_add_bf16_inst, .atomic_global_pk_add_bf16_inst,
.bvh_dual_bvh_8_insts,
.dl_insts, .dl_insts,
.dot10_insts, .dot10_insts,
.dot11_insts, .dot11_insts,
@ -2263,6 +2372,7 @@ pub const cpu = struct {
.atomic_fadd_rtn_insts, .atomic_fadd_rtn_insts,
.atomic_flat_pk_add_16_insts, .atomic_flat_pk_add_16_insts,
.atomic_global_pk_add_bf16_inst, .atomic_global_pk_add_bf16_inst,
.bvh_dual_bvh_8_insts,
.dl_insts, .dl_insts,
.dot10_insts, .dot10_insts,
.dot11_insts, .dot11_insts,
@ -2289,6 +2399,63 @@ pub const cpu = struct {
.vcmpx_permlane_hazard, .vcmpx_permlane_hazard,
}), }),
}; };
pub const gfx1250: CpuModel = .{
.name = "gfx1250",
.llvm_name = "gfx1250",
.features = featureSet(&[_]Feature{
.@"64_bit_literals",
.architected_flat_scratch,
.architected_sgprs,
.ashr_pk_insts,
.atomic_buffer_global_pk_add_f16_insts,
.atomic_buffer_pk_add_bf16_inst,
.atomic_ds_pk_add_16_insts,
.atomic_fadd_no_rtn_insts,
.atomic_fadd_rtn_insts,
.atomic_flat_pk_add_16_insts,
.atomic_fmin_fmax_flat_f64,
.atomic_fmin_fmax_global_f64,
.atomic_global_pk_add_bf16_inst,
.bf16_cvt_insts,
.bf16_trans_insts,
.bitop3_insts,
.cumode,
.cvt_pk_f16_f32_inst,
.dl_insts,
.dot7_insts,
.dot8_insts,
.dpp_src1_sgpr,
.flat_atomic_fadd_f32_inst,
.flat_buffer_global_fadd_f64_inst,
.fmacf64_inst,
.fp8_conversion_insts,
.fp8e5m3_insts,
.gfx12,
.gfx1250_insts,
.kernarg_preload,
.lds_barrier_arrive_atomic,
.ldsbankcount32,
.lshl_add_u64_inst,
.max_hard_clause_length_63,
.memory_atomic_fadd_f32_denormal_support,
.minimum3_maximum3_pkf16,
.packed_fp32_ops,
.packed_tid,
.permlane16_swap,
.prng_inst,
.pseudo_scalar_trans,
.restricted_soffset,
.salu_float,
.scalar_dwordx3_loads,
.setprio_inc_wg_inst,
.shader_cycles_hi_lo_registers,
.sramecc_support,
.transpose_load_f4f6_insts,
.vcmpx_permlane_hazard,
.wait_xcnt,
.wavefrontsize32,
}),
};
pub const gfx12_generic: CpuModel = .{ pub const gfx12_generic: CpuModel = .{
.name = "gfx12_generic", .name = "gfx12_generic",
.llvm_name = "gfx12-generic", .llvm_name = "gfx12-generic",
@ -2303,6 +2470,7 @@ pub const cpu = struct {
.atomic_fadd_rtn_insts, .atomic_fadd_rtn_insts,
.atomic_flat_pk_add_16_insts, .atomic_flat_pk_add_16_insts,
.atomic_global_pk_add_bf16_inst, .atomic_global_pk_add_bf16_inst,
.bvh_dual_bvh_8_insts,
.dl_insts, .dl_insts,
.dot10_insts, .dot10_insts,
.dot11_insts, .dot11_insts,
@ -2629,102 +2797,6 @@ pub const cpu = struct {
.mad_mix_insts, .mad_mix_insts,
}), }),
}; };
pub const gfx940: CpuModel = .{
.name = "gfx940",
.llvm_name = "gfx940",
.features = featureSet(&[_]Feature{
.addressablelocalmemorysize65536,
.agent_scope_fine_grained_remote_memory_atomics,
.architected_flat_scratch,
.atomic_buffer_global_pk_add_f16_insts,
.atomic_ds_pk_add_16_insts,
.atomic_fadd_no_rtn_insts,
.atomic_fadd_rtn_insts,
.atomic_flat_pk_add_16_insts,
.atomic_fmin_fmax_flat_f64,
.atomic_fmin_fmax_global_f64,
.atomic_global_pk_add_bf16_inst,
.back_off_barrier,
.cvt_fp8_vop1_bug,
.dl_insts,
.dot10_insts,
.dot1_insts,
.dot2_insts,
.dot3_insts,
.dot4_insts,
.dot5_insts,
.dot6_insts,
.dot7_insts,
.dpp_64bit,
.flat_atomic_fadd_f32_inst,
.flat_buffer_global_fadd_f64_inst,
.fma_mix_insts,
.fmacf64_inst,
.force_store_sc0_sc1,
.fp8_insts,
.full_rate_64_ops,
.gfx9,
.gfx90a_insts,
.gfx940_insts,
.kernarg_preload,
.ldsbankcount32,
.mai_insts,
.memory_atomic_fadd_f32_denormal_support,
.packed_fp32_ops,
.packed_tid,
.pk_fmac_f16_inst,
.sramecc_support,
.xf32_insts,
}),
};
pub const gfx941: CpuModel = .{
.name = "gfx941",
.llvm_name = "gfx941",
.features = featureSet(&[_]Feature{
.addressablelocalmemorysize65536,
.agent_scope_fine_grained_remote_memory_atomics,
.architected_flat_scratch,
.atomic_buffer_global_pk_add_f16_insts,
.atomic_ds_pk_add_16_insts,
.atomic_fadd_no_rtn_insts,
.atomic_fadd_rtn_insts,
.atomic_flat_pk_add_16_insts,
.atomic_fmin_fmax_flat_f64,
.atomic_fmin_fmax_global_f64,
.atomic_global_pk_add_bf16_inst,
.back_off_barrier,
.cvt_fp8_vop1_bug,
.dl_insts,
.dot10_insts,
.dot1_insts,
.dot2_insts,
.dot3_insts,
.dot4_insts,
.dot5_insts,
.dot6_insts,
.dot7_insts,
.dpp_64bit,
.flat_atomic_fadd_f32_inst,
.flat_buffer_global_fadd_f64_inst,
.fma_mix_insts,
.fmacf64_inst,
.force_store_sc0_sc1,
.fp8_insts,
.full_rate_64_ops,
.gfx9,
.gfx90a_insts,
.gfx940_insts,
.kernarg_preload,
.ldsbankcount32,
.mai_insts,
.memory_atomic_fadd_f32_denormal_support,
.packed_fp32_ops,
.packed_tid,
.pk_fmac_f16_inst,
.sramecc_support,
.xf32_insts,
}),
};
pub const gfx942: CpuModel = .{ pub const gfx942: CpuModel = .{
.name = "gfx942", .name = "gfx942",
.llvm_name = "gfx942", .llvm_name = "gfx942",
@ -2763,6 +2835,7 @@ pub const cpu = struct {
.gfx940_insts, .gfx940_insts,
.kernarg_preload, .kernarg_preload,
.ldsbankcount32, .ldsbankcount32,
.lshl_add_u64_inst,
.mai_insts, .mai_insts,
.memory_atomic_fadd_f32_denormal_support, .memory_atomic_fadd_f32_denormal_support,
.packed_fp32_ops, .packed_fp32_ops,
@ -2816,6 +2889,7 @@ pub const cpu = struct {
.gfx950_insts, .gfx950_insts,
.kernarg_preload, .kernarg_preload,
.ldsbankcount32, .ldsbankcount32,
.lshl_add_u64_inst,
.mai_insts, .mai_insts,
.memory_atomic_fadd_f32_denormal_support, .memory_atomic_fadd_f32_denormal_support,
.packed_fp32_ops, .packed_fp32_ops,
@ -2861,6 +2935,7 @@ pub const cpu = struct {
.gfx940_insts, .gfx940_insts,
.kernarg_preload, .kernarg_preload,
.ldsbankcount32, .ldsbankcount32,
.lshl_add_u64_inst,
.mai_insts, .mai_insts,
.memory_atomic_fadd_f32_denormal_support, .memory_atomic_fadd_f32_denormal_support,
.packed_fp32_ops, .packed_fp32_ops,

1
lib/std/Target/arm.zig
View File

@ -2646,6 +2646,7 @@ pub const cpu = struct {
.name = "star_mc1", .name = "star_mc1",
.llvm_name = "star-mc1", .llvm_name = "star-mc1",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.avoid_muls,
.dsp, .dsp,
.fix_cmse_cve_2021_35465, .fix_cmse_cve_2021_35465,
.fp_armv8d16sp, .fp_armv8d16sp,

497
lib/std/Target/avr.zig
View File

@ -40,7 +40,9 @@ pub const Feature = enum {
tinyencoding, tinyencoding,
wrappingrjmp, wrappingrjmp,
xmega, xmega,
xmega2,
xmega3, xmega3,
xmega4,
xmegau, xmegau,
}; };
@ -318,6 +320,25 @@ pub const all_features = blk: {
.sram, .sram,
}), }),
}; };
result[@intFromEnum(Feature.xmega2)] = .{
.llvm_name = "xmega2",
.description = "The device is a part of the xmega2 family",
.dependencies = featureSet(&[_]Feature{
.addsubiw,
.avr0,
.@"break",
.ijmpcall,
.jmpcall,
.lowbytefirst,
.lpm,
.lpmx,
.movw,
.mul,
.spm,
.spmx,
.sram,
}),
};
result[@intFromEnum(Feature.xmega3)] = .{ result[@intFromEnum(Feature.xmega3)] = .{
.llvm_name = "xmega3", .llvm_name = "xmega3",
.description = "The device is a part of the xmega3 family", .description = "The device is a part of the xmega3 family",
@ -335,6 +356,27 @@ pub const all_features = blk: {
.sram, .sram,
}), }),
}; };
result[@intFromEnum(Feature.xmega4)] = .{
.llvm_name = "xmega4",
.description = "The device is a part of the xmega4 family",
.dependencies = featureSet(&[_]Feature{
.addsubiw,
.avr0,
.@"break",
.elpm,
.elpmx,
.ijmpcall,
.jmpcall,
.lowbytefirst,
.lpm,
.lpmx,
.movw,
.mul,
.spm,
.spmx,
.sram,
}),
};
result[@intFromEnum(Feature.xmegau)] = .{ result[@intFromEnum(Feature.xmegau)] = .{
.llvm_name = "xmegau", .llvm_name = "xmegau",
.description = "The device is a part of the xmegau family", .description = "The device is a part of the xmegau family",
@ -1927,6 +1969,27 @@ pub const cpu = struct {
.xmega3, .xmega3,
}), }),
}; };
pub const attiny3224: CpuModel = .{
.name = "attiny3224",
.llvm_name = "attiny3224",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const attiny3226: CpuModel = .{
.name = "attiny3226",
.llvm_name = "attiny3226",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const attiny3227: CpuModel = .{
.name = "attiny3227",
.llvm_name = "attiny3227",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const attiny4: CpuModel = .{ pub const attiny4: CpuModel = .{
.name = "attiny4", .name = "attiny4",
.llvm_name = "attiny4", .llvm_name = "attiny4",
@ -2503,6 +2566,160 @@ pub const cpu = struct {
.avr1, .avr1,
}), }),
}; };
pub const avr128da28: CpuModel = .{
.name = "avr128da28",
.llvm_name = "avr128da28",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128da32: CpuModel = .{
.name = "avr128da32",
.llvm_name = "avr128da32",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128da48: CpuModel = .{
.name = "avr128da48",
.llvm_name = "avr128da48",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128da64: CpuModel = .{
.name = "avr128da64",
.llvm_name = "avr128da64",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128db28: CpuModel = .{
.name = "avr128db28",
.llvm_name = "avr128db28",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128db32: CpuModel = .{
.name = "avr128db32",
.llvm_name = "avr128db32",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128db48: CpuModel = .{
.name = "avr128db48",
.llvm_name = "avr128db48",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr128db64: CpuModel = .{
.name = "avr128db64",
.llvm_name = "avr128db64",
.features = featureSet(&[_]Feature{
.xmega4,
}),
};
pub const avr16dd20: CpuModel = .{
.name = "avr16dd20",
.llvm_name = "avr16dd20",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16dd28: CpuModel = .{
.name = "avr16dd28",
.llvm_name = "avr16dd28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16dd32: CpuModel = .{
.name = "avr16dd32",
.llvm_name = "avr16dd32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16du14: CpuModel = .{
.name = "avr16du14",
.llvm_name = "avr16du14",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16du20: CpuModel = .{
.name = "avr16du20",
.llvm_name = "avr16du20",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16du28: CpuModel = .{
.name = "avr16du28",
.llvm_name = "avr16du28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16du32: CpuModel = .{
.name = "avr16du32",
.llvm_name = "avr16du32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16ea28: CpuModel = .{
.name = "avr16ea28",
.llvm_name = "avr16ea28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16ea32: CpuModel = .{
.name = "avr16ea32",
.llvm_name = "avr16ea32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16ea48: CpuModel = .{
.name = "avr16ea48",
.llvm_name = "avr16ea48",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16eb14: CpuModel = .{
.name = "avr16eb14",
.llvm_name = "avr16eb14",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16eb20: CpuModel = .{
.name = "avr16eb20",
.llvm_name = "avr16eb20",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16eb28: CpuModel = .{
.name = "avr16eb28",
.llvm_name = "avr16eb28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr16eb32: CpuModel = .{
.name = "avr16eb32",
.llvm_name = "avr16eb32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr2: CpuModel = .{ pub const avr2: CpuModel = .{
.name = "avr2", .name = "avr2",
.llvm_name = "avr2", .llvm_name = "avr2",
@ -2531,6 +2748,146 @@ pub const cpu = struct {
.avr31, .avr31,
}), }),
}; };
pub const avr32da28: CpuModel = .{
.name = "avr32da28",
.llvm_name = "avr32da28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32da32: CpuModel = .{
.name = "avr32da32",
.llvm_name = "avr32da32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32da48: CpuModel = .{
.name = "avr32da48",
.llvm_name = "avr32da48",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32db28: CpuModel = .{
.name = "avr32db28",
.llvm_name = "avr32db28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32db32: CpuModel = .{
.name = "avr32db32",
.llvm_name = "avr32db32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32db48: CpuModel = .{
.name = "avr32db48",
.llvm_name = "avr32db48",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32dd14: CpuModel = .{
.name = "avr32dd14",
.llvm_name = "avr32dd14",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32dd20: CpuModel = .{
.name = "avr32dd20",
.llvm_name = "avr32dd20",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32dd28: CpuModel = .{
.name = "avr32dd28",
.llvm_name = "avr32dd28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32dd32: CpuModel = .{
.name = "avr32dd32",
.llvm_name = "avr32dd32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32du14: CpuModel = .{
.name = "avr32du14",
.llvm_name = "avr32du14",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32du20: CpuModel = .{
.name = "avr32du20",
.llvm_name = "avr32du20",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32du28: CpuModel = .{
.name = "avr32du28",
.llvm_name = "avr32du28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32du32: CpuModel = .{
.name = "avr32du32",
.llvm_name = "avr32du32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32ea28: CpuModel = .{
.name = "avr32ea28",
.llvm_name = "avr32ea28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32ea32: CpuModel = .{
.name = "avr32ea32",
.llvm_name = "avr32ea32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32ea48: CpuModel = .{
.name = "avr32ea48",
.llvm_name = "avr32ea48",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32sd20: CpuModel = .{
.name = "avr32sd20",
.llvm_name = "avr32sd20",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32sd28: CpuModel = .{
.name = "avr32sd28",
.llvm_name = "avr32sd28",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr32sd32: CpuModel = .{
.name = "avr32sd32",
.llvm_name = "avr32sd32",
.features = featureSet(&[_]Feature{
.xmega3,
}),
};
pub const avr35: CpuModel = .{ pub const avr35: CpuModel = .{
.name = "avr35", .name = "avr35",
.llvm_name = "avr35", .llvm_name = "avr35",
@ -2566,6 +2923,146 @@ pub const cpu = struct {
.avr6, .avr6,
}), }),
}; };
pub const avr64da28: CpuModel = .{
.name = "avr64da28",
.llvm_name = "avr64da28",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64da32: CpuModel = .{
.name = "avr64da32",
.llvm_name = "avr64da32",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64da48: CpuModel = .{
.name = "avr64da48",
.llvm_name = "avr64da48",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64da64: CpuModel = .{
.name = "avr64da64",
.llvm_name = "avr64da64",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64db28: CpuModel = .{
.name = "avr64db28",
.llvm_name = "avr64db28",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64db32: CpuModel = .{
.name = "avr64db32",
.llvm_name = "avr64db32",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64db48: CpuModel = .{
.name = "avr64db48",
.llvm_name = "avr64db48",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64db64: CpuModel = .{
.name = "avr64db64",
.llvm_name = "avr64db64",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64dd14: CpuModel = .{
.name = "avr64dd14",
.llvm_name = "avr64dd14",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64dd20: CpuModel = .{
.name = "avr64dd20",
.llvm_name = "avr64dd20",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64dd28: CpuModel = .{
.name = "avr64dd28",
.llvm_name = "avr64dd28",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64dd32: CpuModel = .{
.name = "avr64dd32",
.llvm_name = "avr64dd32",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64du28: CpuModel = .{
.name = "avr64du28",
.llvm_name = "avr64du28",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64du32: CpuModel = .{
.name = "avr64du32",
.llvm_name = "avr64du32",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64ea28: CpuModel = .{
.name = "avr64ea28",
.llvm_name = "avr64ea28",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64ea32: CpuModel = .{
.name = "avr64ea32",
.llvm_name = "avr64ea32",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64ea48: CpuModel = .{
.name = "avr64ea48",
.llvm_name = "avr64ea48",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64sd28: CpuModel = .{
.name = "avr64sd28",
.llvm_name = "avr64sd28",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64sd32: CpuModel = .{
.name = "avr64sd32",
.llvm_name = "avr64sd32",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avr64sd48: CpuModel = .{
.name = "avr64sd48",
.llvm_name = "avr64sd48",
.features = featureSet(&[_]Feature{
.xmega2,
}),
};
pub const avrtiny: CpuModel = .{ pub const avrtiny: CpuModel = .{
.name = "avrtiny", .name = "avrtiny",
.llvm_name = "avrtiny", .llvm_name = "avrtiny",

18
lib/std/Target/loongarch.zig
View File

@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum { pub const Feature = enum {
@"32bit", @"32bit",
@"32s",
@"64bit", @"64bit",
d, d,
div32, div32,
@ -41,10 +42,17 @@ pub const all_features = blk: {
.description = "LA32 Basic Integer and Privilege Instruction Set", .description = "LA32 Basic Integer and Privilege Instruction Set",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.@"32s")] = .{
.llvm_name = "32s",
.description = "LA32 Standard Basic Instruction Extension",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.@"64bit")] = .{ result[@intFromEnum(Feature.@"64bit")] = .{
.llvm_name = "64bit", .llvm_name = "64bit",
.description = "LA64 Basic Integer and Privilege Instruction Set", .description = "LA64 Basic Integer and Privilege Instruction Set",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{
.@"32s",
}),
}; };
result[@intFromEnum(Feature.d)] = .{ result[@intFromEnum(Feature.d)] = .{
.llvm_name = "d", .llvm_name = "d",
@ -65,7 +73,7 @@ pub const all_features = blk: {
}; };
result[@intFromEnum(Feature.frecipe)] = .{ result[@intFromEnum(Feature.frecipe)] = .{
.llvm_name = "frecipe", .llvm_name = "frecipe",
.description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions.", .description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.la_global_with_abs)] = .{ result[@intFromEnum(Feature.la_global_with_abs)] = .{
@ -85,12 +93,12 @@ pub const all_features = blk: {
}; };
result[@intFromEnum(Feature.lam_bh)] = .{ result[@intFromEnum(Feature.lam_bh)] = .{
.llvm_name = "lam-bh", .llvm_name = "lam-bh",
.description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions.", .description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.lamcas)] = .{ result[@intFromEnum(Feature.lamcas)] = .{
.llvm_name = "lamcas", .llvm_name = "lamcas",
.description = "Support amcas[_db].{b/h/w/d}.", .description = "Support amcas[_db].{b/h/w/d}",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.lasx)] = .{ result[@intFromEnum(Feature.lasx)] = .{
@ -107,7 +115,7 @@ pub const all_features = blk: {
}; };
result[@intFromEnum(Feature.ld_seq_sa)] = .{ result[@intFromEnum(Feature.ld_seq_sa)] = .{
.llvm_name = "ld-seq-sa", .llvm_name = "ld-seq-sa",
.description = "Don't use load-load barrier (dbar 0x700).", .description = "Don't use a same-address load-load barrier (dbar 0x700)",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.lsx)] = .{ result[@intFromEnum(Feature.lsx)] = .{

32
lib/std/Target/mips.zig
View File

@ -17,6 +17,8 @@ pub const Feature = enum {
fpxx, fpxx,
ginv, ginv,
gp64, gp64,
i6400,
i6500,
long_calls, long_calls,
micromips, micromips,
mips1, mips1,
@ -137,6 +139,22 @@ pub const all_features = blk: {
.description = "General Purpose Registers are 64-bit wide", .description = "General Purpose Registers are 64-bit wide",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.i6400)] = .{
.llvm_name = "i6400",
.description = "MIPS I6400 Processor",
.dependencies = featureSet(&[_]Feature{
.mips64r6,
.msa,
}),
};
result[@intFromEnum(Feature.i6500)] = .{
.llvm_name = "i6500",
.description = "MIPS I6500 Processor",
.dependencies = featureSet(&[_]Feature{
.mips64r6,
.msa,
}),
};
result[@intFromEnum(Feature.long_calls)] = .{ result[@intFromEnum(Feature.long_calls)] = .{
.llvm_name = "long-calls", .llvm_name = "long-calls",
.description = "Disable use of the jal instruction", .description = "Disable use of the jal instruction",
@ -408,6 +426,20 @@ pub const cpu = struct {
.mips32, .mips32,
}), }),
}; };
pub const @"i6400": CpuModel = .{
.name = "i6400",
.llvm_name = "i6400",
.features = featureSet(&[_]Feature{
.i6400,
}),
};
pub const @"i6500": CpuModel = .{
.name = "i6500",
.llvm_name = "i6500",
.features = featureSet(&[_]Feature{
.i6500,
}),
};
pub const mips1: CpuModel = .{ pub const mips1: CpuModel = .{
.name = "mips1", .name = "mips1",
.llvm_name = "mips1", .llvm_name = "mips1",

132
lib/std/Target/nvptx.zig
View File

@ -34,12 +34,22 @@ pub const Feature = enum {
ptx85, ptx85,
ptx86, ptx86,
ptx87, ptx87,
ptx88,
sm_100, sm_100,
sm_100a, sm_100a,
sm_100f,
sm_101, sm_101,
sm_101a, sm_101a,
sm_101f,
sm_103,
sm_103a,
sm_103f,
sm_120, sm_120,
sm_120a, sm_120a,
sm_120f,
sm_121,
sm_121a,
sm_121f,
sm_20, sm_20,
sm_21, sm_21,
sm_30, sm_30,
@ -217,6 +227,11 @@ pub const all_features = blk: {
.description = "Use PTX version 87", .description = "Use PTX version 87",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.ptx88)] = .{
.llvm_name = "ptx88",
.description = "Use PTX version 88",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_100)] = .{ result[@intFromEnum(Feature.sm_100)] = .{
.llvm_name = "sm_100", .llvm_name = "sm_100",
.description = "Target SM 100", .description = "Target SM 100",
@ -227,6 +242,11 @@ pub const all_features = blk: {
.description = "Target SM 100a", .description = "Target SM 100a",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.sm_100f)] = .{
.llvm_name = "sm_100f",
.description = "Target SM 100f",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_101)] = .{ result[@intFromEnum(Feature.sm_101)] = .{
.llvm_name = "sm_101", .llvm_name = "sm_101",
.description = "Target SM 101", .description = "Target SM 101",
@ -237,6 +257,26 @@ pub const all_features = blk: {
.description = "Target SM 101a", .description = "Target SM 101a",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.sm_101f)] = .{
.llvm_name = "sm_101f",
.description = "Target SM 101f",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_103)] = .{
.llvm_name = "sm_103",
.description = "Target SM 103",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_103a)] = .{
.llvm_name = "sm_103a",
.description = "Target SM 103a",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_103f)] = .{
.llvm_name = "sm_103f",
.description = "Target SM 103f",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_120)] = .{ result[@intFromEnum(Feature.sm_120)] = .{
.llvm_name = "sm_120", .llvm_name = "sm_120",
.description = "Target SM 120", .description = "Target SM 120",
@ -247,6 +287,26 @@ pub const all_features = blk: {
.description = "Target SM 120a", .description = "Target SM 120a",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.sm_120f)] = .{
.llvm_name = "sm_120f",
.description = "Target SM 120f",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_121)] = .{
.llvm_name = "sm_121",
.description = "Target SM 121",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_121a)] = .{
.llvm_name = "sm_121a",
.description = "Target SM 121a",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_121f)] = .{
.llvm_name = "sm_121f",
.description = "Target SM 121f",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sm_20)] = .{ result[@intFromEnum(Feature.sm_20)] = .{
.llvm_name = "sm_20", .llvm_name = "sm_20",
.description = "Target SM 20", .description = "Target SM 20",
@ -377,6 +437,14 @@ pub const cpu = struct {
.sm_100a, .sm_100a,
}), }),
}; };
pub const sm_100f: CpuModel = .{
.name = "sm_100f",
.llvm_name = "sm_100f",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_100f,
}),
};
pub const sm_101: CpuModel = .{ pub const sm_101: CpuModel = .{
.name = "sm_101", .name = "sm_101",
.llvm_name = "sm_101", .llvm_name = "sm_101",
@ -393,6 +461,38 @@ pub const cpu = struct {
.sm_101a, .sm_101a,
}), }),
}; };
pub const sm_101f: CpuModel = .{
.name = "sm_101f",
.llvm_name = "sm_101f",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_101f,
}),
};
pub const sm_103: CpuModel = .{
.name = "sm_103",
.llvm_name = "sm_103",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_103,
}),
};
pub const sm_103a: CpuModel = .{
.name = "sm_103a",
.llvm_name = "sm_103a",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_103a,
}),
};
pub const sm_103f: CpuModel = .{
.name = "sm_103f",
.llvm_name = "sm_103f",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_103f,
}),
};
pub const sm_120: CpuModel = .{ pub const sm_120: CpuModel = .{
.name = "sm_120", .name = "sm_120",
.llvm_name = "sm_120", .llvm_name = "sm_120",
@ -409,6 +509,38 @@ pub const cpu = struct {
.sm_120a, .sm_120a,
}), }),
}; };
pub const sm_120f: CpuModel = .{
.name = "sm_120f",
.llvm_name = "sm_120f",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_120f,
}),
};
pub const sm_121: CpuModel = .{
.name = "sm_121",
.llvm_name = "sm_121",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_121,
}),
};
pub const sm_121a: CpuModel = .{
.name = "sm_121a",
.llvm_name = "sm_121a",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_121a,
}),
};
pub const sm_121f: CpuModel = .{
.name = "sm_121f",
.llvm_name = "sm_121f",
.features = featureSet(&[_]Feature{
.ptx88,
.sm_121f,
}),
};
pub const sm_20: CpuModel = .{ pub const sm_20: CpuModel = .{
.name = "sm_20", .name = "sm_20",
.llvm_name = "sm_20", .llvm_name = "sm_20",

3
lib/std/Target/powerpc.zig
View File

@ -825,7 +825,6 @@ pub const cpu = struct {
.fuse_logical_add, .fuse_logical_add,
.fuse_sha3, .fuse_sha3,
.fuse_store, .fuse_store,
.htm,
.icbt, .icbt,
.isa_future_instructions, .isa_future_instructions,
.isa_v206_instructions, .isa_v206_instructions,
@ -980,7 +979,6 @@ pub const cpu = struct {
.fuse_logical_add, .fuse_logical_add,
.fuse_sha3, .fuse_sha3,
.fuse_store, .fuse_store,
.htm,
.icbt, .icbt,
.isa_v206_instructions, .isa_v206_instructions,
.isel, .isel,
@ -1028,7 +1026,6 @@ pub const cpu = struct {
.fuse_logical_add, .fuse_logical_add,
.fuse_sha3, .fuse_sha3,
.fuse_store, .fuse_store,
.htm,
.icbt, .icbt,
.isa_v206_instructions, .isa_v206_instructions,
.isel, .isel,

704
lib/std/Target/riscv.zig
View File

File diff suppressed because it is too large Load Diff

52
lib/std/Target/s390x.zig
View File

@ -731,6 +731,58 @@ pub const cpu = struct {
.vector_packed_decimal_enhancement_2, .vector_packed_decimal_enhancement_2,
}), }),
}; };
pub const z17: CpuModel = .{
.name = "z17",
.llvm_name = "z17",
.features = featureSet(&[_]Feature{
.bear_enhancement,
.concurrent_functions,
.deflate_conversion,
.dfp_packed_conversion,
.dfp_zoned_conversion,
.distinct_ops,
.enhanced_dat_2,
.enhanced_sort,
.execution_hint,
.fast_serialization,
.fp_extension,
.guarded_storage,
.high_word,
.insert_reference_bits_multiple,
.interlocked_access1,
.load_and_trap,
.load_and_zero_rightmost_byte,
.load_store_on_cond,
.load_store_on_cond_2,
.message_security_assist_extension12,
.message_security_assist_extension3,
.message_security_assist_extension4,
.message_security_assist_extension5,
.message_security_assist_extension7,
.message_security_assist_extension8,
.message_security_assist_extension9,
.miscellaneous_extensions,
.miscellaneous_extensions_2,
.miscellaneous_extensions_3,
.miscellaneous_extensions_4,
.nnp_assist,
.population_count,
.processor_activity_instrumentation,
.processor_assist,
.reset_dat_protection,
.reset_reference_bits_multiple,
.test_pending_external_interruption,
.transactional_execution,
.vector,
.vector_enhancements_1,
.vector_enhancements_2,
.vector_enhancements_3,
.vector_packed_decimal,
.vector_packed_decimal_enhancement,
.vector_packed_decimal_enhancement_2,
.vector_packed_decimal_enhancement_3,
}),
};
pub const z196: CpuModel = .{ pub const z196: CpuModel = .{
.name = "z196", .name = "z196",
.llvm_name = "z196", .llvm_name = "z196",

69
lib/std/Target/sparc.zig
View File

@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model; const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum { pub const Feature = enum {
crypto,
deprecated_v8, deprecated_v8,
detectroundchange, detectroundchange,
fix_tn0009, fix_tn0009,
@ -22,6 +23,7 @@ pub const Feature = enum {
leonpwrpsr, leonpwrpsr,
no_fmuls, no_fmuls,
no_fsmuld, no_fsmuld,
osa2011,
popc, popc,
reserve_g1, reserve_g1,
reserve_g2, reserve_g2,
@ -53,6 +55,8 @@ pub const Feature = enum {
slow_rdpc, slow_rdpc,
soft_float, soft_float,
soft_mul_div, soft_mul_div,
ua2005,
ua2007,
v8plus, v8plus,
v9, v9,
vis, vis,
@ -69,6 +73,13 @@ pub const all_features = blk: {
const len = @typeInfo(Feature).@"enum".fields.len; const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count); std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined; var result: [len]CpuFeature = undefined;
result[@intFromEnum(Feature.crypto)] = .{
.llvm_name = "crypto",
.description = "Enable cryptographic extensions",
.dependencies = featureSet(&[_]Feature{
.osa2011,
}),
};
result[@intFromEnum(Feature.deprecated_v8)] = .{ result[@intFromEnum(Feature.deprecated_v8)] = .{
.llvm_name = "deprecated-v8", .llvm_name = "deprecated-v8",
.description = "Enable deprecated V8 instructions in V9 mode", .description = "Enable deprecated V8 instructions in V9 mode",
@ -154,6 +165,15 @@ pub const all_features = blk: {
.description = "Disable the fsmuld instruction.", .description = "Disable the fsmuld instruction.",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.osa2011)] = .{
.llvm_name = "osa2011",
.description = "Enable Oracle SPARC Architecture 2011 extensions",
.dependencies = featureSet(&[_]Feature{
.vis,
.vis2,
.vis3,
}),
};
result[@intFromEnum(Feature.popc)] = .{ result[@intFromEnum(Feature.popc)] = .{
.llvm_name = "popc", .llvm_name = "popc",
.description = "Use the popc (population count) instruction", .description = "Use the popc (population count) instruction",
@ -311,6 +331,22 @@ pub const all_features = blk: {
.description = "Use software emulation for integer multiply and divide", .description = "Use software emulation for integer multiply and divide",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.ua2005)] = .{
.llvm_name = "ua2005",
.description = "Enable UltraSPARC Architecture 2005 extensions",
.dependencies = featureSet(&[_]Feature{
.vis,
.vis2,
}),
};
result[@intFromEnum(Feature.ua2007)] = .{
.llvm_name = "ua2007",
.description = "Enable UltraSPARC Architecture 2007 extensions",
.dependencies = featureSet(&[_]Feature{
.vis,
.vis2,
}),
};
result[@intFromEnum(Feature.v8plus)] = .{ result[@intFromEnum(Feature.v8plus)] = .{
.llvm_name = "v8plus", .llvm_name = "v8plus",
.description = "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code", .description = "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code",
@ -324,17 +360,23 @@ pub const all_features = blk: {
result[@intFromEnum(Feature.vis)] = .{ result[@intFromEnum(Feature.vis)] = .{
.llvm_name = "vis", .llvm_name = "vis",
.description = "Enable UltraSPARC Visual Instruction Set extensions", .description = "Enable UltraSPARC Visual Instruction Set extensions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{
.v9,
}),
}; };
result[@intFromEnum(Feature.vis2)] = .{ result[@intFromEnum(Feature.vis2)] = .{
.llvm_name = "vis2", .llvm_name = "vis2",
.description = "Enable Visual Instruction Set extensions II", .description = "Enable Visual Instruction Set extensions II",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{
.v9,
}),
}; };
result[@intFromEnum(Feature.vis3)] = .{ result[@intFromEnum(Feature.vis3)] = .{
.llvm_name = "vis3", .llvm_name = "vis3",
.description = "Enable Visual Instruction Set extensions III", .description = "Enable Visual Instruction Set extensions III",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{
.v9,
}),
}; };
const ti = @typeInfo(Feature); const ti = @typeInfo(Feature);
for (&result, 0..) |*elem, i| { for (&result, 0..) |*elem, i| {
@ -544,9 +586,7 @@ pub const cpu = struct {
.llvm_name = "niagara", .llvm_name = "niagara",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.deprecated_v8, .deprecated_v8,
.v9, .ua2005,
.vis,
.vis2,
}), }),
}; };
pub const niagara2: CpuModel = .{ pub const niagara2: CpuModel = .{
@ -555,9 +595,7 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.deprecated_v8, .deprecated_v8,
.popc, .popc,
.v9, .ua2005,
.vis,
.vis2,
}), }),
}; };
pub const niagara3: CpuModel = .{ pub const niagara3: CpuModel = .{
@ -566,21 +604,20 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.deprecated_v8, .deprecated_v8,
.popc, .popc,
.v9, .ua2005,
.vis, .ua2007,
.vis2, .vis3,
}), }),
}; };
pub const niagara4: CpuModel = .{ pub const niagara4: CpuModel = .{
.name = "niagara4", .name = "niagara4",
.llvm_name = "niagara4", .llvm_name = "niagara4",
.features = featureSet(&[_]Feature{ .features = featureSet(&[_]Feature{
.crypto,
.deprecated_v8, .deprecated_v8,
.popc, .popc,
.v9, .ua2005,
.vis, .ua2007,
.vis2,
.vis3,
}), }),
}; };
pub const sparclet: CpuModel = .{ pub const sparclet: CpuModel = .{

29
lib/std/Target/x86.zig
View File

@ -347,14 +347,14 @@ pub const all_features = blk: {
.avx512bf16, .avx512bf16,
.avx512bitalg, .avx512bitalg,
.avx512cd, .avx512cd,
.avx512dq,
.avx512fp16, .avx512fp16,
.avx512ifma, .avx512ifma,
.avx512vbmi, .avx512vbmi,
.avx512vbmi2, .avx512vbmi2,
.avx512vl,
.avx512vnni, .avx512vnni,
.avx512vpopcntdq, .avx512vpopcntdq,
.vaes,
.vpclmulqdq,
}), }),
}; };
result[@intFromEnum(Feature.avx10_1_512)] = .{ result[@intFromEnum(Feature.avx10_1_512)] = .{
@ -443,8 +443,6 @@ pub const all_features = blk: {
.description = "Support 16-bit floating point", .description = "Support 16-bit floating point",
.dependencies = featureSet(&[_]Feature{ .dependencies = featureSet(&[_]Feature{
.avx512bw, .avx512bw,
.avx512dq,
.avx512vl,
}), }),
}; };
result[@intFromEnum(Feature.avx512ifma)] = .{ result[@intFromEnum(Feature.avx512ifma)] = .{
@ -1406,7 +1404,6 @@ pub const cpu = struct {
.avxvnni, .avxvnni,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -1502,7 +1499,6 @@ pub const cpu = struct {
.avxvnniint8, .avxvnniint8,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -1579,7 +1575,6 @@ pub const cpu = struct {
.avxvnniint8, .avxvnniint8,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -2371,7 +2366,6 @@ pub const cpu = struct {
.vpclmulqdq, .vpclmulqdq,
.vzeroupper, .vzeroupper,
.waitpkg, .waitpkg,
.widekl,
.x87, .x87,
.xsavec, .xsavec,
.xsaveopt, .xsaveopt,
@ -2565,6 +2559,8 @@ pub const cpu = struct {
.tuning_fast_imm_vector_shift, .tuning_fast_imm_vector_shift,
.uintr, .uintr,
.usermsr, .usermsr,
.vaes,
.vpclmulqdq,
.vzeroupper, .vzeroupper,
.waitpkg, .waitpkg,
.wbnoinvd, .wbnoinvd,
@ -2587,10 +2583,12 @@ pub const cpu = struct {
.avx512bf16, .avx512bf16,
.avx512bitalg, .avx512bitalg,
.avx512cd, .avx512cd,
.avx512dq,
.avx512fp16, .avx512fp16,
.avx512ifma, .avx512ifma,
.avx512vbmi, .avx512vbmi,
.avx512vbmi2, .avx512vbmi2,
.avx512vl,
.avx512vnni, .avx512vnni,
.avx512vpopcntdq, .avx512vpopcntdq,
.avxvnni, .avxvnni,
@ -2774,7 +2772,6 @@ pub const cpu = struct {
.avxvnni, .avxvnni,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -2898,10 +2895,12 @@ pub const cpu = struct {
.avx512bf16, .avx512bf16,
.avx512bitalg, .avx512bitalg,
.avx512cd, .avx512cd,
.avx512dq,
.avx512fp16, .avx512fp16,
.avx512ifma, .avx512ifma,
.avx512vbmi, .avx512vbmi,
.avx512vbmi2, .avx512vbmi2,
.avx512vl,
.avx512vnni, .avx512vnni,
.avx512vpopcntdq, .avx512vpopcntdq,
.avxvnni, .avxvnni,
@ -2986,10 +2985,12 @@ pub const cpu = struct {
.avx512bf16, .avx512bf16,
.avx512bitalg, .avx512bitalg,
.avx512cd, .avx512cd,
.avx512dq,
.avx512fp16, .avx512fp16,
.avx512ifma, .avx512ifma,
.avx512vbmi, .avx512vbmi,
.avx512vbmi2, .avx512vbmi2,
.avx512vl,
.avx512vnni, .avx512vnni,
.avx512vpopcntdq, .avx512vpopcntdq,
.avxvnni, .avxvnni,
@ -3486,7 +3487,6 @@ pub const cpu = struct {
.avxvnniint8, .avxvnniint8,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -3560,7 +3560,6 @@ pub const cpu = struct {
.avxvnni, .avxvnni,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -3710,7 +3709,6 @@ pub const cpu = struct {
.avxvnniint8, .avxvnniint8,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -3768,7 +3766,6 @@ pub const cpu = struct {
.vpclmulqdq, .vpclmulqdq,
.vzeroupper, .vzeroupper,
.waitpkg, .waitpkg,
.widekl,
.x87, .x87,
.xsavec, .xsavec,
.xsaveopt, .xsaveopt,
@ -3925,7 +3922,6 @@ pub const cpu = struct {
.avxvnni, .avxvnni,
.bmi, .bmi,
.bmi2, .bmi2,
.cldemote,
.clflushopt, .clflushopt,
.clwb, .clwb,
.cmov, .cmov,
@ -4090,10 +4086,12 @@ pub const cpu = struct {
.avx512bf16, .avx512bf16,
.avx512bitalg, .avx512bitalg,
.avx512cd, .avx512cd,
.avx512dq,
.avx512fp16, .avx512fp16,
.avx512ifma, .avx512ifma,
.avx512vbmi, .avx512vbmi,
.avx512vbmi2, .avx512vbmi2,
.avx512vl,
.avx512vnni, .avx512vnni,
.avx512vpopcntdq, .avx512vpopcntdq,
.avxvnni, .avxvnni,
@ -4907,7 +4905,6 @@ pub const cpu = struct {
.sahf, .sahf,
.sbb_dep_breaking, .sbb_dep_breaking,
.sha, .sha,
.slow_shld,
.smap, .smap,
.smep, .smep,
.sse4a, .sse4a,
@ -4980,7 +4977,6 @@ pub const cpu = struct {
.sbb_dep_breaking, .sbb_dep_breaking,
.sha, .sha,
.shstk, .shstk,
.slow_shld,
.smap, .smap,
.smep, .smep,
.sse4a, .sse4a,
@ -5058,7 +5054,6 @@ pub const cpu = struct {
.sbb_dep_breaking, .sbb_dep_breaking,
.sha, .sha,
.shstk, .shstk,
.slow_shld,
.smap, .smap,
.smep, .smep,
.sse4a, .sse4a,

214
lib/std/Target/xtensa.zig
View File

@ -5,7 +5,41 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model; const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum { pub const Feature = enum {
bool,
clamps,
coprocessor,
dcache,
debug,
density, density,
dfpaccel,
div32,
exception,
extendedl32r,
fp,
highpriinterrupts,
highpriinterrupts_level3,
highpriinterrupts_level4,
highpriinterrupts_level5,
highpriinterrupts_level6,
highpriinterrupts_level7,
interrupt,
loop,
mac16,
minmax,
miscsr,
mul16,
mul32,
mul32high,
nsa,
prid,
regprotect,
rvector,
sext,
threadptr,
timers1,
timers2,
timers3,
windowed,
}; };
pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
@ -17,11 +51,191 @@ pub const all_features = blk: {
const len = @typeInfo(Feature).@"enum".fields.len; const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count); std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined; var result: [len]CpuFeature = undefined;
result[@intFromEnum(Feature.bool)] = .{
.llvm_name = "bool",
.description = "Enable Xtensa Boolean extension",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.clamps)] = .{
.llvm_name = "clamps",
.description = "Enable Xtensa CLAMPS option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.coprocessor)] = .{
.llvm_name = "coprocessor",
.description = "Enable Xtensa Coprocessor option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.dcache)] = .{
.llvm_name = "dcache",
.description = "Enable Xtensa Data Cache option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.debug)] = .{
.llvm_name = "debug",
.description = "Enable Xtensa Debug option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.density)] = .{ result[@intFromEnum(Feature.density)] = .{
.llvm_name = "density", .llvm_name = "density",
.description = "Enable Density instructions", .description = "Enable Density instructions",
.dependencies = featureSet(&[_]Feature{}), .dependencies = featureSet(&[_]Feature{}),
}; };
result[@intFromEnum(Feature.dfpaccel)] = .{
.llvm_name = "dfpaccel",
.description = "Enable Xtensa Double Precision FP acceleration",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.div32)] = .{
.llvm_name = "div32",
.description = "Enable Xtensa Div32 option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.exception)] = .{
.llvm_name = "exception",
.description = "Enable Xtensa Exception option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.extendedl32r)] = .{
.llvm_name = "extendedl32r",
.description = "Enable Xtensa Extended L32R option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.fp)] = .{
.llvm_name = "fp",
.description = "Enable Xtensa Single FP instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.highpriinterrupts)] = .{
.llvm_name = "highpriinterrupts",
.description = "Enable Xtensa HighPriInterrupts option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.highpriinterrupts_level3)] = .{
.llvm_name = "highpriinterrupts-level3",
.description = "Enable Xtensa HighPriInterrupts Level3",
.dependencies = featureSet(&[_]Feature{
.highpriinterrupts,
}),
};
result[@intFromEnum(Feature.highpriinterrupts_level4)] = .{
.llvm_name = "highpriinterrupts-level4",
.description = "Enable Xtensa HighPriInterrupts Level4",
.dependencies = featureSet(&[_]Feature{
.highpriinterrupts,
}),
};
result[@intFromEnum(Feature.highpriinterrupts_level5)] = .{
.llvm_name = "highpriinterrupts-level5",
.description = "Enable Xtensa HighPriInterrupts Level5",
.dependencies = featureSet(&[_]Feature{
.highpriinterrupts,
}),
};
result[@intFromEnum(Feature.highpriinterrupts_level6)] = .{
.llvm_name = "highpriinterrupts-level6",
.description = "Enable Xtensa HighPriInterrupts Level6",
.dependencies = featureSet(&[_]Feature{
.highpriinterrupts,
}),
};
result[@intFromEnum(Feature.highpriinterrupts_level7)] = .{
.llvm_name = "highpriinterrupts-level7",
.description = "Enable Xtensa HighPriInterrupts Level7",
.dependencies = featureSet(&[_]Feature{
.highpriinterrupts,
}),
};
result[@intFromEnum(Feature.interrupt)] = .{
.llvm_name = "interrupt",
.description = "Enable Xtensa Interrupt option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.loop)] = .{
.llvm_name = "loop",
.description = "Enable Xtensa Loop extension",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.mac16)] = .{
.llvm_name = "mac16",
.description = "Enable Xtensa MAC16 instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.minmax)] = .{
.llvm_name = "minmax",
.description = "Enable Xtensa MINMAX option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.miscsr)] = .{
.llvm_name = "miscsr",
.description = "Enable Xtensa Miscellaneous SR option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.mul16)] = .{
.llvm_name = "mul16",
.description = "Enable Xtensa Mul16 option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.mul32)] = .{
.llvm_name = "mul32",
.description = "Enable Xtensa Mul32 option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.mul32high)] = .{
.llvm_name = "mul32high",
.description = "Enable Xtensa Mul32High option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.nsa)] = .{
.llvm_name = "nsa",
.description = "Enable Xtensa NSA option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.prid)] = .{
.llvm_name = "prid",
.description = "Enable Xtensa Processor ID option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.regprotect)] = .{
.llvm_name = "regprotect",
.description = "Enable Xtensa Region Protection option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.rvector)] = .{
.llvm_name = "rvector",
.description = "Enable Xtensa Relocatable Vector option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.sext)] = .{
.llvm_name = "sext",
.description = "Enable Xtensa Sign Extend option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.threadptr)] = .{
.llvm_name = "threadptr",
.description = "Enable Xtensa THREADPTR option",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.timers1)] = .{
.llvm_name = "timers1",
.description = "Enable Xtensa Timers 1",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.timers2)] = .{
.llvm_name = "timers2",
.description = "Enable Xtensa Timers 2",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.timers3)] = .{
.llvm_name = "timers3",
.description = "Enable Xtensa Timers 3",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.windowed)] = .{
.llvm_name = "windowed",
.description = "Enable Xtensa Windowed Register option",
.dependencies = featureSet(&[_]Feature{}),
};
const ti = @typeInfo(Feature); const ti = @typeInfo(Feature);
for (&result, 0..) |*elem, i| { for (&result, 0..) |*elem, i| {
elem.index = i; elem.index = i;