From 57c530155f0c7754386c50fb9bc128198cab705c Mon Sep 17 00:00:00 2001 From: Jakub Konka Date: Mon, 13 Jun 2022 19:21:38 +0200 Subject: [PATCH] compiler_rt: correctly export allrem and aullrem for i386-windows-msvc --- lib/compiler_rt.zig | 1 + lib/compiler_rt/aulldiv.zig | 2 -- lib/compiler_rt/aullrem.zig | 13 +++++++++++++ src/compiler_rt.zig | 1 + 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/lib/compiler_rt.zig b/lib/compiler_rt.zig index 92d783cc25..999cce3e65 100644 --- a/lib/compiler_rt.zig +++ b/lib/compiler_rt.zig @@ -62,6 +62,7 @@ comptime { _ = @import("compiler_rt/emutls.zig"); _ = @import("compiler_rt/arm.zig"); _ = @import("compiler_rt/aulldiv.zig"); + _ = @import("compiler_rt/aullrem.zig"); _ = @import("compiler_rt/sparc.zig"); _ = @import("compiler_rt/clear_cache.zig"); diff --git a/lib/compiler_rt/aulldiv.zig b/lib/compiler_rt/aulldiv.zig index 7154cb39a1..38009d7015 100644 --- a/lib/compiler_rt/aulldiv.zig +++ b/lib/compiler_rt/aulldiv.zig @@ -10,8 +10,6 @@ comptime { // Don't let LLVM apply the stdcall name mangling on those MSVC builtins @export(_alldiv, .{ .name = "\x01__alldiv", .linkage = linkage }); @export(_aulldiv, .{ .name = "\x01__aulldiv", .linkage = linkage }); - @export(_allrem, .{ .name = "\x01__allrem", .linkage = linkage }); - @export(_aullrem, .{ .name = "\x01__aullrem", .linkage = linkage }); } } diff --git a/lib/compiler_rt/aullrem.zig b/lib/compiler_rt/aullrem.zig index dbd52cd377..18e9eea0c6 100644 --- a/lib/compiler_rt/aullrem.zig +++ b/lib/compiler_rt/aullrem.zig @@ -1,4 +1,17 @@ +const std = @import("std"); const builtin = @import("builtin"); +const arch = builtin.cpu.arch; +const abi = builtin.abi; +const linkage: std.builtin.GlobalLinkage = if (builtin.is_test) .Internal else .Strong; +pub const panic = @import("common.zig").panic; + +comptime { + if (arch == .i386 and abi == .msvc) { + // Don't let LLVM apply the stdcall name mangling on those MSVC builtins + @export(_allrem, .{ .name = "\x01__allrem", .linkage = linkage }); + @export(_aullrem, .{ .name = "\x01__aullrem", .linkage = linkage }); + } +} pub fn _allrem(a: i64, b: i64) callconv(.Stdcall) i64 { @setRuntimeSafety(builtin.is_test); diff --git a/src/compiler_rt.zig b/src/compiler_rt.zig index 8df14de38c..5149ce192f 100644 --- a/src/compiler_rt.zig +++ b/src/compiler_rt.zig @@ -227,6 +227,7 @@ const sources = &[_][]const u8{ "compiler_rt/emutls.zig", "compiler_rt/arm.zig", "compiler_rt/aulldiv.zig", + "compiler_rt/aullrem.zig", "compiler_rt/sparc.zig", "compiler_rt/clear_cache.zig", };