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Merge pull request #10927 from ziglang/x64-idiv-imul
stage2,x64: implement integer division
This commit is contained in:
Jakub Konka
GitHub
commit
539bb8a2d7
@ -1252,30 +1252,244 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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return self.fail("TODO implement airShlWithOverflow for {}", .{self.target.cpu.arch});
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}
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/// Generates signed or unsigned integer division.
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/// Requires use of .rax and .rdx registers. Spills them if necessary.
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/// Quotient is saved in .rax and remainder in .rdx.
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fn genIntDivOpMir(
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self: *Self,
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ty: Type,
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signedness: std.builtin.Signedness,
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lhs: MCValue,
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rhs: MCValue,
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) !void {
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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if (abi_size > 8) {
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return self.fail("TODO implement genIntDivOpMir for ABI size larger than 8", .{});
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}
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rdx, null);
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self.register_manager.freezeRegs(&.{ .rax, .rdx });
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defer self.register_manager.unfreezeRegs(&.{ .rax, .rdx });
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const dividend = switch (lhs) {
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.register => lhs,
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else => blk: {
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const reg = try self.copyToTmpRegister(ty, lhs);
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break :blk MCValue{ .register = reg };
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},
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};
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try self.genSetReg(ty, .rax, dividend);
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self.register_manager.freezeRegs(&.{dividend.register});
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defer self.register_manager.unfreezeRegs(&.{dividend.register});
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switch (signedness) {
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.signed => {
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_ = try self.addInst(.{
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.tag = .cwd,
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.ops = (Mir.Ops{
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.flags = 0b11,
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}).encode(),
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.data = undefined,
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});
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},
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.unsigned => {
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_ = try self.addInst(.{
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.tag = .xor,
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.ops = (Mir.Ops{
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.reg1 = .rdx,
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.reg2 = .rdx,
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}).encode(),
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.data = undefined,
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});
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},
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}
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const divisor = switch (rhs) {
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.register => rhs,
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else => blk: {
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const reg = try self.copyToTmpRegister(ty, rhs);
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break :blk MCValue{ .register = reg };
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},
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};
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const op_tag: Mir.Inst.Tag = switch (signedness) {
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.signed => .idiv,
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.unsigned => .div,
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};
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switch (divisor) {
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.register => |reg| {
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_ = try self.addInst(.{
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.tag = op_tag,
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.ops = (Mir.Ops{
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.reg1 = reg,
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}).encode(),
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.data = undefined,
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});
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},
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.stack_offset => |off| {
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_ = try self.addInst(.{
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.tag = op_tag,
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.ops = (Mir.Ops{
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.reg2 = .rbp,
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.flags = switch (abi_size) {
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1 => 0b00,
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2 => 0b01,
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4 => 0b10,
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8 => 0b11,
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else => unreachable,
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},
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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});
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},
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else => unreachable,
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}
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}
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fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCValue {
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const signedness = ty.intInfo(self.target.*).signedness;
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const dividend = switch (lhs) {
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.register => |reg| reg,
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else => try self.copyToTmpRegister(ty, lhs),
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};
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self.register_manager.freezeRegs(&.{dividend});
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const divisor = switch (rhs) {
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.register => |reg| reg,
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else => try self.copyToTmpRegister(ty, rhs),
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};
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self.register_manager.freezeRegs(&.{divisor});
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defer self.register_manager.unfreezeRegs(&.{ dividend, divisor });
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try self.genIntDivOpMir(Type.isize, signedness, .{ .register = dividend }, .{ .register = divisor });
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_ = try self.addInst(.{
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.tag = .xor,
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.ops = (Mir.Ops{
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.reg1 = divisor.to64(),
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.reg2 = dividend.to64(),
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}).encode(),
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.data = undefined,
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});
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_ = try self.addInst(.{
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.tag = .sar,
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.ops = (Mir.Ops{
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.reg1 = divisor.to64(),
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.flags = 0b10,
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}).encode(),
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.data = .{ .imm = 63 },
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});
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_ = try self.addInst(.{
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.tag = .@"test",
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.ops = (Mir.Ops{
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.reg1 = .rdx,
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.reg2 = .rdx,
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}).encode(),
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.data = undefined,
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});
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_ = try self.addInst(.{
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.tag = .cond_mov_eq,
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.ops = (Mir.Ops{
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.reg1 = divisor.to64(),
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.reg2 = .rdx,
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}).encode(),
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.data = undefined,
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});
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try self.genBinMathOpMir(.add, Type.isize, .{ .register = divisor.to64() }, .{ .register = .rax });
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return MCValue{ .register = divisor };
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}
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fn airDiv(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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return self.fail("TODO implement div for {}", .{self.target.cpu.arch});
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const tag = self.air.instructions.items(.tag)[inst];
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const ty = self.air.typeOfIndex(inst);
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if (ty.zigTypeTag() != .Int) {
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return self.fail("TODO implement {} for operands of dst type {}", .{ tag, ty.zigTypeTag() });
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}
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if (tag == .div_float) {
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return self.fail("TODO implement {}", .{tag});
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}
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// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rdx, null);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const signedness = ty.intInfo(self.target.*).signedness;
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if (signedness == .unsigned) {
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try self.genIntDivOpMir(ty, signedness, lhs, rhs);
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break :result MCValue{ .register = .rax };
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}
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switch (tag) {
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.div_exact, .div_trunc => {
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try self.genIntDivOpMir(ty, signedness, lhs, rhs);
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break :result MCValue{ .register = .rax };
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},
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.div_floor => {
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break :result try self.genInlineIntDivFloor(ty, lhs, rhs);
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},
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else => unreachable,
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airRem(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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return self.fail("TODO implement rem for {}", .{self.target.cpu.arch});
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const ty = self.air.typeOfIndex(inst);
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if (ty.zigTypeTag() != .Int) {
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return self.fail("TODO implement .rem for operands of dst type {}", .{ty.zigTypeTag()});
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}
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// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rdx, null);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const signedness = ty.intInfo(self.target.*).signedness;
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try self.genIntDivOpMir(ty, signedness, lhs, rhs);
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break :result MCValue{ .register = .rdx };
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airMod(self: *Self, inst: Air.Inst.Index) !void {
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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const result: MCValue = if (self.liveness.isUnused(inst))
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.dead
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else
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return self.fail("TODO implement mod for {}", .{self.target.cpu.arch});
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const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
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const ty = self.air.typeOfIndex(inst);
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if (ty.zigTypeTag() != .Int) {
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return self.fail("TODO implement .mod for operands of dst type {}", .{ty.zigTypeTag()});
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}
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// Spill .rax and .rdx upfront to ensure we don't spill the operands too late.
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try self.register_manager.getReg(.rax, null);
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try self.register_manager.getReg(.rdx, null);
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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const signedness = ty.intInfo(self.target.*).signedness;
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switch (signedness) {
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.unsigned => {
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try self.genIntDivOpMir(ty, signedness, lhs, rhs);
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break :result MCValue{ .register = .rdx };
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},
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.signed => {
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const div_floor = try self.genInlineIntDivFloor(ty, lhs, rhs);
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try self.genIMulOpMir(ty, div_floor, rhs);
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const reg = try self.copyToTmpRegister(ty, lhs);
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try self.genBinMathOpMir(.sub, ty, .{ .register = reg }, div_floor);
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break :result MCValue{ .register = reg };
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},
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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@ -4126,7 +4340,7 @@ fn genInlineMemset(
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}
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fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void {
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const abi_size = ty.abiSize(self.target.*);
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const abi_size = @intCast(u32, ty.abiSize(self.target.*));
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switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => |off| {
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@ -4136,7 +4350,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .lea,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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.reg1 = registerAlias(reg, abi_size),
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.reg2 = .rbp,
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}).encode(),
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.data = .{ .imm = @bitCast(u32, -off) },
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@ -4202,7 +4416,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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.reg1 = registerAlias(reg, abi_size),
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}).encode(),
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.data = .{ .imm = @truncate(u32, x) },
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});
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@ -4249,7 +4463,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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.tag = .mov_sign_extend,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.reg2 = src_reg,
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.reg2 = registerAlias(src_reg, abi_size),
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}).encode(),
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.data = undefined,
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});
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@ -4260,7 +4474,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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.tag = .mov_zero_extend,
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.ops = (Mir.Ops{
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.reg1 = reg.to64(),
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.reg2 = src_reg,
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.reg2 = registerAlias(src_reg, abi_size),
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}).encode(),
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.data = undefined,
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});
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@ -4272,8 +4486,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @divExact(src_reg.size(), 8)),
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.reg2 = src_reg,
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.reg1 = registerAlias(reg, abi_size),
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.reg2 = registerAlias(src_reg, abi_size),
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}).encode(),
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.data = undefined,
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});
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@ -4399,7 +4613,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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_ = try self.addInst(.{
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.tag = .mov,
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.ops = (Mir.Ops{
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.reg1 = registerAlias(reg, @intCast(u32, abi_size)),
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.reg1 = registerAlias(reg, abi_size),
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.reg2 = .rbp,
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.flags = 0b01,
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}).encode(),
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@ -138,8 +138,13 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
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.shr => try emit.mirShift(.shr, inst),
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.sar => try emit.mirShift(.sar, inst),
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.imul => try emit.mirMulDiv(.imul, inst),
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.idiv => try emit.mirMulDiv(.idiv, inst),
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.div => try emit.mirMulDiv(.div, inst),
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.imul_complex => try emit.mirIMulComplex(inst),
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.cwd => try emit.mirCwd(inst),
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.push => try emit.mirPushPop(.push, inst),
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.pop => try emit.mirPushPop(.pop, inst),
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@ -156,6 +161,8 @@ pub fn lowerMir(emit: *Emit) InnerError!void {
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.cond_set_byte_eq_ne,
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=> try emit.mirCondSetByte(tag, inst),
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.cond_mov_eq => try emit.mirCondMov(.cmove, inst),
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.ret => try emit.mirRet(inst),
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.syscall => try emit.mirSyscall(),
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@ -368,6 +375,24 @@ fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) Inne
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return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1.to8()), emit.code);
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}
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fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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if (ops.flags == 0b00) {
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
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}
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const ptr_size: Memory.PtrSize = switch (ops.flags) {
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0b00 => unreachable,
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0b01 => .word_ptr,
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0b10 => .dword_ptr,
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0b11 => .qword_ptr,
|
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};
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return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(ptr_size, .{
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.disp = imm,
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.base = ops.reg2,
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}), emit.code);
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}
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|
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fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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assert(tag == .@"test");
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@ -386,7 +411,7 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
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return lowerToMiEnc(.@"test", RegisterOrMemory.reg(ops.reg1), imm, emit.code);
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}
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// TEST r/m64, r64
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return emit.fail("TODO TEST r/m64, r64", .{});
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return lowerToMrEnc(.@"test", RegisterOrMemory.reg(ops.reg1), ops.reg2, emit.code);
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},
|
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else => return emit.fail("TODO more TEST alternatives", .{}),
|
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}
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@ -683,6 +708,27 @@ fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
|
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}
|
||||
}
|
||||
|
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fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
|
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const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
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if (ops.reg1 != .none) {
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assert(ops.reg2 == .none);
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return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
|
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}
|
||||
assert(ops.reg1 == .none);
|
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assert(ops.reg2 != .none);
|
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const imm = emit.mir.instructions.items(.data)[inst].imm;
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const ptr_size: Memory.PtrSize = switch (ops.flags) {
|
||||
0b00 => .byte_ptr,
|
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0b01 => .word_ptr,
|
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0b10 => .dword_ptr,
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0b11 => .qword_ptr,
|
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};
|
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return lowerToMEnc(tag, RegisterOrMemory.mem(ptr_size, .{
|
||||
.disp = imm,
|
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.base = ops.reg2,
|
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}), emit.code);
|
||||
}
|
||||
|
||||
fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
|
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const tag = emit.mir.instructions.items(.tag)[inst];
|
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assert(tag == .imul_complex);
|
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@ -714,6 +760,17 @@ fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
|
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}
|
||||
}
|
||||
|
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fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
|
||||
const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
|
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const tag: Tag = switch (ops.flags) {
|
||||
0b00 => .cbw,
|
||||
0b01 => .cwd,
|
||||
0b10 => .cdq,
|
||||
0b11 => .cqo,
|
||||
};
|
||||
return lowerToZoEnc(tag, emit.code);
|
||||
}
|
||||
|
||||
fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
assert(tag == .lea);
|
||||
@ -1048,6 +1105,8 @@ const Tag = enum {
|
||||
brk,
|
||||
nop,
|
||||
imul,
|
||||
idiv,
|
||||
div,
|
||||
syscall,
|
||||
ret_near,
|
||||
ret_far,
|
||||
@ -1115,6 +1174,12 @@ const Tag = enum {
|
||||
sal,
|
||||
shr,
|
||||
sar,
|
||||
cbw,
|
||||
cwd,
|
||||
cdq,
|
||||
cqo,
|
||||
cmove,
|
||||
cmovz,
|
||||
|
||||
fn isSetCC(tag: Tag) bool {
|
||||
return switch (tag) {
|
||||
@ -1234,6 +1299,8 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
|
||||
.brk => OpCode.oneByte(0xcc),
|
||||
.nop => OpCode.oneByte(0x90),
|
||||
.syscall => OpCode.twoByte(0x0f, 0x05),
|
||||
.cbw => OpCode.oneByte(0x98),
|
||||
.cwd, .cdq, .cqo => OpCode.oneByte(0x99),
|
||||
else => null,
|
||||
},
|
||||
.d => return switch (tag) {
|
||||
@ -1276,6 +1343,7 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
|
||||
.setnl, .setge => OpCode.twoByte(0x0f, 0x9d),
|
||||
.setle, .setng => OpCode.twoByte(0x0f, 0x9e),
|
||||
.setnle, .setg => OpCode.twoByte(0x0f, 0x9f),
|
||||
.idiv, .div, .imul => OpCode.oneByte(if (is_one_byte) 0xf6 else 0xf7),
|
||||
else => null,
|
||||
},
|
||||
.o => return switch (tag) {
|
||||
@ -1319,6 +1387,7 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
|
||||
.sbb => OpCode.oneByte(if (is_one_byte) 0x18 else 0x19),
|
||||
.cmp => OpCode.oneByte(if (is_one_byte) 0x38 else 0x39),
|
||||
.mov => OpCode.oneByte(if (is_one_byte) 0x88 else 0x89),
|
||||
.@"test" => OpCode.oneByte(if (is_one_byte) 0x84 else 0x85),
|
||||
else => null,
|
||||
},
|
||||
.rm => return switch (tag) {
|
||||
@ -1336,6 +1405,7 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
|
||||
.movzx => OpCode.twoByte(0x0f, if (is_one_byte) 0xb6 else 0xb7),
|
||||
.lea => OpCode.oneByte(if (is_one_byte) 0x8c else 0x8d),
|
||||
.imul => OpCode.twoByte(0x0f, 0xaf),
|
||||
.cmove, .cmovz => OpCode.twoByte(0x0f, 0x44),
|
||||
else => null,
|
||||
},
|
||||
.oi => return switch (tag) {
|
||||
@ -1409,6 +1479,9 @@ inline fn getModRmExt(tag: Tag) ?u3 {
|
||||
=> 0x4,
|
||||
.shr => 0x5,
|
||||
.sar => 0x7,
|
||||
.imul => 0x5,
|
||||
.idiv => 0x7,
|
||||
.div => 0x6,
|
||||
else => null,
|
||||
};
|
||||
}
|
||||
@ -1565,7 +1638,15 @@ const RegisterOrMemory = union(enum) {
|
||||
|
||||
fn lowerToZoEnc(tag: Tag, code: *std.ArrayList(u8)) InnerError!void {
|
||||
const opc = getOpCode(tag, .zo, false).?;
|
||||
const encoder = try Encoder.init(code, 1);
|
||||
const encoder = try Encoder.init(code, 2);
|
||||
switch (tag) {
|
||||
.cqo => {
|
||||
encoder.rex(.{
|
||||
.w = true,
|
||||
});
|
||||
},
|
||||
else => {},
|
||||
}
|
||||
opc.encode(encoder);
|
||||
}
|
||||
|
||||
@ -2204,6 +2285,10 @@ test "lower M encoding" {
|
||||
try expectEqualHexStrings("\xFF\x24\x25\x10\x00\x00\x00", emit.lowered(), "jmp qword ptr [ds:0x10]");
|
||||
try lowerToMEnc(.seta, RegisterOrMemory.reg(.r11b), emit.code());
|
||||
try expectEqualHexStrings("\x41\x0F\x97\xC3", emit.lowered(), "seta r11b");
|
||||
try lowerToMEnc(.idiv, RegisterOrMemory.reg(.rax), emit.code());
|
||||
try expectEqualHexStrings("\x48\xF7\xF8", emit.lowered(), "idiv rax");
|
||||
try lowerToMEnc(.imul, RegisterOrMemory.reg(.al), emit.code());
|
||||
try expectEqualHexStrings("\xF6\xE8", emit.lowered(), "imul al");
|
||||
}
|
||||
|
||||
test "lower M1 and MC encodings" {
|
||||
|
||||
@ -220,10 +220,21 @@ pub const Inst = struct {
|
||||
sar_mem_index_imm,
|
||||
|
||||
/// ops flags: form:
|
||||
/// 0bX0 reg1
|
||||
/// 0bX1 [reg1 + imm32]
|
||||
/// 0b00 reg1
|
||||
/// 0b00 byte ptr [reg2 + imm32]
|
||||
/// 0b01 word ptr [reg2 + imm32]
|
||||
/// 0b10 dword ptr [reg2 + imm32]
|
||||
/// 0b11 qword ptr [reg2 + imm32]
|
||||
imul,
|
||||
idiv,
|
||||
div,
|
||||
|
||||
/// ops flags: form:
|
||||
/// 0b00 AX <- AL
|
||||
/// 0b01 DX:AX <- AX
|
||||
/// 0b10 EDX:EAX <- EAX
|
||||
/// 0b11 RDX:RAX <- RAX
|
||||
cwd,
|
||||
|
||||
/// ops flags: form:
|
||||
/// 0b00 reg1, reg2
|
||||
@ -275,6 +286,13 @@ pub const Inst = struct {
|
||||
cond_jmp_eq_ne,
|
||||
cond_set_byte_eq_ne,
|
||||
|
||||
/// ops flags:
|
||||
/// 0b00 reg1, reg2,
|
||||
/// 0b01 reg1, word ptr [reg2 + imm]
|
||||
/// 0b10 reg1, dword ptr [reg2 + imm]
|
||||
/// 0b11 reg1, qword ptr [reg2 + imm]
|
||||
cond_mov_eq,
|
||||
|
||||
/// ops flags: form:
|
||||
/// 0b00 reg1
|
||||
/// 0b01 [reg1 + imm32]
|
||||
|
||||
@ -50,6 +50,7 @@ test {
|
||||
_ = @import("behavior/tuple.zig");
|
||||
_ = @import("behavior/type.zig");
|
||||
_ = @import("behavior/var_args.zig");
|
||||
_ = @import("behavior/int_div.zig");
|
||||
|
||||
// tests that don't pass for stage1
|
||||
if (builtin.zig_backend != .stage1) {
|
||||
|
||||
93
test/behavior/int_div.zig
Normal file
93
test/behavior/int_div.zig
Normal file
@ -0,0 +1,93 @@
|
||||
const std = @import("std");
|
||||
const builtin = @import("builtin");
|
||||
const expect = std.testing.expect;
|
||||
|
||||
test "integer division" {
|
||||
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
|
||||
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
|
||||
|
||||
try testDivision();
|
||||
comptime try testDivision();
|
||||
}
|
||||
fn testDivision() !void {
|
||||
try expect(div(u32, 13, 3) == 4);
|
||||
try expect(div(u64, 13, 3) == 4);
|
||||
try expect(div(u8, 13, 3) == 4);
|
||||
|
||||
try expect(divExact(u32, 55, 11) == 5);
|
||||
try expect(divExact(i32, -55, 11) == -5);
|
||||
try expect(divExact(i64, -55, 11) == -5);
|
||||
try expect(divExact(i16, -55, 11) == -5);
|
||||
|
||||
try expect(divFloor(i8, 5, 3) == 1);
|
||||
try expect(divFloor(i16, -5, 3) == -2);
|
||||
try expect(divFloor(i64, -0x80000000, -2) == 0x40000000);
|
||||
try expect(divFloor(i32, 0, -0x80000000) == 0);
|
||||
try expect(divFloor(i64, -0x40000001, 0x40000000) == -2);
|
||||
try expect(divFloor(i32, -0x80000000, 1) == -0x80000000);
|
||||
try expect(divFloor(i32, 10, 12) == 0);
|
||||
try expect(divFloor(i32, -14, 12) == -2);
|
||||
try expect(divFloor(i32, -2, 12) == -1);
|
||||
|
||||
try expect(divTrunc(i32, 5, 3) == 1);
|
||||
try expect(divTrunc(i32, -5, 3) == -1);
|
||||
try expect(divTrunc(i32, 9, -10) == 0);
|
||||
try expect(divTrunc(i32, -9, 10) == 0);
|
||||
try expect(divTrunc(i32, 10, 12) == 0);
|
||||
try expect(divTrunc(i32, -14, 12) == -1);
|
||||
try expect(divTrunc(i32, -2, 12) == 0);
|
||||
|
||||
try expect(mod(u32, 10, 12) == 10);
|
||||
try expect(mod(i32, 10, 12) == 10);
|
||||
try expect(mod(i64, -14, 12) == 10);
|
||||
try expect(mod(i16, -2, 12) == 10);
|
||||
try expect(mod(i8, -2, 12) == 10);
|
||||
|
||||
try expect(rem(i32, 10, 12) == 10);
|
||||
try expect(rem(i32, -14, 12) == -2);
|
||||
try expect(rem(i32, -2, 12) == -2);
|
||||
|
||||
comptime {
|
||||
try expect(
|
||||
1194735857077236777412821811143690633098347576 % 508740759824825164163191790951174292733114988 == 177254337427586449086438229241342047632117600,
|
||||
);
|
||||
try expect(
|
||||
@rem(-1194735857077236777412821811143690633098347576, 508740759824825164163191790951174292733114988) == -177254337427586449086438229241342047632117600,
|
||||
);
|
||||
try expect(
|
||||
1194735857077236777412821811143690633098347576 / 508740759824825164163191790951174292733114988 == 2,
|
||||
);
|
||||
try expect(
|
||||
@divTrunc(-1194735857077236777412821811143690633098347576, 508740759824825164163191790951174292733114988) == -2,
|
||||
);
|
||||
try expect(
|
||||
@divTrunc(1194735857077236777412821811143690633098347576, -508740759824825164163191790951174292733114988) == -2,
|
||||
);
|
||||
try expect(
|
||||
@divTrunc(-1194735857077236777412821811143690633098347576, -508740759824825164163191790951174292733114988) == 2,
|
||||
);
|
||||
try expect(
|
||||
4126227191251978491697987544882340798050766755606969681711 % 10 == 1,
|
||||
);
|
||||
}
|
||||
}
|
||||
fn div(comptime T: type, a: T, b: T) T {
|
||||
return a / b;
|
||||
}
|
||||
fn divExact(comptime T: type, a: T, b: T) T {
|
||||
return @divExact(a, b);
|
||||
}
|
||||
fn divFloor(comptime T: type, a: T, b: T) T {
|
||||
return @divFloor(a, b);
|
||||
}
|
||||
fn divTrunc(comptime T: type, a: T, b: T) T {
|
||||
return @divTrunc(a, b);
|
||||
}
|
||||
fn mod(comptime T: type, a: T, b: T) T {
|
||||
return @mod(a, b);
|
||||
}
|
||||
fn rem(comptime T: type, a: T, b: T) T {
|
||||
return @rem(a, b);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user