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Merge pull request #10129 from joachimschmidt557/stage2-aarch64
stage2 AArch64: Implement conditional branches
This commit is contained in:
Jakub Konka
GitHub
commit
53523ef5d0
@ -177,7 +177,7 @@ const StackAllocation = struct {
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};
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const BlockData = struct {
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relocs: std.ArrayListUnmanaged(Reloc),
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relocs: std.ArrayListUnmanaged(Mir.Inst.Index),
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/// The first break instruction encounters `null` here and chooses a
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/// machine code value for the block result, populating this field.
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/// Following break instructions encounter that value and use it for
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@ -185,18 +185,6 @@ const BlockData = struct {
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mcv: MCValue,
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};
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const Reloc = union(enum) {
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/// The value is an offset into the `Function` `code` from the beginning.
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/// To perform the reloc, write 32-bit signed little-endian integer
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/// which is a relative jump, based on the address following the reloc.
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rel32: usize,
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/// A branch in the ARM instruction set
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arm_branch: struct {
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pos: usize,
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cond: @import("../arm/bits.zig").Condition,
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},
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};
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const BigTomb = struct {
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function: *Self,
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inst: Air.Inst.Index,
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@ -426,6 +414,12 @@ fn gen(self: *Self) !void {
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});
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}
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// add sp, sp, #stack_size
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_ = try self.addInst(.{
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.tag = .add_immediate,
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.data = .{ .rr_imm12_sh = .{ .rd = .xzr, .rn = .xzr, .imm12 = @intCast(u12, aligned_stack_end) } },
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});
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// ldp fp, lr, [sp], #16
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_ = try self.addInst(.{
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.tag = .ldp,
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@ -437,12 +431,6 @@ fn gen(self: *Self) !void {
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} },
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});
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// add sp, sp, #stack_size
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_ = try self.addInst(.{
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.tag = .add_immediate,
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.data = .{ .rr_imm12_sh = .{ .rd = .xzr, .rn = .xzr, .imm12 = @intCast(u12, aligned_stack_end) } },
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});
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// ret lr
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_ = try self.addInst(.{
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.tag = .ret,
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@ -1358,7 +1346,9 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
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const stack_offset = try self.allocMem(inst, abi_size, abi_align);
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try self.genSetStack(ty, stack_offset, MCValue{ .register = reg });
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break :blk MCValue{ .stack_offset = stack_offset };
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// TODO correct loading and storing from memory
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// break :blk MCValue{ .stack_offset = stack_offset };
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break :blk result;
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},
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else => result,
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};
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@ -1634,8 +1624,6 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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_ = op;
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const bin_op = self.air.instructions.items(.data)[inst].bin_op;
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if (self.liveness.isUnused(inst))
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return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
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@ -1646,10 +1634,79 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
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const lhs = try self.resolveInst(bin_op.lhs);
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const rhs = try self.resolveInst(bin_op.rhs);
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_ = lhs;
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_ = rhs;
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const result: MCValue = result: {
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const lhs_is_register = lhs == .register;
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const rhs_is_register = rhs == .register;
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// lhs should always be a register
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const rhs_should_be_register = switch (rhs) {
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.immediate => |imm| imm < 0 or imm > std.math.maxInt(u12),
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else => true,
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};
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return self.fail("TODO implement cmp for {}", .{self.target.cpu.arch});
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var lhs_mcv = lhs;
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var rhs_mcv = rhs;
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// Allocate registers
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if (rhs_should_be_register) {
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if (!lhs_is_register and !rhs_is_register) {
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const regs = try self.register_manager.allocRegs(2, .{
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Air.refToIndex(bin_op.rhs).?, Air.refToIndex(bin_op.lhs).?,
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}, &.{});
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lhs_mcv = MCValue{ .register = regs[0] };
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rhs_mcv = MCValue{ .register = regs[1] };
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} else if (!rhs_is_register) {
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rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(bin_op.rhs).?, &.{}) };
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}
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}
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if (!lhs_is_register) {
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lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(bin_op.lhs).?, &.{}) };
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}
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// Move the operands to the newly allocated registers
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const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
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if (lhs_mcv == .register and !lhs_is_register) {
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try self.genSetReg(ty, lhs_mcv.register, lhs);
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branch.inst_table.putAssumeCapacity(Air.refToIndex(bin_op.lhs).?, lhs);
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}
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if (rhs_mcv == .register and !rhs_is_register) {
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try self.genSetReg(ty, rhs_mcv.register, rhs);
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branch.inst_table.putAssumeCapacity(Air.refToIndex(bin_op.rhs).?, rhs);
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}
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// The destination register is not present in the cmp instruction
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// The signedness of the integer does not matter for the cmp instruction
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switch (rhs_mcv) {
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.register => |reg| {
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_ = try self.addInst(.{
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.tag = .cmp_shifted_register,
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.data = .{ .rrr_imm6_shift = .{
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.rd = .xzr,
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.rn = lhs_mcv.register,
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.rm = reg,
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.imm6 = 0,
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.shift = .lsl,
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} },
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});
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},
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.immediate => |imm| {
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_ = try self.addInst(.{
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.tag = .cmp_immediate,
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.data = .{ .rr_imm12_sh = .{
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.rd = .xzr,
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.rn = lhs_mcv.register,
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.imm12 = @intCast(u12, imm),
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} },
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});
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},
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else => unreachable,
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}
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break :result switch (ty.isSignedInt()) {
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true => MCValue{ .compare_flags_signed = op },
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false => MCValue{ .compare_flags_unsigned = op },
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};
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airDbgStmt(self: *Self, inst: Air.Inst.Index) !void {
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@ -1667,9 +1724,153 @@ fn airDbgStmt(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
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_ = inst;
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const pl_op = self.air.instructions.items(.data)[inst].pl_op;
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const cond = try self.resolveInst(pl_op.operand);
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const extra = self.air.extraData(Air.CondBr, pl_op.payload);
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const then_body = self.air.extra[extra.end..][0..extra.data.then_body_len];
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const else_body = self.air.extra[extra.end + then_body.len ..][0..extra.data.else_body_len];
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const liveness_condbr = self.liveness.getCondBr(inst);
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return self.fail("TODO implement condbr {}", .{self.target.cpu.arch});
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const reloc: Mir.Inst.Index = switch (cond) {
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.compare_flags_signed,
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.compare_flags_unsigned,
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=> try self.addInst(.{
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.tag = .b_cond,
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.data = .{
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.inst_cond = .{
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.inst = undefined, // populated later through performReloc
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.cond = switch (cond) {
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.compare_flags_signed => |cmp_op| blk: {
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// Here we map to the opposite condition because the jump is to the false branch.
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const condition = Instruction.Condition.fromCompareOperatorSigned(cmp_op);
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break :blk condition.negate();
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},
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.compare_flags_unsigned => |cmp_op| blk: {
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// Here we map to the opposite condition because the jump is to the false branch.
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const condition = Instruction.Condition.fromCompareOperatorUnsigned(cmp_op);
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break :blk condition.negate();
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},
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else => unreachable,
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},
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},
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},
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}),
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else => return self.fail("TODO implement condr when condition is {s}", .{@tagName(cond)}),
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};
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// Capture the state of register and stack allocation state so that we can revert to it.
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const parent_next_stack_offset = self.next_stack_offset;
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const parent_free_registers = self.register_manager.free_registers;
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var parent_stack = try self.stack.clone(self.gpa);
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defer parent_stack.deinit(self.gpa);
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const parent_registers = self.register_manager.registers;
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try self.branch_stack.append(.{});
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try self.ensureProcessDeathCapacity(liveness_condbr.then_deaths.len);
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for (liveness_condbr.then_deaths) |operand| {
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self.processDeath(operand);
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}
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try self.genBody(then_body);
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// Revert to the previous register and stack allocation state.
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var saved_then_branch = self.branch_stack.pop();
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defer saved_then_branch.deinit(self.gpa);
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self.register_manager.registers = parent_registers;
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self.stack.deinit(self.gpa);
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self.stack = parent_stack;
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parent_stack = .{};
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self.next_stack_offset = parent_next_stack_offset;
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self.register_manager.free_registers = parent_free_registers;
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try self.performReloc(reloc);
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const else_branch = self.branch_stack.addOneAssumeCapacity();
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else_branch.* = .{};
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try self.ensureProcessDeathCapacity(liveness_condbr.else_deaths.len);
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for (liveness_condbr.else_deaths) |operand| {
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self.processDeath(operand);
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}
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try self.genBody(else_body);
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// At this point, each branch will possibly have conflicting values for where
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// each instruction is stored. They agree, however, on which instructions are alive/dead.
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// We use the first ("then") branch as canonical, and here emit
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// instructions into the second ("else") branch to make it conform.
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// We continue respect the data structure semantic guarantees of the else_branch so
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// that we can use all the code emitting abstractions. This is why at the bottom we
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// assert that parent_branch.free_registers equals the saved_then_branch.free_registers
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// rather than assigning it.
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const parent_branch = &self.branch_stack.items[self.branch_stack.items.len - 2];
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try parent_branch.inst_table.ensureUnusedCapacity(self.gpa, else_branch.inst_table.count());
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const else_slice = else_branch.inst_table.entries.slice();
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const else_keys = else_slice.items(.key);
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const else_values = else_slice.items(.value);
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for (else_keys) |else_key, else_idx| {
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const else_value = else_values[else_idx];
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const canon_mcv = if (saved_then_branch.inst_table.fetchSwapRemove(else_key)) |then_entry| blk: {
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// The instruction's MCValue is overridden in both branches.
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parent_branch.inst_table.putAssumeCapacity(else_key, then_entry.value);
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if (else_value == .dead) {
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assert(then_entry.value == .dead);
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continue;
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}
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break :blk then_entry.value;
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} else blk: {
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if (else_value == .dead)
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continue;
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// The instruction is only overridden in the else branch.
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var i: usize = self.branch_stack.items.len - 2;
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while (true) {
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i -= 1; // If this overflows, the question is: why wasn't the instruction marked dead?
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if (self.branch_stack.items[i].inst_table.get(else_key)) |mcv| {
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assert(mcv != .dead);
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break :blk mcv;
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}
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}
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};
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log.debug("consolidating else_entry {d} {}=>{}", .{ else_key, else_value, canon_mcv });
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// TODO make sure the destination stack offset / register does not already have something
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// going on there.
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try self.setRegOrMem(self.air.typeOfIndex(else_key), canon_mcv, else_value);
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// TODO track the new register / stack allocation
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}
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try parent_branch.inst_table.ensureUnusedCapacity(self.gpa, saved_then_branch.inst_table.count());
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const then_slice = saved_then_branch.inst_table.entries.slice();
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const then_keys = then_slice.items(.key);
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const then_values = then_slice.items(.value);
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for (then_keys) |then_key, then_idx| {
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const then_value = then_values[then_idx];
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// We already deleted the items from this table that matched the else_branch.
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// So these are all instructions that are only overridden in the then branch.
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parent_branch.inst_table.putAssumeCapacity(then_key, then_value);
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if (then_value == .dead)
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continue;
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const parent_mcv = blk: {
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var i: usize = self.branch_stack.items.len - 2;
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while (true) {
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i -= 1;
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if (self.branch_stack.items[i].inst_table.get(then_key)) |mcv| {
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assert(mcv != .dead);
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break :blk mcv;
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}
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}
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};
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log.debug("consolidating then_entry {d} {}=>{}", .{ then_key, parent_mcv, then_value });
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// TODO make sure the destination stack offset / register does not already have something
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// going on there.
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try self.setRegOrMem(self.air.typeOfIndex(then_key), parent_mcv, then_value);
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// TODO track the new register / stack allocation
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}
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self.branch_stack.pop().deinit(self.gpa);
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return self.finishAir(inst, .unreach, .{ pl_op.operand, .none, .none });
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}
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fn isNull(self: *Self, operand: MCValue) !MCValue {
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@ -1860,10 +2061,12 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
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return self.fail("TODO airSwitch for {}", .{self.target.cpu.arch});
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}
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fn performReloc(self: *Self, reloc: Reloc) !void {
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switch (reloc) {
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.rel32 => return self.fail("TODO reloc.rel32 for {}", .{self.target.cpu.arch}),
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.arm_branch => return self.fail("TODO reloc.arm_branch for {}", .{self.target.cpu.arch}),
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fn performReloc(self: *Self, inst: Mir.Inst.Index) !void {
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const tag = self.mir_instructions.items(.tag)[inst];
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switch (tag) {
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.b_cond => self.mir_instructions.items(.data)[inst].inst_cond.inst = @intCast(Air.Inst.Index, self.mir_instructions.len),
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.b => self.mir_instructions.items(.data)[inst].inst = @intCast(Air.Inst.Index, self.mir_instructions.len),
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else => unreachable,
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}
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}
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@ -1903,7 +2106,10 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {
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// Emit a jump with a relocation. It will be patched up after the block ends.
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try block_data.relocs.ensureUnusedCapacity(self.gpa, 1);
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return self.fail("TODO implement brvoid for {}", .{self.target.cpu.arch});
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block_data.relocs.appendAssumeCapacity(try self.addInst(.{
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.tag = .b,
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.data = .{ .inst = undefined }, // populated later through performReloc
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}));
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}
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fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
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@ -2050,8 +2256,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
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return self.fail("TODO implement set stack variable from embedded_in_code", .{});
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},
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.register => |reg| {
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_ = reg;
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const abi_size = ty.abiSize(self.target.*);
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const adj_off = stack_offset + abi_size;
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@ -2115,6 +2319,25 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
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else => unreachable, // unexpected register size
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}
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},
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.compare_flags_unsigned,
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.compare_flags_signed,
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=> |op| {
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const condition = switch (mcv) {
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.compare_flags_unsigned => Instruction.Condition.fromCompareOperatorUnsigned(op),
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.compare_flags_signed => Instruction.Condition.fromCompareOperatorSigned(op),
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else => unreachable,
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};
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_ = try self.addInst(.{
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.tag = .cset,
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.data = .{ .rrr_cond = .{
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.rd = reg,
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.rn = .xzr,
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.rm = .xzr,
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.cond = condition,
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} },
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});
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},
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.immediate => |x| {
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_ = try self.addInst(.{
|
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.tag = .movz,
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@ -14,6 +14,7 @@ const DW = std.dwarf;
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const leb128 = std.leb;
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const Instruction = bits.Instruction;
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const Register = bits.Register;
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const log = std.log.scoped(.aarch64_emit);
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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mir: Mir,
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@ -47,9 +48,16 @@ const InnerError = error{
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};
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const BranchType = enum {
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b_cond,
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unconditional_branch_immediate,
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const default = BranchType.unconditional_branch_immediate;
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fn default(tag: Mir.Inst.Tag) BranchType {
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return switch (tag) {
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.b, .bl => .unconditional_branch_immediate,
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.b_cond => .b_cond,
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else => unreachable,
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};
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}
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};
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pub fn emitMir(
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@ -65,8 +73,11 @@ pub fn emitMir(
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const inst = @intCast(u32, index);
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switch (tag) {
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.add_immediate => try emit.mirAddSubtractImmediate(inst),
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.cmp_immediate => try emit.mirAddSubtractImmediate(inst),
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.sub_immediate => try emit.mirAddSubtractImmediate(inst),
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.b_cond => try emit.mirConditionalBranchImmediate(inst),
|
||||
|
||||
.b => try emit.mirBranch(inst),
|
||||
.bl => try emit.mirBranch(inst),
|
||||
|
||||
@ -78,6 +89,10 @@ pub fn emitMir(
|
||||
|
||||
.call_extern => try emit.mirCallExtern(inst),
|
||||
|
||||
.cmp_shifted_register => try emit.mirAddSubtractShiftedRegister(inst),
|
||||
|
||||
.cset => try emit.mirConditionalSelect(inst),
|
||||
|
||||
.dbg_line => try emit.mirDbgLine(inst),
|
||||
|
||||
.dbg_prologue_end => try emit.mirDebugPrologueEnd(),
|
||||
@ -107,29 +122,50 @@ pub fn emitMir(
|
||||
}
|
||||
|
||||
pub fn deinit(emit: *Emit) void {
|
||||
var iter = emit.branch_forward_origins.valueIterator();
|
||||
while (iter.next()) |origin_list| {
|
||||
origin_list.deinit(emit.bin_file.allocator);
|
||||
}
|
||||
|
||||
emit.branch_types.deinit(emit.bin_file.allocator);
|
||||
emit.branch_forward_origins.deinit(emit.bin_file.allocator);
|
||||
emit.code_offset_mapping.deinit(emit.bin_file.allocator);
|
||||
emit.* = undefined;
|
||||
}
|
||||
|
||||
fn optimalBranchType(emit: *Emit, offset: i64) !BranchType {
|
||||
fn optimalBranchType(emit: *Emit, tag: Mir.Inst.Tag, offset: i64) !BranchType {
|
||||
assert(offset & 0b11 == 0);
|
||||
|
||||
// TODO handle conditional branches
|
||||
if (std.math.cast(i26, offset >> 2)) |_| {
|
||||
return BranchType.unconditional_branch_immediate;
|
||||
} else |_| {
|
||||
return emit.fail("TODO support branches larger than +-128 MiB", .{});
|
||||
switch (tag) {
|
||||
.b, .bl => {
|
||||
if (std.math.cast(i26, offset >> 2)) |_| {
|
||||
return BranchType.unconditional_branch_immediate;
|
||||
} else |_| {
|
||||
return emit.fail("TODO support branches larger than +-128 MiB", .{});
|
||||
}
|
||||
},
|
||||
.b_cond => {
|
||||
if (std.math.cast(i19, offset >> 2)) |_| {
|
||||
return BranchType.b_cond;
|
||||
} else |_| {
|
||||
return emit.fail("TODO support conditional branches larger than +-1 MiB", .{});
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
switch (tag) {
|
||||
.b, .bl => switch (emit.branch_types.get(inst).?) {
|
||||
|
||||
if (isBranch(tag)) {
|
||||
switch (emit.branch_types.get(inst).?) {
|
||||
.unconditional_branch_immediate => return 4,
|
||||
},
|
||||
.b_cond => return 4,
|
||||
}
|
||||
}
|
||||
|
||||
switch (tag) {
|
||||
.load_memory => {
|
||||
if (emit.bin_file.options.pie) {
|
||||
// adrp, ldr
|
||||
@ -146,10 +182,32 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
|
||||
return 5 * 4;
|
||||
}
|
||||
},
|
||||
.call_extern => return 4,
|
||||
.dbg_line,
|
||||
.dbg_epilogue_begin,
|
||||
.dbg_prologue_end,
|
||||
=> return 0,
|
||||
else => return 4,
|
||||
}
|
||||
}
|
||||
|
||||
fn isBranch(tag: Mir.Inst.Tag) bool {
|
||||
return switch (tag) {
|
||||
.b, .bl, .b_cond => true,
|
||||
else => false,
|
||||
};
|
||||
}
|
||||
|
||||
fn branchTarget(emit: *Emit, inst: Mir.Inst.Index) Mir.Inst.Index {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
|
||||
switch (tag) {
|
||||
.b, .bl => return emit.mir.instructions.items(.data)[inst].inst,
|
||||
.b_cond => return emit.mir.instructions.items(.data)[inst].inst_cond.inst,
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn lowerBranches(emit: *Emit) !void {
|
||||
const mir_tags = emit.mir.instructions.items(.tag);
|
||||
const allocator = emit.bin_file.allocator;
|
||||
@ -162,41 +220,38 @@ fn lowerBranches(emit: *Emit) !void {
|
||||
// generating MIR
|
||||
for (mir_tags) |tag, index| {
|
||||
const inst = @intCast(u32, index);
|
||||
switch (tag) {
|
||||
.b, .bl => {
|
||||
const target_inst = emit.mir.instructions.items(.data)[inst].inst;
|
||||
if (isBranch(tag)) {
|
||||
const target_inst = emit.branchTarget(inst);
|
||||
|
||||
// Remember this branch instruction
|
||||
try emit.branch_types.put(allocator, inst, BranchType.default);
|
||||
// Remember this branch instruction
|
||||
try emit.branch_types.put(allocator, inst, BranchType.default(tag));
|
||||
|
||||
// Forward branches require some extra stuff: We only
|
||||
// know their offset once we arrive at the target
|
||||
// instruction. Therefore, we need to be able to
|
||||
// access the branch instruction when we visit the
|
||||
// target instruction in order to manipulate its type
|
||||
// etc.
|
||||
if (target_inst > inst) {
|
||||
// Remember the branch instruction index
|
||||
try emit.code_offset_mapping.put(allocator, inst, 0);
|
||||
// Forward branches require some extra stuff: We only
|
||||
// know their offset once we arrive at the target
|
||||
// instruction. Therefore, we need to be able to
|
||||
// access the branch instruction when we visit the
|
||||
// target instruction in order to manipulate its type
|
||||
// etc.
|
||||
if (target_inst > inst) {
|
||||
// Remember the branch instruction index
|
||||
try emit.code_offset_mapping.put(allocator, inst, 0);
|
||||
|
||||
if (emit.branch_forward_origins.getPtr(target_inst)) |origin_list| {
|
||||
try origin_list.append(allocator, inst);
|
||||
} else {
|
||||
var origin_list: std.ArrayListUnmanaged(Mir.Inst.Index) = .{};
|
||||
try origin_list.append(allocator, inst);
|
||||
try emit.branch_forward_origins.put(allocator, target_inst, origin_list);
|
||||
}
|
||||
if (emit.branch_forward_origins.getPtr(target_inst)) |origin_list| {
|
||||
try origin_list.append(allocator, inst);
|
||||
} else {
|
||||
var origin_list: std.ArrayListUnmanaged(Mir.Inst.Index) = .{};
|
||||
try origin_list.append(allocator, inst);
|
||||
try emit.branch_forward_origins.put(allocator, target_inst, origin_list);
|
||||
}
|
||||
}
|
||||
|
||||
// Remember the target instruction index so that we
|
||||
// update the real code offset in all future passes
|
||||
//
|
||||
// putNoClobber may not be used as the put operation
|
||||
// may clobber the entry when multiple branches branch
|
||||
// to the same target instruction
|
||||
try emit.code_offset_mapping.put(allocator, target_inst, 0);
|
||||
},
|
||||
else => {}, // not a branch
|
||||
// Remember the target instruction index so that we
|
||||
// update the real code offset in all future passes
|
||||
//
|
||||
// putNoClobber may not be used as the put operation
|
||||
// may clobber the entry when multiple branches branch
|
||||
// to the same target instruction
|
||||
try emit.code_offset_mapping.put(allocator, target_inst, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -220,21 +275,20 @@ fn lowerBranches(emit: *Emit) !void {
|
||||
|
||||
// If this instruction is a backward branch, calculate the
|
||||
// offset, which may potentially update the branch type
|
||||
switch (tag) {
|
||||
.b, .bl => {
|
||||
const target_inst = emit.mir.instructions.items(.data)[inst].inst;
|
||||
if (target_inst < inst) {
|
||||
const target_offset = emit.code_offset_mapping.get(target_inst).?;
|
||||
const offset = @intCast(i64, target_offset) - @intCast(i64, current_code_offset + 8);
|
||||
const branch_type = emit.branch_types.getPtr(inst).?;
|
||||
const optimal_branch_type = try emit.optimalBranchType(offset);
|
||||
if (branch_type.* != optimal_branch_type) {
|
||||
branch_type.* = optimal_branch_type;
|
||||
all_branches_lowered = false;
|
||||
}
|
||||
if (isBranch(tag)) {
|
||||
const target_inst = emit.branchTarget(inst);
|
||||
if (target_inst < inst) {
|
||||
const target_offset = emit.code_offset_mapping.get(target_inst).?;
|
||||
const offset = @intCast(i64, target_offset) - @intCast(i64, current_code_offset);
|
||||
const branch_type = emit.branch_types.getPtr(inst).?;
|
||||
const optimal_branch_type = try emit.optimalBranchType(tag, offset);
|
||||
if (branch_type.* != optimal_branch_type) {
|
||||
branch_type.* = optimal_branch_type;
|
||||
all_branches_lowered = false;
|
||||
}
|
||||
},
|
||||
else => {},
|
||||
|
||||
log.debug("lowerBranches: branch {} has offset {}", .{ inst, offset });
|
||||
}
|
||||
}
|
||||
|
||||
// If this instruction is the target of one or more
|
||||
@ -242,14 +296,17 @@ fn lowerBranches(emit: *Emit) !void {
|
||||
// potentially update the branch type
|
||||
if (emit.branch_forward_origins.get(inst)) |origin_list| {
|
||||
for (origin_list.items) |forward_branch_inst| {
|
||||
const branch_tag = emit.mir.instructions.items(.tag)[forward_branch_inst];
|
||||
const forward_branch_inst_offset = emit.code_offset_mapping.get(forward_branch_inst).?;
|
||||
const offset = @intCast(i64, forward_branch_inst_offset) - @intCast(i64, current_code_offset + 8);
|
||||
const offset = @intCast(i64, current_code_offset) - @intCast(i64, forward_branch_inst_offset);
|
||||
const branch_type = emit.branch_types.getPtr(forward_branch_inst).?;
|
||||
const optimal_branch_type = try emit.optimalBranchType(offset);
|
||||
const optimal_branch_type = try emit.optimalBranchType(branch_tag, offset);
|
||||
if (branch_type.* != optimal_branch_type) {
|
||||
branch_type.* = optimal_branch_type;
|
||||
all_branches_lowered = false;
|
||||
}
|
||||
|
||||
log.debug("lowerBranches: branch {} has offset {}", .{ forward_branch_inst, offset });
|
||||
}
|
||||
}
|
||||
|
||||
@ -347,6 +404,12 @@ fn mirAddSubtractImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
rr_imm12_sh.imm12,
|
||||
rr_imm12_sh.sh == 1,
|
||||
)),
|
||||
.cmp_immediate => try emit.writeInstruction(Instruction.subs(
|
||||
rr_imm12_sh.rd,
|
||||
rr_imm12_sh.rn,
|
||||
rr_imm12_sh.imm12,
|
||||
rr_imm12_sh.sh == 1,
|
||||
)),
|
||||
.sub_immediate => try emit.writeInstruction(Instruction.sub(
|
||||
rr_imm12_sh.rd,
|
||||
rr_imm12_sh.rn,
|
||||
@ -357,12 +420,37 @@ fn mirAddSubtractImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
}
|
||||
}
|
||||
|
||||
fn mirConditionalBranchImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const inst_cond = emit.mir.instructions.items(.data)[inst].inst_cond;
|
||||
|
||||
const offset = @intCast(i64, emit.code_offset_mapping.get(inst_cond.inst).?) - @intCast(i64, emit.code.items.len);
|
||||
const branch_type = emit.branch_types.get(inst).?;
|
||||
log.debug("mirConditionalBranchImmediate: {} offset={}", .{ inst, offset });
|
||||
|
||||
switch (branch_type) {
|
||||
.b_cond => switch (tag) {
|
||||
.b_cond => try emit.writeInstruction(Instruction.bCond(inst_cond.cond, @intCast(i21, offset))),
|
||||
else => unreachable,
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirBranch(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const target_inst = emit.mir.instructions.items(.data)[inst].inst;
|
||||
|
||||
const offset = @intCast(i64, emit.code_offset_mapping.get(target_inst).?) - @intCast(i64, emit.code.items.len + 8);
|
||||
log.debug("branch {}(tag: {}) -> {}(tag: {})", .{
|
||||
inst,
|
||||
tag,
|
||||
target_inst,
|
||||
emit.mir.instructions.items(.tag)[target_inst],
|
||||
});
|
||||
|
||||
const offset = @intCast(i64, emit.code_offset_mapping.get(target_inst).?) - @intCast(i64, emit.code.items.len);
|
||||
const branch_type = emit.branch_types.get(inst).?;
|
||||
log.debug("mirBranch: {} offset={}", .{ inst, offset });
|
||||
|
||||
switch (branch_type) {
|
||||
.unconditional_branch_immediate => switch (tag) {
|
||||
@ -370,6 +458,7 @@ fn mirBranch(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
.bl => try emit.writeInstruction(Instruction.bl(@intCast(i28, offset))),
|
||||
else => unreachable,
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
@ -453,6 +542,37 @@ fn mirCallExtern(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
}
|
||||
}
|
||||
|
||||
fn mirAddSubtractShiftedRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const rrr_imm6_shift = emit.mir.instructions.items(.data)[inst].rrr_imm6_shift;
|
||||
|
||||
switch (tag) {
|
||||
.cmp_shifted_register => try emit.writeInstruction(Instruction.subsShiftedRegister(
|
||||
rrr_imm6_shift.rd,
|
||||
rrr_imm6_shift.rn,
|
||||
rrr_imm6_shift.rm,
|
||||
rrr_imm6_shift.shift,
|
||||
rrr_imm6_shift.imm6,
|
||||
)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirConditionalSelect(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const rrr_cond = emit.mir.instructions.items(.data)[inst].rrr_cond;
|
||||
|
||||
switch (tag) {
|
||||
.cset => try emit.writeInstruction(Instruction.csinc(
|
||||
rrr_cond.rd,
|
||||
rrr_cond.rn,
|
||||
rrr_cond.rm,
|
||||
rrr_cond.cond,
|
||||
)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirLoadMemory(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
assert(emit.mir.instructions.items(.tag)[inst] == .load_memory);
|
||||
const payload = emit.mir.instructions.items(.data)[inst].payload;
|
||||
|
||||
@ -26,6 +26,8 @@ pub const Inst = struct {
|
||||
pub const Tag = enum(u16) {
|
||||
/// Add (immediate)
|
||||
add_immediate,
|
||||
/// Branch conditionally
|
||||
b_cond,
|
||||
/// Branch
|
||||
b,
|
||||
/// Branch with Link
|
||||
@ -36,13 +38,19 @@ pub const Inst = struct {
|
||||
brk,
|
||||
/// Pseudo-instruction: Call extern
|
||||
call_extern,
|
||||
/// Compare (immediate)
|
||||
cmp_immediate,
|
||||
/// Compare (shifted register)
|
||||
cmp_shifted_register,
|
||||
/// Conditional set
|
||||
cset,
|
||||
/// Pseudo-instruction: End of prologue
|
||||
dbg_prologue_end,
|
||||
/// Pseudo-instruction: Beginning of epilogue
|
||||
dbg_epilogue_begin,
|
||||
/// Pseudo-instruction: Update debug line
|
||||
dbg_line,
|
||||
/// Psuedo-instruction: Load memory
|
||||
/// Pseudo-instruction: Load memory
|
||||
///
|
||||
/// Payload is `LoadMemory`
|
||||
load_memory,
|
||||
@ -97,7 +105,7 @@ pub const Inst = struct {
|
||||
///
|
||||
/// Used by e.g. nop
|
||||
nop: void,
|
||||
/// Another instruction.
|
||||
/// Another instruction
|
||||
///
|
||||
/// Used by e.g. b
|
||||
inst: Index,
|
||||
@ -117,6 +125,13 @@ pub const Inst = struct {
|
||||
///
|
||||
/// Used by e.g. blr
|
||||
reg: Register,
|
||||
/// Another instruction and a condition
|
||||
///
|
||||
/// Used by e.g. b_cond
|
||||
inst_cond: struct {
|
||||
inst: Index,
|
||||
cond: bits.Instruction.Condition,
|
||||
},
|
||||
/// A register, an unsigned 16-bit immediate, and an optional shift
|
||||
///
|
||||
/// Used by e.g. movz
|
||||
@ -141,6 +156,25 @@ pub const Inst = struct {
|
||||
imm12: u12,
|
||||
sh: u1 = 0,
|
||||
},
|
||||
/// Three registers and a shift (shift type and 6-bit amount)
|
||||
///
|
||||
/// Used by e.g. cmp_shifted_register
|
||||
rrr_imm6_shift: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
imm6: u6,
|
||||
shift: bits.Instruction.AddSubtractShiftedRegisterShift,
|
||||
},
|
||||
/// Three registers and a condition
|
||||
///
|
||||
/// Used by e.g. cset
|
||||
rrr_cond: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
cond: bits.Instruction.Condition,
|
||||
},
|
||||
/// Three registers and a LoadStoreOffset
|
||||
///
|
||||
/// Used by e.g. str_register
|
||||
|
||||
@ -295,6 +295,18 @@ pub const Instruction = union(enum) {
|
||||
op: u1,
|
||||
sf: u1,
|
||||
},
|
||||
add_subtract_shifted_register: packed struct {
|
||||
rd: u5,
|
||||
rn: u5,
|
||||
imm6: u6,
|
||||
rm: u5,
|
||||
fixed_1: u1 = 0b0,
|
||||
shift: u2,
|
||||
fixed_2: u5 = 0b01011,
|
||||
s: u1,
|
||||
op: u1,
|
||||
sf: u1,
|
||||
},
|
||||
conditional_branch: struct {
|
||||
cond: u4,
|
||||
o0: u1,
|
||||
@ -309,6 +321,17 @@ pub const Instruction = union(enum) {
|
||||
fixed: u6 = 0b011010,
|
||||
sf: u1,
|
||||
},
|
||||
conditional_select: struct {
|
||||
rd: u5,
|
||||
rn: u5,
|
||||
op2: u2,
|
||||
cond: u4,
|
||||
rm: u5,
|
||||
fixed: u8 = 0b11010100,
|
||||
s: u1,
|
||||
op: u1,
|
||||
sf: u1,
|
||||
},
|
||||
|
||||
pub const Shift = struct {
|
||||
shift: Type = .lsl,
|
||||
@ -376,6 +399,57 @@ pub const Instruction = union(enum) {
|
||||
/// Integer: Always
|
||||
/// Floating point: Always
|
||||
nv,
|
||||
|
||||
/// Converts a std.math.CompareOperator into a condition flag,
|
||||
/// i.e. returns the condition that is true iff the result of the
|
||||
/// comparison is true. Assumes signed comparison
|
||||
pub fn fromCompareOperatorSigned(op: std.math.CompareOperator) Condition {
|
||||
return switch (op) {
|
||||
.gte => .ge,
|
||||
.gt => .gt,
|
||||
.neq => .ne,
|
||||
.lt => .lt,
|
||||
.lte => .le,
|
||||
.eq => .eq,
|
||||
};
|
||||
}
|
||||
|
||||
/// Converts a std.math.CompareOperator into a condition flag,
|
||||
/// i.e. returns the condition that is true iff the result of the
|
||||
/// comparison is true. Assumes unsigned comparison
|
||||
pub fn fromCompareOperatorUnsigned(op: std.math.CompareOperator) Condition {
|
||||
return switch (op) {
|
||||
.gte => .cs,
|
||||
.gt => .hi,
|
||||
.neq => .ne,
|
||||
.lt => .cc,
|
||||
.lte => .ls,
|
||||
.eq => .eq,
|
||||
};
|
||||
}
|
||||
|
||||
/// Returns the condition which is true iff the given condition is
|
||||
/// false (if such a condition exists)
|
||||
pub fn negate(cond: Condition) Condition {
|
||||
return switch (cond) {
|
||||
.eq => .ne,
|
||||
.ne => .eq,
|
||||
.cs => .cc,
|
||||
.cc => .cs,
|
||||
.mi => .pl,
|
||||
.pl => .mi,
|
||||
.vs => .vc,
|
||||
.vc => .vs,
|
||||
.hi => .ls,
|
||||
.ls => .hi,
|
||||
.ge => .lt,
|
||||
.lt => .ge,
|
||||
.gt => .le,
|
||||
.le => .gt,
|
||||
.al => unreachable,
|
||||
.nv => unreachable,
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
pub fn toU32(self: Instruction) u32 {
|
||||
@ -391,9 +465,11 @@ pub const Instruction = union(enum) {
|
||||
.no_operation => |v| @bitCast(u32, v),
|
||||
.logical_shifted_register => |v| @bitCast(u32, v),
|
||||
.add_subtract_immediate => |v| @bitCast(u32, v),
|
||||
.add_subtract_shifted_register => |v| @bitCast(u32, v),
|
||||
// TODO once packed structs work, this can be refactored
|
||||
.conditional_branch => |v| @as(u32, v.cond) | (@as(u32, v.o0) << 4) | (@as(u32, v.imm19) << 5) | (@as(u32, v.o1) << 24) | (@as(u32, v.fixed) << 25),
|
||||
.compare_and_branch => |v| @as(u32, v.rt) | (@as(u32, v.imm19) << 5) | (@as(u32, v.op) << 24) | (@as(u32, v.fixed) << 25) | (@as(u32, v.sf) << 31),
|
||||
.conditional_select => |v| @as(u32, v.rd) | @as(u32, v.rn) << 5 | @as(u32, v.op2) << 10 | @as(u32, v.cond) << 12 | @as(u32, v.rm) << 16 | @as(u32, v.fixed) << 21 | @as(u32, v.s) << 29 | @as(u32, v.op) << 30 | @as(u32, v.sf) << 31,
|
||||
};
|
||||
}
|
||||
|
||||
@ -804,6 +880,35 @@ pub const Instruction = union(enum) {
|
||||
};
|
||||
}
|
||||
|
||||
pub const AddSubtractShiftedRegisterShift = enum(u2) { lsl, lsr, asr, _ };
|
||||
|
||||
fn addSubtractShiftedRegister(
|
||||
op: u1,
|
||||
s: u1,
|
||||
shift: AddSubtractShiftedRegisterShift,
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
imm6: u6,
|
||||
) Instruction {
|
||||
return Instruction{
|
||||
.add_subtract_shifted_register = .{
|
||||
.rd = rd.id(),
|
||||
.rn = rn.id(),
|
||||
.imm6 = imm6,
|
||||
.rm = rm.id(),
|
||||
.shift = @enumToInt(shift),
|
||||
.s = s,
|
||||
.op = op,
|
||||
.sf = switch (rd.size()) {
|
||||
32 => 0b0,
|
||||
64 => 0b1,
|
||||
else => unreachable, // unexpected register size
|
||||
},
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn conditionalBranch(
|
||||
o0: u1,
|
||||
o1: u1,
|
||||
@ -841,6 +946,33 @@ pub const Instruction = union(enum) {
|
||||
};
|
||||
}
|
||||
|
||||
fn conditionalSelect(
|
||||
op2: u2,
|
||||
op: u1,
|
||||
s: u1,
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
cond: Condition,
|
||||
) Instruction {
|
||||
return Instruction{
|
||||
.conditional_select = .{
|
||||
.rd = rd.id(),
|
||||
.rn = rn.id(),
|
||||
.op2 = op2,
|
||||
.cond = @enumToInt(cond),
|
||||
.rm = rm.id(),
|
||||
.s = s,
|
||||
.op = op,
|
||||
.sf = switch (rd.size()) {
|
||||
32 => 0b0,
|
||||
64 => 0b1,
|
||||
else => unreachable, // unexpected register size
|
||||
},
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
// Helper functions for assembly syntax functions
|
||||
|
||||
// Move wide (immediate)
|
||||
@ -1055,6 +1187,48 @@ pub const Instruction = union(enum) {
|
||||
return addSubtractImmediate(0b1, 0b1, rd, rn, imm, shift);
|
||||
}
|
||||
|
||||
// Add/subtract (shifted register)
|
||||
|
||||
pub fn addShiftedRegister(
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
shift: AddSubtractShiftedRegisterShift,
|
||||
imm6: u6,
|
||||
) Instruction {
|
||||
return addSubtractShiftedRegister(0b0, 0b0, shift, rd, rn, rm, imm6);
|
||||
}
|
||||
|
||||
pub fn addsShiftedRegister(
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
shift: AddSubtractShiftedRegisterShift,
|
||||
imm6: u6,
|
||||
) Instruction {
|
||||
return addSubtractShiftedRegister(0b0, 0b1, shift, rd, rn, rm, imm6);
|
||||
}
|
||||
|
||||
pub fn subShiftedRegister(
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
shift: AddSubtractShiftedRegisterShift,
|
||||
imm6: u6,
|
||||
) Instruction {
|
||||
return addSubtractShiftedRegister(0b1, 0b0, shift, rd, rn, rm, imm6);
|
||||
}
|
||||
|
||||
pub fn subsShiftedRegister(
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
shift: AddSubtractShiftedRegisterShift,
|
||||
imm6: u6,
|
||||
) Instruction {
|
||||
return addSubtractShiftedRegister(0b1, 0b1, shift, rd, rn, rm, imm6);
|
||||
}
|
||||
|
||||
// Conditional branch
|
||||
|
||||
pub fn bCond(cond: Condition, offset: i21) Instruction {
|
||||
@ -1070,6 +1244,24 @@ pub const Instruction = union(enum) {
|
||||
pub fn cbnz(rt: Register, offset: i21) Instruction {
|
||||
return compareAndBranch(0b1, rt, offset);
|
||||
}
|
||||
|
||||
// Conditional select
|
||||
|
||||
pub fn csel(rd: Register, rn: Register, rm: Register, cond: Condition) Instruction {
|
||||
return conditionalSelect(0b00, 0b0, 0b0, rd, rn, rm, cond);
|
||||
}
|
||||
|
||||
pub fn csinc(rd: Register, rn: Register, rm: Register, cond: Condition) Instruction {
|
||||
return conditionalSelect(0b01, 0b0, 0b0, rd, rn, rm, cond);
|
||||
}
|
||||
|
||||
pub fn csinv(rd: Register, rn: Register, rm: Register, cond: Condition) Instruction {
|
||||
return conditionalSelect(0b00, 0b1, 0b0, rd, rn, rm, cond);
|
||||
}
|
||||
|
||||
pub fn csneg(rd: Register, rn: Register, rm: Register, cond: Condition) Instruction {
|
||||
return conditionalSelect(0b01, 0b1, 0b0, rd, rn, rm, cond);
|
||||
}
|
||||
};
|
||||
|
||||
test {
|
||||
@ -1231,6 +1423,14 @@ test "serialize instructions" {
|
||||
.inst = Instruction.cbz(.x10, 40),
|
||||
.expected = 0b1_011010_0_0000000000000001010_01010,
|
||||
},
|
||||
.{ // add x0, x1, x2, lsl #5
|
||||
.inst = Instruction.addShiftedRegister(.x0, .x1, .x2, .lsl, 5),
|
||||
.expected = 0b1_0_0_01011_00_0_00010_000101_00001_00000,
|
||||
},
|
||||
.{ // csinc x1, x2, x4, eq
|
||||
.inst = Instruction.csinc(.x1, .x2, .x4, .eq),
|
||||
.expected = 0b1_0_0_11010100_00100_0000_0_1_00010_00001,
|
||||
},
|
||||
};
|
||||
|
||||
for (testcases) |case| {
|
||||
|
||||
@ -68,4 +68,33 @@ pub fn addCases(ctx: *TestContext) !void {
|
||||
"",
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("conditional branches", linux_aarch64);
|
||||
|
||||
case.addCompareOutput(
|
||||
\\pub fn main() void {
|
||||
\\ foo(123);
|
||||
\\}
|
||||
\\
|
||||
\\fn foo(x: u64) void {
|
||||
\\ if (x > 42) {
|
||||
\\ print();
|
||||
\\ }
|
||||
\\}
|
||||
\\
|
||||
\\fn print() void {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{x8}" (64),
|
||||
\\ [arg1] "{x0}" (1),
|
||||
\\ [arg2] "{x1}" (@ptrToInt("Hello, World!\n")),
|
||||
\\ [arg3] "{x2}" ("Hello, World!\n".len),
|
||||
\\ : "memory", "cc"
|
||||
\\ );
|
||||
\\}
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user