From 53210b2304990e9b3b0f35f847e13d4ea4ae4ced Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Tue, 24 Sep 2019 20:56:04 -0400 Subject: [PATCH] better default enabled features for riscv Until ability to specify target CPU features (#2883) is done, this commit gives riscv target better default features. This side-steps #3275 which is a deficiency in compiler-rt when features do not include 32 bit integer division. With this commit, RISC-V compiler-rt tests pass and Hello World works both pure-zig and with musl libc. --- src/codegen.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/codegen.cpp b/src/codegen.cpp index 9937cba1c6..f3bb210902 100644 --- a/src/codegen.cpp +++ b/src/codegen.cpp @@ -30,6 +30,11 @@ enum ResumeId { ResumeIdCall, }; +// TODO https://github.com/ziglang/zig/issues/2883 +// Until then we have this same default as Clang. +// This avoids https://github.com/ziglang/zig/issues/3275 +static const char *riscv_default_features = "+a,+c,+d,+f,+m,+relax"; + static void init_darwin_native(CodeGen *g) { char *osx_target = getenv("MACOSX_DEPLOYMENT_TARGET"); char *ios_target = getenv("IPHONEOS_DEPLOYMENT_TARGET"); @@ -8720,8 +8725,9 @@ static void init(CodeGen *g) { } } else if (target_is_riscv(g->zig_target)) { // TODO https://github.com/ziglang/zig/issues/2883 + // Be aware of https://github.com/ziglang/zig/issues/3275 target_specific_cpu_args = ""; - target_specific_features = "+a"; + target_specific_features = riscv_default_features; } else { target_specific_cpu_args = ""; target_specific_features = ""; @@ -9007,7 +9013,7 @@ void add_cc_args(CodeGen *g, ZigList &args, const char *out_dep_pa args.append("-Xclang"); args.append("-target-feature"); args.append("-Xclang"); - args.append("+a"); + args.append(riscv_default_features); } } if (g->zig_target->os == OsFreestanding) {